Semiconductor device

Abstract

To impart excellent electric characteristics to a semiconductor device.SOLUTION: A semiconductor device comprises a first insulation layer, a second insulation layer, an oxide semiconductor layer, and first to third conductive layers. The oxide semiconductor layer includes a region in contact with the first insulation layer. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulation layer includes a region in contact with the oxide semiconductor layer. The third conductive layer includes a region in contact with the second insulation layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are provided separated from each other. The third region is provided between the first region and the second region. The third region and the third conductive layer include an overlapping region via the second insulation layer. The first region and the second region include a portion having a higher carbon concentration than the third region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, devices, power storage devices, storage devices, driving methods thereof, or manufacturing methods thereof, as examples. Some examples include:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). These are widely used in electronic devices such as semiconductors that can be applied to transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object is to provide a semiconductor device with a high on-state current. Another object of the present invention is to provide a semiconductor device suitable for a highly integrated semiconductor device. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object is to provide a highly reliable semiconductor device. Alternatively, the present invention aims to provide a semiconductor device that retains data even when the power supply is cut off. Another object of the present invention is to provide a novel semiconductor device. It is another object of the present invention to provide a method for manufacturing the semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention relates to a transistor including an oxide semiconductor layer in a channel formation region.

[0010] One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third insulating layers. and a conductive layer, wherein the oxide semiconductor layer has a region in contact with the first insulating layer. The first conductive layer is electrically connected to the oxide semiconductor layer, and the second conductive layer is electrically connected to the oxide semiconductor layer. the second insulating layer is electrically connected to the oxide semiconductor layer, and the second insulating layer has a region in contact with the oxide semiconductor layer; The third conductive layer has a region in contact with the second insulating layer, and the second insulating layer serves as a gate insulating film. The first conductive layer has a region that can function as a source electrode or a drain electrode. The second conductive layer has an area that can function as either a source electrode or a drain electrode. The third conductive layer has a region that can function as the other of the gate electrodes. the oxide semiconductor layer has first to third regions, The first region and the second region are provided separately, and the third region is provided between the first region and the second region. The third region and the third conductive layer have an overlapping region with the second insulating layer interposed therebetween. The first region and the second region have a portion where the carbon concentration is higher than that of the third region. The semiconductor device is characterized by the above.

[0011] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limit.

[0012] In the first region and the second region, phosphorus, arsenic, antimony, boron, aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, The concentration of one or more elements selected from fluorine, chlorine, titanium, zinc, and hydrogen is adjusted to a third It may also be configured to have a portion higher than the region.

[0013] The first region and the second region have a region in contact with the nitride insulating film containing hydrogen. It may also be possible to use the following.

[0014] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, an oxide semiconductor layer, and a second insulating layer. a first insulating layer; a second insulating layer; a third conductive layer; and a second insulating layer. the first conductive layer is electrically connected to the oxide semiconductor layer, and the second conductive layer is electrically connected to the oxide semiconductor layer. The insulating layer is electrically connected to the oxide semiconductor layer, and the second insulating layer is in contact with the oxide semiconductor layer. The third conductive layer has a region in contact with the second insulating layer, and the second insulating layer has a gate The first conductive layer has a region that can function as an insulating film, and the first conductive layer is a source electrode or a drain electrode. The second conductive layer has a region that can function as one of the source and drain electrodes. The third conductive layer has a region that can function as the other of the gate and drain electrodes. The oxide semiconductor layer has a region that can function as a gate electrode, and the oxide semiconductor layer has first to fifth regions. The first region and the second region are provided separately, and the first region overlaps the first conductive layer. the second region has a region overlapping the second conductive layer, and the third region and the third conductive layer The first and second insulating layers have a region where they overlap with each other via a second insulating layer, and the third region has a region where the first and second insulating layers overlap with each other via a second insulating layer. a fourth region is provided between the first region and the third region; a fifth region is provided between the first region and the third region; The region is provided between the second region and the third region, and the fourth region and the fifth region are The carbon concentration in the first region is higher than that in the second region and the third region. This is a semiconductor device characterized by the above.

[0015] In the fourth and fifth regions, phosphorus, arsenic, antimony, boron, and aluminum , silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, The concentration of one or more elements selected from fluorine, chlorine, titanium, zinc, and hydrogen is adjusted to a first The first region may have a portion higher than the second region and the third region.

[0016] The fourth and fifth regions have a structure in which they are in contact with a nitride insulating film containing hydrogen. It may also be possible to use the following.

[0017] In the semiconductor device, a fourth conductive layer is formed to overlap with the oxide semiconductor layer with the first insulating layer interposed therebetween. The configuration may be such that:

[0018] The oxide semiconductor layer has first and second oxide semiconductor layers, and the second oxide semiconductor layer is The oxide semiconductor layer and the first oxide semiconductor layer may be provided in this order. The first oxide semiconductor layer may be provided so as to cover the second oxide semiconductor layer.

[0019] In the above-described oxide semiconductor layer configuration, the first and second oxide semiconductor layers contain In and Zn. , M (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) The atomic ratio of M to In in the first oxide semiconductor layer is larger than that in the second oxide semiconductor layer. It is preferable that it is large.

[0020] The oxide semiconductor layer includes first to third oxide semiconductor layers, and the first to third oxide semiconductor layers are The third oxide semiconductor layer, the second oxide semiconductor layer, and the first oxide semiconductor layer are formed in this order. The first oxide semiconductor layer may be formed between the second oxide semiconductor layer and the first oxide semiconductor layer. The insulating film 3 may be provided so as to cover the oxide semiconductor layer 3.

[0021] In the above-described oxide semiconductor layer structure, the first to third oxide semiconductor layers contain In and Zn, M (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf), The first and third oxide semiconductor layers have an atomic ratio of M to In that is equal to or greater than that of the second oxide semiconductor layer. It is preferable that it is greater than .

[0022] The oxide semiconductor layer may be a non-single crystal, and may have crystals aligned along the c-axis. It is preferable that

[0023] Another embodiment of the present invention is a method for forming an oxide semiconductor film on an insulating surface, A first resist mask is formed on the oxide semiconductor film using the first resist mask. The oxide semiconductor layer is formed by selectively etching the first resist mask. a first insulating film is formed over the oxide semiconductor layer; a conductive film is formed over the first insulating film; A second resist mask is formed on the conductive film and the first The insulating film is selectively etched to form a laminate consisting of a first insulating layer and a conductive layer. The oxide semiconductor layer is formed on the first and second regions thereof, and the first and second regions are exposed. Impurities are added to the first and second regions by laser processing to form oxygen vacancies, and the second laser The resist mask is peeled off to expose the first and second regions of the oxide semiconductor layer, the first insulating layer, and forming a second insulating film containing hydrogen on the conductive layer, and forming a first region and a second insulating film on the conductive layer. The resistance of the first region and the second region is reduced by diffusing hydrogen into the second region. The present invention relates to a method for manufacturing a semiconductor device. [Effects of the Invention]

[0024] By using one embodiment of the present invention, favorable electrical characteristics can be imparted to a semiconductor device. Alternatively, a semiconductor device having a high on-state current can be provided. A semiconductor device with a high degree of integration can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device that retains data even when the power is cut off can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing the semiconductor device can be provided.

[0025] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 2] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 4] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 6] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 8] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 10] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 12] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 14] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 19] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 20] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 21] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 22] FIG. 1 is a top view illustrating a display device. [Figure 23] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 24] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 25] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 26] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 27] 1A and 1B are diagrams illustrating a structural example of a display device and a circuit diagram of a pixel. [Figure 28] FIG. 2 is a diagram illustrating a display module. [Figure 29] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 30] 1A and 1B are a cross-sectional view and a circuit diagram of a memory device. [Figure 31] FIG. 2 is a diagram illustrating an example of the configuration of an RF tag. [Figure 32] FIG. 2 is a diagram illustrating an example of the configuration of a CPU. [Figure 33] FIG. 1 is a circuit diagram of a memory element. [Figure 34] 1A to 1C illustrate a structure of a transistor. [Figure 35] 1A to 1C illustrate a structure of a transistor. [Figure 36] 1A to 1C illustrate a structure of a transistor. [Figure 37] 1A to 1C illustrate a structure of a transistor. [Figure 38] 1A to 1C illustrate a structure of a transistor. [Figure 39] Cross section and band structure of a transistor. [Figure 40] FIG. 1 is a diagram illustrating a calculation model. [Figure 41] FIG. 1 is a diagram illustrating the initial state and the final state. [Figure 42] 1 is a diagram illustrating the activation barrier. [Figure 43] FIG. 1 is a diagram illustrating the initial state and the final state. [Figure 44] 1 is a diagram illustrating the activation barrier. [Figure 45] A diagram explaining VoH transition levels. [Figure 46] 1A to 1C illustrate electronic devices. [Figure 47] FIG. 1 is a diagram illustrating an example of how to use an RF tag. [Figure 48] Cross-sectional TEM image of a transistor. [Figure 49] Cross-sectional TEM image of a transistor. [Figure 50] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 51] FIG. 1 shows the results of a gate bias-temperature stress test. [Figure 52] FIG. 1 shows the results of a gate bias-temperature stress test. [Figure 53] FIG. 1 shows the results of a gate bias-temperature stress test. [Figure 54] FIG. 1 is a diagram illustrating a sample for SIMS analysis. [Figure 55] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 56] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 57] FIG. 10 is a diagram illustrating the temperature dependence of resistivity. [Figure 58] Schematic diagram illustrating a film formation model of CAAC-OS, and cross-sectional views of a pellet and CAAC-OS. [Figure 59] Schematic diagram explaining the film formation model of nc-OS and a diagram showing the pellet. [Figure 60] FIG. [Figure 61] 10A and 10B are diagrams illustrating the force applied to a pellet on a surface to be formed. [Figure 62] 10A and 10B are diagrams illustrating the movement of pellets on a surface to be formed. [Figure 63] A diagram explaining the InGaZnO4 crystal. [Figure 64] A diagram explaining the structure of InGaZnO4 before the atoms collide. [Figure 65] A diagram explaining the structure of InGaZnO4 after the atoms collide. [Figure 66] A diagram explaining the trajectories of atoms after they collide. [Figure 67] Cross-sectional HAADF-STEM images of the CAAC-OS and target. [Figure 68] Electron diffraction pattern of CAAC-OS. [Figure 69] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0028] In this specification, when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, and may be applied to any connection relationship shown in drawings or text. This also includes connections other than those shown in the text.

[0029] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. It has the function to switch between them.

[0030] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0031] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (i.e., there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected across the , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that the

[0032] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0035] In this specification and the like, it is possible to form a transistor using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor. Substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lye. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). These include plastics that can be used for bonding, and flexible synthetic resins such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or polyethylene. Examples of base films include polyester, polyamide, polyvinyl chloride, etc. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, etc., the characteristics, size, We manufacture small-sized transistors with high current capacity and little variation in size or shape. When a circuit is configured using such transistors, the circuit consumes less power. This allows for increased power and higher circuit integration.

[0036] Alternatively, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After completing a semiconductor device in part or in its entirety, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be an inorganic film of, for example, a tungsten film and a silicon oxide film. The laminated structure of the above or a structure in which an organic resin film such as polyimide is formed on a substrate may be used. This can be done.

[0037] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates to which the transistor is transferred. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, and the like. Fan substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate, fabric substrate Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more durable device.

[0038] (Embodiment 1) In this embodiment, a transistor of one embodiment of the present invention will be described with reference to drawings.

[0039] The transistor of one embodiment of the present invention can be formed of silicon (including strained silicon), germanium, silicon, or Germanium, Silicon Carbide, Gallium Arsenide, Aluminum Gallium Arsenide, Indium Phosphorus, gallium nitride, organic semiconductor, or oxide semiconductor is used in the channel formation region. In particular, it is possible to use a charac- ter containing an oxide semiconductor with a band gap larger than that of silicon. It is preferable to form a panel-forming region.

[0040] For example, the oxide semiconductor may contain at least indium (In) or zinc (Zn). It is preferable that the oxide contains In-M-Zn (wherein M is Al, Ti, Ga). a metal such as Ge, Y, Zr, Sn, La, Ce or Hf) It is completed.

[0041] Unless otherwise specified, the following description will be given of a transistor having a channel formation region containing an oxide semiconductor as an example. The transistor will now be described.

[0042] 1A and 1B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 1(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. 1(A) is FIG. 1(A) corresponds to (B). The cross section taken along the dashed line A3-A4 in FIG. 1(A) corresponds to (B). 2(B). In the above drawings, some elements are enlarged for clarity. The dashed line A1-A2 is the channel length direction, and the dashed line A1-A2 is the channel length direction. The direction of the dashed dotted line A3-A4 may be referred to as the channel width direction.

[0043] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). or the source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (drain region or drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is one of the values, the maximum value, and the minimum value in the region where the channel is formed. Or the average value.

[0044] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on state). The region where the gate electrode overlaps with the current-carrying part of the gate, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0045] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in a transistor with a fine, three-dimensional structure, The ratio of the channel region formed on the side of the semiconductor to the channel region formed In this case, the apparent channel width shown in the top view may be larger. The effective channel width where the channel is actually formed is larger than the actual channel width.

[0046] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0047] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The channel width is defined as the "surrounded channel width (SCW)". In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when simply referring to channel width, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. A value can be determined.

[0048] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0049] The transistor 101 includes an insulating layer 120 in contact with a substrate 110 and an oxide layer in contact with the insulating layer 120. a gate insulating film 160 in contact with the oxide semiconductor layer 130; The gate electrode layer 170 in contact with the oxide semiconductor layer 130, the gate insulating film 160, and an insulating layer 175 covering the gate electrode layer 170; an insulating layer 180 in contact with the insulating layer 175; The oxide semiconductor layer 130 and the insulating layer 180 are electrically connected through openings formed in the insulating layer 175 and the insulating layer 180. A source electrode layer 140 and a drain electrode layer 150 are electrically connected to each other, and a In addition, an insulating layer 19 may be formed in contact with the insulating layer 185 as required. 0 (flattening film) or the like may be provided.

[0050] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. The term "electrode layer" can also be used interchangeably with "wiring." can.

[0051] The gate electrode layer 170 is formed of two layers, a conductive layer 171 and a conductive layer 172. Although illustrated, it may be a single layer or a laminate of three or more layers.

[0052] In addition, the source electrode layer 140 is formed of two layers, a conductive layer 141 and a conductive layer 142. Although shown in the figure, the conductive layer 151 may be a single layer or a laminate of three or more layers. The same is true for the drain electrode layer 150 formed at 152.

[0053] When the channel width is reduced, the upper surface of the oxide semiconductor layer 130 is It is preferable that the upper surface is formed to have a curvature. This can improve the coverage of the film to be formed. However, if the channel width is relatively long, As shown in FIG. 2(B), the oxide semiconductor layer 130 may have a flat region on the top. The description regarding the channel width is also applicable to other transistors disclosed in this specification. .

[0054] The transistor according to one embodiment of the present invention includes a gate electrode layer 170, a source electrode layer 140, and a drain electrode layer 150. This is a self-aligned structure in which the inner electrode layer 150 does not have an overlapping region. The parasitic capacitance between the gate electrode layer and the source electrode layer, and between the electrode layers, is extremely small in this structure. Therefore, it is suitable for high-speed operation.

[0055] The oxide semiconductor layer 130 of the transistor 101 has a region 231 (semiconductor layer 130) provided separately. Between region 231 (source region) and region 232 (drain region) and region 231 and region 232 A region 233 (chi) is provided and overlaps with the gate electrode layer 170 via the gate insulating film 160. It has a channel area.

[0056] Here, the regions 231 and 232 are regions that contact the insulating layer 175 as shown in FIG. 1(B). If an insulating material containing hydrogen is used for the insulating layer 175, the region 231 and the region 232 can be made to have a low resistance.

[0057] Specifically, the insulating layer 175 is formed in the regions 231 and 232 by the steps up to the formation of the insulating layer 175. The oxygen vacancies caused by the ion implantation and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232 interact with each other. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, a silicon nitride film or an aluminum nitride film can be used.

[0058] In addition, regions 231 and 232 contain impurities to form oxygen vacancies and increase conductivity. Examples of impurities that form oxygen vacancies in the oxide semiconductor layer include phosphorus. , arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, aluminum of fluorine, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon One or more methods selected from the following can be used as the method of adding the impurity. , plasma processing method, ion implantation method, ion doping method, plasma immersion ion implantation The implantation method can be used.

[0059] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide The conductivity of the semiconductor layer can be increased.

[0060] The method for adding the impurities is preferably a plasma treatment method that can be easily applied to a large area. For example, a pair of electrodes are preferably formed on a substrate on which a transistor is formed so as to be biased. It is placed on one of the electrodes (cathode side), and a high-frequency current is applied between the pair of electrodes in an argon atmosphere under reduced pressure. The treatment is performed by applying a frequency power (such as 13.56 MHz) to generate argon plasma. At this time, a part of the gate electrode layer 170 is sputtered and deposited on the edge of the gate insulating film 160. As a result, the regions 231 and 232 may be short-circuited with the gate electrode layer 170. There is a saying.

[0061] Therefore, when performing the plasma treatment, the gate electrode layer 170 and the gate insulating film 16 The resist mask for forming the pattern of 0 is left on the gate electrode layer 170. It is preferable to carry out plasma treatment.

[0062] By performing plasma treatment with the resist mask remaining on the gate electrode layer 170, the gate Since sputtering of the electrode layer 170 is suppressed, the regions 231 and 232 and the gate electrode layer 170 and can prevent short circuit with the resist and reduce gate leakage current. Since part of the mask is sputtered, for example, when processing with argon plasma, Argon and carbon can be added to regions 231 and 232. As shown above, when carbon is added to an oxide semiconductor layer, oxygen vacancies are formed, and the oxide semiconductor The conductivity of the layer can be made even higher.

[0063] That is, the regions 231 and 232 in the transistor 101 are oxygen deficient. The region 232 has a higher concentration of impurities that form oxygen defects than the region 233. Because hydrogen enters, the regions 231 and 232 have a higher hydrogen concentration than the region 233. By forming a transistor with such a configuration, the source region and the drain region The resistance of the in-region can be reduced, and the on-current of the transistor can be increased. .

[0064] Note that an element that forms oxygen vacancies in the oxide semiconductor layer is used as an impurity (an impurity element). Typical examples of impurity elements are boron, carbon, nitrogen, fluorine, aluminum, Silicon, phosphorus, chlorine, and rare gas elements are examples of rare gas elements. Neon, argon, krypton and xenon.

[0065] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, the oxygen vacancies are Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide semiconductor The conductivity of the oxide semiconductor increases and it becomes a conductor. An oxide semiconductor that has become a conductor is called an oxide conductor. Generally, oxide semiconductors have a large energy gap and are therefore resistant to visible light. On the other hand, oxide conductors are oxide semiconductors that have donor levels near the conduction band. Therefore, the influence of absorption by the donor level is small, and the oxidized It has the same level of transparency as semiconductors.

[0066] Here, the resistance of a film formed of an oxide conductor (hereinafter referred to as an oxide conductor layer) The temperature dependency of the rate will be explained with reference to FIG.

[0067] Here, a sample having an oxide conductor layer was prepared. The oxide conductor layer (OC_SiN) formed by the contact of the conductor layer with the silicon nitride film x ), In a doping device, argon is added to the oxide semiconductor layer and the oxide semiconductor layer is in contact with the silicon nitride film. The oxide conductor layer (OC_Ar doped + SiN x ), or Pla In the plasma processing apparatus, the oxide semiconductor layer is exposed to argon plasma, and the silicon nitride film is The oxide conductive layer formed by contacting with the Ar plasma and SiN x ) The silicon nitride film contains hydrogen.

[0068] Oxide conductor layer (OC_SiN x The method for preparing a sample containing the SiO2 is as follows: After forming a silicon oxynitride film with a thickness of 400 nm by plasma CVD, By exposing the silicon oxynitride film to a magnetic field and adding oxygen ions to the film, oxygen is released by heating. Next, a silicon oxynitride film that releases oxygen when heated was formed. A sputtering target with an atomic ratio of In:Ga:Zn=5:5:6 was used on the film. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering, and then heated at 450°C in nitrogen. After heat treatment in a nitrogen atmosphere, it was heat treated in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, a silicon nitride film with a thickness of 100 nm was formed by plasma CVD. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen at 0°C.

[0069] Oxide conductor layer (OC_Ar doped + SiN x The method for preparing the sample containing A 400 nm thick silicon oxynitride film is formed on a glass substrate using plasma CVD. After that, the silicon oxynitride film is exposed to oxygen plasma to add oxygen ions to the film. Next, a silicon oxynitride film that releases oxygen by heating was formed. On the silicon oxynitride film, a sputtering tantalum with an atomic ratio of In:Ga:Zn=5:5:6 was deposited. A 100 nm thick In-Ga-Zn oxide film was formed by sputtering using a target. After heat treatment in a nitrogen atmosphere at 450°C, the specimen was placed in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, the In-Ga-Zn oxide film was subjected to a heat treatment in a doping device. The voltage is 10 kV and the dose is 5 × 10 14 / cm 2 Add argon to In-G Oxygen vacancies were formed in the α-Zn oxide film. Next, a 100 nm thick film was deposited by plasma CVD. A silicon nitride film was formed. Next, the film was heated at 350°C in a mixed gas atmosphere of nitrogen and oxygen. I understood.

[0070] Oxide conductor layer (OC_Ar plasma + SiN x The preparation method for the sample containing A silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by plasma CVD. After formation, the silicon oxynitride film is exposed to oxygen plasma and released oxygen by heating. Next, a silicon oxynitride film having an atomic ratio of In was formed on the silicon oxynitride film which releases oxygen by heating. :Ga:Zn=5:5:6 sputtering target was used to form a A 100 nm thick In-Ga-Zn oxide film was formed and then heat-treated in a nitrogen atmosphere at 450°C. After that, it was heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. In the device, argon plasma is generated and accelerated argon ions are injected into the In-Ga-Z Next, a 1 mm thick film was prepared by plasma CVD. Next, a silicon nitride film with a thickness of 0.1 nm was formed in a nitrogen and oxygen mixed gas atmosphere at 350°C. It was heat treated in air.

[0071] Next, the resistivity of each sample was measured and the results are shown in Figure 57. Here, the resistivity was measured using a four-terminal The measurement was performed using the van der Pauw method. In Figure 57, the horizontal axis indicates the measurement temperature, and the vertical axis indicates the The resistivity of the oxide conductor layer (OC_SiN x ) measurement results are shown by squares, and Compound conductor layer (OC_Ar plasma+SiN x ) measurement results are shown by triangles, and the oxidation Physical conductor layer (OC_Ar dope+SiN x ) measurement results are indicated by circles.

[0072] Although not shown, the oxide semiconductor layer that is not in contact with the silicon nitride film has a high resistivity. Therefore, the oxide conductor layer has a lower resistivity than the oxide semiconductor layer. It is clear that

[0073] As can be seen from FIG. 57, the oxide conductor layer (OC_Ar doped+SiN x ) and acid Compound conductor layer (OC_Ar plasma+SiN x ) contains oxygen vacancies and hydrogen Typically, the resistivity changes little between 80K and 290K. The resistance change is less than ±20% between 150K and 250K. The mobility is less than ±10%. That is, oxide conductors are degenerate semiconductors, and the conduction band edge and It is estimated that the electric potential of the oxide conductor layer is equal to or almost equal to the Elmi level. By using it as the source and drain regions of a transistor, the oxide conductor layer and the source The contact with the conductive film that functions as the source electrode and drain electrode is an ohmic contact, and the oxide The contact resistance between the conductive layer and the conductive film that functions as the source electrode and the drain electrode can be reduced. In addition, since the resistivity of oxide conductors has low temperature dependency, the oxide conductor layer and the source The fluctuation of the contact resistance with the conductive film that functions as the electrode and drain electrode is small, and the reliability is high. It is possible to fabricate a low-cost transistor.

[0074] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. 3A is a top view of the transistor 102, and the dashed line B1-B The cross sections in the two directions correspond to Fig. 3(B). The cross section is a cross section of the transistor 101 shown in FIGS. 2A and 2B in the channel width direction. In the drawings, some elements may be enlarged, reduced, or omitted for clarity. The dashed dotted line B1-B2 direction is the channel length direction, and the dashed dotted line B3- The B4 direction may be referred to as the channel width direction.

[0075] The transistor 102 includes an insulating layer 120 in contact with the substrate 110 and an oxide layer in contact with the insulating layer 120. a source electrode layer 140 electrically connected to the oxide semiconductor layer 130; a gate insulating film 160 in contact with the oxide semiconductor layer 130; The gate electrode layer 170 in contact with the gate insulating film 160, the oxide semiconductor layer 130, and the gate insulating film 1 60, an insulating layer covering the source electrode layer 140, the drain electrode layer 150 and the gate electrode layer 170; layer 175, an insulating layer 180 in contact with the insulating layer 175, and an insulating layer 180 formed on the above structure. 85. If necessary, an insulating layer 190 (flattening film) may be provided in contact with the insulating layer 185. etc. may be provided.

[0076] In the transistor 102, the source electrode layer 140 and the drain electrode layer 150 are made of oxide. The fact that it is formed directly on the semiconductor layer 130 and the configuration of the source and drain regions The transistor 101 has the same structure as the transistor 101 except for the above.

[0077] The oxide semiconductor layer 130 in the transistor 102 is formed in the region 33 provided separately. 1 and region 332, and region 331 and region 332, and a gate insulating A region 333 overlapping the gate electrode layer 170 via the film 160, a region 331 and a region 333 and a region 335 provided between the region 332 and the region 333. and,

[0078] In the transistor 102, the region 331 has a region in contact with the source electrode layer 140, and The region 332 has a region in contact with the drain electrode layer 150. Therefore, the regions 331 and Region 332 is a metal material used as the source electrode layer 140 and the drain electrode layer 150. As oxygen is absorbed by the oxide, oxygen vacancies occur, causing the oxide to become n-type and have low resistance.

[0079] The region 334 and the region 335 are connected to the source electrode layer 140 and the drain electrode layer 150. The insulating layer 175 is formed in a region that is not in contact with the insulating layer 175 containing hydrogen, but is in contact with the insulating layer 175 containing hydrogen. The oxygen vacancies occurring in the regions 334 and 335 through the process up to this point and the insulating layer 175 forming the region The hydrogen atoms in regions 334 and 335 interact with the hydrogen atoms diffusing into regions 334 and 335. 35 is a low resistance n-type.

[0080] Therefore, regions 331 and 334 are source regions, regions 332 and 335 are It can act as a drain region.

[0081] It should be noted that the regions 231 and 232 of the transistor 101 are different from the regions 334 and 335. As with the region 232, impurities may be added to increase oxygen vacancies.

[0082] At this time, when the impurity is added by plasma treatment, the gate electrode layer 170 A part of the gate insulating film 160 may be sputtered and deposited on the edge of the gate insulating film 160, which may cause damage to the transistor. As with the gate electrode layer 101, a resist mask is left on the gate electrode layer 170, and plasma processing is performed. It is preferable to carry out the following.

[0083] By performing plasma processing in this state, sputtering of the gate electrode layer 170 is suppressed. The regions 334 and 335 are prevented from shorting with the gate electrode layer 170 and the gate leakage current is reduced. In addition, since a part of the resist mask is sputtered, for example, When the treatment is performed with argon plasma, argon and As described above, when carbon is added to the oxide semiconductor layer, Since oxygen vacancies are formed, the conductivity of the oxide semiconductor layer can be further increased.

[0084] That is, the regions 334 and 335 in the transistor 102 form oxygen vacancies. The region 331, the region 332, and the region 333 have a higher impurity concentration for the purpose of In addition, since hydrogen enters the oxygen vacancies, the regions 334 and 335 have a hydrogen concentration has a portion higher than the region 333. A transistor is formed by such a configuration. This allows the source and drain regions to have lower resistance, The on-current can be increased.

[0085] The width of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. In the case of a thickness of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, it is possible to adopt a configuration in which the above-described resistance reduction is not performed.

[0086] As shown in FIGS. 4A and 4B, the transistor of one embodiment of the present invention is an oxide semiconductor. A conductive layer 172 may be provided between the dielectric layer 130 and the substrate 110. By using it as a gate electrode layer (back gate), it is possible to further increase the on-current and The voltage can be controlled. In the cross section in the channel length direction shown in FIG. The width of the conductive layer 172 is reduced so that it does not overlap with the source electrode layer 140, the drain electrode layer 150, etc. Furthermore, the width of the conductive layer 172 may be set to be smaller than the width of the gate electrode layer 170. It may be shortened.

[0087] To increase the on-current, for example, the gate electrode layer 170 and the conductive layer 172 are set to the same potential, It can be driven as a double gate transistor. In this case, a constant potential different from that of the gate electrode layer 170 may be supplied to the conductive layer 172. To make the layer 170 and the conductive layer 172 have the same potential, for example, as shown in FIG. The electrode layer 170 and the conductive layer 172 may be electrically connected via a contact hole. Although FIGS. 4A, 4B, and 4C are examples of modified examples of the transistor 101, The configuration can also be applied to the transistor 102 shown in FIG.

[0088] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 5A is a top view of the transistor 103, and the dashed line C1-C The cross section in the two directions corresponds to Fig. 5(B). The cross section of FIG. 6(A) or FIG. 6(B) corresponds to FIG. 6(A) or FIG. 6(B). Some elements are shown enlarged, reduced, or omitted. is sometimes referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 is sometimes referred to as the channel width direction.

[0089] In the transistor 103 shown in FIGS. 5A and 5B, the oxide semiconductor layer 130 is The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are formed in this order from the side. The configuration of the transistor 101 is the same as that of the transistor 101.

[0090] For example, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c each have a composition Different oxide semiconductor layers or the like can be used.

[0091] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. 7A is a top view of the transistor 104, and the dashed line D1-D1 in FIG. The cross section in the two directions corresponds to Fig. 7(B). The cross section of FIG. 8(A) or FIG. 8(B) corresponds to FIG. 8(A) or FIG. 8(B). Some elements are enlarged, reduced, or omitted. is sometimes referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 is sometimes referred to as the channel width direction.

[0092] The transistor 104 shown in FIGS. 7A and 7B has an oxide semiconductor layer 130b. The other configurations are the same as those of the transistor 103, except that the transistor 103 is covered with a dielectric layer 130c. do.

[0093] The transistor of one embodiment of the present invention may have the structure illustrated in FIGS. 9A is a top view of the transistor 105, and the dashed line E1-E The cross section in the two directions corresponds to Fig. 9(B). The cross section is the same as the cross section of the transistor 103 in the channel width direction shown in FIG. In the drawings, some elements may be enlarged, reduced, or omitted for clarity. The dashed line E1-E2 direction is the channel length direction, and the dashed line E3-E4 direction is the channel length direction. This is sometimes referred to as the width direction of the panel.

[0094] In the transistor 105 shown in FIGS. 9A and 9B, the oxide semiconductor layer 130 is The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are formed in this order from the side. The structure of the oxide semiconductor layer 130 of the transistor 105 is the same as that of the transistor 102. In the transistor 104, the oxide semiconductor layer 130b is covered with the oxide semiconductor layer 130c. It may also be configured so that

[0095] Further, the transistor of one embodiment of the present invention has the following characteristics as shown in FIGS. A conductive layer 172 may be provided between the oxide semiconductor layer 130 and the substrate 110. By using this layer as a second gate electrode layer (back gate), it is possible to further increase the on-current and In addition, the threshold voltage can be controlled by the channel length direction shown in FIG. In the cross section, the width of the conductive layer 172 is shortened to 0. Furthermore, the width of the conductive layer 172 may be set to be equal to or smaller than the width of the gate electrode layer 170. 10(A), (B), and (C) show the width of the transistor 10. 4, this embodiment is similar to the transistor 103 and the transistor 105. It can also be applied to

[0096] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 11A is a top view of the transistor 106, and the dashed line F in FIG. The cross section in the 1-F2 direction corresponds to Fig. 11(B). The cross section in the -F4 direction corresponds to Fig. 12(A) or Fig. 12(B). For clarity, some elements are shown enlarged, reduced, or omitted. The F1-F2 direction is called the channel length direction, and the dashed line F3-F4 direction is called the channel width direction. There are cases where this happens.

[0097] The transistor 106 shown in FIGS. 11A and 11B has an oxide semiconductor layer 130 and an insulating layer 12. From the side of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The other configurations are the same as those of the transistor 101, except that they are formed in this order.

[0098] For example, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 13 Oxide semiconductor layers having different compositions can be used for 0c.

[0099] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 13A is a top view of the transistor 107. The cross section in the 1-G2 direction corresponds to FIG. 13(B). The cross section in the -G4 direction corresponds to Fig. 14(A) or Fig. 14(B). For clarity, some elements are shown enlarged, reduced, or omitted. The G1-G2 direction is called the channel length direction, and the G3-G4 direction is called the channel width direction. There are cases where this happens.

[0100] The transistor 107 shown in FIGS. 13A and 13B includes an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. Except for the structure in which the compound semiconductor layer 130b is covered with the oxide semiconductor layer 130c, the other structures are the same. is the same as transistor 106.

[0101] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 15A is a top view of the transistor 108, and the dashed line H The cross section in the 1-H2 direction corresponds to FIG. 15(B). The cross section along the line H3-H4 corresponds to FIG. 16(A) or FIG. 16(B). In the drawings, some elements may be enlarged, reduced, or omitted for clarity. The direction of the dashed dotted line H1-H2 is called the channel length direction, and the direction of the dashed dotted line H3-H4 is called the channel width direction. It may be referred to as.

[0102] The transistor 108 shown in FIGS. 15A and 15B includes an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. The compound semiconductor layer 130b is partially covered with the oxide semiconductor layer 130c. The configuration of the transistor 106 is the same as that of the transistor 106.

[0103] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 17A is a top view of the transistor 109. The cross section in the direction of 1-I2 corresponds to FIG. 17(B). The cross section in the -I4 direction is the same as the cross section in the channel width direction of the transistor 108 shown in FIG. In the drawings, some elements are enlarged, reduced, or omitted for clarity. The dashed line I1-I2 direction is the channel length direction, and the dashed line I3-I The four directions are sometimes referred to as channel width directions.

[0104] The transistor 109 shown in FIGS. 17A and 17B has an oxide semiconductor layer 130 and an insulating layer 12. From the side of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The other configurations are the same as the transistor 102 except that the transistors are formed in this order. The oxide semiconductor layer 130 of the transistor 109 is As shown in the figure, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, or a part of them, are oxide semiconductors. It may be configured to be covered with a conductor layer 130c.

[0105] Further, as shown in FIGS. 18A, 18B, and 18C, a transistor of one embodiment of the present invention has the following characteristics: A conductive layer 172 may be provided between the oxide semiconductor layer 130 and the substrate 110. By using this layer as a second gate electrode layer (back gate), it is possible to further increase the on-current and In addition, the threshold voltage can be controlled by the channel length direction shown in FIG. In the cross section, the width of the conductive layer 172 is shortened to 0. Furthermore, the width of the conductive layer 172 may be set to be equal to or smaller than the width of the gate electrode layer 170. 18(A), (B), and (C) show the width of the transistor 10. 7, this embodiment is similar to the transistor 106, the transistor 108, and The same can be applied to the transistor 109.

[0106] In the transistors of one embodiment of the present invention (transistors 101 to 109), In either configuration, the gate electrode layer 170 is formed on the oxide semiconductor via the gate insulating film 160. The layer 130 is electrically surrounded in the channel width direction, thereby increasing the on-current. The transistor structure is a surrounded channel (s-channel) structure. It is called construction.

[0107] Also, a transistor having the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, etc. and oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c. In a transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By flowing current through the conductor layer 130b, the device is less susceptible to the influence of interface scattering and a high on-current can be obtained. It should be noted that increasing the thickness of the oxide semiconductor layer 130b can improve the on-state current. For example, when the thickness of the oxide semiconductor layer 130b is set to 100 nm to 200 nm, Good too.

[0108] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0109] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0110] (Embodiment 2) In this embodiment, components of the transistor shown in Embodiment 1 will be described in detail. do.

[0111] The substrate 110 is not limited to being a simple support material, but also includes a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 170 and the source electrode layer 14 of the transistor 0, and one or more of the drain electrode layers 150 are electrically connected to the other devices described above. It may be possible.

[0112] For example, the substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal crystalline semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Silicon on Insulator) A silicon-on-insulator (N-on-insulator) substrate or the like can be used.

[0113] The insulating layer 120 serves to prevent the diffusion of impurities from the substrate 110 and also serves to prevent the oxide semiconductor from diffusing. The insulating layer 120 can supply oxygen to the conductor layer 130. It is preferable that the insulating film contains oxygen in an amount greater than the stoichiometric composition. For example, it is more preferable that the surface temperature of the film is 100°C or higher and 700°C or lower, preferably 1 The TDS method, which is performed by heat treatment at temperatures between 00°C and 500°C, converts oxygen to oxygen atoms. The amount of emission is 1.0×10 19 atoms / cm 3 The membrane is as above. If the substrate 110 is a substrate on which other devices are formed, the insulating layer 120 may be an interlayer insulating film. In this case, CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a flattening process using a method such as mechanical polishing. .

[0114] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. It is also possible.

[0115] In this embodiment, the transistors 106, 107, and 10 The oxide semiconductor layer 130 included in the transistors 8 and 109 is the oxide semiconductor layer 13 0a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are formed in this order from the insulating layer 120 side. The details will be mainly explained for the case of a stacked three-layer structure.

[0116] Note that, like the transistor 101 and the transistor 102, the oxide semiconductor layer 130 is In the case of a layer, a layer corresponding to the oxide semiconductor layer 130b may be used.

[0117] Also, transistors 103, 104, and 105 are oxidized. When the oxide semiconductor layer 130 is a two-layer structure, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are It is sufficient to use a laminate in which layers corresponding to the conductor layer 130c are stacked in order from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer 130c can be interchanged. Cut.

[0118] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is stacked on the oxide semiconductor layer 130 of the three-layer structure, or the three-layer structure Another oxide semiconductor layer may be inserted at any of the interfaces.

[0119] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (ion The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the

[0120] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be formed of a thin oxide semiconductor.

[0121] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 0, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. It is done.

[0122] The oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface states may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0123] The oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film 160 are in contact with each other, Compared to the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, the carrier Therefore, by providing the oxide semiconductor layer 130c, scattering of electrons is less likely to occur. This can increase the field effect mobility of the transistor.

[0124] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may contain, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf as an element having a higher conductivity than the oxide semiconductor layer 130b. Specifically, the atomic ratio is preferably 1.5 times or more. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from occurring in the oxide semiconductor layer. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0125] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least indium (In) or nickel. It is preferable that lead (Zn) is contained. Alternatively, it is preferable that both In and Zn are contained. In addition, in order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, Both preferably include a stabilizer.

[0126] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0127] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0128] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0129] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0130] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 30a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c was In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0131] When Zn and O are removed from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0132] The oxide semiconductor layer 130b is formed by multiplying the oxide semiconductor layer 130a and the oxide semiconductor layer 130b by the same amount. It is preferable to have a higher indium content than the c content. In oxide semiconductors, the s orbital of heavy metals is mainly The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the oxide semiconductor layer 130b has a higher mobility than the oxide semiconductor layer 130b. By using oxides with a high content of sodium, transistors with high field-effect mobility can be realized. It is possible.

[0133] The thickness of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is 3 nm or more and 100 nm or less. The thickness of the oxide semiconductor layer 130b is preferably 3 nm or more and 50 nm or less. is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 10 nm or more and 100 nm or less. It is preferable that the thickness of the insulating layer 130 is thicker than the oxide semiconductor layer 130a and the oxide semiconductor layer 130c.

[0134] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the capacitance of the oxide semiconductor layer is Rear density is 1×10 19 / cm 3 preferably less than 1 x 10 15 / cm 3 Not yet More preferably, it is less than 1×10 13 / cm 3 most preferably less than 1×10 8 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than that.

[0135] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in the layer 130c and at the respective interfaces.

[0136] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. In the analysis of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 The hydrogen concentration is, for example, For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. , 2 × 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Below or less, more preferably 1 x 10 19 atoms / cm 3 Less than 5 × 10, more preferably 1 8 atoms / cm 3 The nitrogen concentration is, for example, In the thickness or in a region of the oxide semiconductor layer, 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0137] In addition, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the oxide The crystallinity of the oxide semiconductor layer may be reduced. For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, or , in a region of the oxide semiconductor layer, the carbon concentration is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than the above.

[0138] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or about 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0139] Note that, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating film, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. Therefore, it is preferable that the region of the oxide semiconductor layer that becomes the channel is separated from the gate insulating film. .

[0140] Therefore, the oxide semiconductor layer 130 is divided into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible to form a

[0141] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers with different compositions. It can also be said that the laminate is physically continuous, and in the drawings of this specification, The respective interfaces are represented by dotted lines.

[0142] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) The layers are fabricated so that a U-shaped well is formed. There are no impurities that form defect levels such as trap centers or recombination centers at the interface. If impurities are mixed between the stacked oxide semiconductor layers, When the energy band is not uniform, the continuity of the energy band is lost and carriers are trapped or recombined at the interface. It will disappear when combined.

[0143] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are made of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), and the oxide semiconductor layer 130b has In:Ga:Zn=1:1:1, 2: In-Ga-Zn oxide with atomic ratios of 1:3, 5:5:6, or 3:1:2 Note that the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and The atomic ratios of the oxide semiconductor layer 130c and the oxide semiconductor layer 130d are respectively determined by adding a plasma of the above atomic ratios as an error. Includes a 20% fluctuation.

[0144] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 becomes a well, and the oxide In the transistor using the semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. The oxide semiconductor layer 130 has a conduction band minimum that changes continuously. Therefore, it can also be called a U-shaped well. can also be called a buried channel.

[0145] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a film such as a silicon oxide film. Trap levels due to impurities or defects can be formed near the interface with the insulating film. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c allows the oxide semiconductor layer 13 This can keep 0b away from the trap level.

[0146] However, the energy of the conduction band minimum of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the bottom of the conduction band of the oxide semiconductor layer 130b and the energy of the bottom of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. The electrons that become the charge of the electron trap are captured in the trap level, and the threshold voltage of the transistor shifts in the positive direction.

[0147] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor layer 130 a and the oxide semiconductor layer 130c, and the energy of the conduction band minimum of the oxide semiconductor layer 130b It is necessary to provide a certain difference between the energy of the conduction band minimum and that of the The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0148] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, it is possible to form a transistor. In addition, the c-axis oriented crystal is resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0149] The gate insulating film 160 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more kinds of tantalum oxide can be used. The gate insulating film 160 may be a laminate of the above materials. , zirconium (Zr), etc. may be contained as impurities.

[0150] Next, an example of the stacked structure of the gate insulating film 160 will be described. The gate insulating film 160 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0151] Hafnium oxide and aluminum oxide are relatively The dielectric constant is high. Therefore, the physical film thickness can be made larger than the equivalent oxide film thickness. Even when the thickness of the valence oxide film is set to 10 nm or less or 5 nm or less, leakage due to tunnel current is That is, a transistor with a small off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure can be used in combination with hafnium oxide having an amorphous structure. Therefore, in order to make a transistor with a small off-state current, For this purpose, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal system include monoclinic and cubic crystal systems. However, one embodiment of the present invention is not limited to these. I can't.

[0152] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed close to the channel region of a transistor, the interface states This may cause deterioration of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating film 160, or may be an oxide semiconductor. The film may be a film included in the conductive film. That is, the film having a buffer function may be silicon oxide. , silicon oxynitride, oxide semiconductor, or the like can be used. The film may contain, for example, a semiconductor having a larger energy gap than the semiconductor that will be the channel region. Alternatively, an insulator is used. Alternatively, the film having a buffer function may be, for example, a film that serves as a channel region. Use a semiconductor or insulator that has a smaller electron affinity than the semiconductor that is used. The film to be formed may contain, for example, a semiconductor having a higher ionization energy than the semiconductor that will be the channel region. Conductors or insulators are used.

[0153] On the other hand, the interface states (trap By trapping charge in the charge center, the threshold voltage of the transistor can be controlled. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, a film with a buffer function may be made of hafnium oxide with a larger ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0154] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges at the interface state in the oxide insulating film 160, Electrons can be moved toward the gate electrode layer 170. For example, under a temperature of 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower, The potential of the gate electrode layer 170 is set higher than the potential of the source electrode and the drain electrode for one second or more. Typically, it is sufficient to maintain the temperature for one minute or more.

[0155] In this way, a transistor in which a desired number of electrons are captured in the interface state of the gate insulating film 160 or the like is formed. The threshold voltage of the gate electrode layer 170 is shifted to the positive side. By adjusting the time for capturing electrons, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If the charges can be trapped, the charges can be trapped within the gate insulating film 160. A laminated film having a similar structure may be used for other insulating layers.

[0156] The gate electrode layer 170 may include, for example, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, M Conductive films of O, Ru, Ag, Mn, Nd, Sc, Ta, W, etc. can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. The conductive layer may be a laminate of a plurality of materials selected from alloys of the materials and conductive nitrides of the above materials. Typically, tungsten, tungsten and titanium nitride lamination, tungsten and titanium nitride lamination, Tantalum lamination can be used. Also, low-resistivity Cu or Cu-Mn alloy can be used. Alternatively, a laminate of the above material and an alloy of Cu or Cu-Mn may be used. The gate electrode layer 170 is formed by using tantalum nitride for the conductive layer 171 and tungsten for the conductive layer 172. Form.

[0157] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. As described above, by using an insulating film containing hydrogen as the insulating layer 175, oxidation The nitride insulating film can also be used as a blocking agent for moisture, etc. It also functions as a blocking film, and can improve the reliability of the transistor.

[0158] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The oxide insulating layer may be a stack of the above materials.

[0159] Here, the insulating layer 180 has a larger amount of oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that the oxygen released from the insulating layer 180 passes through the gate insulating film 160 and is converted into an oxide. Since the ions can be diffused into the channel forming region of the semiconductor layer 130, Therefore, oxygen can be supplied to the oxygen vacancies formed in the transition region. The electrical characteristics of the sintered body can be obtained.

[0160] The source electrode layer 140 and the drain electrode layer 150 may be made of, for example, Al, Cr, Cu, or Ta. , Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of these metal materials A single layer or a laminate of materials can be used. Typically, Ti, which is particularly susceptible to bonding with oxygen, is used. It is recommended to use W, which has a high melting point, because the temperature in the subsequent process can be relatively high. It is also preferable to use a laminate of low-resistance Cu or Cu-Mn alloy and the above materials. In this embodiment, W is used for the conductive layer 141 and the conductive layer 151, and W is used for the conductive layer 142 and the conductive layer 153. The source electrode layer 140 and the drain electrode layer 150 are formed using Cu for the electrode layer 152 .

[0161] The above material has a property of extracting oxygen from the oxide semiconductor film. In a part of the oxide semiconductor layer, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The hydrogen contained in the film in small amounts enters the oxygen vacancies, causing the region to become significantly n-type. Therefore, the n-type region acts as the source or drain of the transistor. It can be made to work.

[0162] The source electrode layer 140, the drain electrode layer 150, and the insulating layer 180 are provided with insulating layers as protective films. It is preferable to form the insulating layer 185. The insulating layer 185 is preferably made of an insulating material similar to the insulating layer 175. An aluminum oxide film can be used as the insulating layer 185. Aluminum oxide films are highly resistant to both impurities such as hydrogen and moisture, and oxygen. Therefore, the aluminum oxide film has a high blocking effect that prevents light from passing through the film. Hydrogen and moisture, which are factors that affect the electrical characteristics of transistors during and after the manufacturing process, and the like into the oxide semiconductor layer 130. Preventing release of oxygen, which is a component material, from the oxide semiconductor layer and eliminating the need for oxygen from the insulating layer 120 It is suitable for use as a protective film that has the effect of preventing the emission of aluminum oxide. Oxygen contained in the silicon film can be diffused into the oxide semiconductor layer.

[0163] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the value is reduced, the on-state current decreases.

[0164] In the transistors 103 to 109 of one embodiment of the present invention, a channel is formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and reduces the on-state voltage of the transistor. The flow can be increased.

[0165] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is Since the gate electrode layer 170 is formed so as to electrically surround the panel in the width direction, the oxide In addition to the gate electric field acting in the vertical direction, the semiconductor layer 130 is also subjected to a gate electric field acting in the lateral direction. That is, the gate electric field is applied to the entire channel forming layer. This increases the effective channel width, further increasing the on-current.

[0166] In addition, in the transistors 106 to 109 of one embodiment of the present invention, the channel is formed The oxide semiconductor layer 130b is formed on the oxide semiconductor layer 130a. The oxide semiconductor layer 130b is positioned as the middle layer in the three-layer structure. This also has the effect of eliminating the influence of impurities from above and below. In addition to the improvement of the on-state current of the transistor mentioned above, the threshold voltage has been stabilized and the S value (sub- Therefore, Icut (gate voltage VG This reduces the current when the voltage is 0V, thereby reducing power consumption. The threshold voltage of the transistor is stabilized, which improves the long-term reliability of the semiconductor device. Furthermore, the transistor of one embodiment of the present invention can suppress deterioration of electrical characteristics due to miniaturization. Since the above-mentioned method can suppress the above-mentioned problem, it can be said that the method is suitable for forming a highly integrated semiconductor device.

[0167] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0168] (Embodiment 3) In this embodiment, an oxide semiconductor that can be used for a transistor according to one embodiment of the present invention will be described. The conductive film will now be described.

[0169] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0170] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0171] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0172] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0173] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, nc-OS, etc.

[0174] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. It can also be described as a structure that has order but does not have long-range order.

[0175] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is converted into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a device that can achieve periodicity in a microscopic area. Although it has a structure, it has voids and is an unstable structure. Therefore, in terms of physical properties, it is an amorphous oxide. It can be said that it is close to a compound semiconductor.

[0176] <caac-os> First, let me explain about CAAC-OS.

[0177] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0178] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0179] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0180] FIG. 19(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 19(A). From Figure 19(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0181] As shown in Figure 19(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 19(B) and Figure 19(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The CA nanocrystals can also be called nanocrystals (nc). AC-OS, CANC (C-Axis Aligned nanocrystals) The oxide semiconductor may also be referred to as an oxide semiconductor having the above structure.

[0182] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 19(D)). The inclination between the pellets observed in FIG. 19(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 19(D).

[0183] In addition, Fig. 20(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 20(A). Enlarged Cs-corrected high-resolution TEM images are shown in Fig. 20(B), Fig. 20(C), and Fig. 20(D), respectively. 20(D). From Fig. 20(B), Fig. 20(C) and Fig. 20(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0184] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 21(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0185] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0186] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 21(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in FIG. 21(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0187] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 68(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in Figure 68(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 68(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 68(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0188] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so we take the opposite view. CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0189] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0190] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0191] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is set to 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly purified intrinsic or substantially highly purified oxide semiconductor. CAAC-OS is called an intrinsic oxide semiconductor. It has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0192] <nc-os> Next, we will explain nc-OS.

[0193] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor with a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are It may not be possible to clearly identify the nanocrystals. Therefore, the crystalline part of nc-OS is referred to as the pellet below. There may be cases where this happens.

[0194] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. For example, for nc-OS, there are cases where it is difficult to distinguish between X particles with a diameter larger than that of the pellet. When using X-rays, peaks indicating crystal planes are not detected in the out-of-plane analysis. In addition, for nc-OS, a probe diameter larger than the pellet (for example, 50n When electron diffraction is performed using an electron beam (over 1000 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than the pellet. When nanobeam electron diffraction is performed using an electron beam with a diameter of n, spots are observed. When nanobeam electron diffraction is performed on c-OS, a circular (ring-shaped) bright spot appears. In some cases, a ring-shaped area is observed. In addition, multiple spots are observed within the ring-shaped area. There are cases where this happens.

[0195] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0196] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0197] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0198] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0199] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0200] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0201] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0202] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0203] Figure 69 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of eOS grows in size according to the cumulative amount of electron irradiation. As shown in Figure 69 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was sized at 4.2 × 10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the crystals grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 69, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. You will realize something.

[0204] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0205] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0206] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0207] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0208] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0209] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0210] (Fourth embodiment) In this embodiment, a display device according to one embodiment of the present invention will be described with reference to drawings.

[0211] In this specification, the term "display device" refers to an image display device or a light source (such as a lighting device). Also refers to connectors such as FPC and TCP (Tape Carrier) The module has a printed wiring board at the end of the TCP. or a module in which the driver circuit is directly mounted on the display element using the COG method. All the rules are included in the display device.

[0212] FIG. 22 is a top view of a display device 500 according to one embodiment of the present invention. For clarity, some elements may be enlarged, reduced, transparent, or omitted.

[0213] The display device 500 includes a pixel portion 502 provided on a substrate 501 and a driving circuit for driving the pixel portion. The pixel portion 502, the circuit portion 504 and the circuit portion 505 for the ... A sealing material 512 is arranged to surround the substrate 501, and a substrate 502 is arranged to face the substrate 501. The circuit portion 504 includes, for example, a signal line driver circuit (source driver circuit). The circuit section 505 has, for example, a scanning line driving circuit (gate driver). It is possible.

[0214] The substrate 501 and the substrate 507 are bonded together by a sealant 512. Although not shown, a display element is provided between the substrate 501 and the substrate 507. The display element 502, the circuit portion 504, the circuit portion 505, and the display element are formed by a substrate 501 and a sealing material 51. 2 and is sealed by a substrate 507.

[0215] In addition, the display device 500 has a region surrounded by a sealing material 512 on the substrate 501. In different regions, a pixel section 502, a circuit section 504, and an F electrically connected to a circuit section 505 are provided. PC terminal part 508 (FPC: Flexible printed circuit) is installed. It can be done.

[0216] In addition, an FPC 516 is connected to the FPC terminal portion 508, and the pixel portion Various signals are supplied to the pixel section 502, the circuit section 504, and the circuit section 505. 2, the circuit section 504, the circuit section 505, and the FPC terminal section 508 are each provided with a signal line 510. Various signals supplied by the FPC 516 are transmitted via the signal line 510. The signal is applied to a pixel section 502 , a circuit section 504 and a circuit section 505 .

[0217] In addition, in FIG. 22, a configuration in which a circuit for driving the pixel portion 502 is arranged in two regions is exemplified. However, the configuration of the circuit is not limited to this. For example, the circuit may be integrated into one area. The circuit may be divided into three or more parts. Only one of the circuit portion 504 and the circuit portion 505 is formed on the substrate 501, and the other circuit is externally formed. It may also be attached.

[0218] The circuit for driving the pixel portion 502 is the same as the transistor included in the pixel portion 502. Alternatively, the substrate 501 may be formed on a COG (Chip On Glass) substrate. s) or the like, an IC chip may be mounted. Also, a configuration in which TCP or the like is connected may be used. may be.

[0219] The pixel portion 502, the circuit portion 504, and the circuit portion 505 of the display device 500 are The panel formation region has a plurality of transistors formed using an oxide semiconductor layer.

[0220] A transistor using an oxide semiconductor layer has high mobility, so the area occupied by the transistor can be reduced. This can reduce the size of the transistor, thereby improving the aperture ratio. The circuit portion 504 and the circuit portion 505 can also be formed on the same substrate as the pixel portion 502 . In addition, the off-state current of the transistor is extremely small, and the retention time of an image signal or the like can be extended. This allows the frame frequency to be lowered, reducing the power consumption of the display device. It can be done.

[0221] The oxide semiconductor layer preferably has crystals oriented in the c-axis direction. When an oxide semiconductor layer having such crystals is used in a channel formation region of a display device, When the device 500 is bent, cracks or the like are less likely to occur in the oxide semiconductor layer, and therefore reliability is improved. It can be improved.

[0222] Therefore, by using a transistor including an oxide semiconductor layer, This allows for the formation of a display device that is superior to that using silicon or polycrystalline silicon layers.

[0223] The display device 500 typically uses a liquid crystal element or a light-emitting element. can be done.

[0224] Next, a liquid crystal display device 500a will be described. 23 is a cross-sectional view taken along the dashed dotted line J1-J2 shown in FIG. 22 when the sensor is used.

[0225] The liquid crystal display device 500a includes a substrate 501, a first element layer, a second element layer, and a substrate 507. are stacked in the above order.

[0226] In FIG. 23, the first element layer includes transistors 550 and 552, a planarization insulating film 570, and , a connection electrode 560, a conductive film 572, and the like. an insulating film 534, a coloring layer 536 (color filter), and a light-shielding layer 538 (black matte). In the first and second element layers, the above elements are It may not include all of the above. It may also include elements other than those listed above.

[0227] Here, the first element layer and the second element layer are sealed by a liquid crystal layer 576 and a sealant 512. This forms a liquid crystal element 575 .

[0228] The liquid crystal display device 500a includes a wiring section 511, a pixel section 502, and a first circuit section 50 4 and an FPC terminal portion 508. The wiring portion 511 includes a signal line 510. It has.

[0229] In the liquid crystal display device 500a, a transistor 550 is provided in the pixel portion 502, and a circuit portion 3 04 illustrates a configuration in which a transistor 552 is provided.

[0230] In FIG. 23, the configuration of the transistor 550 and the transistor 552 is an example. The transistor 550 and the transistor 552 may be appropriately sized (channel The length and width of the channel, or the number of channels, can be changed. Although the circuit section 505 is not shown, it can have the same configuration as the circuit section 504 .

[0231] The signal line 510 of the wiring portion 511 is connected to the source electrode layer of the transistor 550 and The insulating layer can be formed in the step of forming the drain electrode layer.

[0232] The FPC terminal portion 508 includes a connection electrode 560, an anisotropic conductive film 580, and an FPC 516. The connection electrode 560 is connected to the source electrode layer and the drain electrode layer of the transistor 550. The connection electrode 560 can be formed in the process of forming the layer. The terminals are electrically connected to the corresponding terminals via the anisotropic conductive film 580.

[0233] In addition, a signal connected to a transistor in a pixel portion and a transistor used in a driver circuit portion It is preferable to use wiring containing copper as the wire. By using wiring containing copper, This can reduce signal delays and the like caused by wiring resistance.

[0234] 23, a planarizing insulating film is formed on the transistor 550 and the transistor 552. 570 is provided.

[0235] The planarization insulating film 570 may be made of a polyimide resin, an acrylic resin, a polyimide amide resin, Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin By laminating multiple insulating films made of these materials, A planarization insulating film 570 may be formed. Alternatively, a structure in which the planarization insulating film 570 is not provided may be formed as follows. Good too.

[0236] In addition, one of the source electrode layer and the drain electrode layer of the transistor 550 has a conductive The conductive film 572 is formed on the planarization insulating film 570. The conductive film 572 functions as an electrode, that is, one of the electrodes of the liquid crystal element. In this case, it is preferable to use a light-transmitting conductive film. It is preferable to use a material containing one selected from the group consisting of In, zinc (Zn), and tin (Sn).

[0237] The liquid crystal element 575 includes a conductive film 572, a conductive film 574, and a liquid crystal layer 576. 574 is provided on the substrate 507 side and functions as a counter electrode. The display device 500a is configured such that the liquid crystal layer 5 By changing the orientation of 76, light transmission or non-transmission can be controlled, and images can be displayed. can.

[0238] Although not shown in FIG. 23, the conductive films 572 and 574 are provided on the side in contact with the liquid crystal layer 576. In addition, a polarizing member, a phase difference member, an anti-reflection member, and the like may be provided with an alignment film. Optical members (optical substrates) such as stoppers may be provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0239] A spacer 578 is provided between the substrate 501 and the substrate 507. are columnar spacers obtained by selectively etching the insulating film, and The spacer 578 is provided to control the film thickness (cell gap) of the film 6. A spherical spacer may also be used.

[0240] The liquid crystal material constituting the liquid crystal layer 576 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, or a high molecular weight liquid crystal. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can be in a cholesteric phase, smectic phase, cubic phase, or chromatic phase depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0241] When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic so alignment treatment is not required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. This prevents electrostatic damage caused by electrostatic discharge, and prevents defects and damage to the liquid crystal display device during the manufacturing process. The loss can be reduced.

[0242] When a liquid crystal element is used as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmetry ric aligned Micro-cell) mode, OCB (Optical C compensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0243] Furthermore, normally black type liquid crystal display devices, for example, transparent liquid crystal display devices using a vertical alignment (VA) mode, There are several types of vertical alignment modes, for example: For example, the MVA (Multi-Domain Vertical Alignment) model mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0244] The display method in the pixel unit 502 may be a progressive method, an interlace method, or the like. In addition, the color elements controlled by pixels when displaying colors are RGB. (R represents red, G represents green, and B represents blue) For example, the R pixel and the G pixel It may be composed of four pixels: a pixel of B and a pixel of W (white). As shown above, two colors of RGB compose one color element, and two different colors are selected depending on the color element. Or you can add one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. It can also be applied to a display device.

[0245] Next, an EL display device 500b using light-emitting elements will be described. 22 when a light emitting element is used in 00. Note that explanations that overlap with those of the liquid crystal display device 500a described above will be omitted.

[0246] The EL display device 500b includes a substrate 501, a first element layer 610, and a second element layer 611. , and substrate 507 are stacked in the above order.

[0247] In FIG. 24, the first element layer 610 includes transistors 550 and 552 and a planarization insulating film 5 70, a connection electrode 560, a light emitting element 680, an insulating film 530, a signal line 510, and a connection The second element layer 611 includes an insulating film 534, a coloring layer 536, and an electrode 560. The first element layer 610 and the second element layer 611 are covered with a sealing layer 538. 632 and the sealing material 512. The first element layer 610 and the second element layer 612 are sealed. The element layer 611 may not include some of the above elements. It may also contain elements of.

[0248] The light-emitting element 680 includes a conductive film 644, an EL layer 646, and a conductive film 648. The display device 500b displays an image by the EL layer 646 of the light emitting element 680 emitting light. can be displayed.

[0249] The insulating film 530 is provided on the conductive film 644 on the planarization insulating film 570. The conductive film 644 is provided with a layer having a high reflectivity with respect to light emitted from the EL layer. A conductive film having high light-transmitting properties to light emitted from the EL layer is used as the conductive film 648. As a result, the light emitting element 680 can have a top emission structure. A conductive film having a high light-transmitting property to the light is used for the conductive film 4, and a conductive film having a high reflectance to the light is used for the conductive film 648. By using a highly conductive film, the light emitting element 680 can have a bottom emission structure. In addition, both the conductive film 644 and the conductive film 648 are formed of a conductive film that has high light-transmitting properties. By using this, a dual emission structure can be achieved.

[0250] In addition, a colored layer 536 is provided at a position overlapping the light-emitting element 680, and a colored layer 536 is provided at a position overlapping the insulating film 530. A light-shielding layer 538 is provided on the position, the lead wiring portion 511, and the circuit portion 504. The color layer 536 and the light-shielding layer 538 are covered with an insulating film 534. The spaces between the films 534 are filled with a sealing layer 632. In the EL display device 500b, Although the configuration in which the colored layer 536 is provided has been illustrated, the present invention is not limited to this. For example, an EL layer When the colored layer 536 is not provided, the colored layer 536 may be omitted. good.

[0251] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0252] (Embodiment 5) In this embodiment, a transistor included in a display device according to one embodiment of the present invention will be described. do.

[0253] The transistors included in the display device of one embodiment of the present invention do not need to have the same structure. For example, a transistor included in a pixel portion of a display device and a driving circuit for driving the pixel portion By using different transistors for the path, appropriate electrical characteristics can be given to each. This makes it possible to improve the reliability of the display device.

[0254] In addition, the transistors included in the driver circuit section have a double gate structure, which reduces the electric field It is also possible to make a transistor with high effective mobility.

[0255] The channel lengths of the transistors included in the driver circuit portion and the pixel portion may be different. In practice, the channel length of the transistors included in the driver circuit section is set to less than 2.5 μm or 1. The pixel area can be set to 45 μm or more and 2.2 μm or less. The channel length can be set to 2.5 μm or more, or 2.5 μm or more and 20 μm or less. .

[0256] The channel length of the transistor included in the driving circuit section is set to less than 2.5 μm, preferably 1.4 By making the size between 5 μm and 2.2 μm, the current is reduced compared to the transistors included in the pixel area. It is possible to increase the field effect mobility and increase the on-current. A driver circuit portion capable of high-speed operation can be manufactured.

[0257] In addition, the high field effect mobility of the transistors included in the driver circuit section allows for the number of input terminals to be reduced. It can be reduced.

[0258] The liquid crystal display device 500a shown in FIG. 23 and the EL display device 500b shown in FIG. 24 have a pixel portion The transistor 101 shown in FIG. 1 is used as the transistor included in the driver circuit portion. 7 is used as the transistor to be incorporated.

[0259] The transistors included in the pixel section receive light from the backlight or EL element. For example, the atomic ratio of In:Ga:Zn=1:1:1 Or, the film is formed by sputtering using a target made of In:Ga:Zn=5:5:6 material. By using a thin oxide semiconductor layer for the channel formation region, highly reliable transistors can be obtained against light irradiation. A transistor can be formed.

[0260] On the other hand, transistors included in the drive circuit section are desired to have high field-effect mobility. For example, when a material with an atomic ratio of In:Ga:Zn=3:1:2 is used as a target, By using an oxide semiconductor layer formed by sputtering in the channel formation region, field-effect transport Therefore, a highly efficient transistor can be formed.

[0261] In this embodiment, the oxide semiconductor layer of one of the transistors has a stacked structure. Figures 25 and 26 show a method for easily fabricating two types of transistors on the same substrate. The left side of the drawing shows the transistor shown in FIG. 1 illustrates a cross section in the channel length direction of a transistor A having a similar configuration to the transistor 101. Also, on the right side of the drawing, transistor 10 shown in FIG. 7 is used as a transistor in the drive circuit section. 1 illustrates a cross section in the channel length direction of a transistor B having the same configuration as that of transistor 4. The reference numerals of elements common to both transistors A and B are given to only one of them.

[0262] First, an insulating layer 120 is formed on a substrate 110. The type of substrate 110 and the insulating layer 120 For the material, the explanation of the second embodiment can be referred to. The insulating layer 120 is formed by sputtering. It can be formed by using a CVD method, an MBE method, or the like.

[0263] The insulating layer 120 may be formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation or the like. This makes it easier to supply oxygen from the insulating layer 120 to the oxide semiconductor layer 130. Cut.

[0264] Note that the surface of the substrate 110 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no influence of scattering, the insulating layer 120 may not be provided.

[0265] Next, a layer to be the oxide semiconductor layer 130b of the driver circuit transistor is formed on the insulating layer 120. The oxide semiconductor film 130B is formed by sputtering, CVD, MBE, or the like. do.

[0266] Next, a resist mask 821 is formed in the driver circuit region by lithography (FIG. 25 Then, the oxide semiconductor film 130B is selectively etched using the resist mask. The oxide semiconductor layer 130b is formed by etching (see FIG. 25B).

[0267] Next, the oxide semiconductor film 130C is formed so as to cover the oxide semiconductor layer 130b.

[0268] The oxide semiconductor film is formed in a multi-chamber film formation system (e.g., spa It is preferable to form the film using a sputtering apparatus. Each chamber in the sputtering apparatus is In order to remove as much water as possible, which is an impurity for semiconductors, a cryopump is used. High vacuum evacuation (5×10) was performed using an adsorption type vacuum pump. -7 Pa~1×10 -4 Pa degree and the substrate on which the film is to be formed can be heated to 100°C or higher, preferably 500°C or higher. It is preferable to be able to heat the gas. Alternatively, a turbomolecular pump and a cold trap can be combined. This should prevent gas containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is also preferable to use an exhaust system that combines a turbomolecular pump and a cryopump. Good too.

[0269] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas used as sputtering gases are , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film as much as possible. This can be prevented.

[0270] The oxide semiconductor film 130B and the oxide semiconductor film 130C are formed of the oxide semiconductor material described in the second embodiment. The materials of the semiconductor layer 130b and the oxide semiconductor layer 130c can be used. In the embodiment, for example, the oxide semiconductor film 130B is formed of In:Ga:Zn=3:1:2 [element In the oxide semiconductor film 130C, an In-Ga-Zn oxide having a molecular weight ratio of In:Ga:Zn=1: In-Ga-Zn oxide with an atomic ratio of 1:1 or In:Ga:Zn=5:5:6 was used. The atomic ratios of the oxide semiconductor film 130B and the oxide semiconductor film 130C are as follows: The error includes a variation of ±20% of the atomic ratio above. When the target method is used, the above-mentioned material can be used as a target for film formation.

[0271] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0272] After the oxide semiconductor film 130C is formed, first heat treatment may be performed. , at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, The reaction may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to achieve this, the first heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. This increases the crystallinity of the oxide semiconductor film 130B and the oxide semiconductor film 130C, and further improves the insulating properties. impurities such as hydrogen and water are removed from the layer 120, the oxide semiconductor film 130B, and the oxide semiconductor film 130C. The first heat treatment can remove impurities. Alternatively, the etching may be performed after etching to form a stack of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c.

[0273] Next, a resist mask 822 is formed in the pixel region by lithography. The oxide semiconductor layer 130b in the drive circuit region and the oxide semiconductor film 1 It is formed on a layered structure made of 30C (see FIG. 25(C)).

[0274] Next, the oxide semiconductor film 130C is selectively etched using the resist mask. The oxide semiconductor layer 130c is formed in the pixel region. Then, a stack of the oxide semiconductor layer 30b and the oxide semiconductor layer 130c is formed (see FIG. 25(D)). At this time, the oxide semiconductor layer 130c in the drive circuit region covers the oxide semiconductor layer 130b. It is formed as follows.

[0275] Next, the oxide semiconductor layer in the pixel region and the oxide semiconductor layer 130b in the drive circuit region and An insulating film 160a serving as a gate insulating film is formed on the stack of the oxide semiconductor layer 130c and the oxide semiconductor layer 130d. The insulating film 160a can be used for the gate insulating film 160 described in the third embodiment. The insulating film 160a can be formed by a method such as sputtering, CVD, or MBE. etc. can be used.

[0276] Next, a conductive film 171a and a conductive film 172 which will become a gate electrode layer 170 are formed on the insulating film 160a. The conductive film 171a and the conductive film 172a are the same as those of the gate electrode 171a described in the second embodiment. The conductive film 171a and the conductive film 171b may be formed of a material that can be used for the electrode layer 170. The formation of 172a can be achieved by sputtering, CVD, MBE, or the like (see FIG. 2). 6(A)).

[0277] Next, a resist mask 824 is formed over the conductive film 172a. The conductive film 172a, the conductive film 171a, and the insulating film 160a are selectively etched to form a gate. A gate electrode layer 170 and a gate insulating film 160 are formed.

[0278] Next, the resist mask 824 formed in the above step is left in the region 231 and the region Impurities 830 that form oxygen vacancies are added to the semiconductor layer 232 to lower the resistance. A rain region is formed (see FIG. 26(B)). The impurity 830 is, for example, argon. is added by plasma treatment.

[0279] The resist mask is altered by argon plasma, so it is removed by oxygen ashing. It is preferable to remove it.

[0280] Next, an insulating layer 175 is formed on the above structure. The material of the insulating layer 175 is the same as that described in the second embodiment. The insulating layer 175 can be formed by a method such as sputtering, CVD, or MBE. It can be formed by

[0281] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 26(C)). For the material, the explanation of the second embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method can be used for forming the thin film, such as a CVD method or an MBE method.

[0282] Next, a resist mask is formed on the insulating layer 180, and the resist mask is used to form the insulating layer 1 80 and insulating layer 175 are selectively etched to lead to regions 231 and 232. A contact hole is formed.

[0283] Next, a conductive film is formed so as to cover the contact hole, and the conductive film is selectively etched. The source electrode layer 140 and the drain electrode layer 150 are formed by etching the conductive film. For the material, the description of the second embodiment can be referred to. The method can be used for forming the thin film, such as a CVD method or an MBE method.

[0284] Next, an insulating layer 185 is formed on the above structure (see FIG. 26(D)). The description of Embodiment 3 can be referred to. The insulating layer 185 is formed by a sputtering method. It can be formed by the CVD method, MBE method, or the like.

[0285] In addition, the insulating layer 180 and / or the insulating layer 185 may be subjected to a plasma treatment, an ion implantation, an ion implantation, or the like. Oxygen is introduced using methods such as ion doping and plasma immersion ion implantation. By adding oxygen, the insulating layer 180 and / or the insulating layer 1 This makes it easier to supply oxygen from 85 to the oxide semiconductor layer.

[0286] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment can be performed by the following method. Excess oxygen is easily released from the oxide semiconductor layer 5, and oxygen vacancies in the oxide semiconductor layer can be reduced. do.

[0287] Through the above steps, a transistor having an oxide semiconductor layer with a stacked structure and a transistor having a single-layer structure A transistor including an oxide semiconductor layer can be easily formed over the same substrate. It has a pixel section that is capable of high-speed operation, has little deterioration due to light irradiation, and has excellent display quality. A display device can be fabricated.

[0288] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The film can be formed by sputtering or plasma CVD, but other methods, such as thermal It may be formed by a CVD (Chemical Vapor Deposition) method. An example of a thermal CVD method is MOCVD (Metal Organic Chemical Vapor Deposition). Al Vapor Deposition (ALD) and Atomic Layer Deposition (ALD) There are methods such as the holomorphic deposition method.

[0289] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0290] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0291] In the ALD method, the chamber is kept at atmospheric or reduced pressure, and the source gases for the reaction are sequentially introduced. The film may be formed by repeating the gas introduction sequence. , by switching between the respective switching valves (also called high-speed valves), two or more types of raw materials can be The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. At the same time as or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The thickness can be precisely adjusted by changing the number of repetitions, and fine F It is suitable for producing ET.

[0292] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga -ZnO X When forming a (X>0) film, trimethylindium, trimethylgallium In addition, the chemical formula of trimethylindium is , In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. The combination is not limited to the above, and triethylgallium (chemical formula Ga(C2 H5)3) can be used instead of dimethyl zinc, and diethyl zinc (chemical formula Zn(C2 H5)2) can also be used.

[0293] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas is vaporized trimethylsilyl dimethylamidohafnium (TDMAH) and oxidized Two types of gases are used: tetrakisdimethylamidohafnium (O3) and tetrakisdimethylamidohafnium (TDMHA). The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethoxy) Examples include (trimethylamido) hafnium.

[0294] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent A liquid containing an aluminum precursor compound (e.g., trimethylaluminum TMA) is vaporized. Two types of gases are used: the source gas and H2O as an oxidizing agent. The chemical formula of ammonium is Al(CH3)3. Other material liquids include tris(dimethylammonium) Aluminum tris(2,2,2-triisobutylaluminum), aluminum ... 6,6-tetramethyl-3,5-heptanedionate).

[0295] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0296] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0297] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed using a film formation device that uses ALD. X When forming a (X>0) film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form an In-O layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. A mixed compound layer such as a Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. In addition, H2O gas obtained by bubbling an inert gas such as Ar instead of O3 gas However, it is preferable to use O3 gas that does not contain H. In(CH3) In place of the gas In(C2H5)3, gas Ga(CH3)3 may be used. Alternatively, Ga(C2H5)3 gas may be used. That's fine.

[0298] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0299] (Embodiment 6) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0300] [Configuration example] FIG. 27A is a top view of a display device of one embodiment of the present invention, and FIG. 27B is a top view of a display device of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. 27C is a circuit diagram showing a pixel of a display device according to one embodiment of the present invention. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0301] The transistors arranged in the pixel portion can be formed according to the above embodiment modes. Since the transistor can be easily made into an n-channel type, the n-channel transistor in the driver circuit can be easily made into an n-channel type. A part of the driver circuit can be configured with a transistor of the same type as the transistor of the pixel part. In this way, the transistor shown in the above embodiment is formed in the pixel portion or the driver circuit. By using the above, a highly reliable display device can be provided.

[0302] An example of a top view of an active matrix display device is shown in Figure 27(A). On the surface of 700, there are a pixel portion 701, a scanning line driving circuit 702, a scanning line driving circuit 703, a signal line driving circuit 704, a signal line driving circuit 705, a signal line driving circuit 706, a signal line driving circuit 707, a signal line driving circuit 708, a signal line driving circuit 709, a signal line driving circuit 710, a signal line driving circuit 711, a signal line driving circuit 71 The pixel portion 701 has a signal line driver circuit 704. A plurality of signal lines are extended from the signal line driver circuit 704. A plurality of scanning lines are connected to a scanning line driving circuit 702 and a scanning line driving circuit 703. The scanning lines and the signal lines are arranged in such a manner that they extend from each other. The display device substrate 700 is made of an FPC (Flat Printed Circuit). Timing control via connections such as a Removable Printed Circuit It is connected to a circuit (also called a controller or control IC).

[0303] In FIG. 27A, a scanning line driving circuit 702, a scanning line driving circuit 703, a signal line driving circuit 70 4 is formed on the same substrate 700 as the pixel portion 701. Since the number of components such as the above is reduced, costs can be reduced. When an operating circuit is provided, it becomes necessary to extend the wiring, which increases the number of connections between the wiring. If a drive circuit is provided on the 700, the number of connections between the wiring can be reduced, improving reliability. Furthermore, the yield can be improved.

[0304] [Liquid crystal display device] An example of the circuit configuration of a pixel is shown in FIG. 27(B). Here, as an example, a VA type liquid crystal display is used. 1 shows a pixel circuit that can be applied to a pixel of a display device.

[0305] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0306] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are , are separated so that different gate signals can be applied. is used in common for transistor 716 and transistor 717. The transistors 16 and 717 may be any of the transistors described in the above embodiment modes. This makes it possible to provide a highly reliable liquid crystal display device.

[0307] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The electrode layers are separated by slits. The first pixel electrode layer extends in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0308] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 712. The gate electrode is connected to the gate wiring 713. By giving different gate signals to the transistors 716 and 717, the operation timing of the transistors 716 and 717 is By varying the polarity, the orientation of the liquid crystal can be controlled.

[0309] Also, the capacitor wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0310] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0311] It should be noted that the pixel circuit shown in FIG. 27(B) is not limited to this. For example, The pixel may contain new switches, resistors, capacitors, transistors, sensors, or logic circuits. etc. may be added.

[0312] [Organic EL display device] Another example of the circuit configuration of a pixel is shown in Figure 27(C). 1 shows the pixel structure of the device.

[0313] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0314] FIG. 27(C) is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. The film can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0315] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0316] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The source electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to the signal line 725. ) is connected to the gate electrode layer of the driving transistor 722. 22, the gate electrode layer is connected to a power supply line 727 via a capacitor element 723, and the first electrode is connected to a power supply line 727. The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. The second electrode of the light emitting element 724 corresponds to the common electrode 728. It is electrically connected to a common potential line formed on the substrate.

[0317] The switching transistor 721 and the driving transistor 722 may be of other embodiments. This allows for the development of highly reliable organic EL devices. A display device can be provided.

[0318] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and is at least the forward threshold. Includes low voltages.

[0319] The capacitor 723 can be saved by substituting the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the electrode layer and the insulating layer.

[0320] Next, a signal input to the driving transistor 722 will be described. In this case, the driving transistor 722 is either fully on or fully off. A video signal such as this is input to the driving transistor 722. In order to operate the drive transistor 722 in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0321] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 724. , analog gray scale driving can be performed.

[0322] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) The pixel circuit shown in FIG. 1 includes a switch, a resistor, a capacitor, a sensor, a transistor, or a logic element. A logic circuit or the like may be added.

[0323] When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. The source electrode (first electrode) is located on the low potential side, and the drain electrode (second electrode) is located on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0324] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to the current), electron-emitting elements, liquid crystal elements , electronic ink, electrophoretic element, grating light valve (GLV), plasma display Using MEMS (Micro-Electro-Mechanical Systems) Display element, Digital Micromirror Device (DMD), DMS (Digital Micromirror Shutter), MIRASOL (registered trademark), IMOD (Interference Module ration element, shutter-type MEMS display element, optical interference-type MEMS display element , electrowetting element, piezoelectric ceramic display, carbon nanotube In addition to these, the device has at least one of an electric or magnetic display element. The display medium has contrast, brightness, reflectance, transmittance, etc. that change due to electrochemical effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display ( FED) or SED type flat panel display (SED: Surface-conductive tion Electron-emitter Display). An example of a display device using the liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display) is LCD display, reflective LCD display, direct view LCD display, projection LCD display Electronic ink, electronic liquid powder, or electrophoretic elements are used. An example of a display device that uses this technology is electronic paper. When realizing a reflective LCD, some or all of the pixel electrodes are For example, a part or the whole of the pixel electrode may be formed as a reflective electrode. The reflective electrode may be made of aluminum, silver, or the like. It is also possible to provide a memory circuit such as an SRAM below the Power consumption can be reduced.

[0325] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0326] (Embodiment 7) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. 28 will be used for explanation.

[0327] The display module 8000 shown in FIG. 28 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 connected to FPC8003, and touch panel 8005 connected to FPC8005 Display panel 8006, backlight unit 8007, frame 8009, printed circuit board 8010 and a battery 8011. The reader 8011, the touch panel 8004, etc. may not be provided.

[0328] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0329] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel. The shape and dimensions can be changed as needed to fit the size of the 8006.

[0330] The touch panel 8004 is a resistive or capacitive touch panel. 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 ) can also be equipped with a touch panel function. It is also possible to provide an optical sensor in each pixel of the touch panel to make it an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 8006, and a capacitive touch panel is formed. It is also possible to use a panel.

[0331] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the unit 8007 and configured to use a light diffusion plate.

[0332] The frame 8009 protects the display panel 8006 and also prevents the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may also function as a heat sink.

[0333] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a separately provided battery 8011 may be used. In this case, the battery 8011 can be omitted.

[0334] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0335] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0336] (Embodiment 8) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in a drawing. Please refer to the following for explanation.

[0337] [Cross-sectional structure] 29A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. The device has a transistor 2200 with a first semiconductor material on the bottom and a transistor 2200 with a second semiconductor material on the top. The transistor 2100 is made of a conductive material. As the transistor 2100 using the material, the transistor exemplified in the above embodiment may be used. The left side of the dashed line is a cross section of the transistor in the channel length direction. The right side is a cross section in the channel width direction.

[0338] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including silicon dioxide), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum (gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.), and the second semiconductor The material can be an oxide semiconductor. As a material other than an oxide semiconductor, single crystal silicon can be used. On the other hand, transistors using oxide semiconductors can be easily operated at high speed. The transistor has a low off-state current.

[0339] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either of these transistors may be used, and an appropriate transistor may be used depending on the circuit. The transistor of one embodiment of the present invention using a nitride semiconductor is used, and other materials and structures are not limited to these. However, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0340] In the structure shown in FIG. 29A, an insulating film 2201 and an insulating film 2202 are provided over a transistor 2200. The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the lamina allow wiring to be formed in the upper and lower layers. The insulating film 2204 covering the transistor 2100 and the electrodes are electrically connected. 2204, a wiring 2205 and a pair of electrodes of the transistor 2100 are formed on the insulating film 2204. Wiring 2206 obtained by processing the film is provided.

[0341] In this way, stacking two types of transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0342] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 is converted into silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulating film provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that cause the reliability of the transistor 2100 to decrease. Therefore, the upper layer of the transistor 2200 made of silicon-based semiconductor material is oxidized. When the transistor 2100 using a compound semiconductor is stacked, hydrogen diffusion between them It is particularly effective to provide the insulating film 2207 that has the function of preventing the above. 7 improves the reliability of the transistor 2200 by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, and thus the transistor 2100 At the same time, reliability can be improved.

[0343] The insulating film 2207 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0344] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. A blocking film 2208 (transistor) having a function of preventing hydrogen diffusion is formed on the transistor 2100. In the transistors 101 to 103, it is preferable to form an insulating layer 180. The lock film 2208 can be made of the same material as the insulating film 2207, and in particular, it is preferable to use an oxide film. It is preferable to use aluminum. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. It has a high blocking effect, preventing both substances and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film 2208 that covers the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. At the same time, water and hydrogen can be prevented from entering the oxide semiconductor film.

[0345] The transistor 2200 is not limited to a planar transistor, but may be any of various types. For example, FIN type, TRI-GATE type, The transistor may be a ligate type transistor. An example of a cross section of such a transistor is shown below. As shown in FIG. 29(D), an insulating film 2212 is provided on a semiconductor substrate 2211. The conductive substrate 2211 has a protrusion (also called a fin) with a thin tip. When the protrusions are formed, the insulating film is formed on the semiconductor substrate 2. It functions as a mask to prevent 211 from being etched. The protrusion does not have to have a thin tip, and may be, for example, a substantially rectangular parallelepiped protrusion, or may have a thick tip. A gate insulating film 2214 is provided on the protrusion of the semiconductor substrate 2211. The semiconductor substrate 2211 has a gate electrode 2213 formed thereon. The source and drain regions 2215 are formed on the semiconductor substrate. Although the example in which the electrode 2211 has a protrusion is shown, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, a semiconductor region having a protrusion may be formed by processing an SOI substrate. do not have.

[0346] [Circuit configuration example] In the above configuration, the electrode connection configuration of the transistor 2100 and the transistor 2200 is different. By using the above-described structure, various circuits can be configured. An example of a circuit configuration that can be realized by using a semiconductor device will be described.

[0347] [CMOS Circuit] The circuit diagram shown in FIG. 29(B) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The configuration of the S circuit is shown.

[0348] [Analog Switch] The circuit diagram shown in FIG. 29C shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0349] [Example of storage device] By using a transistor according to one embodiment of the present invention, it is possible to preserve stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0350] The semiconductor device shown in FIG. 30A includes a transistor 3200 using a first semiconductor material and a second semiconductor material. The semiconductor device includes a transistor 3300 and a capacitor 3400 made of two semiconductor materials. Note that the transistor described in the above embodiment is used as the transistor 3300. It is possible.

[0351] 30(B) is a cross-sectional view of the semiconductor device shown in FIG. In the figure, a configuration in which a back gate is provided in the transistor 3300 is shown. It may be configured not to provide.

[0352] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that This means that the memory contents can be retained for a longer period of time without requiring a refresh operation. Alternatively, the semiconductor memory device may be one in which the frequency of refresh operations is extremely low. This makes it possible to sufficiently reduce power consumption.

[0353] In FIG. 30A, a wiring 3001 is electrically connected to a source electrode of a transistor 3200. The wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The wiring 3003 is connected to one of the source electrode and the drain electrode of the transistor 3300. The wiring 3004 is electrically connected to the gate electrode of the transistor 3300. The gate electrode of the transistor 3200 is connected to the source of the transistor 3300. The other of the source electrode and the drain electrode is electrically connected to one of the electrodes of the capacitor 3400. The wiring 3005 is electrically connected to the other electrode of the capacitor 3400 .

[0354] In the semiconductor device shown in FIG. 30A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0355] The writing and retention of information will be explained. First, the potential of the wiring 3004 is changed to the potential of the transistor. This sets the potential at which the transistor 3300 is turned on, turning the transistor 3300 on. As a result, the potential of the wiring 3003 is applied to the gate electrode of the transistor 3200 and the capacitor 3 That is, a predetermined charge is applied to the gate of the transistor 3200. Here, the charge that gives two different potential levels (hereafter referred to as Low level) is Then, the wiring The potential of the transistor 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3200, the charge applied to the gate of the transistor 3200 is Retained (retained).

[0356] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long time.

[0357] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring 3001, In this state, when an appropriate potential (read potential) is applied to the wiring 3005, the transistor 3200 Depending on the amount of charge held in the gate, the wiring 3002 takes on different potentials. If the transistor 3200 is an n-channel type, then a High Apparent threshold V when a level charge is applied th_H is transistor 320 The apparent threshold voltage V when a low-level charge is applied to the gate electrode of 0 th_L Here, the apparent threshold voltage is the voltage at which the transistor 3200 is It refers to the potential of the wiring 3005 required to turn it on. The potential of wire 3005 is V th_H and V th_L By setting the potential between For example, in writing, Hi When a gh level charge is applied, the potential of the wiring 3005 becomes V0 (>V th_H ) If this happens, the transistor 3200 will be in the "ON state." In this case, the potential of the wiring 3005 is V0 ( <V th_L ) even if transistor 3 200 remains in the "off state." Therefore, by determining the potential of the wiring 3002, The stored information can be read out.

[0358] When memory cells are arranged in an array, only the information in the desired memory cell can be read. If the information is not read out in this way, the gate state is not affected. The potential at which transistor 3200 is in the "off state" regardless of the th_H twist A small potential may be applied to the wiring 3005. Alternatively, the transistor may be turned on regardless of the state of the gate. The potential at which the 3200 is in the "on" state, i.e., V th_L Applying a larger potential Just give it to line 3005.

[0359] The semiconductor device shown in FIG. 30(C) is different from the semiconductor device shown in FIG. 30(A) in that the transistor 3200 is not provided. In this case, the same operations as above are performed to write and store information. It is possible.

[0360] Next, the reading of information will be described. When the transistor 3300 is turned on, The wiring 3003 in the free state and the capacitor 3400 are electrically connected, and the wiring 3003 and the capacitor 34 00, the charge is redistributed between the wiring 3003 and the wiring 300. As a result, the potential of the wiring 300 changes. The amount of change in the potential of the capacitor 3400 is determined by the potential of the first terminal of the capacitor 3400 (or the potential of the capacitor 3400 It takes on different values ​​depending on the charge stored in the

[0361] For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the wiring The capacitance component of 3003 is CB, and the potential of the wiring 3003 before the charge is redistributed is VB0. Then, the potential of the wiring 3003 after the charge is redistributed is (CB×VB0+C×V) / Therefore, the state of the memory cell is the first state of the capacitor 3400. If the terminal potential takes two states, V1 and V0 (V1>V0), then the potential V1 is maintained. When the potential of the wiring 3003 is The potential of the wiring 3003 when V0 is held is (=(CB×VB0+C×V0) / (CB +C)).

[0362] Then, by comparing the potential of the wiring 3003 with a predetermined potential, information can be read out. do.

[0363] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be stacked on the driver circuit.

[0364] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0365] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film is unlikely to occur. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and it is reliable. Furthermore, the on / off state of the transistor determines the writing and reading of information. Since the data is written into the memory, high speed operation can be easily achieved.

[0366] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0367] (Embodiment 9) In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is used. The tag will be described with reference to FIG.

[0368] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems. High reliability is required.

[0369] The structure of an RF tag will be described with reference to Fig. 31. Fig. 31 is a block diagram showing an example of the structure of an RF tag. FIG.

[0370] As shown in FIG. 31, an RF tag 800 includes a communicator 801 (also known as an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 808. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor showing the rectification action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of achieving this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and communicating through mutual induction. electromagnetic coupling, electromagnetic induction, which communicates by induced electromagnetic fields; and radio wave communication. The RF tag 800 shown in this embodiment can be used with any of these methods. It can also be used for

[0371] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side or A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent power above a certain level from being input to the subsequent circuit. This is a circuit for controlling the

[0372] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0373] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the received signal.

[0374] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0375] The above-mentioned circuits can be selected or removed as needed.

[0376] Here, the memory device described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance between when reading and when writing. To prevent malfunctions or erroneous writing caused by a power shortage when writing data can be done.

[0377] Furthermore, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data so that users cannot freely rewrite it. It is preferable that the manufacturer writes a unique number on the product before shipping it. Instead of assigning a unique number to all RF tags produced, we only assign a unique number to non-defective products that are shipped. It is now possible to assign unique numbers to products, preventing discontinuities in the unique numbers of products after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0378] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0379] (Embodiment 10) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0380] FIG. 32 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0381] The CPU shown in FIG. 32 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and ROM interface 1189 are Of course, the CPU shown in FIG. 32 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 32 is considered as one core, and a configuration including multiple such cores is considered as one core. It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be a bit or the like.

[0382] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0383] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0384] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to various circuits.

[0385] In the CPU shown in FIG. 32, a memory cell is provided in the register 1196. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0386] In the CPU shown in FIG. 32, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0387] FIG. 33 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0388] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the load such as a resistor. The circuit is configured to be grounded.

[0389] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0390] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0391] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0392] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0393] In the transistor 1209 in FIG. 33, the second gate electrode (second gate electrode: back The first gate receives a control signal WE, and the second gate receives a control signal WE. The control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the solenoid voltage of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the source potential of the transistor. This is a potential signal for controlling the threshold voltage of the transistor 1209. In addition, the control signal WE2 is the same potential signal as the control signal WE. The transistor 1209 may be a transistor without a second gate. A resistor can also be used.

[0394] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 33, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0395] In FIG. 33, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0396] In addition, in FIG. 33, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may also include a transistor in which the channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0397] The circuit 1201 in FIG. 33 can be, for example, a flip-flop circuit. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0398] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0399] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when the power supply voltage is not supplied to 200, the signal held in the capacitor element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0400] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0401] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0402] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0403] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R Also applicable to F-ID (Radio Frequency Identification) It is possible.

[0404] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0405] (Embodiment 11) In this embodiment, modified examples of the transistor of one embodiment of the present invention will be described with reference to FIGS. 34 to 38. This will be explained using:

[0406] The transistor shown in FIG. 34 is a transistor including an oxide semiconductor layer formed over an insulating layer 753 on a substrate 751. the oxide semiconductor layer 755; an insulating layer 757 in contact with the oxide semiconductor layer 755; The insulating layer 757 has a conductive layer 759 overlapping with the oxide semiconductor layer 755. The conductive layer 759 functions as a gate insulating layer. do.

[0407] The nitride insulating layer 765 in contact with the oxide semiconductor layer 755 and the nitride insulating layer 765 The nitride insulating layer 765 and the insulating layer 767 are provided in the transistor. In the opening of the edge layer 767, the conductive layers 768 and 769 in contact with the oxide semiconductor layer 755 are The conductive layers 768 and 769 are provided in the transistor. It functions as an electrode layer.

[0408] In the transistor illustrated in FIG. 34A, the oxide semiconductor layer 755 overlaps with the conductive layer 759. A channel region 755a is formed in the region including the impurity. The conductive layer 768 has regions containing organic elements, i.e., low resistance regions 755b and 755c. , 769 are in contact with the low resistance regions 755b, 755c. It functions as wiring.

[0409] Alternatively, as in the transistor illustrated in FIG. 34B, The regions 755d and 755e in contact with the electrode layers 768 and 769 are not doped with impurity elements. In this case, the regions 755d and 755e in contact with the conductive layers 768 and 769 and the channel Between the region 755a and the region having an impurity element, that is, low resistance regions 755b and 755c are formed. When a voltage is applied to the conductive layers 768 and 769, the regions 755d and 755e Since the layer has conductivity, it functions as a source region and a drain region.

[0410] Note that in the transistor shown in FIG. 34B, after the conductive layers 768 and 769 are formed, An impurity element is added to the oxide semiconductor layer using the conductive layers 759 and 768 and 769 as masks. This can be formed by

[0411] The conductive layer 759 may have a tapered end. The angle θ1 between the surface where the conductive layer 757 and the conductive layer 759 are in contact and the side surface of the conductive layer 759 is less than 90°. or 30° to 85°, or 45° to 85°, or 60° to 85° The angle θ1 may be less than 90°, or may be greater than or equal to 30° and less than or equal to 85°, or By setting the angle to 45° or more and 85° or less, or 60° or more and 85° or less, the insulating layer 757 and the conductive layer 758 can be This allows for improved coverage of the nitride insulating layer 765 on the side surfaces of the insulating layer 759.

[0412] Next, modifications of the low resistance regions 755b and 755c will be described. 34(F) is an enlarged view of the vicinity of the oxide semiconductor layer 755 shown in FIG. Here, the channel length L is the distance between the pair of low resistance regions.

[0413] As shown in FIG. 34C, in the cross section in the channel length direction, the channel region 755a The boundary between the low resistance regions 755b and 755c is formed at the end of the conductive layer 759 via the insulating layer 757. That is, in the top view, the channel region 755a and the The boundaries of the low resistance regions 755b and 755c coincide or approximately coincide with the ends of the conductive layer 759. are.

[0414] Alternatively, as shown in FIG. 34(D), in the cross section in the channel length direction, The conductive layer 755a has a region that does not overlap with the conductive layer 759. The region functions as an offset region. The length of the offset region in the channel length direction is denoted as Loff. When there are multiple offset areas, the length of one offset area is called Loff. , included in the channel length L. Also, Loff is less than 20% of the channel length L, or 10 %, or less than 5%, or less than 2%.

[0415] Alternatively, as shown in FIG. 34(E), in the cross section in the channel length direction, the low resistance region 7 The insulating layer 757 is interposed between the conductive layer 759 and the insulating layer 757. The overlap region in the channel length direction functions as an overlap region. The length is denoted as Lov. Lov is less than 20%, or less than 10%, of the channel length L, or Less than 5% or less than 2%.

[0416] Alternatively, as shown in FIG. 34(F), in the cross section in the channel length direction, A low resistance region 755f is provided between the channel region 755a and the low resistance region 755b. The low resistance region 755g is located between the low resistance region 755f and the low resistance region 755c. The low-resistivity regions 755g have a lower concentration of impurity elements and a higher resistivity than the low-resistivity regions 755b and 755c. In this case, the low resistance regions 755f and 755g overlap the insulating layer 757, but the insulating layer 757 and the conductive It may overlap with the conductive layer 759.

[0417] 34(C) to 34(F), the explanation of the transistor shown in FIG. 34(C) to 34(F) are also applicable to the transistor shown in FIG. 34(B). ) structure can be applied as appropriate.

[0418] In the transistor shown in FIG. 35A, the edge of the insulating layer 757 is located outside the edge of the conductive layer 759. That is, the insulating layer 757 is located on the conductive layer 759 side. The nitride insulating layer 765 can be kept away from the panel region 755a. To prevent nitrogen, hydrogen, etc. contained in the layer 765 from penetrating into the channel region 755a. can be done.

[0419] In the transistor shown in FIG. 35B, the insulating layer 757 and the conductive layer 759 have tapered shapes. The angles of the tapered portions are different. The angle θ1 between the surface of the oxide semiconductor layer 755 and the side surface of the conductive layer 759 and the insulating layer 757 The angle θ2 formed by the surface where the insulating layer 757 is in contact with the side surface of the insulating layer 757 is different. The angle may be less than 30° or between 30° and 85°, or between 45° and 70°. For example, when the angle θ2 is smaller than the angle θ1, the coverage of the nitride insulating layer 765 is improved. If the angle θ2 is greater than the angle θ1, the nitride insulating layer 765 is moved away from the channel region 755a. Therefore, nitrogen, hydrogen, etc. contained in the nitride insulating layer 765 can be absorbed into the channel region. It is possible to prevent the light from entering the area 755a.

[0420] Next, regarding modifications of the low resistance regions 755b and 755c, FIGS. 35(C) to 35(F) are shown. 35(C) to 35(F) are the same as those in FIG. FIG. 7 is an enlarged view of the vicinity of the semiconductor layer 755.

[0421] As shown in FIG. 35C, in the cross section in the channel length direction, the channel region 755a The boundary between the low resistance regions 755b and 755c is formed by the end of the conductive layer 759 and the insulating layer 757. That is, in the top view, the channel region 755a and the The boundaries of the low resistance regions 755b and 755c coincide or almost coincide with the ends of the conductive layer 759. is doing.

[0422] Alternatively, as shown in FIG. 35(D), in the cross section in the channel length direction, The conductive layer 755a has a region that does not overlap with the conductive layer 759. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 755b and 755c are in contact with the insulating layer 75. 7 and does not overlap with the edge of the conductive layer 759.

[0423] Alternatively, as shown in FIG. 35(E), in the cross section in the channel length direction, the low resistance region 7 The insulating layer 757 is interposed between the conductive layer 759 and the insulating layer 757. In other words, in the top view, the low resistance regions 755b and 755 The end of c overlaps with the conductive layer 759 .

[0424] Alternatively, as shown in FIG. 35(F), in the cross section in the channel length direction, The low resistance region 755f is located between the channel region 755a and the low resistance region 755b. The low resistance region 755g is located between the low resistance region 755f and the low resistance region 755c. The low-resistivity regions 755g have a lower concentration of impurity elements and a higher resistivity than the low-resistivity regions 755b and 755c. In this example, the low resistance regions 755f and 755g overlap the insulating layer 757, but the insulating layer 757 and the conductive It may overlap with the conductive layer 759.

[0425] 35(C) to 35(F), the explanation of the transistor shown in FIG. 35(A) is As explained above, the transistor shown in FIG. 35B also has the same structure as that shown in FIGS. ) can be applied as appropriate.

[0426] In the transistor shown in FIG. 36A, the conductive layer 759 has a stacked structure and is in contact with the insulating layer 757. The conductive layer 759a is in contact with the conductive layer 759a, and the conductive layer 759b is in contact with the conductive layer 759a. The end of the conductive layer 759a is located outside the end of the conductive layer 759b. The portion a has a shape that protrudes from the conductive layer 759b.

[0427] Next, modifications of the low resistance regions 755b and 755c will be described. 36(E), 37(A), and 37(B) show the oxide semiconductor layer 755 shown in FIG. This is an enlarged view of the vicinity.

[0428] As shown in FIG. 36B, in the cross section in the channel length direction, the channel region 755a The boundary between the low resistance regions 755b and 755c is formed by the conductive layer 759a included in the conductive layer 759. The end portion of the insulating layer 757 is aligned or substantially aligned with the end portion of the insulating layer 757. The boundary between the channel region 755a and the low resistance regions 755b and 755c is the edge of the conductive layer 759. It matches or nearly matches.

[0429] Alternatively, as shown in FIG. 36(C), in the cross section in the channel length direction, The conductive layer 755a has a region that does not overlap with the conductive layer 759. The region functions as an offset region. That is, in the top view, the ends of the low resistance regions 755b and 755c are It does not overlap with the end of the 9.

[0430] Alternatively, as shown in FIG. 36(D), in the cross section in the channel length direction, the low resistance region 7 755b and 755c have regions that overlap with the conductive layer 759, here the conductive layer 759a. The overlapping region is called an overlapping region. The end of 5c overlaps with the conductive layer 759a.

[0431] Alternatively, as shown in FIG. 36(E), in the cross section in the channel length direction, The low resistance region 755f is located between the channel region 755a and the low resistance region 755b. The impurity element is introduced into the conductive layer 759. a and added to the low resistance regions 755f and 755g. The region 55g has a lower concentration of impurity elements and a higher resistivity than the low resistance regions 755b and 755c. Here, the low resistance regions 755f and 755g overlap the conductive layer 759a. 759a and the conductive layer 759b may overlap.

[0432] Alternatively, as shown in FIG. 37A, the conductive layer 759 The end of the conductive layer 759a is located outside the end of the conductive layer 759b, and the conductive layer 759a has a tapered shape. That is, the surface where the insulating layer 757 and the conductive layer 759a are in contact with each other and the surface where the conductive layer 759a is in contact with each other may be formed as follows. The angle between the sides is less than 90°, or 5° to 45°, or 5° to 30° may be.

[0433] Furthermore, the end of the insulating layer 757 may be located outside the end of the conductive layer 759a.

[0434] Furthermore, the side surfaces of the insulating layer 757 may be curved.

[0435] Furthermore, the insulating layer 757 may have a tapered shape. The angle between the surface of the insulating layer 757 and the side of the insulating layer 757 is less than 90°, preferably 3 It may be greater than or equal to 0° and less than 90°.

[0436] The oxide semiconductor layer 755 shown in FIG. 37A includes a channel region 755a and a channel region 755b. Low resistance regions 755f and 755g sandwiching 55a, and low resistance regions 755f and 755g sandwiching Resistance regions 755h and 755i and low resistance region 755 sandwiching low resistance regions 755h and 755i The impurity element passes through the insulating layer 757 and the conductive layer 759a and is reduced. Since it is added to the resistance areas 755f, 755g, 755h, and 755i, the low resistance area 755 f, 755g, 755h, and 755i are regions with less impurity elements than the low-resistance regions 755b and 755c. Low concentration and high resistivity.

[0437] The oxide semiconductor layer 755 shown in FIG. 37B includes a channel region 755a and a channel region 755b. Low resistance regions 755h and 755i sandwiching 55a, and low resistance regions 755h and 755i sandwiching The impurity element passes through the insulating layer 757 to form a low resistance region. Since the regions 755h and 755i are doped, the low resistance regions 755h and 755i are The concentration of impurity elements is lower and the resistivity is higher than in the regions 755b and 755c.

[0438] In addition, the channel region 755a overlaps with the conductive layer 759b in the channel length direction, and a low resistance Resistive regions 755f and 755g overlap conductive layer 759a, which protrudes outside conductive layer 759b. The low resistance regions 755h and 755i are formed by the insulating layer 759a protruding outward from the conductive layer 759a. 57, and low resistance regions 755b and 755c are provided outside the insulating layer 757.

[0439] As shown in FIG. 36E and FIGS. 37A and 37B, the oxide semiconductor layer 755 is in the low resistance region. A low-resistivity region 755f has a lower impurity element concentration and higher resistivity than the regions 755b and 755c. , 755g, 755h, and 755i, the electric field in the drain region can be relaxed. Therefore, it is possible to reduce the variation in the threshold voltage of the transistor.

[0440] 37(C) shows the structure of the transistor shown in FIGS. 37(A) and 37(B) in the channel width direction. 7 is an enlarged view of the vicinity of an end of a conductive layer 759 in FIG.

[0441] The transistor shown in FIG. 38A has a channel region 755a and a low-resistance region 755b. The low-resistance regions 755b and 755c are the channel regions. The region 755b has a thickness smaller than that of the region 755a. The region c has a thickness that is 0.1 nm or more and 5 nm or less smaller than that of the channel region 755a.

[0442] The transistor illustrated in FIG. 38B includes insulating layers 753 and 755 in contact with the oxide semiconductor layer 755. At least one of the insulating layers 753 and 7 has a multi-layer structure. For example, the insulating layer 753 includes an insulating layer 753a and an insulating layer 753b. The insulating layer 753b is in contact with the insulating layer 753a and the oxide semiconductor layer 755. The layer 757 includes an insulating layer 757a in contact with the oxide semiconductor layer 755 and a thin film insulating layer 757b in contact with the insulating layer 757a. The insulating layer 757b is formed on the insulating layer 757a.

[0443] The insulating layers 753b and 757a have an energy level at the top of the valence band (E v_o s ) and the energy at the bottom of the conduction band (E c_os ) between the oxides of nitrogen and the oxides of nitrogen with low level density It can be formed using a material insulating film. v_os and E c_os During As an oxide insulating film with a low potential density, a silicon oxynitride film which emits a small amount of nitrogen oxide, or Alternatively, an aluminum oxide nitride film or the like which emits a small amount of nitrogen oxides can be used. The insulating layers 753b and 757a have an average film thickness of 0.1 nm or more and 50 nm or less, or 0. It is between 5 nm and 10 nm.

[0444] The silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectroscopy (TDS). (Thermal Desorption Spectroscopy) This is a membrane that releases more ammonia than elemental oxides, and typically releases ammonia. The amount is 1 x 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is ammonia. The amount of release is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by the heat treatment below.

[0445] The insulating layers 753a and 757b are formed using an oxide insulating film that releases oxygen by heating. The insulating layers 753a and 757b have an average film thickness of 5 nm to 1000 nm. or less, or 10 nm or more and 500 nm or less.

[0446] Typical examples of oxide insulating films that release oxygen when heated include silicon oxynitride films and silicon oxynitride films. Examples include aluminum oxide films.

[0447] Nitrogen oxides (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO2 Alternatively, NO forms a level in the insulating layer 753 and the insulating layer 757. The nitride semiconductor layer 755 is located within the energy gap of the nitride semiconductor layer 755. When the oxide semiconductor layer 755 is diffused to the interface between the insulating layer 753 and the oxide semiconductor layer 757, the level 3, 757 side may trap electrons. As a result, the trapped electrons , and remain near the interface between the insulating layers 753 and 757 and the oxide semiconductor layer 755. This shifts the threshold voltage in the positive direction.

[0448] Nitrogen oxide reacts with ammonia and oxygen during the heat treatment. The nitrogen oxide contained in the insulating layers 753b and 757b is removed by the heat treatment. The nitrogen oxides contained in the insulating layers 753a and 757b react with the ammonia contained therein, and thus the nitrogen oxides contained in the insulating layers 753a and 757b are reduced. Therefore, at the interfaces between the insulating layers 753 and 757 and the oxide semiconductor layer 755, Electrons are less likely to be trapped.

[0449] The insulating layers 753b and 757a are made of E v_os and E c_os The density of nitrogen oxide levels between By using an oxide insulating film with a low thermal conductivity, a shift in the threshold voltage of a transistor can be reduced. This makes it possible to reduce fluctuations in the electrical characteristics of the transistor.

[0450] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300°C or higher but lower than the substrate distortion point. By the heat treatment, the insulating layers 753b and 757a were measured at ESR below 100K. The first signal in the spectrum has a g value between 2.037 and 2.039, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 A third signal is observed. The width, split width of the second signal, and split width of the third signal are measured by the X-band ESR measurement. The g value is about 5 mT at 2.037 to 2.039. , the second signal with a g value of 2.001 to 2.003, and the second signal with a g value of 1.964 to 1. The sum of the spin densities of the third signals that are 0.966 or less is 1 x 1018 spins / c m 3 less than 1×1017 spins / cm 3 Over 1×1018spin s / cm 3 is less than.

[0451] In addition, in the ESR spectrum below 100K, the g value is between 2.037 and 2.039. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value between 1. The third signal, between 964 and 1.966, is nitrogen oxides (NOx, where x is between 0 and 2). , preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include: Nitric oxide, nitrogen dioxide, etc. That is, the first group with a g value of 2.037 or more and 2.039 or less signal, a second signal with a g-value between 2.001 and 2.003, and a g-value between 1.96 The smaller the sum of the spin densities of the third signals, which is between 4 and 1.966, the more oxide It can be said that the content of nitrogen oxides contained in the insulating layer is low.

[0452] In addition, the heat treatment in the manufacturing process of the transistor is typically performed at temperatures above 300°C and below the substrate distortion point. After the heat treatment, the oxide insulating layer containing nitrogen and having few defects was observed by SIMS (Sec The nitrogen concentration measured by ion mass spectrometry (Ion Mass Spectrometry) It is less than 6×1020 atoms / cm3.

[0453] The substrate temperature is 220°C or higher, or 280°C or higher, or 350°C or higher, and silane and Using the plasma CVD method with dinitrogen monoxide, oxide containing nitrogen and with few defects was produced. By forming a solid insulating layer, a dense and hard film can be formed.

[0454] The transistor illustrated in FIG. 38C includes an oxide semiconductor layer 755, an insulating layer 757, and a conductive layer Between 759 and the nitride insulating layer 765 is an insulating layer 775. The insulating layer 775 is The insulating layers 753b and 757a in FIG. 8(B) are oxide insulating layers containing nitrogen and having a small amount of defects. It can be formed using a border layer.

[0455] In addition, in the cross section in the channel length direction, the channel region 755a and the low resistance region 755 and a low resistance region 755f between the channel region 755a and the low resistance region 755c. The low resistance regions 755f and 755g are the low resistance regions 755b , the concentration of impurity elements is lower than that of 755c, and the resistivity is higher. 55f and 755g overlap the insulating layer 775 that contacts the side surfaces of the insulating layer 757 and the conductive layer 759. The low resistance regions 755f and 755g are formed by the insulating layer 757 and the conductive layer 759. It may overlap with.

[0456] In the transistor illustrated in FIG. 38D, the insulating layer 757 is formed between the channel of the oxide semiconductor layer 755 and the insulating layer 757. The insulating layer 755a is in contact with the low resistance regions 755b and 755c. 757 is a low resistance region 755b, 755 compared to the region in contact with the channel region 755a. The film thickness in the area in contact with c is thin, typically with an average film thickness of 0.1 nm or more and 50 nm or less. As a result, the oxide semiconductor is formed through the insulating layer 757. Impurity elements can be added to the conductor layer 755, and the nitride insulating layer 765 can also contain impurity elements. The hydrogen contained in the oxide semiconductor layer 755 can be transferred to the oxide semiconductor layer 755 through the insulating layer 757. As a result, low resistance regions 755b and 755c can be formed.

[0457] Furthermore, the insulating layer 753 has a multilayer structure of insulating layers 753a and 753b, and is heated to release oxygen. The insulating layer 753a is formed using an oxide insulating layer that contains nitrogen and has a small amount of defects. The insulating layer 753b is formed using an oxide insulating layer. The insulating layer 757 is formed using an oxide insulating layer containing nitrogen and having a small amount of defects. The oxide semiconductor layer 755 can be covered with an oxide insulating layer that is not Oxygen contained in 3a is transferred to the oxide semiconductor layer 755 by heat treatment, and the oxide semiconductor The insulating layers 753b and 755c are formed by reducing oxygen vacancies in the channel region 755a of the insulating layer 755. The number of carrier traps at the interface between the oxide semiconductor layer 57a and the oxide semiconductor layer 755 can be reduced. As a result, it is possible to reduce the shift in the threshold voltage of the transistor. This reduces fluctuations in the electrical characteristics of the transistor.

[0458] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0459] (Embodiment 12) The band structure of a transistor of one embodiment of the present invention in an arbitrary cross section will be described below. do.

[0460] FIG. 39A is a cross-sectional view of a transistor according to one embodiment of the present invention.

[0461] The transistor shown in FIG. 39A includes an insulating layer 401 on a substrate 400 and a A conductive layer 404a, a conductive layer 404b on the conductive layer 404a, a conductive layer 404b on the insulating layer 401, and a conductive layer 404b on the insulating layer 401. 4a and the insulating layer 402a on the conductive layer 404b, and the insulating layer 402b on the insulating layer 402a. a semiconductor layer 406a on the insulating layer 402b; and a semiconductor layer 406b on the semiconductor layer 406a. , an insulating layer 412 on the semiconductor layer 406b, a conductive layer 414a on the insulating layer 412, and a conductive layer 414b. The conductive layer 414b on the insulating layer 402b, the semiconductor layer 406a, and the semiconductor layer 406 an insulating layer 408 on the insulating layer 412, the conductive layer 414a, and the conductive layer 414b; An insulating layer 418 on the edge layer 408, and a conductive layer 416a1 and a conductive layer 416 on the insulating layer 418. b1, and conductive layers 416a2 and 416b1 on the conductive layers 416a1 and 416b1, respectively. and conductive layer 416b2, and on insulating layer 418, conductive layer 416a2, and conductive layer 416b2. and an insulating layer 428.

[0462] The insulating layer 401 has a function of preventing impurities from entering a channel formation region of a transistor. For example, the conductive layer 404b may be formed by forming a semiconductor layer 406a such as copper or When the semiconductor layer 406b has impurities, the insulating layer 401 blocks copper and the like. It may have a function.

[0463] The stack of the conductive layer 404a and the conductive layer 404b is collectively referred to as the conductive layer 404. The conductive layer 404 may function as a gate electrode of a transistor. The insulating film may have a function of blocking light from a channel formation region of a transistor.

[0464] The insulating layer 402a and the insulating layer 402b are collectively referred to as the insulating layer 402. The insulating layer 402a may function as a gate insulating layer of a transistor. In some cases, the semiconductor device has a function of preventing impurities from entering the channel formation region of a transistor. For example, the conductive layer 404b may be made of copper or the like. When the insulating layer 402a has impurities for copper, etc., There is a match.

[0465] The semiconductor layer 406a and the semiconductor layer 406b are collectively referred to as the semiconductor layer 406. 6 may function as a channel formation region of a transistor.

[0466] The semiconductor layer 406a overlaps with the insulating layer 412, the conductive layer 414a, the conductive layer 414b, and the like. The semiconductor layer 406b has an insulating region 407a1 and an insulating region 407b1. The region 407a2 and the region 407b that do not overlap with the layer 412, the conductive layer 414a, the conductive layer 414b, etc. The region 407a1 and the region 407b1 are insulating regions of the semiconductor layer 406a. The region has a lower resistance than the region overlapping with the layer 412, the conductive layer 414a, the conductive layer 414b, etc. The region 407a2 and the region 407b2 are formed by the insulating layer 412 of the semiconductor layer 406b, the conductive layer 412, and the insulating layer 412. The resistance of the region is lower than that of the region overlapping with the conductive layer 414a, the conductive layer 414b, etc. The region with low carrier density can also be called a region with high carrier density.

[0467] The area 407a1 and the area 407a2 are collectively referred to as the area 407a. Area 407b1 and area 407b2 are collectively referred to as area 407b. O7b may function as the source and drain regions of a transistor. do.

[0468] The conductive layer 414a and the conductive layer 414b are collectively referred to as the conductive layer 414. The conductive layer 414 may function as a gate electrode of a transistor. It may have a function of blocking light from the channel forming region of a transistor.

[0469] The insulating layer 412 may function as a gate insulating layer of a transistor.

[0470] The insulating layer 408 has a function of preventing impurities from entering a channel formation region of the transistor. For example, the conductive layer 416a2 and the conductive layer 416b2 may be made of copper or the like. When the semiconductor layer 406a or the semiconductor layer 406b has impurities, the insulating layer 40 8 may have the function of blocking copper and other metals.

[0471] The insulating layer 418 may function as an interlayer insulating layer of a transistor. By providing the insulating layer 418, parasitic capacitance between wirings of the transistors can be reduced in some cases. do.

[0472] The conductive layer 416a1 and the conductive layer 416a2 are collectively referred to as the conductive layer 416a. The conductive layer 416b1 and the conductive layer 416b2 are collectively referred to as the conductive layer 416b. The conductive layer 416b functions as a source electrode and a drain electrode of the transistor. This may be the case.

[0473] The insulating layer 428 has a function of preventing impurities from entering a channel formation region of the transistor. It may have the ability.

[0474] Here, FIG. 39(B) shows a cross section taken along the line K1-K2 including the channel forming region of the transistor. The semiconductor layer 406a has a higher energy band structure than the semiconductor layer 406b. In addition, the insulating layer 402a, the insulating layer 402b, and the insulating layer 412 are The energy gap of the semiconductor layer 406 is sufficiently larger than that of the semiconductor layer 406a and the semiconductor layer 406b. In addition, the semiconductor layer 406a, the semiconductor layer 406b, the insulating layer 402a, the insulating layer 402b, and The Fermi levels (denoted as Ef) of the insulating layer 412 and the intrinsic Fermi levels (denoted as Ei). is set to the same position as the Fermi level.

[0475] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, the semiconductor layer 406a and the semiconductor layer Due to the difference in energy between the bottom of the conduction band and the semiconductor layer 406b, electrons preferentially pass through the semiconductor layer 406a. In other words, it can be assumed that electrons are embedded in the semiconductor layer 406a. , the energy at the bottom of the conduction band is denoted as Ec, and the energy at the bottom of the valence band is denoted as Ev. .

[0476] Therefore, the transistor according to one aspect of the present invention can suppress the interface scattering by implanting electrons. Therefore, the transistor according to one embodiment of the present invention has a low channel resistance. is small.

[0477] Next, in FIG. 39(C), L1-L2 including the source region or drain region of the transistor is shown. The band structure in the cross section is shown in Fig. 4. The regions 407a1, 407b1, and 407a 2 and the region 407b2 are in a degenerated state. The Fermi level of 406a is set to be approximately equal to the energy of the bottom of the conduction band. In 2, the Fermi level of the semiconductor layer 406b is set to be approximately the same as the energy of the bottom of the conduction band. The same applies to the area 407a1 and the area 407a2.

[0478] At this time, the conductive layer 416b having a function as a source electrode or a drain electrode and the region The energy barrier between 407b2 and 407b2 is small enough to form an ohmic contact. 407b2 and the region 407b1 form an ohmic contact. The conductive layer 416a functioning as a drain electrode and the region 407a2 are connected to each other. The barrier is small enough to provide ohmic contact. Therefore, the conductive layer 416a and the conductive layer 416b are in ohmic contact with each other. Electrons are smoothly exchanged between the semiconductor layer 406a and the semiconductor layer 406b. We can see that.

[0479] As described above, the transistor according to one embodiment of the present invention has a source electrode and a drain electrode. The electrons are smoothly exchanged between the electrode and the channel forming region, and the channel resistance is low. In other words, it is a transistor with excellent switching characteristics. It can be seen that...

[0480] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0481] (Embodiment 13) In this embodiment, the effect of oxygen vacancies in an oxide semiconductor layer and hydrogen entering the oxygen vacancies is considered. We will explain about this.

[0482] <(1). V o Ease of formation and stability of H> When the oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, H is preferentially During the heat treatment at 450°C, H diffuses along the ab plane and Therefore, in this study, we investigated the oxygen vacancy V in IGZO. o If there is , H is oxygen vacancy V o Here, we will explain whether it is easy to enter the oxygen vacancy V o During The state where H exists is V o It is written as H.

[0483] For the calculation, the InGaZnO4 crystal model shown in Figure 40 was used. Here, V o H in H V o The activation barrier (E a ) to NEB (Nudg The calculation conditions are shown in Table 1.

[0484] [Table 1]

[0485] In addition, in the InGaZnO4 crystal model, the difference in the metal elements to which oxygen is bonded and their number As shown in FIG. 40, there are oxygen sites 1 to 4. Here, oxygen vacancies V o The calculation was carried out for oxygen site 1 and oxygen site 2, which are likely to form

[0486] First, oxygen deficiency V o As oxygen site 1, which is likely to form Calculations were performed for the bonded oxygen sites.

[0487] The model of the initial state is shown in Figure 41(A), and the model of the final state is shown in Figure 41(B). , the calculated activation barrier (E a ) is shown in Figure 42. The initial state here is oxygen vacancy V o There is an H inside (V o H) and the final state is , oxygen deficiency V o and the state where oxygen bonded to one Ga and two Zn atoms is bonded to H (H -O).

[0488] As a result of the calculation, oxygen deficiency V o It takes about 1.52 eV of energy for the H in the molecule to bond with another O. is necessary, whereas H bonded to O is oxygen vacant V o To enter it, you need about 0.46 eV Energy was needed.

[0489] Here, the calculated activation barrier (E a ) and Equation 1 to calculate the reaction frequency (Γ) In addition, in the formula 1, k B is the Boltzmann constant and T is the absolute temperature.

[0490]

number

[0491] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of 1 / sec. The frequency of H moving from the model shown in Figure 41(A) to the model shown in Figure 41(B) is 5.52 x10 0 [1 / sec]. Also, from the model shown in Figure 41(B), The frequency of H transfer to the model shown is 1.82 × 10 9 [1 / sec]. Therefore, H diffusing in IGZO is near oxygen vacant V. o There is V o H is easily formed, DanV o H forms oxygen vacancy V o It can be said that it is difficult to be released from

[0492] Next, oxygen deficiency V o As oxygen site 2, which is likely to form Calculations were performed for the selected oxygen sites.

[0493] The model of the initial state is shown in Figure 43(A), and the model of the final state is shown in Figure 43(B). , the calculated activation barrier (E a ) is shown in Figure 44. The initial state here is oxygen vacancy V o There is an H inside (V o H) and the final state is , oxygen deficiency V o and the state where oxygen bonded to one Ga and two Zn atoms is bonded to H (H -O).

[0494] As a result of the calculation, oxygen deficiency V o It takes about 1.75 eV of energy for the H in the molecule to bond with another O. is necessary, whereas H bonded to O is oxygen vacant V o To enter it, you need about 0.35 eV Energy was needed.

[0495] In addition, the calculated activation barrier (E a ) and the above formula 1, the reaction frequency (Γ) is calculated. I put it out.

[0496] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of 1 / sec. The frequency of H moving from the model shown in Figure 43(A) to the model shown in Figure 43(B) is 7.53 x10 -2 [1 / sec]. Also, from the model shown in Figure 43(B), The frequency of H transfer to the model shown in is 1.44×10 10 [1 / sec]. So, for now, V o H forms oxygen vacancy V o Therefore, it can be said that H is difficult to release.

[0497] From the above, it can be seen that H in IGZO is easily diffused during annealing, and oxygen vacancy V o If there is Oxygen deficiency V o Enter V o It was found that H is easily obtained.

[0498] <(2). V o H transition level > Oxygen vacancy V in IGZO o and H exists, <(1). V o Ease of formation of H From the calculation using the NEB method shown in Figure 1, oxygen vacancy V o and H is V o Form H Easy to use and V o H can be said to be stable. Therefore, V o H is related to carrier traps To find out how V o The transition levels of H were calculated.

[0499] The calculation was performed using an InGaZnO4 crystal model (112 atoms). 1 and V for oxygen site 2 o An H model was created and the transition level was calculated. The conditions are shown in Table 2.

[0500] [Table 2]

[0501] By adjusting the mixing ratio of the exchange terms to obtain a band gap close to the experimental value, we obtained a defect-free The band gap of the InGaZnO4 crystal model is 3.08 eV, which is lower than the experimental value of 3.15 The result was close to eV.

[0502] The transition level (ε(q / q')) of the model with defect D is calculated by the following equation 2: . Note that ΔE(D q ) is the formation energy of defect D at charge q, calculated using Eq. 3 will be done.

[0503]

number

[0504]

number

[0505] In Equation 2 and Equation 3, E tot (D q ) is the total charge q of the model including the defect D. Energy, E tot (bulk) is the total energy of a defect-free model (perfect crystal), Δ n i is the number of atoms i that are added or removed due to the defect, μ i is the chemical potential of atom i, ε VBM is a defect The energy of the top of the valence band in the model without q is the compensation for the electrostatic potential positive term, E F is the Fermi energy.

[0506] Calculated V o The transition levels of H are shown in Figure 45. The values ​​in Figure 45 represent the depth from the bottom of the conduction band. From Figure 45, V for oxygen site 1 o The transition level of H is 0.05 below the conduction band edge. eV, and V for oxygen site 2 o The transition level of H is 0.11 eV below the conduction band edge. Since each V o H is thought to be involved in electron trapping. V o It was revealed that H acts as a donor. o IGZO with H It was found to be conductive.

[0507] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0508] (Embodiment 14) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0509] FIG. 46A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908 The portable game machine shown in FIG. 46A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0510] FIG. 46(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and and a display device to which a function as a position input device is added to at least one of the first display unit 911 and the second display unit 912. The function as a position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device. can be done.

[0511] FIG. 46(C) shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard, and a keyboard. The computer has a keyboard 923, a pointing device 924, and the like.

[0512] FIG. 46(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband 9 33, etc. The display unit 932 may be a touch panel.

[0513] FIG. 46(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0514] FIG. 46(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a lamp. It has Ito 954 etc.

[0515] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0516] (Embodiment 15) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. 47 . RF tags are used in a wide range of applications, including banknotes, coins, securities, and bearer Bonds, certificates (driver's license, resident card, etc., see Figure 47(A)), vehicles (bicycles, etc., see Figure 47(A)) 47(B), packaging containers (wrapping paper, bottles, etc., see Fig. 47(C)), recording media ( DVDs (see Figure 47(D) and videotapes, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( LCD displays, EL displays, televisions, or mobile phones) or other items It can be attached to tags attached to each item (see Figure 47 (E) and (F)) and used. .

[0517] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, if it is a book, it is embedded in the paper, and if it is a package made of organic resin, it is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each product. The 4000 is small, thin, and lightweight, so even after being fixed to an item, it does not change the design of the item itself. In addition, banknotes, coins, securities, bearer bonds, or certificates By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to various items, such as items, recording media, personal belongings, food, clothing, household goods, or electronic devices. By attaching RF tags according to the above, the efficiency of systems such as inspection systems can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0518] As described above, the RF tag according to one aspect of the present invention is used for each of the applications listed in this embodiment. This reduces the operating power consumption, including the writing and reading of information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even when the power is cut off. Therefore, it can be used for applications where the frequency of writing and reading is low. Cut.

[0519] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. (Embodiment 16)

[0520] <Film formation model> The following describes the film formation models for CAAC-OS and nc-OS.

[0521] FIG. 58(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0522] The target 5130 is glued onto a backing plate. A plurality of magnets are disposed under the backing plate. Therefore, a magnetic field is generated above the target 5130. Film formation is performed using the magnetic field of the magnet. A sputtering method that increases the rate is called magnetron sputtering.

[0523] The target 5130 has a polycrystalline structure, and each crystal grain includes a cleavage plane. The cleavage plane will be described in detail later.

[0524] The substrate 5120 is disposed facing the target 5130, and the distance d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is set to 0.02 m or more and 0.5 m or less. Most of the film deposition gas (e.g., oxygen) It is filled with a gas mixture containing hydrogen, argon, or oxygen at a ratio of 50% by volume or more, and The pressure is controlled to 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge begins and plasma is generated. It is confirmed that a high density plasma region is formed by the magnetic field on the target 5130. In the high density plasma region, the deposition gas is ionized, generating ions 5101. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (Ar + ) etc.

[0525] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. 5100a and pellet 5100b are impacted by the impact of ions 5101 into the structure. Distortion may occur.

[0526] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, the shape may be made up of 2 to 6 triangles. In some cases, two squares (or polygons) are joined together to form a quadrilateral (diamond).

[0527] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes.

[0528] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. For example, if pellet 5100a has negatively charged oxygen atoms on its side, An example of a sphere with a charge of the same polarity is shown in Figure 60. The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, the indium, gallium, and zinc atoms bonded to The oxygen atom may be negatively charged.

[0529] As shown in FIG. 58(A), for example, a pellet 5100 flies like a kite through the plasma. The pellet 5100 then flutters up onto the substrate 5120. Therefore, when an area where other pellets 5100 are already deposited approaches, a repulsive force is generated. Here, a magnetic field parallel to the upper surface of the substrate 5120 is generated on the upper surface of the substrate 5120. In addition, since a potential difference is applied between the substrate 5120 and the target 5130, A current flows from the substrate 5120 to the target 5130. 5100 is a substrate 5120 with a force (roller) generated by the action of a magnetic field and an electric current on the upper surface of the substrate 5120. This can be understood by Fleming's left-hand rule. In order to increase the force applied to the pellet 5100, the upper surface of the substrate 5120 In the above, the magnetic field parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more. It is preferable to provide a region where the resistance is 30 G or more, and more preferably 50 G or more. Alternatively, on the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 is applied to the substrate The magnetic field strength is 1.5 times or more, preferably 2 times or more, more preferably 1.5 times or more, of the magnetic field in the direction perpendicular to the top surface of 5120. It is advisable to provide a region where the density is at least three times, more preferably at least five times.

[0530] In addition, the substrate 5120 is heated, and friction between the pellet 5100 and the substrate 5120 is reduced. As a result, as shown in FIG. 62(A), pellet 5 The pellet 5100 glides over the upper surface of the substrate 5120. This occurs with the flat surface facing the substrate 5120. After that, as shown in FIG. 62(B), When the pellets reach the sides of other piled pellets 5100, the sides join together. When the oxygen atom is released from the side of the pellet 5100, Since oxygen vacancies in CAAC-OS can be filled, CAAC-O with low defect level density can be obtained. It becomes S.

[0531] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, causing defects such as grain boundaries. In addition, the gaps are filled with elastic metal atoms, etc. The sides of the 5100 pellets, which are laid out and misaligned, are connected like a highway. It is thought that...

[0532] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface to be formed does not have a crystalline structure, For example, it is possible to form a CAAC-OS film on the substrate 5120. CAAC-OS can be deposited even if the top surface (surface to be formed) has an amorphous structure. is.

[0533] In addition, the CAAC-OS can be applied not only to a flat surface but also to the surface of the substrate 5120 on which the CAAC-OS is to be formed. It can be seen that even if the surface is uneven, the pellets 5100 are arranged along the shape of the surface. For example, if the top surface of the substrate 5120 is atomically flat, the pellet 5100 will be flat with the ab plane. The flat surface is placed facing downwards, resulting in a uniform thickness, flatness, and high crystallinity. Then, by stacking these layers n levels (n is a natural number), AC-OS can be obtained (see Figure 58(B)).

[0534] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510 The structure is made up of n layers (n is a natural number) of 0s arranged along the convex surface. Since the surface 20 has unevenness, gaps tend to occur between the pellets 5100. However, there is an intermolecular force between the pellets, so even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. This can be a CAAC-OS (see FIG. 58(C)).

[0535] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is a problem, uniform film formation is possible.

[0536] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0537] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0538] In addition to the pellet 5100, CAAC-OS also has a coating model with zinc oxide particles. This can also be explained.

[0539] The zinc oxide particles have a smaller mass than the pellets 5100 and therefore reach the substrate 5120 first. On the upper surface of the substrate 5120, zinc oxide particles grow preferentially in the horizontal direction. A thin zinc oxide layer is formed by the above process. The zinc oxide layer has a c-axis orientation. The c-axis of the lead layer crystal is oriented parallel to the normal vector of the substrate 5120. The CAAC-OS crystals were grown on the substrate, which acted as a seed layer for CAAC-OS growth. The zinc oxide layer has a thickness of 0.1 nm or more and 5 nm or less. Most of the zinc oxide layer is between 1 nm and 3 nm thick. The zinc oxide layer is thin enough that it barely crosses the grain boundaries. It is difficult to confirm.

[0540] Therefore, to form a highly crystalline CAAC-OS film, a higher than stoichiometric composition is required. It is preferable to use a target containing a small proportion of zinc.

[0541] Similarly, the nc-OS can be understood by the film formation model shown in Figure 59. The only difference between FIG. 59 and FIG. 58(A) is whether or not the substrate 5120 is heated.

[0542] Therefore, the substrate 5120 is not heated, and the space between the pellet 5100 and the substrate 5120 As a result, the pellet 5100 is pressed against the substrate 51 Since it cannot glide across the top surface of the 20, it falls and accumulates irregularly. You can get nc-OS by

[0543] <cleavage plane> Below, we explain the cleavage plane of the target described in the CAAC-OS film formation model. do.

[0544] First, the cleavage plane of the target will be explained using Figure 63. The crystal structure of O4 is shown in Figure 63(A). The c-axis is pointing upward and parallel to the b-axis. The structure of the InGaZnO4 crystal is shown when observed from the c-axis. The figure shows the structure of an InGaZnO4 crystal when observed from a direction parallel to the plane.

[0545] The energy required for cleavage on each crystal plane of an InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using a pseudopotential and a density functional process using a plane wave basis. The pseudopotential used is an ultra-soft pseudopotential (CASTEP). The functional is GGA PBE. The energy is set to 400 eV.

[0546] The energy of the structure in the initial state is derived after structural optimization including the cell size. In addition, the energy of the structure after cleavage on each plane is calculated by the atomic arrangement with the cell size fixed. It is derived after structural optimization of the position.

[0547] Based on the crystal structure of InGaZnO4 shown in Figure 63, the first, second, and third planes A structure cleaved at either of the fourth planes was fabricated, and structural optimization calculations were performed with the cell size fixed. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and (0 The second plane is a crystal plane parallel to the α-plane (or ab-plane) (see Figure 63(A)). The crystal plane between the Ga-Zn-O layers is the (001) plane (or ab The third plane is a crystal plane parallel to the (110) plane (see Figure 63(A)). The fourth plane is a crystal plane (see Figure 63(B)). It is a straight crystal plane (see Figure 63(B)).

[0548] Under the above conditions, the energy of the structure after cleavage on each plane is calculated. The difference between the energy of the structure and the energy of the initial state is divided by the area of ​​the cleavage plane. The cleavage energy, which is a measure of the ease of cleavage on each plane, is calculated. Energy is the kinetic energy of the electrons and the interatomic and atomic energies of the atoms and electrons contained in the structure. -This is the energy that takes into account the interactions between electrons and electrons themselves.

[0549] As a result of calculations, the cleavage energy of the first facet is 2.60 J / m 2 , the cleavage energy of the second face is 0.68J / m 2 , the cleavage energy of the third face is 2.18 J / m 2 , 4th plane cleavage Energy is 2.12J / m 2 It was found that (see table below).

[0550] [Table 3]

[0551] From this calculation, in the crystal structure of InGaZnO4 shown in Figure 63, The cleavage energy is lowest between the Ga-Zn-O layer and the Ga-Zn-O layer. is the plane (cleavage plane) that is easiest to cleave. When referring to the cleavage plane, it refers to the second plane, which is the plane that is easiest to cleave.

[0552] Since the cleavage plane is on the second plane between the Ga-Zn-O layers, the structure shown in FIG. 6 The InGaZnO4 crystal shown in 3(A) can be separated by a plane equivalent to two second planes. Therefore, when ions or the like are bombarded with the target, the highest cleavage energy is The minimum size is a wafer-like unit (we call it a pellet) cleaved along the lower plane of the In this case, the InGaZnO4 pellets are It consists of three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0553] The first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, which is the (001) plane ( The third plane (crystal plane parallel to the (110) plane) and the fourth plane (crystal plane parallel to the (110) plane) are more closely spaced than the ab plane. Since the cleavage energy of the plane (crystal plane parallel to the (100) plane (or bc plane)) is low, This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0554] Next, classical molecular dynamics calculations were performed to identify the target InGaZ Assuming a crystal of nO4, the target is spat out with argon (Ar) or oxygen (O). The cleavage plane of the InGaZnO4 crystal (268 8 atoms) is shown in Fig. 64(A) and the top view structure is shown in Fig. 64(B). The fixed layer shown in A) is a layer in which the atomic arrangement is fixed so that the position does not fluctuate. The temperature control layer shown in 4(A) is a layer that is always kept at a constant temperature (300K).

[0555] For classical molecular dynamics calculations, Fujitsu Materials Explorer 5. 0 is used. The initial temperature is 300K, the cell size is constant, and the time step width is 0.01 The calculation assumes that the atom is subjected to 300e V energy is applied, and atoms are introduced into the cell from a direction perpendicular to the ab plane of the InGaZnO4 crystal. Let it enter.

[0556] FIG. 65(A) shows the state where argon is incident on the cell having the InGaZnO4 crystal shown in FIG. Figure 65(B) shows the atomic arrangement 99.9 picoseconds (psec) after the cell The atomic arrangement is shown in Figure 65, 99.9 picoseconds after oxygen is incident on the A part of the fixed layer shown in A) is omitted.

[0557] From Figure 65(A), within 99.9 picoseconds after argon entered the cell, Therefore, cracks occur from the cleavage plane corresponding to the second plane shown in Fig. 1. When argon collides with the crystal, the top surface is the second surface (0th), and the second surface (2 It can be seen that large cracks occur in the first (second) crack.

[0558] On the other hand, from Figure 65(B), within 99.9 picoseconds after oxygen entered the cell, the ) and the cracks start from the cleavage plane corresponding to the second plane shown in Fig. 1. When the collision occurs, a large crack occurs on the second (first) surface of the InGaZnO4 crystal. It can be seen that...

[0559] Therefore, from the top surface of the target containing InGaZnO4 crystals with a homologous structure When atoms (ions) collide with the InGaZnO4 crystal, the InGaZnO4 crystal cleaves along the second plane, forming a flat surface. It can be seen that plate-shaped particles (pellets) peel off. At this time, the size of the pellets is It was found that the collision with oxygen was smaller than that with argon. do.

[0560] The above calculations suggest that the detached pellet contains a damaged area. The damaged area contained in the nucleus can be repaired by reacting oxygen with the defects caused by the damage. There is a match.

[0561] Therefore, we investigated whether the pellet size differs depending on the atom that is collided. do.

[0562] In FIG. 66(A), argon is incident on the cell having the InGaZnO4 crystal shown in FIG. After that, the trajectories of each atom are shown from 0 picoseconds to 0.3 picoseconds. 6(A) corresponds to the period between FIG. 64 and FIG. 65(A).

[0563] From Figure 66(A), it can be seen that argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer). When the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer), the zinc It can be seen that lead reaches the vicinity of the sixth layer (Ga-Zn-O layer). The argon that hits the substrate is repelled outwards. When argon is bombarded onto the target, a crack appears on the second surface (2nd) in Figure 64(A). It is thought that this will be included.

[0564] Also, in FIG. 66(B), oxygen enters the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom is shown from 0 picoseconds to 0.3 picoseconds after irradiation. 66(B) corresponds to the period between FIG. 64 and FIG. 65(A).

[0565] On the other hand, as shown in Figure 66(B), oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that zinc does not reach the fifth layer (In-O layer). Therefore, the target containing InGaZnO4 crystals is When the element is collided, it is thought that a crack will appear on the second surface (first surface) in Figure 64(A). do.

[0566] From this calculation, it can be seen that when atoms (ions) collide with InGaZnO4 crystals, It is suggested that peeling occurs.

[0567] In addition, we will consider the difference in crack depth from the viewpoint of conservation laws. The existence law can be expressed as Equation 4 and Equation 5, where E is the argon concentration before the collision. Or the energy of oxygen (300 eV), m A is the mass of argon or oxygen, v A teeth The velocity of argon or oxygen before the collision, v' A is the velocity of argon or oxygen after the collision, m G a is the mass of gallium, v Ga is the velocity of gallium before the collision, v' Ga is the mass of gallium after the collision It's speed.

[0568]

number

[0569]

number

[0570] Assuming that the collisions of argon or oxygen are elastic, v A , v' A , v Ga and v' Ga The relationship can be expressed as in Equation 3.

[0571]

number

[0572] From Equation 4, Equation 5 and Equation 6, v Ga If argon or oxygen collides, The velocity of gallium after Ga can be expressed as in Equation 7.

[0573]

number

[0574] In Equation 7, m A Substitute the mass of argon or the mass of oxygen into The velocity of gallium after the collision is compared. The energy of argon and oxygen before the collision is For the same amount of oxygen, the impact of argon is 1.24 times greater than that of oxygen. We can see that the velocity of gallium is high. Therefore, the energy of gallium is also higher than that of argon. When an electron collides with an electron, the velocity is higher by the square of the velocity than when an oxygen collides with an electron.

[0575] When argon is bombarded, the speed of gallium after the bombardment is higher than when oxygen is bombarded. Therefore, when argon is collided with the However, it is believed that cracks occurred at a deeper position than when oxygen was bombarded.

[0576] From the above calculations, the target containing InGaZnO4 crystals with a homologous structure was It can be seen that when sputtered, the cleaved surface peels off and a pellet is formed. Sputtering other structural areas of the target that do not have the pores does not result in pellet formation. The sputtered particles are formed at the atomic level, which is smaller than the particles. Since it is smaller than the nozzle, it can be easily evacuated via a vacuum pump connected to the sputtering system. Therefore, the crystal of InGaZnO4 with homologous structure When a target containing gallium is sputtered, particles of various sizes and shapes fly to the substrate and are deposited. It is difficult to imagine a model in which a film is formed by depositing sputtered pellets. The model shown in Figure 58(A) for forming an -OS film is reasonable.

[0577] The density of the CAAC-OS film formed in this way is comparable to that of single-crystal OS. For example, the density of a single crystal OS with a homologous structure of InGaZnO4 is 6.36 g / cm 3 In contrast, the density of CAAC-OS, which has a similar atomic ratio, is 6.3 g / cm 3 It will be about that amount.

[0578] Figure 67 shows the In-Ga-Zn oxide (CAAC-OS) film formed by sputtering. See Figure 67(A).) and the element in the cross section of its target (see Figure 67(B). The atomic arrangement is shown. High-angle scattering annular dark-field scanning transmission electron microscopy (HAA) was used to observe the atomic arrangement. DF-STEM:High-Angle Annular Dark Field Sc anning Transmission Electron Microscopy) In HAADF-STEM, the image intensity of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31) have similar atomic numbers. The HAADF-STEM uses a Hitachi HD-270 scanning transmission electron microscope. Use 0.

[0579] Comparing Figure 67(A) and Figure 67(B), both CAAC-OS and the target It can be seen that they have homologous structures and the arrangement of their atoms corresponds to each other. Therefore, as shown in the film formation model in Figure 58(A), the crystal structure of the target is transferred. It can be seen that a CAAC-OS film is formed by this.

[0580] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. [Example]

[0581] In this example, the source region and the drain region of a transistor of one embodiment of the present invention are The experimental results regarding the plasma processing method for forming the transistor structure are described below. is equivalent to the transistor 101 shown in FIG.

[0582] In this embodiment, the presence or absence of a resist mask on the gate electrode layer during plasma processing is a condition. Two types of transistors were fabricated using the above method. The fabrication methods are described in detail below.

[0583] A glass substrate is used as the substrate, and a 100 nm nitride film is formed on the glass substrate as an underlying insulating film. A laminated film of a silicon film and a 400 nm silicon oxynitride film is formed by plasma CVD. did.

[0584] Next, the heat treatment on the base insulating film is performed using RTA (Rapid Thermal Anneal). The heating was carried out at 650°C for 6 minutes.

[0585] Next, a 5 nm thick tantalum nitride film is formed on the base insulating film, and the nitride film is then etched by oxygen plasma treatment. Oxygen was added to the base insulating film through the tantalum film.

[0586] Next, a sputtering method was used to deposit 50 An oxide semiconductor film having a thickness of nm was formed.

[0587] Next, the oxide semiconductor film was subjected to heat treatment at 450° C. in a nitrogen atmosphere for 1 hour. The reaction was carried out in an oxygen mixed atmosphere for 1 hour.

[0588] Next, the oxide semiconductor film is selectively etched to form an oxide semiconductor layer. A 100 nm silicon oxynitride film, which will become the gate insulating film, is deposited on the conductor layer by plasma CVD. The film was formed.

[0589] Next, a 30 nm tantalum nitride film and a 150 nm tantalum nitride film are deposited on the gate insulating film to form the gate electrode layer. The tungsten film was formed by sputtering.

[0590] Next, a resist mask is formed on the tungsten film, and the tungsten film and tantalum nitride film are The silicon oxynitride film and the silicon oxide semiconductor film are selectively etched in this order to remove a part of the oxide semiconductor layer (the first region The first and second regions were exposed.

[0591] Next, the conditions for whether or not the resist mask is peeled off are set, and plasma processing is performed under the same conditions. For plasma processing, a true plasma processing system was used, which can apply high frequency power (13.56 MHz) between a pair of electrodes. The substrate was placed on the cathode side, and the substrate temperature was 20°C and the pressure was 5 Pa. Power density of 0.47 or 0.94 W / cm in a pressurized atmosphere 2 A high frequency is applied to generate plasma. The mixture was allowed to stand for 1 minute.

[0592] Next, a 100 nm thick silicon nitride film containing hydrogen is formed on the above structure. A 300 nm silicon oxynitride film was formed on the film. Both were formed using the plasma CVD method. The film was formed.

[0593] Next, the first and second regions of the oxide semiconductor layer are formed on the silicon nitride film and the silicon oxynitride film. A contact hole leading to region 2 was formed.

[0594] Next, a 50 nm tungsten film and a 400 nm aluminum film were deposited to cover the contact holes. A laminate consisting of a 100 nm thick aluminum film and a 100 nm thick titanium film was formed in this order using the sputtering method. The stacked layers were selectively etched to form a source electrode layer and a drain electrode layer.

[0595] Next, a silicon nitride film is formed on the above structure as a passivation film by plasma CVD. Heat treatment was carried out at 350°C for 1 hour in a mixed atmosphere of nitrogen and oxygen.

[0596] A transistor was fabricated by the above method. After the resist mask was removed, plasma treatment was performed. The transistor manufactured by this method is called Transistor A, and the transistor is treated with plasma before the resist mask is removed. The transistor fabricated by carrying out the above steps was designated as transistor B.

[0597] 48(A) and (B) are cross sections of the channel region end in the channel length direction of a transistor. TEM photographs. Figure 48(A) is a cross section of transistor A, and Figure 48(B) is a cross section of transistor B. This is a cross section of Zister B.

[0598] In the case of transistor A, the edge of the gate insulating film has a deposit with a color tone similar to that of the gate electrode layer. It was found that a deposit was formed on transistor B, and no similar deposit was formed on transistor B. do.

[0599] Figures 49(A) and (B) show the analysis results of the transistor fabricated using the same method as the above-mentioned transistor fabrication method. FIG. 49(A) is a cross-sectional view of a sample in the channel length direction. 49(B) is a cross section of a sample corresponding to transistor B. The area enclosed by the square in the center of both cross-sectional images shows EDX (Energy Dispersion X-ray) data. The results of the transverse X-ray spectroscopy analysis are shown in Table 4. .

[0600] [Table 4]

[0601] From Table 4, it is estimated that the deposits on the edge of the gate insulating film in Figure 48(A) are tungsten. The tungsten deposit is formed by sputtering the tungsten film of the gate electrode layer. The fact that no tungsten was detected in transistor B It was found that the resist mask suppressed tungsten sputtering.

[0602] Figures 50(A), (B), and (C) show the Id-Vg characteristics of the fabricated transistor. (A) is 0.94 W / cm after removing the resist mask. 2 Transistors that were plasma treated with Figure 50(B) shows the ID-VG characteristics of the MOS transistor A. cm 2 50 shows the Id-Vg characteristics of the transistor B1 subjected to plasma treatment. (C) is 0.94 W / cm before resist mask removal. 2 Transistors that were plasma treated with This is the Id-Vg characteristics of the power supply B2.

[0603] Transistor A shown in Figure 50(A) has an extremely large gate leakage current (Ig). This is because the tungsten deposits at the edge of the gate insulating film shown in FIG. This is because it is called Kupas.

[0604] On the other hand, in the transistors B1 and B2 shown in FIGS. 50(B) and 50(C), The leak current is sufficiently low. Plasma treatment prevents tungsten deposits from forming on the edge of the gate insulating film. Understood.

[0605] Next, a gate bias-temperature stress test was conducted on the fabricated transistor. In both the dark and bright states, the substrate temperature was 60°C, and the source and drain were connected to a common voltage. The voltage was applied to the gate for 1 hour. The illuminance was set to 10,000 lx.

[0606] Figure 51 shows the results of the gate bias-temperature stress test. The shift value and the Δshift indicate the amount of change in the pressure. is the voltage at which the current rises in the Id-Vg characteristics, and is the drain current (Id: [A]) 1 × 10 -12 This is the value defined as the gate voltage (Vg: [V]) in case A.

[0607] In the gate negative bias test in the bright state, ΔVth, Δshift and The amount of fluctuation is large for both transistors, but the amount of fluctuation is small for transistors B1 and B2. It was found that...

[0608] FIG. 52 shows a top-gate, self-aligned (TGSA) transistor B2 and It is the same TGSA type as transistor B2, and has ion doping in the source and drain regions. The transistors were doped with argon in a lithography system and channel-etched bottom gate top contact transistors. Comparison of negative gate bias-temperature stress test results with contact-type transistor (BGTC) The vertical axis is -ΔVth and the horizontal axis is stress time. The ping was performed at an acceleration voltage of 10 kV with a dose of 5E 14 ions / cm 2 Also, BG For the TC transistor, the gate bias was set to -30V and the transistor The size of the transistor is L / W=6 / 576 μm, which is different from the TGSA transistor. different.

[0609] As shown in FIG. 52, the transistor B2 that has been subjected to the argon plasma treatment has a threshold voltage It was found that the fluctuation of was smaller than that of other transistors.

[0610] Figure 53 shows a channel-protected bottom-gate transistor (BGTC) This is a comparison of the results of tests in which positive and negative biases were applied alternately to the gate in the dark. The size of the channel-protected bottom-gate transistor is L / W=10.2 / 8. The gate bias was set to ±30V.

[0611] As shown in FIG. 53, the transistor B2 that was subjected to the argon plasma treatment has a short L length. However, it was found that the fluctuation of the threshold voltage was small.

[0612] As a result, the source and drain regions are formed by argon plasma treatment. The fabricated transistor was found to have good electrical characteristics and reliability.

[0613] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. [Example]

[0614] In this example, a sample corresponding to a transistor of one embodiment of the present invention was fabricated. The region corresponding to the source region and drain region of the capacitor, and the region corresponding to the channel region The results of the SIMS analysis are explained below.

[0615] First, an oxide semiconductor layer was formed on a glass substrate in accordance with the method for fabricating a transistor described in Example 1. (IGZO), gate insulating film (silicon oxynitride), gate electrode layer (tantalum nitride, tantalum After forming the structure shown in FIG. 54(A), the structure is Argon was injected from above using an ion doping device at 30 kV and a dose of 1.0E15 ions. / cm 2 The addition was performed under the following conditions: An insulating layer was formed between the glass substrate and the oxide semiconductor layer. The manufacturing method of the transistor is different from that of the transistor. A sample without the addition was also prepared.

[0616] Next, a silicon nitride film containing hydrogen is formed on the above structure in accordance with the manufacturing method of a transistor, as shown in FIG. After forming the structure shown in 4(B), regions X (corresponding to the source and drain regions) and SIMS analysis of hydrogen was performed on region Y (corresponding to the channel region). The S analysis was performed from the glass substrate side.

[0617] Figures 55(A) and (B) show the depth profile of hydrogen in region X. Figure 55(B) shows the analysis results of the sample with argon added, and Figure 55(C) shows the results of the sample without argon added. The results of the analysis of the oxide semiconductor layer in region X of the sample to which argon was added are shown in Fig. The hydrogen concentration is 4 x 10 20 In contrast, the sample without argon added showed a much higher It was found to be smaller.

[0618] Also, Figure 56(A) and (B) show the depth profile of hydrogen in region Y. (A) shows the analysis results of a sample with argon added, and (B) shows the results without argon added. The results of the sample analysis. In area Y, the hydrogen depth with and without argon addition No change in profile, but lower hydrogen concentration than region X of the argon-added sample I found out that...

[0619] As a result, in the transistor configuration, the source region and the drain region to which argon is added are It was revealed that the junction region has a region with a higher hydrogen concentration than the channel region.

[0620] That is, by adding argon, oxygen vacancies are formed in the oxide semiconductor layer, and the oxide Hydrogen diffuses from the nitride insulating film containing hydrogen formed in contact with the oxide semiconductor layer into the oxide semiconductor layer. It was shown that

[0621] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0622] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0623] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0624] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0625] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, the upper limit of a certain value can be set. When a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, one aspect of the invention that excludes part of the scope is defined. ...

Claims

[Claim 1] A semiconductor device including a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers, the oxide semiconductor layer has a region in contact with the first insulating layer, the first conductive layer is electrically connected to the oxide semiconductor layer, and the second conductive layer is electrically connected to the oxide semiconductor layer; the second insulating layer has a region in contact with the oxide semiconductor layer, the third conductive layer has a region in contact with the second insulating layer, the second insulating layer has a region that can function as a gate insulating film; the first conductive layer has a region that can function as one of a source electrode and a drain electrode; the second conductive layer has a region that can function as the other of the source electrode and the drain electrode, the third conductive layer has a region that can function as a gate electrode; the oxide semiconductor layer has first to third regions, the first region and the second region are provided apart from each other, the third region is provided between the first region and the second region, and the third region and the third conductive layer have an overlapping region with the second insulating layer interposed therebetween; The first region and the second region have portions having a higher carbon concentration than the third region.

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