Semiconductor device

Abstract

To provide a semiconductor device having a structure capable of suppressing deterioration of electric characteristics which becomes noticeable at the time of miniaturization.SOLUTION: A semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film on the second oxide film, and a gate electrode in contact with the gate insulating film, and the upper end portion of the oxide semiconductor film in the channel width direction has a curved surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices such as: Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. It is being done.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. are.

[0005] In addition, a technique for improving carrier mobility by forming an oxide semiconductor film into a stacked structure is also known. are disclosed in Patent Documents 2 and 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-124360 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-138934 Summary of the Invention [Problem to be solved by the invention]

[0007] Generally, miniaturization of transistors is an essential technology for increasing circuit integration. When transistors are miniaturized, the on-current, threshold voltage, S value (subthreshold value), etc. It is known that the electrical characteristics of the transistor deteriorate.

[0008] For example, in silicon transistors, shortening the channel length leads to subthreshold Short channel effects such as deterioration of the stress coefficient (S value) and shift of the threshold voltage to the negative side occur. It is known that

[0009] On the other hand, transistors using oxide semiconductors have an accumulation layer with electrons as the majority carrier. Since it is a transistor that uses an inversion gate of silicon, etc. Shorter channel transistors than transistors with a layer channel (also called inversion transistors) Drain-Induced Barrier Lowering (DIBL) occurs in A transistor using an oxide semiconductor has resistance to the short-channel effect. This can also be rephrased.

[0010] Furthermore, there is a concern that reducing the channel width of a transistor may result in a decrease in on-state current. To improve flow, the active layer is thickened so that channels are formed on the sides of the active layer. There are also known methods for increasing the surface area where channels are formed, which leads to the formation of channels in the channel-forming region. The scattering of carriers increases at the interface between the gate insulating film and the semiconductor region, so a sufficient improvement in on-current cannot be obtained. It's not easy to get into.

[0011] Therefore, one embodiment of the present invention can suppress deterioration of electrical characteristics that becomes significant with miniaturization. It is an object of the present invention to provide a semiconductor device having a highly integrated structure. Another object is to provide a semiconductor device in which deterioration of on-state current is reduced. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a highly reliable semiconductor device. Another object of the present invention is to provide a semiconductor device that retains data even when the power supply is cut off. Another object is to provide a novel semiconductor device.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention relates to a semiconductor device including stacked oxide semiconductor films.

[0014] One embodiment of the present invention is a semiconductor device including a first oxide film, an oxide semiconductor film on the first oxide film, and an oxide semiconductor film. a source electrode and a drain electrode in contact with the oxide semiconductor film; a second oxide film on the drain electrode; a gate insulating film on the second oxide film; and a gate insulating film. a gate electrode in contact with the oxide semiconductor film, and an upper end portion of the oxide semiconductor film in a channel width direction has a curved surface. The semiconductor device is characterized by having:

[0015] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of constituent elements. It should be noted that the numbers are added to indicate the number of items to be processed, and are not intended to limit the number of items.

[0016] In the above structure, the top surface of the oxide semiconductor film may have a flat portion.

[0017] In the above structure, the radius of curvature r of the end portion in the channel width direction of the oxide semiconductor film (end If there are two, each radius of curvature (r1, r2) is greater than 0 and less than half the channel width W. (0 <r(または、r1、r2)≦W / 2)である。

[0018] In the above structure, an upper end of the second oxide film coincides with a lower end of the gate insulating film, The upper end of the gate insulating film may coincide with the lower end of the gate electrode.

[0019] In the above structure, the first oxide film and the second oxide film are made of a material having a higher insulating property than an oxide semiconductor film. The energy of the conduction band minimum is in the range of 0.05 eV to 2 eV, which is close to the vacuum level. is preferred.

[0020] In the above structure, the first oxide film, the oxide semiconductor film, the source electrode, the drain electrode a second oxide film, a gate insulating film, and a barrier film that contacts and covers the gate electrode; Good too.

[0021] In the above structure, the first oxide film, the oxide semiconductor film, and the source The semiconductor device may have a first sidewall insulating film provided on the sidewalls of the electrode and the drain electrode.

[0022] In the above structure, the second oxide film, the gate insulating film and the gate insulating film are connected via the barrier film. The semiconductor device may have a second sidewall insulating film provided on the sidewall of the back electrode. [Effects of the Invention]

[0023] By using one embodiment of the present invention, it is possible to suppress deterioration of electrical characteristics that becomes significant with miniaturization. Alternatively, a semiconductor device with a high degree of integration can be provided. Alternatively, a semiconductor device in which deterioration of on-state current is reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device that retains data even when the power is cut off can be provided. Alternatively, a novel semiconductor device can be provided. The description of these effects does not preclude the existence of other effects. The method does not necessarily have to have all of these effects. In addition, effects other than these may include: It is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 2] FIG. 2 is a diagram illustrating the band structure of a multilayer film. [Figure 3] FIG. [Figure 4] FIG. 1 is a cross-sectional view of a transistor in a channel width direction. [Figure 5] FIG. 1 is a cross-sectional view of a transistor in a channel width direction. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 7] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] 1A and 1B are cross-sectional STEM photographs of transistors fabricated in Examples. [Figure 11] 10A to 10C illustrate evaluation of electrical characteristics of transistors fabricated in Examples. [Figure 12] 10A to 10C illustrate evaluation of electrical characteristics of transistors fabricated in Examples. [Figure 13] 10A to 10C illustrate evaluation of electrical characteristics of transistors fabricated in Examples. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 16] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 17] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 18] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 19] 1A and 1B illustrate an inverter using a semiconductor device of one embodiment of the present invention. [Figure 20] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 21] 1 is a block diagram of a semiconductor device according to an embodiment; [Figure 22] FIG. 1 is a circuit diagram illustrating a memory device according to an embodiment. [Figure 23] 1. An electronic device according to an embodiment. [Figure 24] FIG. 1 is an equivalent circuit diagram illustrating an example of a semiconductor device. [Figure 25] FIG. 1 is a cross-sectional view of a transistor in a channel width direction. [Figure 26] FIG. 1 is a cross-sectional view of a transistor in a channel length direction. [Figure 27] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 28]FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 29] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 30] FIG. 10 is a graph showing the temperature dependence of a transistor. [Figure 31] FIG. 10 is a graph showing the temperature dependence of a transistor. [Figure 32] 1A and 1B are diagrams illustrating the reliability of transistors. [Figure 33] 1A and 1B are diagrams illustrating the reliability of transistors. [Figure 34] 10A and 10B are diagrams showing electrical characteristics of a transistor. [Figure 35] 10A and 10B are diagrams showing electrical characteristics of a transistor. [Figure 36] Schematic diagram of transistor structure. [Figure 37] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of oxide semiconductor films. [Figure 38] FIG. 1 is a diagram showing an example of a transmission electron diffraction measurement device. [Figure 39] FIG. 1 is a diagram showing an example of structural analysis by transmission electron diffraction measurement. [Figure 40] FIG. 10 is a graph showing the temperature dependence of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. and variations in form and details may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that modifications may be made. It should not be construed as being limited to the description of the embodiments. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The following terms will be used throughout the text, and repeated explanations may be omitted.

[0026] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0027] 1A to 1C are top views and cross-sectional views of a transistor of one embodiment of the present invention. FIG. 1(A) is a top view, and the cross section of the dashed line AB shown in FIG. 1(A) is shown in FIG. 1(B). , the cross section of the dashed line CD corresponds to FIG. 1(C). For clarity, some elements are omitted in the illustration. The longitudinal direction, or the dashed line CD direction, is sometimes called the channel width direction. The length of the channel forming region in the direction in which carriers flow. The width refers to the length of the channel forming region in the direction perpendicular to the channel length direction.

[0028] The transistor 450 shown in FIGS. 1A to 1C includes a base insulating film 4 02, and the first oxide film 404a and the oxide semiconductor film 404b over the base insulating film 402. , the source electrode 406a and the source electrode 406b on the first oxide film 404a and the oxide semiconductor film 404b. The drain electrode 406b, the oxide semiconductor film 404b, the source electrode 406a, and the drain A second oxide film 404c on the electrode 406b and a gate insulating film on the second oxide film 404c 408, a gate electrode 410 on the gate insulating film 408, a source electrode 406a, a drain electrode The oxide insulating film 412 is formed on the electrode 406b and the gate electrode 410. The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are collectively referred to as The resulting film is called a multilayer film 404.

[0029] Furthermore, when the channel length and channel width of a transistor are reduced, the resist mask There are cases where the ends of electrodes, semiconductor films, etc. to be processed have rounded (curved surfaces). The shape of the oxide semiconductor film 404b of this embodiment is such that the upper end portion is rounded when viewed from the cross-section, and it is semi- circular. With such a configuration, the coverage of the gate insulating film 408, gate electrode 410, and oxide insulating film 412 formed on the oxide semiconductor film 404b can be improved. Also, the electric field concentration that may occur at the ends of the source electrode 406a and drain electrode 406b can be alleviated, and deterioration of the transistor can be suppressed.

[0030] Note that the oxide semiconductor film 404b has a curvature composed of a contact circle with a radius of curvature of r. Note that the radius of curvature is equal to the radius of the contact circle of the curve. Also, the oxide semiconductor film 404b may have curvatures composed of different contact circles at two or more locations.

[0031] Specifically, the oxide semiconductor film 404b shown in FIG. 1 has a radius of curvature r1 at the upper end portion in the channel width direction, and a radius of curvature r2 at the upper end portion in the channel width direction that is separated from the upper end portion having the radius of curvature r1 by the channel width W. It is preferable that r1 and r2 are greater than 0 and less than or equal to half of the channel width W (0 < r1, r2 ≦ W / 2 ). Also, as shown in FIG. 6(C), when there is no flat portion on the upper surface of the oxide semiconductor film 404b in the channel width direction, it is preferable that the radius of curvature r3 of the upper end portion is greater than 0 and less than or equal to half of the channel width W (0 < r3 ≦ W / 2).

[0032] Note that the functions of "source" and "drain" of the transistor may be interchanged when different polarities of transistors are adopted or when the direction of current changes in the circuit operation. For this reason, in this specification, the terms "source" and "drain" are interchangeable. can be used instead.

[0033] The substrate 400 is not limited to being a simple support material, but also includes a substrate on which other devices such as transistors are formed. In this case, the gate electrode 410 and the source electrode 420 of the transistor 450 may be formed on a substrate. At least one of the drain electrode 406a and the drain electrode 406b is electrically connected to the other devices. The power supply may be electrically connected.

[0034] The base insulating film 402 has a role of preventing the diffusion of impurities from the substrate 400. Therefore, the base insulating film 402 can serve to supply oxygen to the base insulating film 404. The insulating film preferably contains oxygen, and the insulating film preferably contains oxygen in an amount greater than the stoichiometric composition. As described above, it is more preferable that the substrate 400 is a substrate on which other devices are formed. In this case, the base insulating film 402 also functions as an interlayer insulating film. Since the surface of the insulating film 402 is uneven, it is necessary to perform CMP (Chemical Mechanical Polishing) to make the surface flat. It is possible to perform flattening treatment using methods such as mechanical polishing. preferable.

[0035] The base insulating film 402 is formed using an aluminum oxide film that can supply oxygen. The aluminum oxide film is preferably capable of supplying oxygen and also capable of It has the effect of blocking hydrogen, water, and oxygen. The aluminum oxide film containing silicon oxide was formed using a target mixed with silicon dioxide. In this case, the content of silicon oxide is 0.1 wt% or more and 30 wt% or less. It is preferable that:

[0036] In addition, in the region where the channel of the transistor 450 is formed, the multilayer film 404 is From the side of 400, a first oxide film 404a, an oxide semiconductor film 404b, and a second oxide film 404 The oxide semiconductor film 404b has a stacked structure of the first oxide film 4 The structure is surrounded by a first oxide film 404a and a second oxide film 404c. As shown in (C), the gate electrode 410 is formed on the oxide semiconductor film 40 in the channel width direction. It has a structure that electrically surrounds 4b.

[0037] Here, for example, the oxide semiconductor film 404b is formed by the first oxide film 404a and the second oxide film 404b. The electron affinity (energy from the vacuum level to the bottom of the conduction band) is higher than that of the second oxide film 404c. The electron affinity is determined by the energy between the vacuum level and the top of the valence band. The energy difference between the bottom of the conduction band and the top of the valence band (energy The value can be calculated by subtracting the energy gap.

[0038] The first oxide film 404a and the second oxide film 404c are formed on the oxide semiconductor film 404b. The oxide semiconductor film 4 contains one or more constituent metal elements, and the energy of the conduction band minimum is, for example, 0.05eV, 0.07eV, 0.1eV, or 0.15eV or more than 04b and the vacuum level is within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable to form the insulating film from an oxide semiconductor having a similar structure.

[0039] In this structure, when an electric field is applied to the gate electrode 410, A channel is formed in the oxide semiconductor film 404b, which has the lowest energy at the bottom of the conduction band. That is, the second oxide film 40 is formed between the oxide semiconductor film 404b and the gate insulating film 408. By forming 4c, the channel of the transistor does not come into contact with the gate insulating film. It is made of.

[0040] The first oxide film 404a contains one of the metal elements included in the oxide semiconductor film 404b. Since the oxide semiconductor film 404b and the base insulating film 402 are in contact with each other, Compared with the interface, the interface between the oxide semiconductor film 404b and the first oxide film 404a has an interface state The interface state may form a channel, which may cause a transistor failure. Therefore, the provision of the first oxide film 404a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0041] The second oxide film 404c contains one of the metal elements included in the oxide semiconductor film 404b. Since the oxide semiconductor film 404b and the gate insulating film 408 are in contact with each other, Compared with the interface between the oxide semiconductor film 404b and the second oxide film 404c, the capacitance is higher at the interface between the oxide semiconductor film 404b and the second oxide film 404c. Therefore, by providing the second oxide film 404c, This makes it possible to increase the field effect mobility of the transistor.

[0042] The first oxide film 404a and the second oxide film 404c may contain, for example, Al, Ti, G a, Ge, Y, Zr, Sn, La, Ce or Hf is higher than the oxide semiconductor film 404b Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor film has a function of suppressing oxygen vacancies from being generated in the oxide semiconductor film. The first oxide film 404a and the second oxide film 404c are thicker than the oxide semiconductor film 404b. It can be said that oxygen deficiency is unlikely to occur.

[0043] Note that the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c , at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, L a, metal such as Ce or Hf), the first oxide film The oxide semiconductor film 404a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor film 404b is In:M:Zn=x2:y2:z2 [atomic ratio], and the second oxide film 404c was In:M: Zn=x 3: y 3: z3 [atomic ratio], y1 / x1 and y3 / x3 are y2 / x It is preferable that y1 / x1 and y3 / x3 are 1 times greater than y2 / x2. The oxide is preferably 0.5 times or more, more preferably 2 times or more, and even more preferably 3 times or more. In the semiconductor film 404b, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor increases. Therefore, it is preferable that y2 is less than three times x2.

[0044] In, excluding Zn and O in the first oxide film 404a and the second oxide film 404c The atomic ratio of In to M is preferably less than 50 atomic % and M is 50 atomic %. % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more In addition, the atomic ratio of In to M excluding Zn and O in the oxide semiconductor film 404b is In is preferably 25 atomic % or more, and M is less than 75 atomic %, and more preferably Preferably, In is 34 atomic % or more and M is less than 66 atomic %.

[0045] The thickness of the first oxide film 404a and the second oxide film 404c is 3 nm or more and 100 nm or less. The thickness of the oxide semiconductor film 404b is set to be equal to or less than 100 nm, preferably equal to or greater than 3 nm and equal to or less than 50 nm. The thickness is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably The thickness is generally between 3 nm and 50 nm.

[0046] The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c may include, for example, For example, an oxide semiconductor containing indium, zinc, and gallium can be used. In addition, when the oxide semiconductor film 404b contains indium, carrier mobility is increased. preferable.

[0047] In order to provide stable electrical characteristics to a transistor using an oxide semiconductor film as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor film is reduced to make the oxide semiconductor film intrinsic or substantially Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor film is Degrees is 1 x 10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 Less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0048] In addition, part of hydrogen in the oxide semiconductor film is captured by oxygen vacancies, and the oxide semiconductor film becomes an n-type Therefore, an oxide semiconductor film containing a large amount of hydrogen becomes a highly purified intrinsic oxide semiconductor. The Fermi level (Ef) is closer to the bottom of the conduction band (Ec) than the conductive film, The oxide semiconductor film is expected to be intrinsic or substantially intrinsic. Then, the Fermi energy of the oxide semiconductor film is the mid-gap (energy of the oxide semiconductor film). In this case, the oxidation There is concern that a decrease in the number of carriers contained in the compound semiconductor film may result in a decrease in field-effect mobility.

[0049] However, in the transistor of one embodiment of the present invention, the oxide semiconductor film is In addition to the gate field from the top, a gate field from the side is applied. A gate electric field is applied to the entire semiconductor film, and current flows through the entire oxide semiconductor film. This allows for the suppression of fluctuations in electrical characteristics due to the high purity of the intrinsic semiconductor, while also improving the transistor performance. This makes it possible to improve the field effect mobility of the semiconductor.

[0050] In addition, in the oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and gold other than the main component are For example, hydrogen and nitrogen contribute to the formation of donor levels and In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor film. The impurity levels become traps and may degrade the electrical characteristics of a transistor. Therefore, the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 4 It is preferable to reduce the impurity concentration in the O4c film and at the respective interfaces.

[0051] In order to make the oxide semiconductor film intrinsic or substantially intrinsic, SIMS (Second Generation MS) is used. In the analysis of oxide semiconductors, for example, At a certain depth in the conductor film or in a certain region of the oxide semiconductor film, the silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Not yet less than 1×10 18 atoms / cm 3 The company has a portion that is less than The hydrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor film or In a region of the oxide semiconductor film, 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 It has the following parts: The nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor film or , 5×10 in a region of the oxide semiconductor film 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 It has the following parts: It is preferable.

[0052] In addition, when the oxide semiconductor film contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor film may be oxidized. In order to prevent the crystallinity of the oxide semiconductor film from being reduced, For example, the oxide semiconductor film may be formed at a certain depth or in a certain region of the oxide semiconductor film. In the region, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than and In addition, for example, at a certain depth in the oxide semiconductor film, is the carbon concentration in a region of the oxide semiconductor film that is 1×10 19 atoms / cm 3 Not yet less than 5 × 10 18 atoms / cm 3 less than 1×10 18 a toms / cm 3 It is sufficient that the part is less than the above.

[0053] In addition, as described above, a transistor using a highly purified oxide semiconductor film for a channel formation region can be fabricated. The off-state current of a transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, When the voltage is set to about 5V or 10V, the off-state current normalized by the channel width of the transistor is It is possible to reduce the current to a few yA / μm to a few zA / μm.

[0054] Note that insulating films containing silicon are often used as gate insulating films for transistors. For the above reasons, the region serving as the channel of the multilayer film is Therefore, it is preferable that the gate insulating film does not come into contact with the insulating film. When a channel is formed at the interface between the semiconductor and the multilayer film, scattering of carriers occurs at the interface, and From this point of view, the field effect mobility of the multilayer film may be reduced. It is preferable to separate the region that will become the panel from the gate insulating film.

[0055] Therefore, the multilayer film 404 is composed of a first oxide film 404a, an oxide semiconductor film 404b, and a second oxide film 404b. By using a stacked structure of the oxide semiconductor film 404b and the oxide film 404c, a channel is formed in the oxide semiconductor film 404b. This allows the formation of transistors with high field-effect mobility and stable electrical characteristics. It can be achieved.

[0056] Next, the band structure of the multilayer film 404 will be explained. The layer corresponding to the second oxide film 404a and the second oxide film 404c has an energy gap of 3.5e V, an In-Ga-Zn oxide layer corresponding to the oxide semiconductor film 404b, The In-Ga-Zn oxide with a gap of 3.15 eV was used, and the multilayer film 404 was This is done by creating a laminated layer.

[0057] The thicknesses of the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are The energy gap was measured using a spectroscopic ellipsometer (HORIBA J The measurements were performed using a OBIN YVON UT-300. The energy difference between the two edges was determined by ultraviolet photoelectron spectroscopy (UPS). toelectron spectroscopy) equipment (PHI VersaPro be) was measured.

[0058] Figure 2(A) shows the energy difference between the vacuum level and the top of the valence band, and the energy gap of each layer. The energy difference between the vacuum level and the bottom of the conduction band (electron affinity) is calculated as the difference between FIG. 2(A) shows a part of the band structure of the first oxide film 404a and the second oxide film 404b. 1 is a band diagram when a silicon oxide film is provided in contact with the oxide film 404c of FIG. , Ev is the energy of the vacuum level, EcI1 and EcI2 are the minimum conduction bands of the silicon oxide film. EcS1 is the energy of the bottom of the conduction band of the first oxide film 404a, EcS2 is the energy of the bottom of the conduction band of the oxide semiconductor film 404b, and EcS3 is the c is the energy at the bottom of the conduction band.

[0059] As shown in FIG. 2A, the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404b are In the oxide film 404c, the energy of the conduction band minimum changes continuously. The oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c have similar compositions. This can be understood from the fact that oxygen easily diffuses between the first and second oxides. The oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are stacked layers with different compositions. Although it is a layered structure, it can also be said to be physically continuous, and in the drawings, The respective interfaces are shown by dotted lines.

[0060] The multilayer film 404, which is made up of layers of the same main component, is not simply made up of layers but is made up of continuous layers. In this case, the energy of the bottom of the conduction band changes continuously between layers. The structure (U Shape Well) is formed at the interface of each layer. There are no impurities that form defect levels such as trap centers or recombination centers in the If impurities are present between the layers of the laminated multilayer film, The continuity of the energy band is lost, and carriers are trapped or annihilated by recombination at the interface. It ends up like this.

[0061] In addition, in FIG. 2(A), the case where EcS1 and EcS3 are the same is shown. For example, EcS1 has a higher energy than EcS3. In this case, part of the band structure is shown in Figure 2(B).

[0062] For example, when EcS1=EcS3, the first oxide film 404a and the second oxide film 404b are The film 404c has In:Ga:Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 (atomic ratio), In in the oxide semiconductor film 404b : In-Ga-Zn oxide with Ga:Zn=1:1:1 or 3:1:2 (atomic ratio) In addition, when EcS1>EcS3, the first oxide film 404 a) In:Ga:Zn=1:6:4 or 1:9:6 (atomic ratio), and the oxide semiconductor film 40 4b: In:Ga:Zn=1:1:1, 1:1:1.2, 1:1:1.5 or 3:1: 2 (atomic ratio), and the second oxide film 404c has In:Ga:Zn=1:3:2, 1:3:3 , In-Ga-Zn oxide with an atomic ratio of 1:3:4, etc. can be used.

[0063] 2A and 2B, the oxide semiconductor film 404b in the multilayer film 404 is a well. In the transistor using the multilayer film 404, the channel is an oxide semiconductor It can be seen that the multilayer film 404 is formed in the film 404b. Because it changes continuously, it can also be called a U-shaped well. The formed channel can also be called a buried channel.

[0064] The first oxide film 404a and the second oxide film 404c may be formed of a silicon oxide film or the like. In the vicinity of the interface with the insulating film, trap levels due to impurities or defects can be formed. The oxide semiconductor film 404a and the second oxide film 404c are formed. However, EcS1 or EcS3 When the energy difference between EcS2 and EcS3 is small, electrons in the oxide semiconductor film 404b The electron can reach the trap level beyond the energy difference. This generates a negative fixed charge at the insulating film interface, and the threshold voltage of the transistor increases in the positive direction. It shifts to.

[0065] Therefore, to reduce the variation in the threshold voltage of a transistor, EcS1 and Ec It is necessary to create an energy difference between EcS3 and EcS2. The energy difference is preferably 0.1 eV or more, more preferably 0.15 eV or more.

[0066] Note that the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor This allows the starter to have stable electrical characteristics.

[0067] When an In-Ga-Zn oxide is used for the multilayer film 404, the In gate insulating film In order to prevent diffusion of In, the second oxide film 404c contains less In than the oxide semiconductor film 404b. It is preferable to have a composition that does not contain such a component.

[0068] The source electrode 406a and the drain electrode 406b are made of a conductive material that easily bonds with oxygen. For example, Al, Cr, Cu, Ta, Ti, Mo, W, etc. can be used. Among the above materials, Ti, which is particularly likely to bond with oxygen, and It is more preferable to use W, which has a high melting point, because it can effectively increase the melting point. Conductive materials that are easily combined also include materials through which oxygen easily diffuses.

[0069] When a multilayer film is brought into contact with a conductive material that easily bonds with oxygen, the oxygen in the multilayer film bonds with the oxygen. This phenomenon occurs when the metal diffuses to the conductive material, which is more easily affected by the temperature. The transistor manufacturing process involves several heating steps, and the above phenomenon can cause multilayer Oxygen vacancies occur in the area of ​​the film near the contact with the source or drain electrode, and a small amount of oxygen is released into the film. The hydrogen contained in the region binds to the oxygen vacancy, making the region n-type. The n-type region can then function as the source or drain of a transistor. can.

[0070] The n-type region is shown in the enlarged cross section of the transistor in Figure 3 (cross section in the channel length direction). A boundary 435 indicated by a dotted line in the oxide semiconductor film 404b is a boundary between an intrinsic semiconductor region and an intrinsic semiconductor region. The source electrode 406a or The region in the vicinity of the boundary 43 in contact with the drain electrode 406b becomes an n-type region. 5 is a schematic illustration and may not be clear in reality. 4 shows a state in which the boundary 435 is positioned so as to extend laterally in the oxide semiconductor film 404b. However, the oxide semiconductor film 404b and the source electrode 406a or the drain electrode 406b are In some cases, the entire region sandwiched between the first oxide film 404a and the second oxide film 404b may be converted to n-type in the thickness direction. Although not shown, the first oxide film 404a or the second oxide film 404c also contains n In some cases, a typified region may be formed.

[0071] When a transistor with an extremely short channel length is formed, the occurrence of the oxygen vacancies The n-type region may extend in the channel length direction of the transistor. The electrical characteristics of the transistor include threshold voltage shift and on / off control by gate voltage. Therefore, a transistor with an extremely short channel length is formed. When using a semiconductor device, the source and drain electrodes should be made of a conductive material that easily bonds with oxygen. However, this is not necessarily desirable.

[0072] In such a case, the source electrode 406a and the drain electrode 406b are made of the above-mentioned materials. It is preferable to use a conductive material that is less likely to bond with oxygen than the conductive material. For example, a material containing tantalum nitride, titanium nitride, or ruthenium can be used. When the conductive material is in contact with the oxide semiconductor film 404b, the source electrode 40 6a and the drain electrode 406b are formed by the conductive material and the conductive material which is easily bonded to oxygen. The material may be laminated.

[0073] The gate insulating film 408 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more of tantalum oxide and tantalum oxide can be used. may be a laminate of the above materials.

[0074] The gate electrode 410 may be made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Conductive films such as Ag, Ta and W can be used. The gate electrode 410 may be a layered structure of a conductive film containing nitrogen. Good too.

[0075] An oxide insulating film 412 is formed on the gate insulating film 408 and the gate electrode 410. The oxide insulating film 412 may be formed of aluminum oxide, magnesium oxide, or Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide An insulating film containing at least one of hafnium and tantalum oxide can be used. The oxide insulating film 412 may be a stack of the above materials.

[0076] Here, the oxide insulating film 412 preferably contains excess oxygen. The oxide insulating film is an oxide insulating film that can release oxygen by heat treatment or the like. Preferably, the amount of released oxygen, calculated as oxygen atoms, is 1.0 in thermal desorption spectroscopy analysis. x10 19 atoms / cm 3 The oxide insulating film is a film having the above structure. The element can be diffused into the channel forming region of the multilayer film 404 via the gate insulating film 408. Therefore, even if oxygen vacancies are formed in the channel formation region, oxygen can be compensated for. Therefore, stable electrical characteristics of the transistor can be obtained.

[0077] An aluminum oxide film is preferably used for the oxide insulating film 412. The aluminum film can not only supply oxygen but also block hydrogen, water, and oxygen. The film is formed using a target that is a mixture of aluminum oxide and silicon oxide. An aluminum oxide film containing silicon oxide can also be used. The silicon dioxide content is preferably 0.1 wt % or more and 30 wt % or less.

[0078] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the size of the transistors shrinks, especially the channel The reduction in on-current, which is a direct result of the reduced width, is significant.

[0079] 4A and 4B show the channel structure of a conventional transistor using an oxide semiconductor film. The transistor is formed on a substrate 210, a base insulating film 220, and An oxide semiconductor film 230 formed on a base insulating film, a gate electrode formed on the oxide semiconductor film, The gate insulating film 260 and the gate electrode 270 are provided.

[0080] FIG. 4A shows the oxide semiconductor film 230 in the channel width direction rather than the thickness of the oxide semiconductor film 230. The length of the upper surface of the semiconductor film (W T ) is a transistor with a sufficiently large channel Width is W T It is safe to define it as such.

[0081] The electric field applied to the side surface of the oxide semiconductor film 230 from the gate electrode 270 Therefore, the formation of a channel on the side surface of the oxide semiconductor film 230 is In addition, the side length (W S1 , W S 2) is the length of its upper surface (W T ) is small, so it is assumed that a channel is formed. However, the contribution is estimated to be small. T The smaller, that is, the finer It can be said that the on-current decreases as the

[0082] Also, as shown in FIG. 4(B), W T to the same extent as the film thickness of the oxide semiconductor film 230 In the case of a scaled-down transistor, the gate electrode 270 is printed on the side surface of the oxide semiconductor film 230. Since the applied electric field extends over the entire oxide semiconductor film 230, the side surfaces of the oxide semiconductor film 230 Therefore, by increasing the thickness of the oxide semiconductor film 230, However, in conventional transistors, the channel formation layer (oxide Since carrier scattering occurs at the interface between the oxide semiconductor film 230 and the gate insulating film 260, The on-state current is not improved sufficiently.

[0083] In addition, depending on the film formation method, the film of the gate insulating film 260 covering the side surface of the oxide semiconductor film 230 may be Thickness (T GI2 ) is the thickness (T GI1 ) is likely to be thinner than the gate insulating film 260. This can cause problems and reduce the reliability of the transistor.

[0084] Also, TGI1 and T GI2 Since the gate electrode 270 and the oxide semiconductor film 230 are different in This causes variations in the electric field applied to the device, which can lead to variations in the on-state current. do.

[0085] On the other hand, in the transistor of one embodiment of the present invention, as described above, the oxide in which the channel is formed is A second oxide film 404c is formed between the oxide semiconductor film 404b and the gate insulating film 408. Therefore, the carriers generated at the interface between the channel formation layer and the gate insulating film This can suppress scattering of electrons and increase the field effect mobility of the transistor.

[0086] In the transistor of one embodiment of the present invention, the oxide semiconductor film 40 where a channel is formed is Since the second oxide film 404c is formed to cover the oxide semiconductor film 404b, The scattering of carriers can be suppressed on the side surface of b in the same way as on the top surface. The transistor of the present invention can have a higher on-state current than conventional transistors. do.

[0087] Therefore, the transistor of one embodiment of the present invention has a structure as shown in particular in FIGS. Una W T was reduced to the same thickness as or less than that of the oxide semiconductor film 404b. It has excellent structural effects.

[0088] In the case of the transistor shown in FIG. 5(A) and FIG. 5(B), the gate electrode 170 is oxidized. Since the electric field applied to the side surface of the oxide semiconductor film 404b extends to the entire oxide semiconductor film 404b, A channel similar to the channel formed on the top surface of the oxide semiconductor film 404b is also formed on the side surface of the oxide semiconductor film 404b. will be done.

[0089] When a channel region 137 as shown in FIG. 5(A) is formed in a transistor, The width is W T , W S1 , and W S2 The transistor in question has the following characteristics: An on-current flows according to the channel width.

[0090] In addition, as shown in Figure 5(B), T For transistors with extremely small 138 is W of the oxide semiconductor film 404b T In this case, the acid Since current flows through the entire compound semiconductor film 404b, the transistor In addition, in the transistor shown in FIG. T , W S When 1 is sufficiently small, a current flows through the entire oxide semiconductor film 404b.

[0091] In addition, in the transistor according to one embodiment of the present invention, the T GI1 and T G I2 Therefore, the oxide semiconductor film 404b has a characteristic that The electric field applied from the gate electrode 170 does not vary, and the oxide semiconductor film 404b Uniform channels are formed on the face and sides. S1 , W S2 W T is equivalent to When the channel is formed only on the top surface, the on-current is about three times higher. We can also obtain W S1 , W S2 W T When the thickness is twice as large as that of the It is possible to obtain an on-current that is approximately five times higher than that estimated to be formed.

[0092] In addition, in the transistor according to one embodiment of the present invention, the T GI1 and T G I2 Since the values ​​are almost the same, a portion with a low dielectric strength voltage is locally generated in the gate insulating film 260. A highly reliable transistor can be formed without any problem.

[0093] In order to efficiently improve the on-state current of a transistor, T / W S1 (W S2 )=3 Below, preferably W T / W S1 (W S2 ) = 1 or so. Specifically, W T / W S1 ( W S2 ) = 0.7 to 1.3. T / W S1 (W S2 ) is greater than 3, then S The value and off-state current may increase.

[0094] Therefore, the transistor of one embodiment of the present invention can be miniaturized. Even if such an oxide semiconductor film is electrically gated, a sufficiently high on-state current can be obtained. The structure of the transistor in which the on-state current is increased by the surrounding gate electrode is called the surrounde It is also called d channel (s-channel) structure.

[0095] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor film 404b is formed on the first oxide film 4 The formation of the oxide semiconductor film 404b on the oxide semiconductor film 404a makes it difficult to form an interface state. By using this as the middle layer in a three-layer structure, it is possible to eliminate the influence of impurities from above and below. Therefore, the oxide semiconductor film 404b has a structure in which the first oxide film 404a and the second oxide film This structure is surrounded by a thin film 404c, and in addition to improving the on-current of the transistor as described above, This makes it possible to stabilize the threshold voltage and reduce the S value. (current when gate voltage VG is 0V) can be lowered, reducing power consumption. Furthermore, the threshold voltage of the transistor is stabilized, which improves the long-term reliability of the semiconductor device. It can improve the performance.

[0096] In addition, in the transistor according to one embodiment of the present invention, a conductive film is formed between the base insulating film 120 and the substrate 110. The conductive film may be used as a second gate electrode to provide a further on-state current. It is possible to increase the on-current and control the threshold voltage. For example, the gate electrode 170 and the conductive film are set to the same potential, and the transistor is driven as a dual gate transistor. In order to control the threshold voltage, a constant voltage different from that of the gate electrode 170 may be applied. The potential can be supplied to the conductive film.

[0097] Alternatively, a transistor 460 as shown in FIG. 6 can be used. 6(C) is a top view and a cross-sectional view of the transistor 460. The cross section of the dashed line AB in FIG. 6(A) is shown in FIG. 6(B), and the cross section of the dashed line CD is shown in FIG. In the top view of Figure 6(A), some elements are omitted for clarity. The diagram is as follows:

[0098] The difference between Figure 6 and Figure 1 is that the oxide semiconductor The point is whether or not there is a flat portion on the upper surface of the film 404b.

[0099] The transistor 450 shown in FIG. 1 and the transistor 460 shown in FIG. 6 are made of an oxide semiconductor. A multilayer structure in which a dielectric film 404b is sandwiched between a first oxide film 404a and a second oxide film 404c. However, the present invention is not limited to this, and a first transistor such as a transistor 470 shown in FIG. The oxide film 404a and the second oxide film 404c are not included, and only the oxide semiconductor film 404b is included. It may be in a certain configuration.

[0100] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0101] (Embodiment 2) In this embodiment, a method for manufacturing the transistor 450 illustrated in FIGS. 1A and 1B described in Embodiment 1 will be described. This will be explained with reference to FIGS. 8 and 9.

[0102] First, a base insulating film 402 is formed on a substrate 400 (see FIG. 8(A)).

[0103] The substrate 400 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) It is also possible to use a substrate such as an insulator, and a semiconductor element can be mounted on such a substrate. may be used.

[0104] The base insulating film 402 is formed by depositing aluminum oxide by plasma CVD or sputtering. , magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide Yttrium oxide, Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide oxide insulating films such as aluminum and tantalum oxide, silicon nitride, silicon nitride oxide, aluminum nitride The insulating film is made of nitride such as aluminum or aluminum oxide nitride, or a film made of a mixture of the above materials. It may also be a laminate of the above materials, and may be formed of at least 4 multilayer films. The upper layer in contact with the multilayer film 404 is made of a material containing excess oxygen, which can be a source of oxygen to the multilayer film 404. It is preferable to form

[0105] In addition, the base insulating film 402 is formed by ion implantation, ion doping, plasma immersion, etc. Oxygen may be added by using an ion implantation method or the like. This makes it easier to supply oxygen from the base insulating film 402 to the multilayer film 404. can.

[0106] The surface of the substrate 400 is an insulator, and the influence of impurity diffusion into the multilayer film 404 to be formed later is small. If there is no influence, the base insulating film 402 may not be provided.

[0107] Next, a first oxide film 404a and an oxide semiconductor film 404b are formed on the base insulating film 402 by spat. The film is formed by a quartz crystal deposition method, a CVD method, an MBE method, an ALD method, or a PLD method (FIG. 8( At this time, even if the base insulating film 402 is slightly over-etched as shown in the figure, By excessively etching the base insulating film 402, the gate electrode 410 to be formed later can be formed. This can make it easier to cover the second oxide film 404c.

[0108] Note that when the first oxide film 404a and the oxide semiconductor film 404b are formed into island shapes, first a film to be a hard mask (for example, a tungsten film) over the oxide semiconductor film 404b; A resist mask is provided, and a film to be a hard mask is etched to form a hard mask; After that, the resist mask is removed, and the first oxide film 404a is formed using the hard mask as a mask. The oxide semiconductor film 404b is then etched. Then, the hard mask is removed. As the etching proceeds, the hard mask gradually shrinks, so the hard mask Accordingly, the shape of the oxide semiconductor film 404b is also changed to a curved shape. With this structure, the oxide semiconductor film 404b The second oxide film 404c, the gate insulating film 408, the gate electrode 410, and the oxide film 404b are formed on the surface of the gate insulating film 408. The covering property of the insulating film 412 is improved, and defects in shape such as breaks can be prevented. , and prevents electric field concentration that may occur at the ends of the source electrode 406a and the drain electrode 406b. This can alleviate the problem and suppress the deterioration of the transistor.

[0109] In addition, the first oxide film 404a and the oxide semiconductor film 404b are stacked, and a thin film formed in a later step is formed. In order to form a continuous junction in the stack including the second oxide film 404c, Using a multi-chamber film-forming device (e.g., sputtering device) equipped with a locking chamber, It is necessary to laminate layers continuously without exposing them to the atmosphere. Each chamber is cleaned to remove as much water as possible, which is an impurity for oxide semiconductors. High vacuum evacuation (5×10) was performed using an adsorption type vacuum pump such as a Lyopump. -7 Pano to 1×10 -4 The substrate on which the film is to be formed must be heated to 100°C or higher, preferably It is preferable that the temperature can be increased to 500°C or higher. By combining a trap, gas containing carbon components and moisture can flow back into the chamber from the exhaust system. It is preferable to keep this from happening.

[0110] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas are used as sputtering gases. The dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas highly purified by the above method, moisture and the like can be taken into the oxide semiconductor film. can be prevented as much as possible.

[0111] The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404b formed in a later step The oxide film 404c can be formed using the material described in Embodiment 1. For example, The first oxide film 404a contains In:Ga:Zn=1:3:4 or 1:3:2 [atomic ratio] In:Ga:Zn=1:1:1[ In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1 In-Ga-Zn oxide with an atomic ratio of 1:3:4 or 1:3:2 can be used. .

[0112] In addition, the first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c The oxide semiconductor that can be used as the oxide semiconductor is at least indium (In) or zinc ( It is preferable that the alloy contains In and Zn. Alternatively, it is preferable that the alloy contains both In and Zn. In order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, , preferably including a stabilizer.

[0113] The stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides include lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. do.

[0114] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn Oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D In-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn Oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-A In-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0115] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It also means that metal elements other than In, Ga, and Zn are included. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0116] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one metal element selected from Ga, Fe, Mn, and Co. In2SnO5(ZnO) n (n>0 and n is an integer Materials expressed as (number) may also be used.

[0117] However, as described in detail in the first embodiment, the first oxide film 404a and the second oxide film 404b are The oxide semiconductor film 404c is made of a material having a smaller electron affinity than the oxide semiconductor film 404b. Select.

[0118] Note that the oxide film and the oxide semiconductor film are preferably formed by a sputtering method. As the sputtering method, RF sputtering, DC sputtering, AC sputtering, etc. can be used. In particular, it is possible to reduce dust generated during film formation and to make the film thickness distribution uniform. Therefore, it is preferable to use a DC sputtering method.

[0119] The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are made of I When n-Ga-Zn oxide is used, the atomic ratio of In, Ga, and Zn is, for example, I n:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn= 1:1:1.5, In:Ga:Zn=2:2:1, In:Ga:Zn=3:1:2, In :Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=1:4 :3, In:Ga:Zn=1:5:4, In:Ga:Zn=1:6:6, In:Ga:Z n=2:1:3, In:Ga:Zn=1:6:4, In:Ga:Zn=1:9:6, In The material is either In:Ga:Zn=1:1:4 or In:Ga:Zn=1:1:2. The electron affinities of the first oxide film 404a and the second oxide film 404c are different from those of the oxide semiconductor film 40 It is enough to make it smaller than 4b.

[0120] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (aA) 2 +(bB) 2 +(cC) 2 ≦r 2 It means that the following is satisfied. For example, 0.05 can be used as r. The same is true for other oxides.

[0121] The oxide semiconductor film 404b is formed by the first oxide film 404a and the second oxide film 404b. It is preferable to have a higher indium content than 4c. In oxide semiconductors, the heavy metal s The orbitals contribute to carrier conduction, and by increasing the In content, more s Because of the overlap of orbitals, oxides with a composition in which In is more abundant than Ga have the same or less In than Ga. The mobility of the oxide semiconductor film 404b is higher than that of an oxide having a composition without the oxide. By using oxide with a high indium content, a high mobility transistor can be realized. It is possible.

[0122] The structure of the oxide semiconductor film will be described below.

[0123] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0124] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0125] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0126] First, the CAAC-OS film will be described.

[0127] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0128] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystals are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0129] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0130] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0131] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm on the top surface of the CAAC-OS film is observed. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See Figure 37(A)).

[0132] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0133] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0134] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0135] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layers confirmed by the cross-sectional TEM observation mentioned above are Each layer of metal atoms arranged in a lattice is parallel to the ab plane of the crystal.

[0136] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, the CAAC-OS When the shape of the film is changed by etching, the c-axis of the crystal is aligned with the surface of the CAAC-OS film. It may not be parallel to the normal vector of the forming surface or top surface.

[0137] Furthermore, the crystallinity of the CAAC-OS film may not be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface to be formed. When impurities are added to the AC-OS film, the crystallinity of the region where the impurities are added changes, and the Regions of differing crystallinity may be formed.

[0138] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0139] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0140] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0141] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. The film has a small number of carrier generation sources, so the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative. (also called normally-on) is rare. An oxide semiconductor film with intrinsic purity has few carrier traps. Transistors using conductor films have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time it takes for the impurity concentration to reach the target is long, and it may behave as if it were a fixed charge. A transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0142] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0143] Next, the polycrystalline oxide semiconductor film will be described.

[0144] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in the TEM observation image. The crystal grains contained in the crystalline oxide semiconductor film are, for example, 2 nm or more in a TEM observation image. The particle size is 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the polycrystalline oxide semiconductor film, the grain boundaries can be confirmed in the TEM observation image. This may be the case.

[0145] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, when an XRD device is used for a polycrystalline oxide semiconductor film, When structural analysis is performed, for example, the out of polycrystalline oxide semiconductor film having InGaZnO4 crystals In the t-of-plane analysis, there is a peak at 2θ around 31° and a peak at 2θ around 36°. peak or other peaks may appear.

[0146] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in a polycrystalline oxide semiconductor film, impurities may segregate at the grain boundaries. The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the oxide semiconductor film may become a carrier trap or a carrier generation source, The transistors using the CAAC-OS film showed a small change in electrical characteristics compared to the transistors using the CAAC-OS film. may result in a transistor with low reliability.

[0147] Next, a microcrystalline oxide semiconductor film will be described.

[0148] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, the grain boundaries may not be clearly visible.

[0149] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, in the case of nc-OS films, X-rays with a diameter larger than that of the crystals are used. When structural analysis is performed using an RD device, the crystal In addition, the peaks indicating the crystal planes were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter of 50 nm or more. When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal. When nanobeam electron diffraction is performed on the nc-OS film, spots are observed. When you do this, you may see a circular (ring-shaped) area of ​​high brightness. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. may be observed (see Figure 37(B)).

[0150] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0151] Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density may have high electron mobility. In some cases, a transistor using an nc-OS film has high field-effect mobility. The nc-OS film has a higher defect density than the CAAC-OS film, which leads to a higher carrier transport. Therefore, the transistor using the nc-OS film is Compared to transistors using OS films, the electrical characteristics fluctuate greatly and the reliability is low. However, the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, it is easier to form than the CAAC-OS film, and it is suitable for some applications. Therefore, a semiconductor having a transistor using an nc-OS film can be The devices may be manufacturable.

[0152] Next, the amorphous oxide semiconductor film will be described.

[0153] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0154] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in the TEM observation image.

[0155] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the analysis by the plane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0156] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0157] An oxide semiconductor film with a high impurity concentration and a high density of defect states has carrier traps and The oxide semiconductor film is a common source of CO2.

[0158] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film may not be able to Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film may be preferably used as a photoresist. Therefore, when an amorphous oxide semiconductor film is used, the carrier traps may increase. The transistors using the CAAC-OS film and the nc-OS film have the following characteristics: The electrical characteristics vary greatly, resulting in a transistor with low reliability.

[0159] Next, a single crystal oxide semiconductor film will be described.

[0160] The single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. Furthermore, since the single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single-crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0161] Note that the oxide semiconductor film has a high density when it has few defects. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of a single-crystal oxide semiconductor film is higher than that of a CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0162] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0163] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0164] FIG. 38(A) shows an electron gun chamber 10, an optical system 12 below the electron gun chamber 10, and a a sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation A transillumination system having a camera 18 installed in a chamber 20 and a film chamber 22 below the observation chamber 20. The figure shows a device for measuring electron diffraction. The camera 18 is installed facing the inside of the observation chamber 20. The room chamber 22 may not be provided.

[0165] FIG. 38(B) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 38(A). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 is irradiated onto a substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the light plate 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. It is possible to measure the

[0166] The camera 18 is set facing the fluorescent screen 32 and captures the pattern that appears on the fluorescent screen 32. A line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32 is The angle between the line and the upper surface of the fluorescent screen 32 is, for example, 15° or more and 80° or less, or 30° or more. The angle is set to 75° or less, or 45° to 70°. The smaller the angle, the more accurate the image captured by the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be distorted. If the electron beam is irradiated with the sample, it is possible to correct distortions in the obtained transmission electron diffraction pattern. In some cases, the camera 18 may be placed in the film chamber 22. For example, The fluorescent screen may be installed in the room chamber 22 so as to face the direction of incidence of the electrons 24. A transmission electron diffraction pattern with little distortion can be taken from the back side of 32.

[0167] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function to move the object 28 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range of movement is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance 28. That's fine.

[0168] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0169] For example, as shown in FIG. 38(B), the irradiation position of the electron 24, which is a nanobeam, in the material By changing (scanning) the In this case, if the substance 28 is a CAAC-OS film, the structure shown in FIG. If the material 28 is an nc-OS film, the diffraction pattern shown in Figure 37(B) is The diffraction pattern shown is observed.

[0170] By the way, even if material 28 is a CAAC-OS film, it may be partially composed of nc-OS films. Therefore, the quality of the CAAC-OS film can be determined by the diffraction pattern. , the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAA For example, in a high-quality CAAC-OS film, If present, the CAAC conversion rate is 60% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern is different from that of the CAAC-OS film. The percentage of the area where this is observed is denoted as the non-CAAC rate.

[0171] As an example, immediately after film formation (denoted as as-depo), after heat treatment at 350°C or after 450°C After the heat treatment at ℃, the top surface of each sample with the CAAC-OS film was scanned. The electron diffraction pattern was acquired by scanning at a speed of 5 nm / sec for 60 sec. The diffraction pattern is observed and converted into a still image every 0.5 seconds. The CAAC rate was calculated using a nano-beam electron beam with a probe diameter of 1 nm. A sagittal line was used.

[0172] The CAAC conversion rate for each sample is shown in Figure 39. The comparison shows the CAAC conversion rate immediately after film formation and after heat treatment at 350°C. In all cases, it can be seen that the CAAC conversion rate is higher after heat treatment at 450°C. Heat treatment at high temperatures (e.g., 400°C or higher) reduces the non-CAAC ratio (C Here, the diffraction pattern is different from that of the CAAC-OS film. Most of the diffraction patterns were similar to those of the nc-OS film. Therefore, regions with a similar structure to the nc-OS film are redistributed due to the influence of the structures of the neighboring regions. This suggests that the CAAC has been formed.

[0173] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0174] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The film can be formed by a sputtering method. Ions collide with the sputtering target. Then, the crystalline region contained in the sputtering target cleaves from the ab plane and forms a flat ab plane. The particles may peel off as flat or pellet-shaped sputter particles with a rough surface. In this case, the plate-shaped or pellet-shaped sputtered particles are charged and therefore agglomerate in the plasma. The CAAC-OS film can be deposited by maintaining its crystalline state on the substrate. .

[0175] After the oxide semiconductor film 404b is formed, first heat treatment may be performed. is inactive at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The treatment may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is removed. To compensate for this, the first heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. Therefore, the crystallinity of the oxide semiconductor film 404b is improved, and the base insulating film 402 and the first oxide semiconductor film 404b are Impurities such as hydrogen and water can be removed from the oxide semiconductor film 404a. A first heating step may be performed before the etch that forms 04b.

[0176] Next, the source electrode 406a is formed on the first oxide film 404a and the oxide semiconductor film 404b. A first conductive film is formed to become the drain electrode 406b. Use Cr, Cu, Ta, Ti, Mo, W, or alloy materials with these as the main components. For example, a titanium film of 100 nm can be formed by sputtering. The tungsten film may be formed by the VD method.

[0177] Next, the first conductive film is etched to be divided over the oxide semiconductor film 404b. A source electrode 406a and a drain electrode 406b are formed (see FIG. 8(C)). Due to the over-etching of the first conductive film, a part of the base insulating film 402 is etched. It may also have a shape.

[0178] Next, the first oxide film 404a, the oxide semiconductor film 404b, the source electrode 406a, and A second oxide film 403c is formed on the drain electrode 406b.

[0179] Note that a second heat treatment may be performed after the second oxide film 403c is formed. The second heat treatment can be carried out under the same conditions as the first heat treatment. Impurities such as hydrogen and water can be removed from the oxide film 403c. impurities such as hydrogen and water are further removed from the oxide semiconductor film 404a and the oxide semiconductor film 404b. It is possible.

[0180] Next, an insulating film 407 that will become a gate insulating film 408 is formed on the second oxide film 403c. (See FIG. 9A.) The insulating film 407 is made of aluminum oxide, magnesium oxide, silicon oxide, or the like. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide The insulating film 407 can be made of the above-mentioned materials such as fluorine and tantalum oxide. The insulating film 407 may be formed by a method such as sputtering, CVD, MBE, or ALD. Alternatively, the gate insulating film 408 can be formed by using a PLD method or the like. By adjusting the material, temperature, pressure, electrode distance, input power, etc., the T shown in Figure 5(A) was obtained. GI1 and T GI2 It is preferable to form the film under conditions that improve the covering property so that the thicknesses of the films are approximately equal. For example, the film is formed under high temperature and high pressure conditions within the range where the film quality as a gate insulating film can be maintained. By doing so, the covering property can be improved.

[0181] Next, a second conductive film 409 that will become a gate electrode 410 is formed on the insulating film 407 (FIG. 9). The second conductive film 409 may be made of Al, Ti, Cr, Co, Ni, Cu, Y , Zr, Mo, Ru, Ag, Ta, W, or alloy materials containing these as the main components. The second conductive film 409 can be formed by a sputtering method, a CVD method, or the like. In addition, a conductive film containing nitrogen may be used as the second conductive film 409. A laminate of a conductive film containing a material and a conductive film containing nitrogen may be used.

[0182] Next, using a resist mask for forming the gate electrode 410, the second conductive film 40 9 is selectively etched to form a gate electrode 410 (see FIG. 9(C)).

[0183] Next, the insulating film 407 is selected using the resist mask or the gate electrode 410 as a mask. Selective etching is performed to form a gate insulating film 408 .

[0184] Next, the second oxide film 4 is formed using the resist mask or the gate electrode 410 as a mask. O3c is etched to form a second oxide film 404c.

[0185] That is, the upper end of the second oxide film 404c coincides with the lower end of the gate insulating film 408, and the gate The upper end of the gate insulating film 408 coincides with the lower end of the gate electrode 410. 10 is used as a mask to form the gate insulating film 408 and the second oxide film 404c. However, the present invention is not limited to this, and the gate insulating film 408 and the second oxide film 409 may be formed before the second conductive film 409 is formed. A film 404c may be formed.

[0186] Next, an oxide insulating layer is formed on the source electrode 406a, the drain electrode 406b, and the gate electrode 410. The oxide insulating film 412 is formed on the same substrate as the base insulating film 402 (see FIG. 1B). The oxide insulating film 412 can be formed using a material and a method such as aluminum oxide. aluminum film, magnesium oxide film, silicon oxide film, silicon oxynitride film, silicon nitride oxide film Kon film, silicon nitride film, gallium oxide film, germanium oxide film, yttrium oxide film, Zirconium oxide film, lanthanum oxide film, neodymium oxide film, hafnium oxide film, tantalum oxide film The oxide insulating film 412 may be formed using a sputtering film or an oxide insulating film containing nitrogen. It can be formed by using a photocatalytic method, a CVD method, an MBE method, an ALD method or a PLD method. It is preferable that the layer film 404 contains excess oxygen so that oxygen can be supplied to the layer film 404 .

[0187] The oxide insulating film 412 may be formed by ion implantation, ion doping, or plasma immersion. Oxygen may be added by using a method such as ion implantation. This makes it easier to supply oxygen from the oxide insulating film 412 to the multilayer film 404. This can be done.

[0188] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed under the following conditions. This makes it easier for excess oxygen to be released from the oxide insulating film 412, thereby reducing oxygen vacancies in the multilayer film 404. can be reduced.

[0189] Through the above steps, the transistor 450 shown in FIG. 1 can be manufactured.

[0190] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0191] (Embodiment 3) In this embodiment, a transistor having a different structure from the transistor described in the first embodiment is used. This section explains the data.

[0192] 14A to 14C are top views and cross-sectional views of a transistor of one embodiment of the present invention. 14(A) is a top view, and the cross section taken along the dashed line AB shown in FIG. 14(B), and the cross section of the dashed line CD corresponds to FIG. 14(C). In the plan view, some elements are omitted for clarity. The direction indicated by the dashed dotted line CD may be referred to as the channel length direction, and the direction indicated by the dashed dotted line CD may be referred to as the channel width direction.

[0193] The transistor 550 shown in FIGS. 14A to 14C is a transistor having an insulating base layer on a substrate 400. The base insulating film 402, the first oxide film 404a over the base insulating film 402, and the oxide semiconductor film 404 b, and the source electrode 406a and the source electrode 406b on the first oxide film 404a and the oxide semiconductor film 404b. and the drain electrode 406b, the oxide semiconductor film 404b, the source electrode 406a and the drain electrode 406b. The second oxide film 404c on the gate electrode 406b and the gate insulating film 404c on the second oxide film 404c are The insulating film 408, the gate electrode 410 on the gate insulating film 408, the source electrode 406a, the drain electrode 406b, The barrier film 41 on the gate electrode 406b, the second oxide film 404c, and the gate electrode 410 4, and the first oxide film 404a, the oxide semiconductor film 404b, and the silicon dioxide film 404b are connected via a barrier film 414. A sidewall insulating film 416 covering the sidewalls of the source electrode 406a and the drain electrode 406b, and a barrier film The second oxide film 404c, the gate insulating film 408 and the gate electrode 410 are connected via the gate insulating film 414. A sidewall insulating film 418 covering the sidewall, a source electrode 406a, a drain electrode 406b, a gate electrode The oxide insulating film 412 on the electrode 410, the sidewall insulating film 416, and the sidewall insulating film 418, and the oxide An opening is provided in the insulating film 412, and a source electrode 406a and a drain electrode 406b are embedded in the opening. Electrodes 419a and 419b electrically connected to electrode 406b, and electrodes 419a and The wiring 420a and the wiring 420b are electrically connected to the electrode 419b. The first oxide film 404a, the oxide semiconductor film 404b, and the second oxide film 404c are collectively This is referred to as a multilayer film 404.

[0194] The oxide semiconductor film 404b has a shape such that the edges are rounded and the shape resembles a half circle. With this structure, the oxide semiconductor film 404b formed on the oxide semiconductor film 404b This can improve the coverage of the gate insulating film 408 and the gate electrode 410.

[0195] The barrier film 414 is formed of an insulating film having a blocking effect against hydrogen, water, and oxygen. It is preferable that the aluminum oxide film is formed of an aluminum oxide film. In addition to the blocking effect, it is an insulating film that can supply oxygen. Silicon oxide film formed using a target containing aluminum and silicon oxide An aluminum film can also be used. In this case, the content of silicon oxide is 0.1 wt%. It is preferable that the content is 30 wt % or more.

[0196] In addition, the coverage of the barrier film 414 in contact with the sidewalls of the multilayer film 404 and the gate electrode 410 is poor. Therefore, the sidewall insulating film 416 and the sidewall insulating film 418 are used to cover the area. The sidewall insulating film 416 and the sidewall The insulating film 418 can be formed using a material similar to that of the base insulating film 402 and the gate insulating film 408. Cut.

[0197] The electrodes 419a and 419b are connected to the source electrode 406a and the drain electrode 406b. The wiring 420a and the wiring 420b are electrically connected to the electrodes 419a and The oxide insulating film 412 is electrically connected to the electrode 419b. , so as to be electrically connected to the source electrode 406a and the drain electrode 406b through the openings. When the wiring 420a and the wiring 420b are formed in the opening, the wiring 420a may extend to the bottom of the opening. The wiring 420b does not reach the opening, and therefore an electrical connection cannot be made. The opening is filled with electrodes 419a and 419b, and then wires 420a and 420b are inserted. It is necessary to form a layer b in contact with the source electrode 406a and the drain electrode 406b. If the wiring 420a and the wiring 420b are made of a material that can be used, the electrodes 419a and There is no need to use electrode 419a.

[0198] The electrode 419a, the electrode 419b, the wiring 420a, and the wiring 420b are connected to the source electrode 406 a, the same materials as those of the drain electrode 406b and the gate electrode 410 can be used.

[0199] In addition, in the case of a transistor 560 shown in FIG. 18A, which does not have a sidewall insulating film 416, Alternatively, the sidewall insulating film 416 and the The sidewall insulating film 418 may be omitted.

[0200] Furthermore, the electrode 419a and the electrode 41b are connected to the transistor 580 shown in FIG. Alternatively, the structure may be such that the electrode 9b reaches the source electrode 406a and the drain electrode 406b.

[0201] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0202] (Fourth embodiment) In this embodiment, the method for manufacturing the transistor 550 shown in FIGS. 14A and 14B described in Embodiment 3 will be described. The method will be described with reference to FIGS.

[0203] First, a base insulating film 402, a first oxide film 403a, an oxide semiconductor film 404, and a 15A. The substrate 400, the base insulating film 402, the first oxide film 03b are formed (see FIG. 15A). The above embodiment may be referred to for materials and formation methods of the oxide semiconductor film 403a and the oxide semiconductor film 403b. It is possible.

[0204] Next, a source electrode 406a and a drain electrode 406b are formed on the oxide semiconductor film 403b. A conductive film is formed, and only the portion overlapping the portion to be the channel region is etched. The source electrode 406a and the conductive film 405b are formed (see FIG. 15B). The above embodiment can be referred to for the material and manufacturing method of the conductive film to be the drain electrode 406b. It is possible.

[0205] Next, a resist mask is formed over the conductive film 405a and the conductive film 405b. 1, the oxide film 403a, the oxide semiconductor film 403b, the conductive film 405a, and the conductive film 405b. The first oxide film 404a, the oxide semiconductor film 404b, and the source electrode 406 are etched. The drain electrode 406a and the drain electrode 406b are formed (see FIG. 15(B)). By forming it finely, the size of the conductive film 4 is gradually reduced as it is etched. The edges of the conductive film 405a and the conductive film 405b may naturally be rounded and have curved surfaces. By adopting such a configuration, the electrodes formed on the source electrode 406a and the drain electrode 406b The second oxide film 404c, the gate insulating film 408, the gate electrode 410, and the oxide insulating film The covering property of 412 is improved, and defects in shape such as cuts can be prevented.

[0206] Next, the first oxide film 404a, the oxide semiconductor film 404b, the source electrode 406a, and A second oxide film 403c and an insulating film 407 are formed on the drain electrode 406b (FIG. 16 The materials and manufacturing methods of the second oxide film 403c and the insulating film 407 are the same as those in the previous example. The form of implementation can be taken into consideration.

[0207] Note that a second heat treatment may be performed after the second oxide film 403c is formed. The second heat treatment can be carried out under the same conditions as the first heat treatment. Impurities such as hydrogen and water can be removed from the oxide film 404c. impurities such as hydrogen and water are further removed from the oxide semiconductor film 404a and the oxide semiconductor film 404b. It is possible.

[0208] Next, a second conductive film that will become a gate electrode 410 is formed on the insulating film 407, and a resist mask is formed on the second conductive film. The second conductive film is selectively etched using a mask to form a gate electrode 410 (FIG. 1). 6(B)). The material and manufacturing method of the gate electrode 410 may be the same as those described in the previous embodiment. It is possible.

[0209] Next, the insulating film 407 is selected using the resist mask or the gate electrode 410 as a mask. Selective etching is performed to form a gate insulating film 408 .

[0210] Next, the second oxide film 4 is formed using the resist mask or the gate electrode 410 as a mask. O3c is etched to form a second oxide film 404c.

[0211] Next, the base insulating film 402, the source electrode 406a, the drain electrode 406b, and the gate electrode 406c are A barrier film 414 is formed on the substrate 10 (see FIG. 16(C)).

[0212] The barrier film 414 is an insulating film that has a blocking effect against hydrogen, water, and oxygen. Therefore, oxygen contained in the multilayer film 404, the base insulating film 402, and the gate insulating film 408 diffuses to the outside. Therefore, oxygen can be efficiently supplied to the oxide semiconductor film, and the amount of oxygen vacancies can be reduced. Therefore, electrical characteristics are improved, and a highly reliable semiconductor device can be provided. It is possible.

[0213] Next, the insulating films that will become the sidewall insulating films 416 and 418 are subjected to highly anisotropic etching. By the bonding process, the multilayer film 404, the source electrode 406a, and the The drain electrode 406b, the gate insulating film 408, and the gate electrode 410 are provided with sidewall insulating films. 416, a sidewall insulating film 418 can be formed (see FIG. 17(A)).

[0214] Next, the oxide insulating film 412 is formed over the barrier film 414 (see FIG. 17B). The above embodiment can be referred to for a material and a manufacturing method of the insulating film 412.

[0215] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed under the following conditions. This makes it easier for excess oxygen to be released from the oxide insulating film 412, thereby reducing oxygen vacancies in the multilayer film 404. can be reduced.

[0216] Next, openings are formed in the oxide insulating film 412 and the barrier film 414. and electrically connected to the source electrode 406a and the drain electrode 406b through the opening. Electrodes 419a and 419b are formed.

[0217] The electrodes 419a and 419b are embedded in the openings. The electrode 419b is embedded in the oxide insulating film 412 and in the opening. A conductive film that will become the electrodes 9a and 419b is formed, and the conductive film is subjected to a removal (polishing) process. Thus, part of the conductive film is removed so that the oxide insulating film 412 is exposed (see FIG. 17C). ).

[0218] The removal method is chemical mechanical polishing. It is preferable to use a chemical mechanical polishing (CMP) process.

[0219] In this embodiment, the CMP process is used to remove a part of the conductive film. Alternatively, a polishing process such as CMP and etching (dry etching, For example, CMP (wet etching) and plasma treatment may be combined. After processing, dry etching or plasma processing (reverse sputtering, etc.) is performed. The flatness of the surface may be improved. In the removal process, etching, plasma treatment, etc. When the above process is performed in combination with the CMP process, the order of the processes is not particularly limited. The thickness can be set appropriately according to the surface irregularities. The remaining conductive film may be removed by dry etching or the like.

[0220] The CMP process may be performed only once or multiple times. When performing CMP, first polishing with a high polishing rate is performed, followed by finishing with a low polishing rate. By combining polishing processes with different polishing rates in this way, Therefore, the flatness of the surfaces of the conductive films (electrodes 419a and 419b) can be further improved. can.

[0221] Next, the electrode 419a and the electrode 419b are formed over the oxide insulating film 412 and the electrodes 419a and 419b. 9b (see FIG. 14(B)). ).

[0222] Through the above steps, the transistor 550 illustrated in FIG. 14 can be manufactured.

[0223] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0224] (Embodiment 5) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the surface.

[0225] 19(A) and 19(B) show circuit diagrams of the semiconductor device, and FIG. 19(C) and 19(D) show 19(C) and 19(D) show cross-sectional views of the semiconductor device. A cross-sectional view of the transistor 450 in the channel length direction is shown on the right, and a cross-sectional view in the channel width direction is shown on the left. In addition, the circuit diagram clearly shows that the transistor is made of an oxide semiconductor. In order to do so, the notation "OS" is added.

[0226] The semiconductor device shown in FIG. 19(C) and FIG. 19(D) has a transistor using a first semiconductor material in the lower part. The transistor 2200 has a second semiconductor material on top. In this example, the transistor using the second semiconductor material is the transistor exemplified in the first embodiment. An example in which the resistor 450 is applied will be described.

[0227] Here, the first semiconductor material and the second semiconductor material are materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon, ruthenium, silicon germanium, silicon carbide, or gallium arsenide, etc.), The second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors that use single crystal silicon as a non-conductor material are easy to operate at high speeds. On the other hand, a transistor including an oxide semiconductor has a low off-state current.

[0228] Here, the transistor 2200 is described as a p-channel transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. In addition, other than using the transistor using an oxide semiconductor as described in Embodiment 1, The specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is described below. There is no need to be limited to what is shown here.

[0229] The configurations shown in Figures 19(A), 19(C), and 19(D) are p-channel transistors. A transistor and an n-channel transistor are connected in series, and the gates of each transistor are connected. An example of the configuration of a so-called CMOS circuit is shown.

[0230] The transistor including the oxide semiconductor of one embodiment of the present invention has increased on-state current. This allows the circuit to operate at high speed.

[0231] In the structure shown in FIG. 19C, a transistor 2200 is provided with an insulating film 2201 therebetween. The transistor 450 is provided between the transistor 2200 and the transistor 4 A plurality of wirings 2202 are provided between the wirings 50. In addition, a plurality of wirings 2202 embedded in various insulating films are provided. The plugs 2203 electrically connect the wiring and electrodes provided on the upper and lower layers. In addition, an insulating film 2204 covering the transistor 450 and a wiring layer 2206 formed on the insulating film 2204 are provided. 2205 and a wiring formed by processing the same conductive film as the pair of electrodes of the transistor 450. 2206 and are provided.

[0232] In this way, stacking two transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0233] In FIG. 19C, one of the source and drain of the transistor 450 and the Either the source or the drain of the capacitor 2200 is electrically connected by a wiring 2202 or a plug 2203. The gate of the transistor 450 is connected to the wiring 2205 and the wiring 220 6, via the plug 2203 and the wiring 2202, etc., to the gate of the transistor 2200 and is electrically connected.

[0234] In the structure shown in FIG. 19D, a plug 2203 is formed in the gate insulating layer of the transistor 450. An opening for embedding is provided, and the gate of the transistor 450 is connected to the plug 2203. This configuration not only makes it easier to integrate circuits, but also , the number and length of wiring and plugs to be passed through can be reduced compared to the configuration shown in FIG. 19(C). , the circuit can be operated at a higher speed.

[0235] In the configurations shown in FIGS. 19C and 19D, the transistor 450 and the transistor By changing the electrode connection configuration of the transistor 2200, various circuits can be configured. For example, as shown in FIG. 19(B), the source and drain of each transistor By connecting the two, the circuit can function as an analog switch. This can be done.

[0236] Furthermore, an image sensor that reads information about an object using the transistor of the above embodiment can be used. A semiconductor device having a sensor function can be manufactured.

[0237] FIG. 24 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0238] The photodiode 602 has one electrode connected to a photodiode reset signal line 658, The other electrode is electrically connected to the gate of transistor 640. 0 indicates that either the source or the drain is connected to the photosensor reference signal line 672, and The other terminal is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has a gate connected to a gate signal line 659 and a drain connected to a floating gate. It is electrically connected to the photo sensor output signal line 671 .

[0239] The photodiode 602 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance ( A pin type in which a semiconductor layer having an i-type conductivity and a semiconductor layer having an n-type conductivity are stacked A photodiode of the type described above can be applied.

[0240] By detecting the light incident on the photodiode 602, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. You can be there.

[0241] The transistor 640 and the transistor 656 may be any of the transistors in the previous embodiments. A transistor in which a channel is formed in an oxide semiconductor, as shown in the example of In FIG. 24, the transistor 640 and the transistor 656 include an oxide semiconductor. To make this clear, the transistor symbol is marked with "OS."

[0242] The transistor 640 and the transistor 656 are the same as the transistors shown as examples in the above embodiment. The transistor has a structure in which an oxide semiconductor film is electrically surrounded by a gate electrode. In addition, the oxide semiconductor film preferably has a curved surface with a rounded upper end. The coverage of the film formed on the semiconductor film can be improved. This can reduce the electric field concentration that may occur at the end of the drain electrode, and Therefore, the deterioration of the transistor 640 and the transistor 656 can be suppressed. is an electrically stable transistor in which fluctuations in electrical characteristics are suppressed. By including the semiconductor device, a highly reliable semiconductor device having an image sensor function as shown in FIG. A conductor device can be provided.

[0243] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0244] (Sixth embodiment) In this embodiment, a transistor according to one embodiment of the present invention is used, and a power supply is not supplied. A semiconductor device (memory) that can retain its memory contents even under certain circumstances and has no limit on the number of times it can be written. An example of the device will be described with reference to the drawings.

[0245] FIG. 20 shows a circuit diagram of each semiconductor device.

[0246] The semiconductor device shown in FIG. 20 includes a transistor 3200 using a first semiconductor material and a second The semiconductor device includes a transistor 3300 and a capacitor 3400 made of a semiconductor material. The transistor described in Embodiment 1 can be used as the transistor 3300. can.

[0247] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 3300 has a small off-state current, so that It is possible to retain the stored contents for a longer period of time, i.e., no refresh operation is required. A semiconductor memory device that does not require refresh operations or requires extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0248] In FIG. 20, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the gate electrodes of the transistor 3300. The gate electrode of the transistor 3200 and the The other of the source electrode and the drain electrode of the transistor 3300 is connected to the electrode of the capacitor 3400. The fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400. are actively connected.

[0249] In the semiconductor device shown in FIG. 20, the potential of the gate electrode of the transistor 3200 can be maintained. By utilizing this feature, it is possible to write, store, and read information as follows.

[0250] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitor element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning the transistor 3300 to the off state, the The charge applied to the gate electrode is retained (retention).

[0251] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrode is maintained for a long period of time.

[0252] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. Generally, if the transistor 3200 is an n-channel type, the transistor 320 The apparent threshold voltage V when a high level charge is applied to the gate electrode of t h_H When a low level charge is applied to the gate electrode of the transistor 3200, The apparent threshold voltage V th_L Here, the apparent threshold The voltage is the voltage across the fifth wiring 3005 required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th _L By setting the potential V0 between For example, if a high level charge is applied during writing, In this case, the potential of the fifth wiring 3005 is V0 (>V th_H ), then transistor 32 00 is in the "ON state." When a low level charge is applied, the fifth wiring 3 The potential of 005 is V0( <V th_L ), transistor 3200 is in the "off state" Therefore, by determining the potential of the second wiring 3002, the potential that is being maintained can be determined. The information can be read out.

[0253] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. Alternatively, depending on the state of the gate electrode, The potential at which transistor 3200 remains "on," i.e., V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0254] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By applying transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is not required or the refresh operation is Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0255] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating layer does not occur at all. In this device, there is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory. Reliability will be dramatically improved. Furthermore, the on / off state of the transistor determines the information Since the data is written in the memory, high-speed operation can be easily achieved.

[0256] As described above, semiconductors that have achieved miniaturization and high integration and are endowed with high electrical properties are being developed. A body device can be provided.

[0257] (Embodiment 7) In this embodiment, the transistor described in the previous embodiment can be used. A CPU including the storage device described in the embodiment will be described.

[0258] FIG. 21 shows a CPU that uses the transistor described in the first embodiment at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0259] The CPU shown in FIG. 21 includes an ALU 1191 (Arithmetic and logic unit) on a board 1190. tic logic unit, arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and ROM interface 1189 can be mounted on separate chips. Of course, the CPU shown in FIG. 21 is merely an example of a simplified configuration, and in practice The actual CPU has a wide variety of configurations depending on its application. For example, the CPU shown in Figure 21 A configuration including U or an arithmetic circuit is considered to be one core, and multiple such cores are included, and each core is It may be configured to operate in parallel. Also, the CPU may handle the internal arithmetic circuit and data bus. The number of bits that can be used may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc. can be done.

[0260] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0261] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0262] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals that control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generator generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0263] In the CPU shown in FIG. 21, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0264] In the CPU shown in FIG. 21, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0265] FIG. 22 is a circuit diagram of an example of a storage element that can be used as the register 1196. The memory element 700 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706 The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708 includes a transistor 709 and a transistor 710. The element 700 may further include other elements such as diodes, resistors, and inductors as needed. It may also have

[0266] Here, the memory device described in the above embodiment can be used for the circuit 702. When the supply of power supply voltage to the memory element 700 is stopped, the first transistor 709 in the circuit 702 The gate of the transistor 709 is supplied with a ground potential (0V) or a potential that turns the transistor 709 off. For example, the first gate of the transistor 709 is connected to the first gate of the transistor 709 via a load such as a resistor. It is configured to be grounded.

[0267] The switch 703 is implemented by using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is configured to have a transistor of a conductivity type opposite to one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 703 is a transistor 714. The second terminal of the switch 703 corresponds to one of the source and drain of the transistor 713. The switch 703 corresponds to the other of the source and drain of the transistor 713. The control signal RD input to the gate of the transistor 3 controls the conduction or non-conduction between the first and second terminals. The switch 713 is turned off (i.e., the transistor 713 is turned on or off). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The first terminal of the switch 704 is turned on by a control signal RD input to the gate of the transistor 714. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on or off state of transistor 714) OFF state) is selected.

[0268] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. and the gate of the transistor 710. The node M2 ​​is connected to one of the source and drain of the transistor 710. The other is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703 The first terminal (one of the source and the drain of the transistor 713) is electrically connected to the first terminal of the transistor 713. The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is connected to the 704 (one of the source and drain of the transistor 714) The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is electrically connected to a wiring that can supply a power supply potential VDD. The second terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704 terminal (one of the source and drain of the transistor 714) and the input terminal of the logic element 706 is electrically connected to one of the pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential ( VDD or the like) can be input to one of the pair of electrodes of the capacitor 707. The other is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, when a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input, The other of the pair of electrodes of the capacitor 708 is connected to a low power supply potential. It is electrically connected to a wiring that can supply power (for example, a GND line).

[0269] The capacitors 707 and 708 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it sparingly.

[0270] A control signal WE is input to the first gate (first gate electrode) of the transistor 709. The switches 703 and 704 are controlled by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no electrical continuity between the terminals.

[0271] The other of the source and drain of the transistor 709 is connected to a data held in the circuit 701. In FIG. 22, the signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other terminal (the other of the source and drain of transistor 713) is input to logic element 7 The logic value is inverted by 06 to become an inverted signal, and is sent to the circuit 701 via the circuit 720. is entered.

[0272] In FIG. 22, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input is transmitted to the circuit 70 via the logic element 706 and the circuit 720. 1 is shown as an example, but is not limited to this. The signal output from the other of the source and drain of the transistor 713 is inverted in logic value. For example, the input from the input terminal may be input to the circuit 701 without being input to the circuit 701. When there is a node where a signal whose logic value is inverted from the signal inputted to the switch 70 is held, 3 (the other of the source and drain of the transistor 713) It can be input to the node.

[0273] The transistor 709 in FIG. 22 is the transistor described in Embodiment 1. As explained in the third embodiment, the second gate (second gate electrode) A control signal WE is input to the first gate, and a control signal WE is input to the second gate. The control signal WE2 can be input as a signal with a constant potential. The constant potential may be, for example, a ground potential GND or a source potential of the transistor 709. The control signal WE2 is a potential smaller than the threshold voltage of the transistor 709. This is a potential signal for controlling the voltage, and it is possible to further reduce Icut of the transistor 709. Note that the transistor 709 may be a transistor without a second gate. It can also be used.

[0274] In addition, in FIG. 22, among the transistors used in the memory element 700, The transistors other than the transistor 709 are formed on a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon layer or The memory element 7 can be a transistor in which the channel is formed in the silicon substrate. All the transistors used in 00 are transistors whose channels are formed using oxide semiconductor films. Alternatively, the memory element 700 may include a transistor other than the transistor 709. The other transistor may include a transistor in which the channel is formed using an oxide semiconductor film. The transistor is a transistor in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be a transistor.

[0275] For example, a flip-flop circuit can be used as the circuit 701 in FIG. The logic element 706 may be, for example, an inverter or a clocked inverter. This can be done.

[0276] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 700, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. It can be held by this.

[0277] In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using this transistor as the transistor 709, the memory element 7 The signal held in the capacitor 708 is maintained for a long time even while power supply voltage is not supplied to the capacitor 700. In this way, the storage element 700 maintains its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold

[0278] Furthermore, by providing the switches 703 and 704, the precharge operation Since the memory element is characterized by performing the above, after the power supply voltage is restarted, the circuit 701 returns to the original state. This reduces the time required to re-store data.

[0279] In the circuit 702, the signal held by the capacitor 708 is 10. Therefore, the supply of the power supply voltage to the memory element 700 is resumed. After that, the signal held by the capacitor 708 is transferred to the transistor 710 in the ON state ( or OFF state) and can be read out from the circuit 702. Even if the potential corresponding to the signal held in 708 fluctuates slightly, the original signal can be read accurately. It is possible to do this.

[0280] Such a storage element 700 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0281] In this embodiment, the storage element 700 is used as a CPU. 00 is a DSP (Digital Signal Processor), custom LS I, LSI such as PLD (Programmable Logic Device), RF -Can also be applied to ID (Radio Frequency Identification) It is Noh.

[0282] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0283] (Embodiment 8) In this embodiment, the transistors described in the first embodiment, the fifth embodiment, and the 6, or the CPU etc. (DSP, custom LS) described in the seventh embodiment. Examples of electronic devices that can use the ID (including I, PLD, and RF-ID) will be described below.

[0284] The transistor described in the first embodiment, the memory device described in the fifth embodiment, and the memory device described in the sixth embodiment The CPU etc. described in the seventh embodiment can be used in various electronic devices (including gaming machines). The electronic devices include display devices such as televisions and monitors, lighting devices, and photovoltaic devices. Personal computers, word processors, image playback devices, portable audio players Radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones , transceivers, radios, game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translation Translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips , microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioners air conditioning equipment such as showers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation measuring devices, dialysis machines, X-ray machines Medical equipment such as diagnostic equipment, etc. Smoke detectors, heat detectors, gas alarms, Examples include alarm devices such as burglar alarms. In addition, guide lights, traffic lights, conveyor belts, Industrial equipment such as elevators, escalators, industrial robots, and power storage systems are also included. In addition, the vehicle is propelled by an engine using fuel or an electric motor using power from a non-aqueous secondary battery. Moving objects that move forward are also included in the category of electronic devices. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that replace these tires with tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes Examples of these electronic devices include planetary probes and spacecraft. Some specific examples are shown in Figure 23.

[0285] A television set 8000 shown in FIG. 23A includes a housing 8001 and a display unit 8002. The display unit 8002 displays images and the speaker unit 8003 outputs sounds. The transistors described in the above embodiments can be incorporated into the housing 8001. The semiconductor laser diode can be used in a driver circuit or pixel for operating the display portion 8002. .

[0286] The display unit 8002 is a light-emitting device having a light-emitting element such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Device) ce), PDP (Plasma Display Panel), etc. You can be there.

[0287] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via (from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to do so.

[0288] The television device 8000 also includes a CPU 8004 for performing information communication, a memory The CPU 8004 and the memory may include the transistors shown in the above embodiments. , storage device, or CPU can be used to reduce power consumption.

[0289] The alarm device 8100 shown in FIG. 23(A) is a residential fire alarm, and is used to detect smoke or heat. 8 is an example of an electronic device using a microcomputer 8101 and a power supply 8102. The computer 8101 may include a transistor, a memory device, or a CP shown in the above embodiment. Contains U.

[0290] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The sensor may be a device including a transistor, a memory device, a CPU, or the like shown in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a In FIG. 23A, the CPU 8203 controls the indoor unit 8200. 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor shown in the above embodiment may be used as a CP of an air conditioner. By using U, power consumption can be reduced.

[0291] An electric refrigerator-freezer 8300 shown in FIG. 23(A) is the same as the transformer shown in the previous embodiment. This is an example of an electronic device that includes a register, a memory device, or a CPU. The storage room 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 83 23A, a CPU 8304 is provided inside a housing 8301. The transistor described in the above embodiment is used in the CPU 830 of the electric refrigerator-freezer 8300. By using 4, power saving can be achieved.

[0292] 23(B) and 23(C) show an example of an electric vehicle, which is an example of an electronic device. A secondary battery 9701 is mounted on the automobile 9700. The power of the secondary battery 9701 is The output is adjusted by the circuit 9702 and supplied to the driver 9703. , and is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). By using the transistor described in the above embodiment for the CPU of the electric vehicle 9700, This allows for power savings.

[0293] The drive unit 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured by combining the operations of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., information about the drive wheels) The circuit 970 outputs a control signal to the circuit 9702 based on input information (such as load information). 2 is a secondary battery 9701 supplied with electric energy in response to a control signal from a processing device 9704. The output of the drive unit 9703 is controlled by adjusting the gear ratio. Although not shown, an inverter for converting direct current to alternating current is also built in.

[0294] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. [Example]

[0295] In this example, a transistor having the same structure as the transistor 460 shown in FIG. 6A was used as an example sample. The transistor was fabricated and its cross-sectional shape was investigated. The characteristics were evaluated.

[0296] First, the method for preparing the example samples will be described.

[0297] First, a 300 nm thick silicon oxynitride (SiO The silicon oxynitride film was formed by sputtering with argon and oxygen. (Argon:Oxygen=25sccm:25sccm) mixed atmosphere, pressure 0.4P a) Power supply power (power output) 5.0 kW is applied, and the distance between the silicon substrate and the target is The film was formed under the conditions of a thickness of 60 mm and a substrate temperature of 100°C.

[0298] After polishing the surface of the silicon oxynitride film, a first oxide film with a thickness of 10 nm and a second oxide film with a thickness of 40 nm were formed. The first oxide film was formed by stacking In:Ga:Zn Sputtering using an oxide target (IGZO(132)) with an atomic ratio of 1:3:2 The ring method was used to mix argon and oxygen (argon:oxygen = 30sccm:15sccm). In the mixed atmosphere, a pressure of 0.4 Pa and a power supply of 0.5 kW were applied to the target and the substrate. The distance between the electrodes was 60 mm, and the substrate temperature was 200°C. The oxide semiconductor film was formed using In:Ga: Spatial analysis using oxide target (IGZO(111)) with Zn=1:1:1 (atomic ratio) Argon and oxygen (argon:oxygen = 30sccm:15sccm) were mixed by the pulsating method. ) In a mixed atmosphere, a pressure of 0.4 Pa and a power supply of 0.5 kW were applied, and the target and The film was formed with the distance between the substrates set to 60 mm and the substrate temperature set to 300° C. The oxide semiconductor film and the oxide semiconductor film were successively formed without exposure to the air.

[0299] Next, a heat treatment was carried out. The heat treatment was carried out in a nitrogen atmosphere at 450°C for 1 hour, and then in an oxygen atmosphere. The heating was carried out at 450°C for 1 hour under atmospheric pressure.

[0300] Next, a tungsten film having a thickness of 5 nm was formed as a hard mask on the oxide semiconductor film. A hard mask was formed by etching. By using the inductively coupled plasma etching method, carbon tetrafluoride Under nitrogen (CF4=100sccm) atmosphere, power supply power 2000W, bias power 50W, pressure The process was carried out at a pressure of 0.67 Pa, and then carbon tetrafluoride and oxygen (CF4:O2 = 60 sccm:4 0 sccm) mixed atmosphere, power supply power 1000 W, bias power 25 W, pressure 2.0 Pa I went there.

[0301] Next, the first oxide film and the oxide semiconductor film are etched by an ICP etching method using methane and and argon (CH4:Ar = 16 sccm: 32 sccm) mixed atmosphere, power supply power 6 Etching was performed at 100 W, bias power 100 W, pressure 1.0 Pa, and substrate temperature 70°C. The first oxide film and the oxide semiconductor film were processed into island-shaped films.

[0302] Next, a source electrode and a drain electrode are formed on the first oxide film and the oxide semiconductor film. The deposition conditions were as follows: tungsten target: In an argon (argon 80sccm) atmosphere, A pressure of 0.8 Pa and a power supply power (power output) of 1.0 kW were applied to the silicon substrate and the target. The film was formed under the conditions of a distance of 60 mm between the electrodes and a substrate temperature of 230°C.

[0303] Next, a resist mask was formed on the tungsten film, and etching was performed. The first etching was performed by ICP etching using carbon tetrafluoride (CF4 = 100 sc). The test was carried out in a 2000W (cm) atmosphere with a source power of 2000W, a bias power of 50W, and a pressure of 0.67Pa. Then, the second etching was performed with carbon tetrafluoride and oxygen (CF4:O2 = 60 sccm: 40 s ccm) mixed atmosphere, power supply power 1000 W, bias power 25 W, pressure 2.0 Pa A source electrode and a drain electrode were formed.

[0304] Next, a second oxide film having a thickness of 5 nm was formed on the oxide semiconductor film, the source electrode, and the drain electrode. The film was formed under the following conditions: In:Ga:Zn=1:3:2 (atomic ratio) oxide target Argon and oxygen (Al) were deposited by sputtering using IGZO(132). In a mixed atmosphere of ethanol and oxygen (30sccm:15sccm), the pressure was 0.4Pa and the voltage was The source power was 0.5 kW, the distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C. It was decided.

[0305] Next, a 10 nm silicon oxynitride film was formed by CVD to serve as a gate insulating film.

[0306] Next, a titanium nitride film with a thickness of 10 nm was formed on the silicon oxynitride film by sputtering. In a nitrogen (N2 = 50 sccm) atmosphere, a pressure of 0.2 Pa and a power supply power of 12 kW were applied. The distance between the target and the substrate was 400 mm, and the substrate temperature was room temperature. A 10 nm tungsten film was deposited under an argon (Ar=100 sccm) atmosphere at a pressure of 2.0 P. a) Power supply power of 4 kW is applied, the distance between the target and the substrate is 60 mm, and the substrate temperature is 230 The film was formed by laminating at 100°C.

[0307] Next, a 10 nm thick titanium nitride film and a 10 nm thick titanium nitride film were formed by ICP etching. The tungsten film stack was etched under the etching conditions of chlorine, carbon tetrafluoride, and acid. Under a mixed atmosphere of Cl2:CF4:O2 = 45sccm:55sccm:55sccm The first etching was performed at a source power of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa. After the first etching, boron trichloride and chlorine (BCl3:Cl2 = 150 sccm: 50sccm) mixed atmosphere, power supply power 1000W, bias power 50W, pressure A second etch was performed at a force of 0.67 Pa to form the gate electrode.

[0308] Next, the gate insulating film and the second insulating film are formed by ICP etching using the gate electrode as a mask. The oxide film stack was etched under the etching conditions of methane and argon (CH4 : Ar = 16 sccm: 32 sccm) mixed atmosphere, power supply power 600 W, bias power Etching was carried out at 100 W, a pressure of 1.0 Pa, and a substrate temperature of 70°C.

[0309] Next, an aluminum oxide film with a thickness of 20 nm was formed on the gate electrode by sputtering. A silicon oxynitride film having a thickness of 150 nm was formed thereon by the CVD method.

[0310] A cross-sectional STEM photograph of the example sample prepared by the above method is shown in FIG. 10. 10(B) is a cross-sectional view in the channel width direction.

[0311] As shown in FIG. 10B, the channel width direction of the IGZO(111) oxide semiconductor film The cross section of the side is semicircular with rounded edges. Improved coverage of the second oxide film, gate insulating film, and gate electrode formed on the semiconductor film It was confirmed that no defects in shape such as cuts occurred.

[0312] The channel length of the fabricated transistor was 68 nm and the channel width was 34 nm. .

[0313] Next, in the fabricated transistor, the drain voltage (V d :[V]) is 0.1V or 1V, and the gate voltage (V g : [V]) from -3V to 3V, the drain voltage Flow (I d The measurement results for the example transistor are shown in FIG. 29, the solid line indicates the drain voltage (V d :[V]) is 1V, and the point The line indicates the drain voltage (V d The horizontal axis shows the measurement results when the gate voltage (V) is 0.1V. Pressure (V g :[V]), and the vertical axis is the drain current (I d : [A]. Note that "drain voltage (V d :[V]) is the potential difference between the drain and source with respect to the source, and Voltage (V g :[V]) is the potential difference between the gate and source relative to the source.

[0314] As shown in FIG. 29, the on-state current of the transistor fabricated in this example increases with increasing drain voltage (V d When the drain voltage was 0.1 V, the current was 5.31 μA. The field-effect mobility is 20.0 cm 2 / Vs. The shift value was 0.13 A. Note that the drain current was 1 × 10 -12 A The gate voltage value at this point is defined as the shift value. The drain voltage was 0.65 V. The S value was 113.1 mV when the drain voltage was 0.1 V. / dec. In addition, the off-state current at a drain voltage of 1 V was below the lower limit of measurement. .

[0315] From the above, it can be seen that the transistor of this embodiment has excellent electrical characteristics. was shown. [Example]

[0316] In this example, the temperature dependency of the transistor fabricated in Example 1 was evaluated.

[0317] The evaluation was performed under three conditions: -25°C, 50°C, and 150°C. d:[V]) 1V, gate voltage (V g :[V]) from -3V to 3V, the drain current ( I d The field effect mobility (μFE) of the example transistor was measured. The measurement results are shown in Figure 30. In Figure 30, the horizontal axis represents the gate voltage (V g :[V]), on the left The vertical axis is the drain current (I d :[A]), and the vertical axis on the right is the field-effect mobility (μFE:cm 2 / Vs).

[0318] As shown in FIG. 30, the transistor fabricated in Example 1 exhibited a change in on-current and It was confirmed that the field-effect mobility did not change significantly.

[0319] FIG. 31 shows the temperature dependency of the threshold voltage.

[0320] It was confirmed that the threshold voltage value does not change significantly with temperature changes.

[0321] From the above, it is shown that the transistor of this example is a transistor with temperature resistance. Ta. [Example]

[0322] In this example, the reliability of the transistor fabricated in Example 1 was evaluated.

[0323] The evaluation was carried out under the stress test conditions of source voltage (Vs: [V]) and drain voltage ( Vd: [V]) was 0V, gate voltage was -1.8V, and drain voltage was applied at 150°C for 1 hour. The measurement results of the example transistor are shown in FIG. In Figure 32(A), when the drain voltage (Vd: [V]) is 0.1V and 1V, The horizontal axis shows the gate voltage (Vg: [V]) and the vertical axis shows the drain current (Id: [ A]).

[0324] In addition, the source voltage (Vs: [V]) and gate voltage (Vg :[V]) was applied at 0V, drain voltage was 1.8V, and the temperature was 150°C for 1 hour. The drain current ( The measurement results of the example transistor are shown in FIG. In Figure 32(B), the measurement results are shown for drain voltages (Vd: [V]) of 0.1V and 1V. The horizontal axis is the gate voltage (Vg: [V]) and the vertical axis is the drain current (Id: [A]). ) is shown.

[0325] The solid line in the figure represents the measurement results before the stress test, and the dotted line represents the measurement results after the stress test. As shown in Fig. 32(A) and Fig. 32(B), the transistor prepared in Example 1 The change in threshold voltage ΔVth when the drain voltage (Vd: [V]) of the transistor is 1V is 0.03V in Figure 32(A) and 0.11V in Figure 32(B), which is a small change. there were.

[0326] Also, in Figure 33 (the square in the figure), the source voltage (Vs: [V]) and gate voltage (Vg :[V]) at 0V, 125℃ for 0.01 years (87.6 hours), drain voltage (Vd:[V ]) is applied at 1.8 V, and the change in threshold voltage is shown.

[0327] Also, in Figure 33 (diamonds in the figure), the source voltage (Vs: [V]) and drain voltage (V d:[V]) at 0V, 125℃ for 0.01 years (87.6 hours), gate voltage (Vg:[V ]) is applied at -1.8V, and the change in threshold voltage is shown.

[0328] As shown in Figure 33, the change in threshold voltage of the transistor fabricated in Example 1 was 0. It was confirmed that the amount of change was small even after 01 years had passed.

[0329] From the above, it can be seen that the transistor of this embodiment has high electrical stability. was shown. [Example]

[0330] In this example, the electrical characteristics of the transistor fabricated in Example 1 are evaluated with respect to the channel width. was carried out.

[0331] First, the drain voltage (V d :[V]) is the on-current (I on :[A]) was measured. The measurement results of the example transistor are shown in FIG. In FIG. 34(A), the horizontal axis is the channel length [nm] and the vertical axis is the on-current (I on :[A]) In the figure, the diamonds have a channel width of 40 nm, the triangles have a channel width of 100 nm, The squares indicate the measurement results when the channel width is 500 nm.

[0332] As shown in Figure 34(A), even if the channel width is narrowed, the on-current I on It has been confirmed that came.

[0333] Next, the drain voltage (V d :[V]) is 0.1V, the electric field effect on the channel width The mobility was measured. The measurement results of the example transistor are shown in FIG. 34(B). In B), the horizontal axis is the channel length [nm] and the vertical axis is the field effect mobility (μFE: cm 2 / V In the figure, the diamonds indicate a channel width of 40 nm, and the triangles indicate a channel width of 100 nm. m, and the squares indicate the measurement results when the channel width was 500 nm.

[0334] It was confirmed from FIG. 34(B) that the mobility was higher when the channel width was narrower.

[0335] Next, the drain voltage (V d :[V]) is the threshold voltage for the channel width when The measurement results of the example transistor are shown in FIG. 34(C). In the graph, the horizontal axis is the channel length [nm] and the vertical axis is the threshold voltage (V th :[V]) The diamonds in the figure have a channel width of 40 nm, the triangles have a channel width of 100 nm, and the squares have a channel width of 100 nm. The measurement results are shown when the channel width is 500 nm.

[0336] It can be seen from FIG. 34(C) that the threshold voltage does not change much.

[0337] Next, the drain voltage (V d : [V]) is 1V, the shift value for the channel width is measured. The shift value is the rising voltage, and the drain current (I d :[A] ) is 1E-12A when the gate voltage (V g :[V]) Example Transistor The measurement results are shown in Figure 34(D). In Figure 34(D), the horizontal axis is the channel length [nm], The vertical axis shows the shift value [V]. The diamonds in the figure show the channel width of 40 nm, and the triangles show the channel width of 10 nm. The squares show the measurement results when the channel width was 100 nm, and the squares show the measurement results when the channel width was 500 nm.

[0338] From Figure 34(D), it was confirmed that the narrower the channel width, the smaller the change in the shift value. .

[0339] Next, the drain voltage (V d: [V]) is 0.1V. The measurement results of the example transistor are shown in FIG. 35(A). In the figure, the horizontal axis indicates the channel length [nm] and the vertical axis indicates the S value [mV / dec.]. The squares have a channel width of 40 nm, the triangles have a channel width of 100 nm, and the squares have a channel width of 50 nm. The measurement results at 0 nm are shown.

[0340] It was confirmed from FIG. 35(A) that the S value decreased as the channel width became narrower.

[0341] Next, we measured the DIBL as a function of the channel width. d :[V]) The drain voltage (V d :[V]) is 1V The value obtained by subtracting the value voltage from the output voltage and dividing it by 0.9 is the DIBL. The measurement results are shown in Figure 35(B). In Figure 35(B), the horizontal axis is the channel length [nm]. The vertical axis indicates the DIBL value [V / V]. The diamonds in the figure indicate the channel width of 40 nm. The triangles show the measurement results when the channel width was 100 nm, and the squares show the measurement results when the channel width was 500 nm. vinegar.

[0342] Figure 35(B) shows that the DIBL decreases as the channel width becomes narrower. Confirmed.

[0343] From the above, it can be seen that the transistor of this embodiment has better electrical characteristics as the channel width becomes narrower. It was shown to be a transistor. [Example]

[0344] In this example, a transistor having the same structure as the transistor 460 shown in FIG. 6A was used as an example sample. The transistors were fabricated and their electrical characteristics were evaluated.

[0345] First, the method for preparing the example samples will be described.

[0346] The manufacturing method of the example sample can be referred to Example 1. Unlike Example 1, the first oxide film in this example has a thickness of 10 nm, and the film formation conditions are as follows: Oxide target (IGZO(134)) with In:Ga:Zn=1:3:4 (atomic ratio) Argon and oxygen (argon:oxygen = 30 sccm) were deposited by sputtering. 15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5kW, The film was formed with the distance between the target and the substrate set to 60 mm and the substrate temperature set to 200°C.

[0347] Moreover, an example transistor having a channel length of 70 nm and a channel width of 40 nm was fabricated.

[0348] Next, in the fabricated transistor, the drain voltage (V d :[V]) is 1V, Voltage (V g :[V]) from -3V to 3V, the drain current (I d :[A ]) was measured. In addition, the field effect mobility (μFE) at a drain voltage of 0.1 V was The measurement results of the example transistor are shown in FIG. Input Voltage (V d :[V]) is 1V, and the horizontal axis is the gate voltage (V g :[ V]), and the left vertical axis is the drain current (I d :[A]), and the vertical axis on the right is the field-effect mobility (μ FE:cm 2 / Vs).

[0349] As shown in FIG. 11, the on-state current of the transistor fabricated in this example increases with increasing drain voltage (V d When the drain voltage was 0.1 V, the current was 5.08 μA. The field-effect mobility is 17.0 cm 2 / Vs.

[0350] From the above, it can be seen that the transistor of this embodiment has excellent electrical characteristics. was shown. [Example]

[0351] In this example, a transistor having the same structure as the transistor 460 shown in FIG. 6A was used as an example sample. The transistors were fabricated and their electrical characteristics were evaluated with respect to the channel width.

[0352] First, the method for preparing the example samples will be described.

[0353] The method for preparing the example samples can be referred to Example 1. The first oxide film is IGZO(132) with a thickness of 10 nm, and the oxide semiconductor film is 40 nm. IGZO (111)) was used as sample A, and the sample used in Example 5 (the first oxide film was 10 nm thick) was used as sample B. IGZO(134) with a thickness of 40 nm, and IGZO(111) with a thickness of 40 nm. The first oxide film is IGZO(132) with a thickness of 20 nm, and the oxide semiconductor film is 15 nm. The IGZO(111) surface was used for the sample C, which was otherwise identical in structure to the sample A. The film formation conditions for material C were as follows: the first oxide film was an oxide of In:Ga:Zn=1:3:2 (atomic ratio); Argon and oxygen were deposited by sputtering using a metal target (IGZO(132)). Under a mixed atmosphere of argon and oxygen (argon:oxygen = 30sccm:15sccm), the pressure was 0.4 Pa, power supply power 0.5kW, distance between target and substrate 60mm, substrate temperature The oxide semiconductor film was formed at 200°C with an atomic ratio of In:Ga:Zn=1:1:1. Argon and ZnO were deposited by sputtering using an oxide target (IGZO(111)). Under a mixed atmosphere of argon and oxygen (argon:oxygen = 30sccm:15sccm), pressure 0 0.4 Pa, power supply power 0.5 kW, the distance between the target and the substrate was 60 mm, and the substrate The film was formed at a temperature of 300°C.

[0354] Moreover, an example transistor having a channel length of 40 nm was fabricated.

[0355] Next, in the fabricated transistor, the drain voltage (V d :[V]) is 1V On-state current (I on :[A]) was measured. The on-state current is the current value when the gate voltage is the threshold voltage +1V. The measurement results are shown in Figures 12 and 13. In Figures 12 and 13, the horizontal axis represents the number of channels. The vertical axis represents the on-state current (I on :[A]).

[0356] As shown in FIG. 12, sample C, in which the thickness of the oxide semiconductor film is 15 nm, has a short channel width W. As the on-current I on On the other hand, when the thickness of the oxide semiconductor film is increased to 40 nm, In the case of samples A and B, the on-current I on No decrease in It was.

[0357] When the oxide semiconductor film is thicker, the electric field of the lateral gate electrode becomes smaller when the channel width is short. The on-current I onis presumed to have improved.

[0358] FIG. 13A shows the characteristics of the transistor of sample A, and FIG. 13B shows the characteristics of the transistor of sample B. The characteristics of the transistor of sample C are shown in Fig. 13(C). Therefore, under all conditions of Sample A, Sample B, and Sample C, as the channel width W increases, On-state current I on It was confirmed that there is an increasing trend. [Example]

[0359] In this example, a transistor having the same structure as the transistor 460 shown in FIG. 6A was used as an example sample. The transistors were fabricated and the electrical characteristics of the fabricated transistors were evaluated.

[0360] First, the method for preparing the example samples will be described.

[0361] First, a 300 nm thick silicon oxynitride (SiO The silicon oxynitride film was formed by sputtering with argon and oxygen. (Argon:Oxygen=25sccm:25sccm) mixed atmosphere, pressure 0.4P a) Power supply power (power output) 5.0 kW is applied, and the distance between the silicon substrate and the target is The film was formed under the conditions of a thickness of 60 mm and a substrate temperature of 100°C.

[0362] After polishing the surface of the silicon oxynitride film, a first oxide film with a thickness of 20 nm and a second oxide film with a thickness of 20 nm were formed. The first oxide film was formed by stacking In:Ga:Zn Sputtering using an oxide target (IGZO(134)) with an atomic ratio of 1:3:4 Argon and oxygen (argon:oxygen = 40sccm:5sccm) mixed by the ring method In the atmosphere, a pressure of 0.4 Pa and a power supply of 0.5 kW were applied, and the distance between the target and the substrate was The distance between the electrodes was 60 mm, and the substrate temperature was 200°C. The oxide semiconductor film was In:Ga:Z Sputtering using an oxide target (IGZO(111)) with n=1:1:1 (atomic ratio) Argon and oxygen (argon:oxygen = 30sccm:15sccm) were mixed by the tarring method. In the mixed atmosphere, a pressure of 0.4 Pa and a power supply of 0.5 kW were applied, and the target and the substrate were The distance between the plates was 60 mm, and the substrate temperature was 300°C. The oxide semiconductor film and the oxide semiconductor film were successively formed without exposure to the air.

[0363] Next, a heat treatment was carried out. The heat treatment was carried out in a nitrogen atmosphere at 450°C for 1 hour, and then in an oxygen atmosphere. The heating was carried out at 450°C for 1 hour under atmospheric pressure.

[0364] Next, a tungsten film to be a source electrode and a drain electrode was formed on the oxide semiconductor film. The film was deposited to a thickness of 50 nm by sputtering using a tungsten target. Under an argon (argon 80sccm) atmosphere, the pressure was 0.8Pa, and the power supply power ( The source power was 1.0 kW, the distance between the silicon substrate and the target was 60 mm, and the substrate The film was formed at a temperature of 230°C.

[0365] Next, a resist mask was formed on the tungsten film, and etching was performed. The first etching was performed using an ICP etching method with chlorine, carbon tetrafluoride, and oxygen (C l2:CF4:O2=45sccm:55sccm:55sccm) under mixed atmosphere, power supply The power was 3000 W, the bias power was 110 W, and the pressure was 0.67 Pa. Then, the second Etching was performed in an oxygen (O2 = 100 sccm) atmosphere, with a power supply of 2000 W and a bias power of The third etching was performed with chlorine, carbon tetrafluoride, and oxygen. Under a mixed atmosphere of (Cl2:CF4:O2 = 45sccm:55sccm:55sccm), The power supply was 3000 W, the bias power was 110 W, and the pressure was 0.67 Pa. A gate electrode and a drain electrode were formed.

[0366] Next, a resist mask is formed over the oxide semiconductor film, and the first oxide film and the oxide semiconductor film are The conductive film was etched by ICP etching in a boron trichloride (BCl3 = 80 sccm) atmosphere. The test was performed under the conditions of a power supply power of 450 W, a bias power of 100 W, a pressure of 1.2 Pa, and a substrate temperature of 70°C. The first oxide film and the oxide semiconductor film were processed into island-shaped films.

[0367] Next, a second oxide film having a thickness of 5 nm was formed on the oxide semiconductor film, the source electrode, and the drain electrode. The film was formed under the following conditions: In:Ga:Zn=1:3:2 (atomic ratio) oxide target Argon and oxygen (Al) were deposited by sputtering using IGZO(132). In a mixed atmosphere of ethanol and oxygen (30sccm:15sccm), the pressure was 0.4Pa and the voltage was The source power was 0.5 kW, the distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C. It was decided.

[0368] Next, a 20 nm silicon oxynitride film was formed by CVD to serve as a gate insulating film.

[0369] Next, a tantalum nitride film with a thickness of 30 nm was formed on the silicon oxynitride film by sputtering. under an atmosphere of tantalum nitride and argon (TaN:Ar=50sccm:10sccm) The pressure was 0.6 Pa, the power was 1 kW, and the distance between the target and the substrate was 60 mm. The substrate temperature was set at room temperature for film formation, and a tungsten film with a thickness of 135 nm was then deposited on top of it using argon (A r = 100sccm) atmosphere, pressure 2.0Pa, power supply power 4kW was applied, and the target The film was deposited by stacking with the distance between the substrate and the film set to 60 mm and the substrate temperature set to 230°C.

[0370] Next, a tantalum nitride film with a thickness of 30 nm and a tantalum nitride film with a thickness of 135 nm were formed by ICP etching. The etching conditions were chlorine, carbon tetrafluoride, and Oxygen (Cl2:CF4:O2=45sccm:55sccm:55sccm) mixed atmosphere The first electrode was placed under the following conditions: source power 3000W, bias power 110W, pressure 0.67Pa After the first etching, the electrode was removed under a chlorine (Cl2 = 100 sccm) atmosphere. The second etching was performed at a source power of 1000 W, a bias power of 50 W, and a pressure of 0.67 Pa. A gate electrode was formed.

[0371] Next, the gate insulating film and the second oxide film are etched by ICP etching. The etching conditions were a boron trichloride (BCl3 = 80 sccm) atmosphere with a power supply of 4 Etching was performed at 50 W, bias power 100 W, pressure 1.2 Pa, and substrate temperature 70°C. went.

[0372] Next, an aluminum oxide film with a thickness of 140 nm was formed on the gate electrode by sputtering. A silicon oxynitride film having a thickness of 300 nm was formed thereon by the CVD method.

[0373] The channel length of the fabricated transistor was 0.48 μm and the channel width was 0.5 μm. .

[0374] Next, the temperature dependence of the fabricated transistor was evaluated.

[0375] The evaluation was carried out under six conditions: 25°C, 50°C, 100°C, 150°C, 200°C and 250°C. Rain voltage (V d :[V]) is 1V, and the gate voltage (V g :[V]) from -3V to 3V The drain current (I d :[A]) was measured. The measurement results of the example transistor are shown in FIG. 40(A). In FIG. 40(A), the horizontal axis is the gate voltage (V g :[V]), and the vertical axis is the drain current (I d :[A]). The arrows in the middle indicate that the temperature increases from the base of the arrow to the tip. are.

[0376] As shown in FIG. 40, the transistor fabricated in this example has an on-current due to temperature changes. It was confirmed that there was no significant change.

[0377] The temperature dependence of the threshold voltage and S value is shown in Figures 40(B) and 40(C). ) shown.

[0378] It was confirmed that the threshold voltage and S value do not change significantly with temperature changes.

[0379] From the above, it is shown that the transistor of this example is a transistor with temperature resistance. Ta. [Example]

[0380] In this example, a difference in electrical characteristics depending on the shape of an oxide semiconductor film was investigated by simulation. A survey was conducted and evaluated.

[0381] First, the structure of the transistor will be described.

[0382] FIG. 25A shows a transistor having an oxide semiconductor film with a rectangular upper end portion (hereinafter, referred to as a rectangular structure). This is a cross-sectional view of a transistor (also called a transistor with a MOSFET structure) in the channel width direction. The thickness of the oxide semiconductor film was set to W / 2.

[0383] FIG. 25B shows a structure in which the upper end portion of the oxide semiconductor film, which is one embodiment of the present invention, has a curved surface. The channel width direction of a transistor having a semicircular structure (hereinafter also referred to as a transistor having a semicircular structure) In the figure, r indicates the radius of curvature, and is set to r=W / 2.

[0384] In the square and semicircular structures, the effective channel width is The sum of the face and top surface is 2W, and in the semicircular structure, the circumference is πr = πW / 2 = 1.57W. In this case, the ratio of the effective channel width W is 0.785.

[0385] 25(A) and 25(B) are cross-sectional views in the channel length direction of the transistors shown in FIG. In both cases, the L indicates the channel length.

[0386] Next, the calculation conditions will be described.

[0387] The calculation was performed using Synopsys' Sentaurus under the conditions shown in Table 1. Simulation was performed.

[0388] [Table 1]

[0389] Figure 27 shows the drain voltage (Vd :[V]) is 0.1V when I d -V g properties and mobility, Figure 28 shows the drain voltage (V d :[V]) is 1V when I d -V g The properties and mobility are shown.

[0390] From Figures 27 and 28, the semicircular structure I d -V g The characteristics are faster than the square structure. The mobility calculated using the effective channel width W is The structure is larger.

[0391] Table 2 shows a comparison of various characteristic values ​​obtained from FIGS. 27 and 28.

[0392] [Table 2]

[0393] Table 2 shows that the semicircular structure is superior to the square structure in all other characteristics except for the on-current. The ratio of the on-current is also 0.892, which is the ratio of the effective channel width W to the on-current. This means that the semicircular structure makes it easier to induce electrons in the channel area. It can be said that this is the case.

[0394] The reason why the semicircular structure is more likely to induce electrons in the channel region is that the effective channel width W and One possible reason is the relationship between the on-current and the capacitance of the gate insulating film (hereafter, It is thought that the GI capacitance is proportional to the GI capacitance (also called the GI capacitance), but in the semicircular structure, the GI capacitance is calculated using the equation is not expressed by the formula, but is approximately expressed by the formula below.

[0395]

number

[0396] C r is the GI capacitance per unit channel length of the semicircular structure, ε is the dielectric constant of the gate insulating film, t GI is the thickness of the gate insulating film, t OS represents the thickness of the oxide semiconductor film.

[0397] For a semicircular structure, the GI capacitance is determined by the effective channel width W(πt OS ) and on The current cannot be discussed in terms of the ratio of the effective channel width W as described above.

[0398] On the other hand, the GI capacity per unit channel length of a square structure is approximately expressed by the following formula:

[0399]

number

[0400] To calculate the on-current, it is necessary to consider the ratio of the GI capacitance, and the square structure calculated from Equation 2 The ratio of the GI capacity of the semicircular structure calculated from Equation 1 to the GI capacity of the semicircular structure is C r / C s =0.9 This is approximately 68, which is larger than the ratio of the effective channel width W to the The semicircular structure is similar to the one shown in the figure, so it does not match the ratio calculated by simulation. It can be said that electrons are more easily induced in the channel portion in the case of <Reference example>

[0401] In this reference example, the transistor using the CAAC-OS film has high resistance to the short-channel effect. This section explains why there is sufficient

[0402] The characteristic length is used as an index of resistance to short channel effects. The characteristic length is the length at which the potential of the channel is bent. The shorter the characteristic length, the steeper the potential rises. Resistant to vibration effects.

[0403] The transistor using the CAAC-OS film is an accumulation-mode transistor. The reason why transistors using S film are resistant to the short channel effect is that the characteristic length of the accumulation type transistor is This is thought to be due to the fact that the characteristic length is shorter than that of an inversion type transistor.

[0404] A detailed description will be given using a schematic diagram of the transistor structure in FIG. S is the semiconductor film Dielectric constant, ε OX is the dielectric constant of the gate insulating film, t S is the thickness of the semiconductor film, t OX is the gate insulating film The thickness is

[0405] First, consider an n-channel inversion transistor and solve its Poisson equation to find the The potential of the channel portion is analyzed. The following formula was derived by applying Gauss's law to the small section x to x+dx in the conductive film.

[0406]

number

[0407] Here, φ(x) is the potential at position x (surface potential), φ(x+dx ) is the potential (surface potential) at the position x + dx, V G is the gate voltage, V F B is the flat band voltage, e is the elementary charge, N A is the acceptor density.

[0408] The above formula 3 can be rearranged as follows:

[0409]

number

[0410] Here, the following formula 5 was substituted into formula 4 to obtain formula 6.

[0411]

number

[0412]

number

[0413] Furthermore, a general solution to Equation 6 was obtained using Equation 7 below, and Equation 8 was obtained.

[0414]

number

[0415]

number

[0416] Furthermore, the potential φ(x) satisfies the following boundary conditions:

[0417]

number

[0418] By finding and rearranging the coefficients A and B so that the above boundary conditions are satisfied, the particular solution of the differential equation can be obtained. and the potential φ(x) is

[0419]

number

[0420] In fact, by substituting x=0 or x=L, Equation 10 can be expressed as the boundary of Equation 9. It is easy to verify that the conditions are met.

[0421] Here, l in the formula is the characteristic length, which is an index of the ease of bending of the potential. The potential of the FET channel changes more sharply.

[0422] Therefore, the characteristic length of the inversion transistor is as follows:

[0423]

number

[0424] Next, we investigated the accumulation-mode transistors including the transistors using the CAAC-OS film. The same consideration is made for the characteristic lengths of the small holes in the semiconductor film that forms the channel. Applying Gauss's law to the interval x to x+dx, we derived the following equation:

[0425]

number

[0426] where n i is the intrinsic carrier density, k B is the Boltzmann constant, φ F is the Fermi potential It is.

[0427] The above formula can be rearranged as follows:

[0428]

number

[0429] Here, l is equal to the characteristic length of an inversion transistor.

[0430] The right side of Equation 13 is expanded using the following approximation (Equation 14) to the above equation, and Equation 15 is obtained. obtained.

[0431]

number

[0432]

number

[0433] Here, n1 is the electron density at the position x1. Furthermore, the following formulas 16 and 17 Substituting this into Equation 15, we obtain Equation 18.

[0434]

number

[0435]

number

[0436]

number

[0437] Furthermore, Equation 18 was rearranged using Equation 19 below to obtain Equation 20.

[0438]

number

[0439]

number

[0440] Note that the above formula is only valid in the vicinity of point x1.

[0441] From the above discussion, the characteristic length of an accumulation-type transistor in the vicinity of point x1 is as follows: becomes.

[0442]

number

[0443]

number

[0444] From the above formula, it can be seen that l(inv)>l(acc).

[0445] The characteristic length l(acc) of the accumulation-type transistor calculated from point x1 is , changes, but in either case it is shorter than an inverting transistor. The electron density is higher near the source / drain, so the potential rises more steeply. .

[0446] As a result, the characteristic length of the accumulation-type transistor is shorter than that of the inversion-type transistor. It has been shown that this will happen. [Explanation of symbols]

[0447] 110 Substrate 120 Undercoat insulating film 137 Channel Region 138 Channel Region 160 Gate insulating film 170 gate electrode 210 Substrate 220 Undercoat insulating film 230 Oxide semiconductor film 260 Gate insulating film 270 gate electrode 400 boards 402 Undercoat insulating film 403a First oxide film 403b Oxide semiconductor film 403c Second oxide film 404 Multilayer film 404a First oxide film 404b Oxide semiconductor film 404c Second oxide film 405a Conductive film 405b Conductive film 406a Source electrode 406b Drain electrode 407 Insulating Film 408 Gate insulating film 409 Conductive Film 410 gate electrode 412 Oxide insulating film 414 Barrier Film 416 Sidewall insulating film 418 Sidewall insulating film 419a electrode 419b Electrode 420a wiring 420b wiring 435 Boundary 450 transistors 460 transistors 470 transistors 550 transistors 560 transistors 570 Transistors 580 transistors 602 Photodiode 640 transistors 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 672 Photo sensor reference signal line 700 memory elements 701 circuits 702 circuits 703 Switch 704 Switch 706 Logic Elements 707 Capacitor 708 Capacitor 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 circuits 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 transistors 2201 Insulating film 2202 Wiring 2203 Plug 2204 Insulating film 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detector 8200 indoor unit 8201 Housing 8202 Ventilation outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing equipment

Claims

[Claim 1] a first oxide film; an oxide semiconductor film on the first oxide film; a source electrode and a drain electrode in contact with the oxide semiconductor film; a second oxide film on the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film on the second oxide film; a gate electrode in contact with the gate insulating film, an upper end portion of the oxide semiconductor film in a channel width direction has a curved surface; an upper surface of the oxide semiconductor film has a flat portion; each of two end portions of the oxide semiconductor film in a channel width direction has a radius of curvature that is greater than 0 and equal to or less than half the channel width; a radius of curvature of an upper end portion of the oxide semiconductor film in a channel width direction is greater than 0 and equal to or less than half the channel width.

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