Semiconductor device

Abstract

To provide a semiconductor device with a novel structure and a manufacturing method for the same, and for example, to improve reliability of a transistor driven at high voltage or large current.SOLUTION: In order to improve reliability of a transistor, a buffer layer that relieves electric field concentration is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer, and an end of the buffer layer has a sectional shape that projects through a side face of the drain electrode layer (or the source electrode layer). The buffer layer is composed of a lamination layer including a single layer or a plurality of layers, for example, an In-Ga-Zn-O film including nitrogen, an In-Sn-O film including nitrogen, an In-Sn-O film including SiOx, or the like is used.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a transistor or a circuit including a transistor. For example, the present invention relates to a semiconductor device, a transistor in which a channel formation region is formed of an oxide semiconductor, The present invention relates to a semiconductor device having a circuit including a transistor. [Background technology]

[0002] A transistor or the like is manufactured using an oxide semiconductor film in the channel formation region, and the transistor is applied to a display device. For example, zinc oxide (ZnO) is used as the oxide semiconductor film. Transistors and InGaO3 (ZnO) m These transistors include A transistor using the oxide semiconductor film is formed over a light-transmitting substrate, and an image display device is manufactured using the transistor. Patent Documents 1 and 2 disclose techniques used for switching elements in devices.

[0003] An oxide semiconductor film containing In, Ga, and Zn was used as the semiconductor layer, and the semiconductor layer and the source electrode A reverse staggered type (bore type) in which a buffer layer made of metal oxide is provided between the electrode and drain electrode layers. A transistor with a Tom gate structure is disclosed in Patent Document 3. This transistor has the following features: A metal oxide layer is provided as a buffer layer between the source electrode layer, the drain electrode layer and the semiconductor layer. By intentionally providing this, an ohmic contact is formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-056539 Summary of the Invention [Problem to be solved by the invention]

[0005] There are various types of display devices, and blue phase liquid crystals are attracting attention in liquid crystal display devices. In addition, a display device called electronic paper uses a medium whose contrast can be electrically changed. In addition, electroluminescent materials (also known as electronic ink) are used. Self-luminous display devices using luminescent materials are also being put to practical use. In order to support this display method, transistors used in display devices are required to have higher breakdown voltage. It is being considered.

[0006] In addition, the transistors used in the display device have a gate voltage that is as close to 0V as possible. It is desirable that the channel is formed at the threshold voltage of the transistor. When the gate voltage is 0V, current flows between the source and drain electrodes. In an active matrix display device, the circuit The electrical characteristics of the transistors that make up the display are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is important among the electrical characteristics of a transistor. Even if the field effect mobility is high, if the threshold voltage value is negative, it is difficult to control it as a circuit. It is difficult to form a channel and have a drain current flow even under negative voltage conditions. However, this type of transistor is not suitable for use in circuits.

[0007] In view of the above problems, one embodiment of the present invention provides a semiconductor device having a novel structure or a manufacturing method thereof. The objective is to provide

[0008] The threshold voltage of the transistor can be made positive, so that it is a so-called normally-off switch. It is an object of the present invention to provide a semiconductor device having a structure capable of realizing a switching element.

[0009] In addition, depending on the material and manufacturing conditions, the manufactured transistor may not be normally off. Even in this case, it is important to approach the normally-off characteristics, and the threshold voltage value is Even if the transistor is normally on, the threshold voltage approaches zero. It is also an object of the present invention to provide a structure and a manufacturing method thereof.

[0010] Another object of the present invention is to improve the reliability of transistors driven by high voltages or large currents. It shall be one. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a buffer layer in contact with the oxide semiconductor layer, and a buffer layer. a source electrode layer or a drain electrode layer overlapping with the oxide semiconductor layer via a layer; a gate insulating layer in contact with the oxide semiconductor layer; and a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween. the gate electrode layer has a laminated structure, and one layer of the gate electrode layer is in contact with the gate insulating layer. The buffer layer is preferably a metal oxide containing nitrogen. This is a semiconductor device characterized by the above.

[0012] As one layer of the gate electrode layer in contact with the gate insulating layer, a metal oxide containing nitrogen, specifically, Nitrogen-containing In-Ga-Zn-O film, nitrogen-containing In-Sn-O film, nitrogen-containing In -Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn-O film, nitrogen-containing In-O film or metal nitride film (InN, SnN, etc.) is used. These films have a 5 eV , preferably has a work function of 5.5 eV or more, and when used as a gate electrode layer, The threshold voltage of the electrical characteristics of the transistor can be made positive, which is called a normally-off transistor. This makes it possible to realize a switching element.

[0013] In addition, in order to improve the reliability of the transistor, the edge of the buffer layer is connected to the drain electrode layer (or The cross-sectional shape of the gate electrode protrudes from the side of the source electrode layer, thereby reducing the electric field concentration.

[0014] The material used for the oxide semiconductor layer is at least indium (In) or zinc (Z It is preferable that the oxide contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors In addition, it is preferable to contain gallium (Ga). Also, tin (S) is used as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is also preferable that the stabilizer contains aluminum (Al). It's nice.

[0015] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0016] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxide, In-Sn-Zn oxide (also called ITZO (registered trademark)), Sn-Ga -Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf- Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Z n-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide Oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides, and oxides of quaternary metals. In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-G a-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide In-Hf-Al-Zn based oxides can be used.

[0017] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0018] The buffer layer is composed of a single layer or a laminate of multiple layers, and is, for example, an In-Ga- containing nitrogen layer. Zn-O film, In-Sn-O film containing nitrogen, In-Sn-O film containing SiOx, etc. The resistance value of the buffer layer is determined by the nitrogen content in the case of an In-Ga-Zn-O film containing nitrogen. It can be set appropriately by adjusting the value. In the case of an In-Sn-O film containing SiOx, The thickness can be appropriately set by adjusting the content of SiOx. Since the buffer layer has a structure in which the oxide semiconductor layer forming the channel formation region is laminated with the buffer layer, The resistance value of the buffer layer can also be adjusted by adjusting the thickness.

[0019] The buffer layer has a lower light transmittance than the oxide semiconductor layer. When an In-Ga-Zn-O film containing silicon is used, the light transmittance is higher than that of an In-Ga-Zn-O film. Since the oxide semiconductor layer has a low refractive index and a light-shielding property, it can prevent light from being irradiated to a region of the oxide semiconductor layer that overlaps with the buffer layer. In addition, a nitrogen-containing In-Ga-Zn-O film is used as the buffer layer. In this case, the nitrogen concentration in the buffer layer is set to be higher than that in the oxide semiconductor layer in contact with the buffer layer. The concentration is also high.

[0020] The buffer layer is at least connected to the gate electrode layer via the oxide semiconductor layer and the gate insulating layer. There is also some overlap.

[0021] The gate electrode layer is a laminated layer using aluminum, copper, or the like in at least one layer. When copper is used as one layer of the gate electrode layer, the process after forming the gate electrode layer is preferably The temperature must be 450°C or less.

[0022] In addition, when aluminum is used as one layer of the gate electrode layer, the process after forming the gate electrode layer The process temperature is 250°C or higher and 380°C or lower, preferably 300°C or higher and 350°C or lower. In addition, when aluminum is used as the material for the gate electrode layer, the aluminum in contact with the oxide film Because oxides (such as alumina) may form on the surface, tantalum nitride is used as a barrier layer. Titanium nitride or titanium dioxide is used.

[0023] As one layer of the gate electrode layer, an In-G containing nitrogen layer is further formed between the barrier layer and the gate insulating layer. a-Zn-O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Ga-O film, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, In-O film containing nitrogen, metal It is preferable to use a gate electrode layer in which a nitride film (InN, SnN, etc.) is laminated. One of the gate electrode layers is made of the same material as the buffer layer, so that the same common sputtering A tarring target can be used, reducing manufacturing costs.

[0024] The gate insulating layer is formed by depositing silicon oxide, nitride, etc., using plasma CVD or sputtering. Silicon, silicon oxynitride, silicon nitride oxide, gallium oxide, aluminum oxide, nitride aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or The mixed material can be used to form a single layer or a laminated layer. Considering that it functions as a gate insulating layer for the photovoltaic device, hafnium oxide, tantalum oxide, and oxide were used. Yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium Hafnium aluminate (HfAlxOy(x>0, y>0)), nitrogen-doped hafnium Uses materials with high relative dielectric constants, such as silicate and nitrogen-doped hafnium aluminate. The sputtering method is preferred because it is less likely to be contaminated with hydrogen or water. It is suitable.

[0025] When the oxide semiconductor layer is crystallized, the gate insulating layer and the oxide semiconductor layer in contact with the oxide semiconductor layer are The crystalline structure contained in the oxide semiconductor layer is used as the material for the passivation layer in contact with the semiconductor layer. A matching material is preferable, and Ga-Zn-O film or α-Ga2O3 film with a hexagonal crystal structure is used. In this case, the crystals of the oxide semiconductor layer and the crystals of the gate insulating layer or the passivation layer are This is preferable because it allows for continuous alignment. For example, and a second Ga—Zn—O film in contact with the oxide semiconductor layer. The transistor preferably has a stacked structure. [Effects of the Invention]

[0026] The threshold voltage of the transistor can be made positive, so that it is a so-called normally-off switch. In addition, even if the transistor is normally on, The threshold value of the capacitor can be brought close to zero. The reliability of the transistor can be improved. [Brief explanation of the drawings]

[0027] [Figure 1] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 2] 1 is a graph showing light transmittance. [Figure 3] 1 is a graph showing the results of TDS measurement. [Figure 4] FIG. 1 is a plan view of a pixel illustrating one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view of a pixel illustrating one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 7] FIG. 1 is a diagram illustrating an example of an electronic device. [Figure 8] 1 is a graph showing the results of XRD measurement. [Figure 9] 10 is a graph showing the results of Hall measurement. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0029] (Embodiment 1) In this embodiment, an example of manufacturing a transistor over a substrate is shown in FIGS. This will be explained with reference to FIG. 1(C).

[0030] First, three conductive layers made of different materials are formed on the substrate 101, and a first film is formed on the conductive layers. A resist mask is formed using a photomask, and selective etching is performed to form a gate electrode layer. Then, the resist mask is removed. If necessary, a conductive film is formed. Before that, the insulating substrate such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. A membrane may be provided.

[0031] The substrate 101 is made of aluminosilicate glass, aluminoborosilicate glass, barium borate, or the like. For mass production, the substrate 101 is made of glass material such as vitreous acid glass. 160mm x 2460mm), 9th generation (2400mm x 2800mm, or 2450 mm x 3050mm), 10th generation (2950mm x 3400mm) mother glass It is preferable to use mother glass. If the processing temperature is high and the processing time is long, the mother glass will shrink significantly. Therefore, when mass production is carried out using mother glass, the heat treatment in the manufacturing process is °C or less, preferably 450 °C or less.

[0032] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can also be used as the substrate 101. Alternatively, crystallized glass or the like can be used. Furthermore, it is possible to use the surface of a semiconductor substrate such as a silicon wafer or a metal material. A conductive substrate having an insulating layer formed on its surface can also be used.

[0033] The first electrode layer 102a is a low-resistance conductive film, specifically an aluminum film or a copper film, or These films are coated with titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo ), chromium (Cr), Nd (neodymium), Sc (scandium) Alternatively, an alloy film in which a plurality of layers are combined is used.

[0034] The second electrode layer 102b is a metal nitride film, such as titanium nitride, nitride, or the like, which functions as a barrier layer. Tantalum, tungsten nitride, molybdenum nitride, chromium nitride, etc. are used.

[0035] The third electrode layer 102c is made of an In—Ga—Zn—O film containing nitrogen or an In—Sn film containing nitrogen. -O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn--O film, nitrogen-containing In--O film, or metal nitride film (InN, SnN, etc.) is used. As the third electrode layer 102c, these films have a resistance of 5 electron volts, preferably 5.5 electron volts. or more, the threshold voltage of the electrical characteristics of the transistor can be made positive. This allows realization of a so-called normally-off switching element. It can be said that n-type transistors using silicon are different from p-type transistors. The gate electrode is made of an element that gives p-type conductivity, or a small amount of impurity element that gives p-type conductivity is doped into silicon. On the other hand, by using an In-Ga-Zn-O film as the semiconductor layer, The transistors that have been used in this study can have a positive threshold voltage by using a gate electrode containing nitrogen. This can be done.

[0036] In this embodiment, a nitrogen-containing In-Ga-Zn-O film is used. 3: Oxide target of Ga2O3:ZnO = 2:2:1 [molar ratio] (Mitsui Metals) The distance between the substrate and the target (also called the TS distance) is set to 40 mm or more and 300 mm or less. The following conditions were met: pressure 0.4 to 0.6 Pa, argon gas flow rate 0 to 175 sccm, nitrogen gas flow rate 2 The flow rate is 5 to 200 sccm, the power is 1 kW to 5 kW, and the substrate temperature is 80°C or higher but lower than 450°C. In addition, the resistance of the nitrogen-containing In-Ga-Zn-O film decreases when it is heated. If necessary, a heat treatment may be performed to reduce the resistance. When aluminum is used as the first electrode layer 102a, the temperature is 380° C. or less. In the case of In-Ga-Zn-O films containing nitrogen, the heat treatment should be performed at 450°C or less. The polycrystal has a c-axis orientation and is highly crystalline. As a result of measuring a single film formed by sputtering, it was found that the In-Ga-Zn-O film containing nitrogen The work function of is 5.6 electron volts.

[0037] In addition, a film with a thickness of 300 nm was formed on a quartz substrate, and the film was then heated under a nitrogen atmosphere for 4 hours. The nitrogen-containing In-Ga-Zn-O film of the sample after heat treatment at 50°C for 1 hour Hall effect measurement (Hall effect device: ResiTest8300 series, Toyo Tech Co., Ltd.) The results are shown in Figure 9. The vertical axis of the graph in Figure 9 is the carrier concentration. The horizontal axis shows the ratio of nitrogen gas to the total deposition gas. It can be seen from Figure 9 that the carrier concentration increases as the proportion of nitrogen gas increases. In addition, the carrier type of the nitrogen-containing In-Ga-Zn-O film became N-type.

[0038] In addition, the results of measuring a single film formed by sputtering with a nitrogen gas flow rate of 40 sccm were The work function of the nitrogen-containing In-O film is 5.4 eV. As a result of measuring a single film formed by sputtering at 0 sccm, the In-S containing nitrogen The work function of the nO film is 5.5 eV. The nitrogen gas flow rate is 40 sccm. As a result of measuring the work of a single film formed by sputtering, the work of an In-Ga-O film containing nitrogen was The function is 5.4 electron volts. Also, the sputtering was performed with a nitrogen gas flow rate of 40 sccm. As a result of measuring a single film formed by the coating method, the work function of the nitrogen-containing In-Zn-O film was found to be 5.5 The single film was formed by sputtering with a nitrogen gas flow rate of 40 sccm. Measurements showed that the work function of the nitrogen-containing Sn—O film was 5.1 eV.

[0039] Next, a gate insulating layer 103 is formed to cover the gate electrode layer. The thickness is 10 nm or more and 300 nm or less.

[0040] The gate insulating layer 103 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. Silicon nitride, silicon oxynitride, silicon nitride oxide, gallium oxide, zinc oxide Aluminum (also called GZO), aluminum oxide, aluminum nitride, aluminum oxynitride , aluminum oxide nitride, hafnium oxide, or a mixture of these materials in a single layer or laminated. For example, SiH4, oxygen, and nitrogen are used as the deposition gas. A silicon oxynitride layer may be formed by plasma CVD.

[0041] Next, an oxide semiconductor film is formed over the gate insulating layer 103.

[0042] The oxide semiconductor film is formed by sputtering a metal oxide target containing at least zinc. The film thickness obtained under an oxygen atmosphere or a mixed atmosphere of argon and oxygen is 5 nm or more. A typical example of a metal oxide target is a quaternary metal oxide, I n-Sn-Ga-Zn-O based metal oxides and ternary metal oxides such as In-Ga-Zn- O-based metal oxides, In-Sn-Zn-O-based metal oxides, In-Al-Zn-O-based metal oxides Sn-Ga-Zn-O metal oxides, Al-Ga-Zn-O metal oxides, Sn-A In-Zn-O based metal oxides, binary metal oxides such as In-Zn-O based metal oxides, and S A target such as an n-Zn-O based metal oxide can be used.

[0043] In addition, in order to shift the threshold voltage of the electrical characteristics of the transistor in the positive direction, By adding a small amount of nitrogen to the semiconductor film, the Fermi level (E F ) may be lowered. When a trace amount of nitrogen is contained in the oxide semiconductor film, the nitrogen concentration of the oxide semiconductor film is adjusted to the The nitrogen concentration is set to be lower than that of the buffer layer.

[0044] In addition, when the oxide semiconductor film is formed, the pressure in the treatment chamber of the sputtering apparatus is set to 0.4 Pa or less. This reduces the contamination of impurities such as alkali metals and hydrogen into the surface and object on which the film is to be formed. The hydrogen contained in the film-forming object may be hydrogen atoms, hydrogen molecules, water, or water. It may be present as an acid group or a hydride.

[0045] In addition, when forming the oxide semiconductor film, the distance between the targets (TS distance) is set to 40 mm or less. The top should be 300mm or less (preferably 60mm or more).

[0046] In addition, when the oxide semiconductor film is formed by sputtering, the temperature of the film formation surface is 25 The temperature should be 0°C or higher, preferably below the upper limit of the substrate heat treatment temperature. 250°C is used to prevent impurities such as water and hydrogen from being present. This temperature prevents impurities from being mixed into the film-forming object and releases impurities into the gas phase in the chamber. In addition, the upper limit of the temperature of the surface to be deposited during film deposition by sputtering is the same as the upper limit of the heat treatment of the substrate. Temperature, or the upper limit temperature of the film (the temperature at which the components in the film change significantly when exceeded) )

[0047] In addition, when the oxide semiconductor film is formed, the leakage rate of the treatment chamber of the sputtering apparatus is set to 1×1 0 -10 Pa·m 3 / sec or less, the acid during film formation by sputtering method can be reduced. It is possible to reduce the inclusion of impurities such as alkali metals and hydrides in the nitride semiconductor film. In addition, by using an adsorption type vacuum pump (such as a cryopump) as an exhaust system, Impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides are released from the exhaust system. This can reduce backflow of materials.

[0048] The gate insulating layer 103 and the oxide semiconductor film are preferably formed in succession without exposure to air. When films are formed continuously, they may be contaminated by atmospheric components or impurity elements floating in the air. Each lamination interface can be formed without any problem.

[0049] After the oxide semiconductor film is formed, if necessary, the oxide semiconductor film may be heated in an atmosphere containing almost no hydrogen or moisture (nitrogen Noise atmosphere, oxygen atmosphere, dry air atmosphere (for example, moisture dew point below -40°C, Preferably, heat treatment (temperature range 200°C to 450°C) at a dew point of -60°C or less. This heat treatment may be performed as a dehydration treatment for eliminating H, OH, and the like from the oxide semiconductor layer. This can also be called dehydrogenation, where the temperature is increased under an inert atmosphere and then switched to oxygen-containing atmosphere. When heat treatment is performed in an atmosphere containing oxygen or in an oxygen atmosphere, It can also be called processing.

[0050] Next, a resist mask is formed over the oxide semiconductor film using a second photomask. Then, selective etching is performed to form the island-shaped oxide semiconductor layer 104. Remove the block.

[0051] Next, the buffer layer 105, the first conductive film 106a, and the second conductive film 106b are formed on the island-shaped oxide semiconductor layer 104. A second conductive film 106b and a third conductive film 106c are formed. The cross-sectional view at this stage is shown in FIG. is.

[0052] The buffer layer 105 is an In—Ga—Zn—O film containing nitrogen or an In—Sn -O film or the like can be used.

[0053] The nitrogen-containing In-Ga-Zn-O film is used as a buffer layer 105 and a part of the gate electrode layer. The film properties are significantly different from those of the In-Ga-Zn-O film used in the oxide semiconductor layer. In the detailed description, oxygen gas is used when forming a film using an In-Ga-Zn-O oxide semiconductor target. The film obtained by introducing this into the chamber is called an In-Ga-Zn-O film.

[0054] Figures 2(A) and 2(B) show the In-Ga-Zn-O film and nitrogen obtained by actual film formation. 1 shows the optical transmittance of an In—Ga—Zn—O film containing In—Ga—Zn—O.

[0055] All the samples shown in Fig. 2(A) were prepared using the same target (In2O3:Ga2O3:ZnO=2 The oxide target (Mitsui Metals) with a molar ratio of 1:2:2 was used, and the TS distance was set to 60 mm, pressure 0.4 Pa, power 500 W, substrate temperature 200°C, A film with a thickness of 100 nm was formed on quartz glass. The results of varying the film formation gas flow rate are shown in Figure 2(A). Sample 1 has an argon gas flow rate of 35 sccm and a nitrogen gas flow rate of 5 sccm. Sample 2 had an argon gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sccm. Sample 3 had a nitrogen gas flow rate of 40 sccm, and sample 4 had an oxygen gas flow rate of 40 sccm. Sample 5 had an oxygen gas flow rate of 30 sccm and a nitrogen gas flow rate of 10 sccm. Sample 6 had an oxygen gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sccm, and sample 7 had an oxygen The flow rate of the nitrogen gas was 30 sccm.

[0056] Also, Figure 2(B) shows the results of light transmittance when the substrate temperature during film formation was 400°C. All samples shown in Fig. 1 were obtained from the same target (In2O3:Ga2O3:ZnO=2:2:2 The oxide target (Mitsui Metals Co., Ltd.) was used, and the TS distance was set at 60 mm. The pressure was 0.4 Pa and the power was 500 W, and a film with a thickness of 100 nm was formed on a quartz glass plate with a thickness of 0.5 mm. Sample 1' was prepared with an argon gas flow rate of 35 sccm and a nitrogen gas flow rate of 5 sccm. Sample 3' had a nitrogen gas flow rate of 40 sccm, and Sample 4' had an oxygen gas flow rate of 4 0 sccm, and sample 6' had an oxygen gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sccm. cm.

[0057] As shown in Figures 2(A) and 2(B), oxygen gas was introduced into the chamber during film formation. The In-Ga-Zn-O film used in this process has high light transmittance and is almost transparent. In-Ga-Zn- containing nitrogen obtained by introducing nitrogen without introducing nitrogen gas into the chamber The O membrane is a brown membrane that has light-blocking properties.

[0058] In addition, these samples were each heat treated at 450°C for 1 hour in a nitrogen atmosphere. In addition, there was almost no change in the light transmittance. Thermal Desorption Spectroscopy (TDS) Figure 3 shows the thermal desorption spectrum of H2O molecules desorbed from the film measured by the thermal desorption (TDE) method. The measurement conditions were a temperature rise of approximately 30°C / min, and a 1×10 -8 Start measurement from (Pa) During the measurement, the -7 (Pa) is the degree of vacuum.

[0059] Sample 8 was prepared with an oxygen gas flow rate of 15 sccm and a nitrogen gas flow rate of 30 sccm. The In-Ga-Zn-O film (film thickness: 50 nm) obtained at a substrate temperature of 200°C was measured by TDS. The thermal desorption spectrum of H2O molecules desorbed from the film is shown in Figure 3(B).

[0060] From Figure 3(A) and Figure 3(B), it can be seen that the H2O content is almost the same at the same substrate temperature. It can be said that both films have the same thermal stability. The results of TDS measurement of Sample 1 to detect N2 molecules and the results of In-Ga- containing nitrogen in Sample 1 The Zn-O film was heat-treated in a nitrogen atmosphere at 450°C for 1 hour, and then TDS was measured. The results of detecting the molecules were almost the same.

[0061] The film formation conditions were a substrate temperature of 400°C, a nitrogen gas flow rate of 40 sccm, and a 30 Sample 9 was deposited with a thickness of 0 nm, and the deposition conditions were a substrate temperature of 400°C and an oxygen gas flow rate of 40 s ccm on a quartz substrate, and OUT The XRD measurement was carried out in the plane, and the results are shown in Figure 8(A) and Figure 8(B). The nitrogen-containing In-Ga-Zn-O film (sample 9) had high crystallinity immediately after deposition, as shown in Figure 8( A sharp peak can be seen in Fig. 1A. In addition, when only oxygen gas was used as the sputtering gas, The In-Ga-Zn-O film (sample 10) formed using this method has lower crystallinity than sample 9. As can be seen, the In-Ga-Zn-O film and the nitrogen-containing In-Ga The film quality of the -Zn-O film is significantly different.

[0062] Next, a resist mask 111 is formed over the third conductive film 106c using a third photomask. and selectively etching the source electrode layers 108a to 108c or the drain electrode layers By this etching, the side surface of the resist mask 111 is and the side surfaces of the source electrode layers 108a to 108c or the drain electrode layers 109a to 109c coincide with each other. The etching conditions are set to be such that no

[0063] Then, the buffer layer is selectively etched using the resist mask 111. A first buffer layer 112a and a second buffer layer 112b are formed. The oxide semiconductor layer 107 having a recess is formed by the etching step.

[0064] The cross-sectional view at this stage is shown in FIG. 1(B). The first buffer layer 112a has a cross-sectional shape, and the drain electrode layers 109a to 109c are The second buffer layer 112b having a cross-sectional shape projecting upward is formed. The order of etching is not important as long as the same cross section as that of the etching step (1) is obtained.

[0065] Thereafter, the resist mask 111 is removed.

[0066] Next, an insulating layer 110 is formed, which functions as a passivation layer. The cross section at this stage is shown in FIG. 1(C).

[0067] The insulating layer 110 is formed by depositing silicon oxide, nitride, or the like using a plasma CVD method or a sputtering method. silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, zinc gallium oxide, Aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, It can be formed as a single layer or a laminate using hafnium oxide or a mixture of these materials. For example, a film is formed by plasma CVD using SiH4, oxygen, and nitrogen as the film forming gas. A silicon oxynitride layer may be formed.

[0068] In this manner, the transistor shown in FIG. 1C can be manufactured using three photomasks. In the case where the transistor shown in FIG. 1C is manufactured as a switching element of a display device, In addition, a contact hole reaching the gate electrode layer or the drain electrode layer is formed in the insulating layer 11. 0, and then the pixel electrode is formed on the insulating layer 110. A fourth photomask is used for the formation of the electrodes, and a fifth photomask is used for the formation of the pixel electrodes. Therefore, a total of five photomasks are used.

[0069] The transistor has a first buffer layer protruding beyond the side surfaces of the source electrode layers 108a-c. 112a and the second buffer layer 11 protruding from the side surfaces of the drain electrode layers 109a to 109c. 2b, and these buffer layers alleviate the electric field concentration. .

[0070] The area of ​​the buffer layer protruding from the side surface of the drain electrode layer (or the source electrode layer) The length L of the region in the channel length direction can be adjusted appropriately by adjusting the etching conditions, etc. The length L of the buffer layer region in the channel length direction is The second buffer layer 112b (or the first buffer layer 112c) is formed on the lower end of the source electrode layer 108a-c. The horizontal distance from the bottom of the buffer layer 112a to the bottom of the buffer layer 112b is defined as the horizontal distance from the bottom of the buffer layer 112a to the bottom of the buffer layer 112b.

[0071] The resistivity of the tapered portion of the buffer layer, which is the electric field concentration relaxation region, depends on the thickness of the region, the channel Depending on the length (L) in the longitudinal direction, the implementer can select the material of the buffer layer and set the film thickness as appropriate. The desired resistivity can be achieved by designing the size of the tapered portion. At least the resistivity of the tapered portion of the buffer layer is higher than that of the channel formation region of the oxide semiconductor layer 107. The value should be lower than the above.

[0072] (Embodiment 2) In this embodiment, a transistor is manufactured using a total of four photomasks, one less than in the first embodiment. An example of manufacturing a transistor and a pixel electrode will be described with reference to FIGS. Since the manufacturing process is only partially different from that of the first embodiment, a detailed description of the same parts will not be given here. So I'll skip that.

[0073] FIG. 4 is a top view showing the planar configuration of the pixel 310, and FIG. 5 shows the stacked configuration of the pixel 310. 4. It should be noted that A1-A2, B1-B2, C1-C2, and D1-D2 in FIG. The dashed lines in Figs. 5(A) to 5(D) represent cross sections A1-A2, B1-B2, and C 1-C2, which corresponds to section D1-D2.

[0074] In the transistor 311 described in this embodiment, the drain electrode layer 206b is formed in a U-shape (C-shape The source electrode layer 206a is surrounded by a square-shaped (or U-shaped) source electrode layer 206a. This makes it possible to ensure a sufficient channel width even if the transistor area is small, It is possible to increase the amount of current that flows when the transistor is on (also called on-state current). .

[0075] The wiring 203 functions as a capacitance electrode or a capacitance wiring. The drain electrode layer 206b overlaps with the gate electrode layer 206c to form a capacitor 313.

[0076] In addition, the semiconductor device described in this embodiment is the same as that in the first embodiment in order to simplify the process. Photolithography for forming island-shaped oxide semiconductor layers without using a photomask (2) Since no etching process or etching step is performed, the oxide semiconductor layer 205 remains in the entire pixel region. As a result, the wiring 212-i functions as a gate electrode layer of a three-layer structure, and the wiring 21 6-j functions as one of a source electrode layer and a drain electrode layer, and a wiring 216-j+1 A parasitic transistor is created that functions as the other of the source and drain electrode layers.

[0077] Therefore, in this embodiment, the pixel 310 is provided with the groove 230 where the oxide semiconductor layer 205 is removed. The groove 230 is provided so that the above-mentioned parasitic transistor is not generated. By providing the wiring so that it crosses over both ends in the line width direction, the generation of a parasitic transistor can be prevented. In addition, the groove 230 is designed to cross over both ends of the wiring 203 in the line width direction. By doing so, it is possible to prevent the generation of other parasitic transistors. A plurality of grooves 230 or grooves 230 on the wiring 203 may be provided. The groove 230 must be provided parallel to the wiring 216-j or the wiring 216-j+1. The conductor may be curved or may have bends or curved portions.

[0078] The cross section A1-A2 shows the stacked structure of the transistor 311 and the capacitor 313. The transistor 311 is a transistor with a bottom gate structure. The stacked structure from the wiring 216-j to the wiring 216-j+1, including the electrode 210 and the groove portion 230 The cross section C1-C2 shows the intersection of the wiring 216-j and the wiring 212-i. The cross section D1-D2 shows the laminated structure of the wiring 216-j+1 and the wiring The intersection of 212-i and the stacked structure of groove 230 are shown.

[0079] In the cross section A1-A2 shown in FIG. 5(A), an underlying insulating layer 201 is formed on a substrate 200. A gate electrode layer 202 and a wiring 203 are formed on a base insulating layer 201. A gate insulating layer 204 and an oxide semiconductor layer 205 are formed on the gate electrode layer 202 and the wiring 203. In addition, buffer layers 312a and 312b, a source An electrode layer 206a and a drain electrode layer 206b are formed on the oxide semiconductor layer 2. The insulating layer 207 is in contact with a part of the source electrode layer 206a and the drain electrode layer 206b. The pixel electrode 210 is formed on the insulating layer 207. The drain electrode layer 206b is electrically connected to the drain electrode layer 206b through a contact hole 208. do.

[0080] In the cross section B1-B2 shown in FIG. 5(B), an underlying insulating layer 201 is formed on a substrate 200. A gate insulating layer 204 is formed on the base insulating layer 201, and an oxide film is formed on the gate insulating layer 204. The oxide semiconductor layer 205 is formed on the insulating film 204. The buffer layers 312a and 312b are formed on the insulating film 204. 2c is formed, and wiring 216-j is formed on the buffer layer 312a, and the buffer layer 312 a wiring 216-j+1 is formed over the oxide semiconductor layer 205, the buffer layer 312a, and An insulating layer 207 is formed on the wiring 312c, the wiring 216-j, and the wiring 216-j+1. In addition, a pixel electrode 210 is formed on the insulating layer 207 .

[0081] In the cross section C1-C2 shown in FIG. 5(C), an underlying insulating layer 201 is formed on a substrate 200. 2, a wiring 212-i is formed on the base insulating layer 201. In addition, on the wiring 212-i, A gate insulating layer 204 and an oxide semiconductor layer 205 are formed. A buffer layer 312a is formed on the substrate 05, and a wiring 216-j is formed on the buffer layer 312a. An insulating layer 207 is formed on the wiring 216-j.

[0082] In the cross section D1-D2 shown in FIG. 5(D), an underlying insulating layer 201 is formed on a substrate 200. The wiring 212-i is formed on the base insulating layer 201. The wiring 212-i has a three-layer structure. In this embodiment, a copper film, a tungsten nitride film on the copper film, and a tungsten nitride film A layered structure of an In-Ga-Zn-O film containing nitrogen is formed on the wiring 212-i. A gate insulating layer 204 and an oxide semiconductor layer 205 are formed. A buffer layer 312c is formed on the substrate 05, and a wiring 216-j+1 is formed on the buffer layer 312c. An insulating layer 207 is formed over the wiring 216-j+1. The buffer layer 312c is an In—Sn—O film containing SiOx. A part of the edge layer 204, a part of the oxide semiconductor layer 205, and a part of the insulating layer 207 were removed. A groove 230 is formed.

[0083] The groove 230 is formed in the same process as the contact hole 208 formed in the insulating layer 207. Although not shown here, a contact that reaches the gate electrode layer is formed. The tact holes are also formed using the same photomask.

[0084] The oxide semiconductor layer 205 has sufficient light-transmitting properties and overlaps with the pixel electrode 210. For example, oxygen gas is introduced to form a film. The In-Ga-Zn-O film obtained by this method has high transparency as shown in Figures 2(A) and 2(B). Since it has optical properties, it is suitable as a material for the oxide semiconductor layer 205.

[0085] The semiconductor device described in this embodiment mode includes a first photomask for forming a gate electrode layer, a barrier layer, and a gate insulating layer. a second photomask for forming a buffer layer, a source electrode layer, and a drain electrode layer; A third photomask for forming the hole and groove, a fourth photomask for forming the pixel electrode, It can be fabricated using a total of four photomasks.

[0086] When a liquid crystal display device is manufactured using a pixel including the transistor shown in FIGS. The substrate is bonded to the substrate 200, and a liquid crystal layer is provided between them. In the filter method, the color filter and black matrix are connected to the pixel electrode and backlight. If the liquid crystal display device is a field sequential type, different colors can be displayed. Using multiple light sources (e.g., R (red), G (green), B (blue)) that emit specific colors, The desired color is formed by dividing the time by each.

[0087] Furthermore, a liquid crystal layer that exhibits a blue phase without using an alignment film may be used. It is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the isotropic phase. This is the phase that appears just before the transition to the blue phase. Since the blue phase appears only in a narrow temperature range, The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the anti-reflective agent has a short response time of 10 μsec or more and 100 μsec or less. It is preferable because it is optically isotropic, does not require alignment treatment, and has little viewing angle dependency. .

[0088] When an organic light-emitting display device is manufactured using the transistors shown in FIGS. 4 and 5, two The above transistors are provided, and a pixel electrode is electrically connected to at least one of the transistors. An organic light-emitting element is formed using the pixel electrodes as the cathode or anode. In order to provide a partition wall made of Therefore, an organic light-emitting display device can be manufactured using a total of five photomasks.

[0089] (Embodiment 3) In the first and second embodiments, examples of bottom gate type transistors are shown. An example of fabricating a top-gate transistor is shown in Figure 6(A), (B), and (C). In this description, the same parts as those in FIGS. 1(A), 1(B), and 1(C) are designated by the same reference numerals. do.

[0090] In addition, this embodiment is a manufacturing example in which the oxide semiconductor layer is formed in two separate steps.

[0091] First, an oxide insulating film 160 serving as a base insulating layer is formed over a substrate 101 .

[0092] The oxide insulating film 160 is formed using an oxide insulating film from which part of oxygen is released by heating. As an oxide insulating film from which part of the oxygen is released by heating, the oxygen content is higher than that which satisfies the stoichiometric ratio. It is preferable to use an oxide insulating film containing as much oxygen as possible. The oxide insulating film can diffuse oxygen into the crystalline oxide semiconductor film by heating. The oxide insulating film 160 is typically formed of silicon oxide, silicon oxynitride, or silicon nitride oxide. Aluminum oxide, aluminum oxide nitride, gallium oxide, hafnium oxide, oxide It can be formed from yttrium or the like.

[0093] The oxide insulating film 160 is made of a Ga-Zn-O film or an α-Ga2O3 film having a hexagonal crystal structure. This allows the crystals of an oxide semiconductor layer to be formed later to bond with the oxide insulating film 160 serving as a base insulating layer. This is preferable because it allows for continuous alignment of the crystals.

[0094] The oxide insulating film 160 has a thickness of 50 nm or more, preferably 200 nm or more and 500 nm or less. By increasing the thickness of the oxide insulating film 160, the amount of oxygen released from the oxide insulating film 160 can be increased. The increase in the oxide insulating film 160 and the oxide film formed later can be prevented. It is possible to reduce defects at the interface with the compound semiconductor film.

[0095] The oxide insulating film 160 is formed by a sputtering method, a CVD method, or the like. The oxide insulating film from which part of the oxygen is released can be easily formed by using a sputtering method. Therefore, it is preferable.

[0096] Next, a first oxide semiconductor film having a thickness of 1 nm to 10 nm is formed over the oxide insulating film 160. Form.

[0097] In this embodiment, a target for an oxide semiconductor (for an In—Ga—Zn—O-based oxide semiconductor) Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]), The distance between the substrate and the target was 170 mm, the substrate temperature was 250°C, the pressure was 0.4 Pa, and the DC (DC) power supply 0.5 kW, oxygen only or argon and oxygen atmosphere, 5 nm thick film first An oxide semiconductor film is formed.

[0098] Next, the chamber atmosphere in which the substrate is placed is changed to nitrogen (with a dew point of -50°C or less, preferably Preferably, the dew point is -60°C or less), or dry air (with respect to moisture, the dew point is -50°C or less, preferably The first heat treatment is carried out at a temperature of 35°C or below the dew point of -60°C. The temperature is 0°C or higher and 750°C or lower. The heating time of the first heat treatment is 1 minute or higher and 24 hours or lower. By the first heat treatment, a first crystalline oxide semiconductor layer 164 is formed (FIG. 6( See A).

[0099] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer 164. Form a film.

[0100] In this embodiment, a target for an oxide semiconductor (for an In—Ga—Zn—O-based oxide semiconductor) Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]), The distance between the substrate and the target was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the DC (DC) power supply 0.5 kW, oxygen only or argon and oxygen atmosphere, 25 nm thick film An oxide semiconductor film 2 is formed.

[0101] Next, the chamber atmosphere in which the substrate is placed is changed to nitrogen (with a dew point of -50°C or less, preferably Preferably, the dew point is -60°C or less), or dry air (with respect to moisture, the dew point is -50°C or less, preferably The second heat treatment is carried out at a temperature of 35°C or below the dew point of -60°C. The temperature is 0°C or higher and 750°C or lower. The heating time of the second heat treatment is 1 minute or higher and 24 hours or lower. By the second heat treatment, a second crystalline oxide semiconductor layer 165 is formed (FIG. 6( In FIG. 6B, the first crystalline oxide semiconductor layer 164 and the second crystalline oxide semiconductor layer 165 are The interface of the semiconductor layer 165 is indicated by a dotted line, and the description is of an oxide semiconductor stack. It does not actually exist, but is illustrated merely to make the explanation easier to understand.

[0102] The first crystalline oxide semiconductor layer 164 and the second crystalline oxide semiconductor layer 165 is neither a single crystal structure nor an amorphous structure, and at least a portion of it is crystalline. C-axis aligned crystalline oxide semiconductors talline Oxide Semiconductor; also called CAAC-OS )

[0103] In addition, the steps from the formation of the oxide insulating film 160 to the second heat treatment are performed without exposure to air. It is preferable that the first and second oxide semiconductor layers are successively crystallized. When the oxide semiconductor film or the second oxide semiconductor film is formed, an oxygen gas containing a small amount of nitrogen is used. Argon gas may be introduced into the deposition chamber using a cylinder or an argon gas cylinder containing a small amount of nitrogen. stomach.

[0104] Next, a crystalline oxide semiconductor layer including a first crystalline oxide semiconductor layer 164 and a second crystalline oxide semiconductor layer 165 is formed. The stack of oxide semiconductor layers is processed to form island-shaped stacks of oxide semiconductor layers.

[0105] The oxide semiconductor stack is processed by forming a mask of a desired shape on the oxide semiconductor using a first photomask. After forming the oxide semiconductor layer on the conductor layer, the oxide semiconductor layer is etched. The above-mentioned mask can be formed using a method such as photolithography. Alternatively, the mask may be formed using a method such as an inkjet method.

[0106] The etching of the oxide semiconductor stack can be performed by either dry etching or wet etching. Of course, these may be used in combination.

[0107] Next, a buffer layer, a first conductive film, a second conductive film, and a third conductive film are formed on the oxide semiconductor stack. The buffer layer, the first conductive film, the second conductive film, and the third conductive film are formed. Prepare according to form 1.

[0108] Next, a mask is formed on the third conductive film using a second photomask. Etching is performed to form the source electrode layers 108a-c or the drain electrode layers 109a-c. This etching removes the side surface of the resist mask and the source electrode layers 108a to 108c in cross section. The etching conditions are set so that the side surfaces of the drain electrode layers 109a to 109c do not coincide with each other.

[0109] Then, the buffer layer is selectively etched using the resist mask to form the first A first buffer layer 112a and a second buffer layer 112b are formed. Remove.

[0110] Next, the source electrode layers 108a to 108c or the drain electrode layers 109a to 109c are covered with an acid. The gate insulating layer 103 is formed in contact with the Ga- When a Zn-O film or an α-Ga2O3 film with a hexagonal crystal structure is used, the crystal structure of the oxide semiconductor stack can be This is preferable because the crystallinity of the gate insulating layer 103 can be continuously matched with that of the gate insulating layer 102 .

[0111] Next, a third electrode layer 102c is formed on the gate insulating layer 103, and a second electrode The layer 102b is formed on the first electrode layer 102a, and the first electrode layer 102b is formed on the first electrode layer 102a. In order to correspond to the stacked gate electrode layers in FIG. 1(A), the same names are used for the same materials. and explain.

[0112] The third electrode layer 102c in contact with the gate insulating layer 103 is formed by doping nitrogen in the same manner as in the first embodiment. In-Ga-Zn-O film containing nitrogen, In-Sn-O film containing nitrogen, In-Ga -O film, nitrogen-containing In-Zn-O film, nitrogen-containing Sn-O film, nitrogen-containing In- O film or metal nitride film (InN, SnN, etc.) is used.

[0113] Through the above steps, a top-gate transistor is formed (see FIG. 6(C)). The first buffer layer 112a protrudes beyond the side surfaces of the source electrode layers 108a-c. and the second buffer layer 112b protruding from the side surfaces of the drain electrode layers 109a to 109c. These buffer layers provide a structure in which electric field concentration is alleviated.

[0114] The area of ​​the buffer layer protruding from the side surface of the drain electrode layer (or the source electrode layer) The length L of the region in the channel length direction can be adjusted appropriately by adjusting the etching conditions, etc. The length L of the buffer layer region in the channel length direction is The second buffer layer 112b (or the first buffer layer 112c) is formed on the lower end of the source electrode layer 108a-c. The horizontal distance from the bottom of the buffer layer 112a to the bottom of the buffer layer 112b is defined as the horizontal distance from the bottom of the buffer layer 112a to the bottom of the buffer layer 112b.

[0115] The resistivity of the tapered portion of the buffer layer, which is the electric field concentration relaxation region, depends on the thickness of the region, the channel Depending on the length (L) in the longitudinal direction, the implementer can select the material of the buffer layer and set the film thickness as appropriate. The desired resistivity can be achieved by designing the size of the tapered portion. At least the resistivity of the tapered portion of the buffer layer is It is set to a value lower than that of the channel forming region 166b.

[0116] Note that the oxide semiconductor stack obtained in this embodiment is single-crystal in its entirety. It is a non-single-crystal layer with its c-axis oriented perpendicular to the surface of the oxide semiconductor stack. The layer contains multiple crystals, but their ab planes do not coincide.

[0117] Furthermore, the buffer layer obtained in this embodiment has a c-axis perpendicular to the surface of the buffer layer. The polycrystalline film is oriented and has higher crystallinity than the stacked oxide semiconductor layers.

[0118] Although an example of a top gate structure is shown in this embodiment, the present invention is not limited to this. A structure in which gate electrode layers are provided above and below the stacked layer may be used.

[0119] This embodiment mode can be freely combined with Embodiment Mode 1 or 2. For example, in this embodiment, the oxide semiconductor film having the c-axis orientation is formed by performing film formation in two steps. The stacked layer can also be used as the oxide semiconductor layer in Embodiment 1. The stack of oxide semiconductor layers formed in two separate steps was used as the oxide semiconductor layer in Embodiment 2. Alternatively, the oxide semiconductor layer may remain in the entire pixel region.

[0120] (Fourth embodiment) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the display devices described in the above embodiments will be described. do.

[0121] FIG. 7A shows a portable information terminal, which includes a main body 3001, a housing 3002, a display unit 3003, and a display unit 3004. The display unit 3003b has a touch input function. The keyboard buttons 3004 displayed on the display unit 3003b are used as a panel. By touching the display unit 3003a, you can operate the screen and input characters. The semiconductor device shown in the first embodiment may be configured as a panel having a switching function. A liquid crystal panel or an organic light-emitting panel is manufactured as a display element to form display units 3003a and 3003b. By applying the above, a highly reliable portable information terminal can be obtained.

[0122] Figure 7(A) shows the functions for displaying various information (still images, videos, text images, etc.), Functions for displaying date, time, etc. on the display, and for operating or editing the information displayed on the display It has the function of controlling the processing by various software (programs), etc. In addition, there are external connection terminals (earphone terminal, USB terminal) on the back and sides of the housing. The configuration may include a recording medium insertion section, etc.

[0123] The portable information terminal shown in FIG. 7(A) may be configured to be capable of transmitting and receiving information wirelessly. You can purchase and download desired book data from the electronic book server wirelessly. It is also possible to configure it as follows.

[0124] The portable information terminal shown in FIG. 7A has two display units 3003a and 3003b. One of the two can be removed, and the view when removed is shown in Figure 7(B). The 3003a also has a panel with touch input functionality, making it even lighter when carried around. It is convenient because the housing 3002 can be held with one hand and operated with the other. do.

[0125] Furthermore, the housing 3002 shown in FIG. 7B may be provided with an antenna, a microphone function, and a wireless function, and may be used as a mobile phone. It may also be used as a mobile phone.

[0126] FIG. 7C shows an example of a television device. The television device 9600 is A display unit 9603 is built into the body 9601. The display unit 9603 displays an image. In addition, the stand 9605 with the built-in CPU can be used to mount the case 9 The semiconductor device described in Embodiment 1 is configured to support the display portion 9603. By applying the above, the television device 9600 can be made highly reliable.

[0127] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0128] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0129] The television device 9600 also includes an external connection terminal 9604 and a storage medium playback / recording unit 96 02, external memory slot. The external connection terminal 9604 is for connecting a USB cable etc. It can be connected to various cables, enabling data communication with a personal computer, etc. The storage medium playback / recording unit 9602 receives a disc-shaped recording medium and records the data on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 9606 inserted into the slot. It is also possible to display it on the display unit 9603.

[0130] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0131] 101 Substrate 102a to 102c gate electrode layer 103 Gate insulating layer 104 Oxide semiconductor layer 105 Buffer Layer 106a~106c Conductive film 107 Oxide semiconductor layer 108a to 108c source electrode layers 109a to 109c drain electrode layer 110 Insulating layer 111 Resist mask 111 Post resist mask 112a Buffer layer 112b buffer layer 160 oxide insulating film 164 Crystalline oxide semiconductor layer 165 Crystalline oxide semiconductor layer 166a, 166b oxide semiconductor layer 200 boards 201 Undercoat insulation layer 202 gate electrode layer 203 Wiring 204 Gate insulating layer 205 Oxide semiconductor layer 206a Source electrode layer 206b Drain electrode layer 207 Insulating layer 208 Contact Hole 210 pixel electrode 212 Wiring 216 Wiring 230 Groove 310 pixels 311 Transistor 312a Buffer layer 312b buffer layer 312c buffer layer 313 Capacitor 3001 main unit 3002 Case 3003a Display section 3003b Display section 3004 Keyboard Buttons 9600 Television Equipment 9601 Housing 9602 Storage media playback and recording unit 9603 Display section 9604 External connection terminal 9605 Stand 9606 External Memory

Claims

1. A gate electrode layer; a wiring having the same material as the gate electrode layer; a first insulating layer having a region in contact with an upper surface of the gate electrode layer and a region in contact with an upper surface of the wiring; an oxide semiconductor layer having a region overlapping with the gate electrode layer with the first insulating layer interposed therebetween; a metal oxide layer having a region in contact with the oxide semiconductor layer; a pixel electrode electrically connected to the metal oxide layer, the metal oxide layer has a region overlapping with the gate electrode layer with the oxide semiconductor layer interposed therebetween, the pixel electrode has an area overlapping with the wiring, the metal oxide layer contains indium, gallium, and zinc in a region overlapping with the gate electrode layer; the oxide semiconductor layer contains indium, gallium, and zinc in a region overlapping with the gate electrode layer, the oxide semiconductor layer has a crystal structure, The metal oxide layer has c-axis oriented crystals.

2. In claim 1, The semiconductor device, wherein the first insulating layer is a stack of silicon oxide and silicon nitride.

Images