Methods and systems for UV LED structures

Abstract

To provide improved systems and methods that can be used to produce high quality devices and structures.SOLUTION: Exemplary processing methods of forming an LED structure may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The methods may include heating the aluminum nitride layer to a temperature greater than or about 1500°C. The methods may include forming an ultraviolet light emitting diode structure overlying the aluminum nitride layer utilizing a metal-organic chemical vapor deposition or molecular beam epitaxy.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Non-Provisional Application No. 17 / 345,992, entitled "METHOD AND SYSTEMS FOR UV LED STRUCTURES," filed June 11, 2021, the entire contents of which are incorporated herein by reference.

[0002]

[0002] This technology relates to semiconductor processing and materials. More particularly, this technology relates to processes and materials for forming LED components. [Background technology]

[0003]

[0003] An LED panel or device can be formed with a large number of light sources that act as pixels on the device. The pixels can be formed with a single color light source and then fed through a conversion layer to produce a color, or the pixels can be formed with individual red, blue, and green light sources. In either scenario, any number of light sources, up to millions, can be formed, connected, and operated. While visible LEDs are well developed, LEDs operating in the ultraviolet spectrum exhibit significantly reduced performance.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technique. Summary of the Invention

[0005] An exemplary processing method for forming an LED structure may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The method may include heating the aluminum nitride layer to a temperature of about 1500° C. or greater. The method may include forming an ultraviolet light emitting diode structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy.

[0006] In some embodiments, the method may include transferring the substrate to a carrier after depositing the aluminum nitride layer. The carrier may be or may include carbon, and the carrier may define a ledge on which the substrate can rest. A first cover wafer may be disposed above the substrate on the carrier. A second cover wafer may be disposed below the substrate on the carrier. Each of the first cover wafer and the second cover wafer may be a substrate having an aluminum nitride layer. The first cover wafer and the second cover wafer may be oriented in approximately the same direction as the substrate. The substrate may be disposed face-down on the carrier. At least two substrates may be disposed in direct contact between the first cover wafer and the second cover wafer on the carrier. The aluminum nitride layer may be heated to a temperature of about 1600°C to about 1800°C. The aluminum nitride layer may be heated to above about 1000°C for at least 100 minutes. The full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer may be about 300 arc seconds or less. After heating the aluminum nitride layer, the substrate may maintain about 85% or greater coverage of the aluminum nitride layer.

[0007] Some embodiments of the present technology may include a method for forming an LED structure. The method may include depositing an aluminum nitride layer on a first substrate and a second substrate via a physical vapor deposition process. The method may include positioning the first substrate face-down on a carrier. The method may include positioning the second substrate face-down in contact with the first substrate. The method may include heating the first substrate and the second substrate to a temperature of about 1500°C or greater.

[0008] In some embodiments, the method may include forming an ultraviolet light-emitting diode structure on an aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy. The aluminum nitride layer may be heated to a temperature of about 1600°C to about 1800°C. The carrier may be or may include carbon, and the carrier may define a ledge on which both the first substrate and the second substrate sit. Positioning the first substrate face-down on the carrier may include positioning the first substrate on a first cover wafer. The method may include positioning a second cover wafer on the carrier over the second substrate. Each of the first cover wafer and the second cover wafer may be a substrate having an aluminum nitride layer. Each of the first cover wafer, the second cover wafer, the first substrate, and the second substrate may be oriented in approximately the same direction.

[0009] Some embodiments of the present technology may include a method for forming an LED structure. The method may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The method may include positioning the substrate face down on a first cover wafer positioned on a carrier. The method may include positioning a second cover wafer over the substrate. The method may include heating the aluminum nitride layer to a temperature of about 1500°C or greater. The method may include forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy. In some embodiments, the full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer may be about 300 arc seconds or less.

[0010] The above techniques may offer numerous advantages over conventional systems and techniques. For example, the techniques may provide a method for forming high-quality buffer layers characterized by reduced threading dislocations. Furthermore, the techniques may utilize carrier and positioning arrangements to fabricate ultraviolet light-emitting diodes characterized by improved performance over conventional devices. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0011] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a top view of one embodiment of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2] 1A-1D illustrate selected steps in a method of forming a light emitting diode structure according to some embodiments of the present technology. [Figure 3] FIG. 1A is a schematic diagram showing the developed device according to some embodiments of the present technology, and FIG. 1B is a graph showing a rocking curve scan of the fabricated film according to some embodiments of the present technology. [Figure 4] 1 is a schematic diagram illustrating a carrier for high temperature processing according to some embodiments of the present technology; [Figure 5] 10 is a graph showing wafer bow of substrates with films fabricated according to some embodiments of the present technique; [Figure 6] 1A-B show rocking curve scans of fabricated membranes according to some embodiments of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0019] Some of the figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless the scale is specifically stated. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0014]

[0020] In the accompanying figures, similar components and / or features may be labeled with the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar components. When only a first reference label is used herein, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0015]

[0021] Deep ultraviolet light refers to light generated within the wavelength range of approximately 280 nm to approximately 200 nm, traditionally produced by mercury gas discharge lamps. However, as more environmentally friendly methods of generating UV light become more widespread, conventional technologies are no longer able to support these wavelengths with sufficient operating efficiency. Many conventional UV light-emitting diodes ("LEDs") are formed on an aluminum nitride buffer physically deposited on a sapphire substrate. While this type of substrate may work effectively with standard blue LED configurations, it may not work effectively with UV LEDs. For example, blue LEDs are characterized by quantum efficiencies of approximately 50% or higher, meaning that sufficient light can be generated even with relatively low-quality LED structures. However, UV LEDs are characterized by much lower quantum efficiencies, such as approximately 10% or less, or even less, due to several structural and material issues. For example, poor crystalline quality materials can be a limiting factor that can significantly degrade UV LED performance.

[0016]

[0022] As mentioned above, many gallium nitride-based structures used in LEDs may include a substrate, which may be silicon or sapphire. To improve device operation, the present technology allows for the formation of a buffer layer on the substrate prior to forming the LED structure by metalorganic chemical vapor deposition or molecular beam epitaxy. However, the buffer layer, which may be a dielectric material such as, but not limited to, aluminum nitride, may feature a different crystal structure compared to sapphire. This may result in a lattice mismatch between the materials, potentially causing the buffer layer to relax and develop threading dislocations in the buffer layer. These dislocations may thread through subsequent device layers formed, including the LED active region, further reducing the quantum efficiency of the device.

[0017]

[0023] The present technology overcomes these problems by performing a high-temperature anneal of the buffer layer after formation. The annealing process can promote rearrangement and improvement of the crystalline structure of the buffer layer, reducing or eliminating threading dislocations within the buffer layer. This can improve the quality of subsequently formed LED structures and promote improved quantum efficiency of the devices. While the remainder of the disclosure will always identify specific LED materials and processes using the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of materials and processes that may be used to manufacture displays. Thus, the present technology should not be considered limited to use solely with UV processes. After describing an exemplary chamber system that may be used in accordance with some embodiments of the present technology, methods and components for producing high-quality devices will be described.

[0018]

[0024] FIG. 1 is a top view illustrating a multi-chamber processing system 100 that may be specifically configured to perform aspects or steps according to some embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer load locks 110 and 112 (although dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheat chambers 123 and 125, and robots 126 and 128. The single-wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between the robots 126 and 128. The platforms 102, 104 may be open to the transfer and buffer chambers, or the platforms may be selectively isolated or sealed from the chambers so that different operating pressures can be maintained between the transfer chamber 106 and the buffer chamber 108. The transfer platforms 102, 104 may each include one or more tools 105, such as for orientation or measurement steps.

[0019]

[0025] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Accordingly, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium that, when executed, can perform the operations described in connection with methods according to embodiments of the present technology. The processing chambers 114, 116, 118, 120, 122, and 124 may each be configured to perform one or more process steps in the fabrication of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including dry etching processes, cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation, among any number of other substrate processes.

[0020]

[0026] Turning to FIG. 2 , selected steps of a manufacturing method 200 for forming an LED structure are illustrated. Method 200 may include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the described steps. For example, in some embodiments, a degassing step may be performed on a substrate, such as a silicon substrate or a sapphire substrate, to prepare the substrate for deposition. The method may also include numerous optional steps that may or may not be particularly relevant to some embodiments of the method of the present technology. For example, many of the steps are described to provide a broader range of structure formations, but are not critical to the present technology or can be performed by alternative methodologies, as described further below. Method 200 describes the steps shown generally in FIG. 3 , but that illustration will be discussed in conjunction with the steps of method 200. It should be understood that FIG. 3 shows only a partial schematic diagram, and that the substrate may include any number of LED sections having the illustrated features, as well as alternative structural features that can also benefit from aspects of the present technology.

[0021]

[0027] Method 200 may include optional steps for developing the structure for a particular manufacturing process. As shown in FIG. 3 , an LED source substrate 305 may be used to facilitate the formation or growth of multiple LEDs on the substrate. While only one LED structure is illustrated, it should be understood that the substrate may have hundreds, thousands, millions, or more LEDs formed thereon, and may be of any size, as the present technology may encompass micro LEDs, among other types of LED structures. Substrate 305 may be any substrate upon which a structure may be formed, such as a silicon-containing material, an aluminum material including sapphire, or any other material that may be used in display or semiconductor manufacturing. The substrate may be any size, including 2 inches, 3 inches, 4 inches, 6 inches, or larger than the substrate size in embodiments of the present technology. The substrate may be cleaned or treated, for example, in preparation for depositing one or more layers of material on the substrate to fabricate an LED, although any number of other semiconductor structures may similarly benefit from aspects of the present technology. The present technology may be applied to fabricate any type of LED structure, and in some embodiments, the structure may be a blue LED, such as a deep UV LED.

[0022]

[0028] The method 200 may include forming or depositing a buffer layer of material, such as buffer layer 310, on the substrate, as shown in FIG. 3 . The buffer layer is formed of a material that can facilitate the formation of structures thereon and may be fabricated, for example, by metalorganic chemical vapor deposition or molecular beam epitaxy. Including a buffer layer between the substrate and the LED structure can improve device performance. The buffer layer may be any number of materials, and in some embodiments, may be aluminum nitride. While the buffer layer may be formed by any number of processes for deposition or formation, in some embodiments, an aluminum nitride buffer layer may be formed by a physical vapor deposition process. Forming the buffer layer by physical vapor deposition can reduce the thermal budget of LED fabrication, improve crystalline orientation and morphology between layers, allow for faster deposition compared to conventional techniques, and potentially reduce the formation of threading dislocations.

[0023]

[0029] As explained above, aluminum nitride layers can feature a different crystal structure than the underlying substrate, such as sapphire. Therefore, due to this lattice mismatch, the aluminum nitride layer may form under stress. When the structure relaxes after formation, the structure may adjust, and threading dislocations, such as dislocation 312 shown in FIG. 3, may form within the layer. During formation, numerous dislocations may form throughout the buffer layer, which, if untreated, may extend through the subsequently formed LED structure. Therefore, the present techniques may include additional steps to treat or rearrange the buffer layer structure to limit or reduce the number of remaining dislocations. Reducing the number of threading dislocations can improve the quality of the LED structure, thereby increasing the quantum efficiency of the resulting LED structure.

[0024]

[0030] To improve the crystalline quality of the buffer layer and reduce the number of threading dislocations, the present technique may perform an annealing process on the buffer layer. The annealing may be performed in any of the processing chambers on a system such as system 100, although in some embodiments, the annealing step may be performed in a separate chamber. For example, a substrate including a buffer layer such as aluminum nitride may be transferred to a carrier after depositing the aluminum nitride layer in optional step 210. The carrier may then be positioned in a furnace chamber or other chamber that can heat the substrate. Method 200 may then include heating the substrate or buffer layer to a temperature sufficient to improve the crystalline quality and remove threading dislocations in step 215. Following the heating step, an LED structure may be formed on the reconditioned buffer layer in step 220, which may include the formation of a UV LED structure. The LED structure may be formed by a metalorganic chemical vapor deposition process or molecular beam epitaxy, as well as any other formation technique capable of producing any number of LED structures, such as the structure shown in FIG. 3 . For example, a structure including any number of materials and / or layers may be formed on buffer layer 310. As one non-limiting example, the structure may include an n-doped layer 315, such as aluminum gallium nitride. A multi-quantum well layer 320 may be formed over the n-doped region, and an electron blocking layer 325 may be formed over the multi-quantum well layer. In some embodiments, both layers may be aluminum gallium nitride, although any number of other materials could be used as well.

[0025]

[0031] A p-doped layer 330 may be formed on the electron blocking layer, followed by a subsequent p-doped layer 335 formed on layer 330. These layers may also be or include aluminum gallium nitride, gallium nitride, or any number of other materials. The structure may then be patterned and contacts may be formed. For example, an n-metal contact may be formed on n-doped layer 315, and a p-metal contact may be formed on p-doped layer 335. Because threading dislocations 312 may thread through the structure, performing an anneal in accordance with embodiments of the present technology may limit dislocations extending through the structure and improve quantum efficiency. For example, by using processes according to some embodiments of the present technology, the efficiency of deep UV LEDs may be about 1% or greater, about 2% or greater, or about 5% or greater.

[0026]

[0032] The annealing step can be performed to reduce threading dislocations within the layer and promote crystalline structure reorganization, and heating can be performed at a temperature sufficient to repair defects within the crystalline structure. For example, for an aluminum nitride buffer layer, the substrate and / or aluminum nitride layer can be heated to about 1000°C or higher, about 1100°C or higher, about 1200°C or higher, about 1300°C or higher, about 1400°C or higher, about 1500°C or higher, about 1550°C or higher, about 1600°C or higher, about 1650°C or higher, about 1700°C or higher, about 1750°C or higher, about 1800°C or higher, about 1850°C or higher, or higher. While not intending to bind the present technology to any particular theory, there may be a temperature at which the activation energy is sufficient to repair crystalline defects and improve the crystalline structure of the buffer layer. However, as the temperature continues to increase, thermal roughening of the surface can occur, potentially resulting in edge material loss. For example, the deposition process may reduce thickness at the edge of the substrate, producing a film that is more susceptible to loss during the annealing process. Furthermore, defects, such as aluminum nitride damage, may begin to appear at the surface of the buffer layer, reducing operational efficiency. Therefore, in some embodiments, the temperature may be maintained at or below about 1850°C, and may be maintained at or below about 1800°C, about 1750°C, about 1600°C to about 1800°C, about 1650°C to about 1750°C, or about 1675°C to about 1725°C to ensure removal of threading dislocations while limiting material loss and defect generation.

[0027]

[0033] The pressure within the processing chamber may be variable; thus, in some embodiments, the pressure may be maintained at a slight vacuum of about 700 Torr or less, about 600 Torr or less, about 500 Torr or less, about 400 Torr or less, or less. Additionally, the annealing may be performed in an inert environment, such as a nitrogen environment. To provide a more uniform process across the substrate, the process time at any of the above temperatures may be maintained for about 60 minutes or more, about 80 minutes or more, about 100 minutes or more, about 110 minutes or more, about 120 minutes or more, about 130 minutes or more, about 140 minutes or more, about 150 minutes or more, about 160 minutes or more, about 170 minutes or more, about 180 minutes or more, about 190 minutes or more, about 200 minutes or more, or more. By performing the annealing for a sufficient time, the uniformity of crystalline quality may be further spread across the substrate. For example, Figure 3B shows a rocking curve scan along the x-direction, or parallel to the wafer flat, showing that the film quality is substantially uniform across the substrate, with full-width half-maximum measurements of less than 260 arc seconds across the wafer. However, the longer the process may run, the more likely it is that additional loss of buffer layer material will occur across the substrate. Therefore, to preserve material and improve the annealing process, some embodiments of the present technology may use a carrier to seat the substrate during the annealing process.

[0028]

[0034] FIG. 4 is a schematic diagram illustrating a carrier 400 for high-temperature processing according to some embodiments of the present technology, which may be used, for example, in the annealing step described with respect to method 200. Carrier 400 is illustrated to illustrate exemplary features of carriers encompassed by the present technology, and the carrier is not limited by any particular features illustrated. Carriers according to some embodiments of the present technology may be configured to seat one or more substrates, such as substrates having a buffer layer deposited thereon. For example, carrier 400 may include a housing 405 that may define a ledge 410 on which one or more substrates 415 may seat. The one or more substrates, including each substrate, may include a buffer layer 416 disposed on a first surface of the substrate.

[0029]

[0035] While one ledge and a set of substrates are illustrated, carriers according to embodiments of the present technology may include multiple ledges, each capable of supporting one or more substrates and / or cover wafers, as described below. The carrier may have a generally open design, such as two, three, four, or more posts 420 defining one or more ledges along the length of the posts. A removable rod or element 425 may fit into one of the posts or into a gap between the posts, threaded into the carrier, or otherwise removably seated. For example, the element 425 may be accessible through the head of the carrier and seated in a recess formed in the base of the carrier. Components such as springs or detent mechanisms may be included to seat or unseat the posts, although in some embodiments, the carrier may not explicitly include these components because the carrier may be exposed to high-temperature processes. The element 425 may be removed to deposit or remove a substrate from one or more ledges of the carrier, and the element may then be replaced to secure the substrate prior to processing.

[0030]

[0036] The carrier 400 may be or include one or more materials configured to withstand the furnace environment and limit thermal stress issues with the carrier and between the carrier and the substrate or substrates. For example, in some embodiments, the carrier 400 may be or include carbon or a carbon-containing material. For example, the carrier may be or include graphite, coated graphite, such as silicon carbide-coated graphite materials, or any other material capable of withstanding high-temperature environments. In some embodiments, the substrate may be positioned in contact with at least one additional substrate or other component, as shown. Furthermore, the substrate may be oriented in one or more ways within the carrier. For example, the substrates may be oriented face-to-face or back-to-back within the carrier, although in some embodiments, the substrates may be oriented in approximately the same direction as at least one additional substrate, and in some illustrated embodiments, each substrate may be oriented in the same direction. Orienting the substrates in approximately the same direction can improve buffer layer coverage, which can be significantly improved compared to other orientations.

[0031]

[0037] Tests have shown that when substrates are positioned face-to-face, such as with the buffer layer of a first substrate facing the buffer layer of a second substrate, increased buffer layer material loss and reduced material quality may occur. For example, a face-to-face orientation may be characterized by having about 80% or less coverage across the entire surface of the substrate after annealing, such as about 75% or less coverage, about 65% or less coverage, about 60% or less coverage, or less coverage, due to, for example, evaporation of material during annealing. However, when the substrates are oriented face-down in the same direction as shown, the substrates may maintain about 80% or more coverage across the entire surface of the substrate after annealing, and may maintain about 85% or more coverage, about 90% or more coverage, or more.

[0032]

[0038] Furthermore, substrate orientation can affect film stress effects caused by duration at high temperatures. For example, if a substrate is maintained in a state that is neither a top nor a bottom substrate, film stress may be less affected by annealing compared to the top or bottom substrate. Substrates on which aluminum nitride films are formed may be characterized by some degree of warping due to the internal stress characteristics of the film. When multiple substrates are stacked as shown, outer substrates, such as the first and last substrates or top and bottom substrates, may be characterized by increased substrate warping, which may increase by about 10 μm or more, about 15 μm or more, about 20 μm or more, or about 25 μm or more. This may lead to film delamination or increased damage to the substrate. However, the internal substrates may be characterized by an increase in warpage of about 10 μm or less, no increase in wafer warpage at all, or an increase in warpage of about 5 μm or less, about 3 μm or less, about 1 μm or less, or less, including reductions in wafer warpage of about 1 μm or more, about 3 μm or more, about 5 μm or more, or more. For example, as shown in FIG. 5, a wafer located in the center of a wafer stack, in some embodiments, is characterized by limited or substantially no warpage, regardless of orientation.

[0033]

[0039] Thus, in some embodiments, the processing step may include using one or more cover wafers during positioning of the substrates in the carrier. While the cover wafer can be formed of any material that can withstand the annealing environment, in some embodiments, the cover wafer may include a film similar to the internal substrate being annealed. By including a similar substrate, such as sapphire, with a similar layer of material, such as physical vapor deposited aluminum nitride, the cover wafer may be characterized by a similar wafer bow to the other substrates being processed, improving the effectiveness of the anneal on the internal wafers. For example, a first cover wafer may be seated on the carrier ledge 410, and one or more substrates to be annealed may be seated on top of the first cover wafer. While two such substrates are shown, embodiments encompassed by the present technology may include about one or more substrates, about two or more substrates, about three or more substrates, about four or more substrates, about five or more substrates, about six or more substrates, about seven or more substrates, about eight or more substrates, about nine or more substrates, about ten or more substrates, or more substrates.

[0034]

[0040] A second cover wafer may then be positioned over one or more of the interior substrates of the stack. As a result, the processed substrate may not sit directly on the carrier but may only make contact at discreet locations, such as point contact with the outer rails of the carrier. In some embodiments, the interior substrates of the stack may have little or no contact with the carrier. Furthermore, in some embodiments, the cover wafer may be characterized by a larger diameter than the substrates being processed, which may further ensure that the substrates have no or limited contact with the carrier and reduce any temperature effects across the substrates.

[0035]

[0041] As shown, the substrates may be positioned in direct contact with one another, and in some embodiments, a buffer layer formed on a first surface of a substrate may be positioned in contact with a second surface of an adjacent substrate or cover wafer being processed, the second surface being opposite the first surface, such as the backside of the substrate. The substrates may all be oriented in the same direction, and in some embodiments, all substrates and cover wafers may be positioned face-down within a stack of carriers. Positioning the substrates face-down may at least partially counteract stresses imposed by the film through orientation, further helping to reduce or limit increases in film stress or wafer bow during the annealing process. Thus, internal substrates, or any substrates processed according to embodiments of the present technology, may be characterized by improved coverage as described above, and may limit evaporation or other losses, by limiting film exposure during annealing.

[0036]

[0042] X-ray diffraction of tested substrates has shown that annealing the substrate or buffer film at a sufficient temperature for a sufficient time, for example, while orienting the substrate in a specific configuration, can improve film quality and consistency across the substrate. For example, X-ray diffraction rocking curves generated from buffer layers with an average aluminum nitride thickness of up to 300 nm can produce full-width-at-half-maximum measurements along the (102) crystal direction of about 300 arc seconds or less, and full-width-at-half-maximum measurements along the (102) crystal direction of about 290 arc seconds or less, about 280 arc seconds or less, about 270 arc seconds or less, about 260 arc seconds or less, about 250 arc seconds or less, about 240 arc seconds or less, about 230 arc seconds or less, about 220 arc seconds or less, or less. For example, Figures 6A-6B show X-ray diffraction rocking curves for aluminum nitride. Figure 6A shows the curve along the (002) crystal direction and illustrates the intensity change between the pre-annealed curve (line 605) and the post-annealed curve (line 610). Similarly, FIG. 6B shows curves along the (102) crystal direction, illustrating the intensity change between the pre-annealed curve by line 615 and the post-annealed curve by line 620. These measurements may be consistent across both the x-direction, which may be parallel to the wafer flat, and the y-direction, which may be perpendicular to the wafer flat. Using processes and materials according to embodiments of the present technology, high-quality buffer layers characterized by reduced threading dislocations and improved surface coverage may be fabricated. This may reduce the time required to fabricate LED structures on the buffer layer and may result in LEDs characterized by improved operating efficiency over conventionally fabricated devices.

[0037]

[0043] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0038]

[0044] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Moreover, in order to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Thus, the above description should not be deemed to limit the scope of the technology.

[0039]

[0045] Where a range of values ​​is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limit of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value in that stated range is also included. The upper and lower limits of these smaller ranges may independently be included or excluded, and each range where the smaller range includes one, both, or neither limit is also included within the technology, subject to any specifically excluded limit in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0040]

[0046] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a layer" includes a plurality of such layers, a reference to "an LED" includes a reference to one or more LEDs and equivalents thereof known to those skilled in the art, and so forth.

[0041]

[0047] Also, as used in this specification and the claims that follow, the terms "comprise," "comprising," "contain," "containing," "include," and "including" specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer onto a substrate via a physical vapor deposition process; heating the aluminum nitride layer to a temperature of about 1500°C or greater; forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy; A method comprising:

2. transferring the substrate to a carrier after depositing the aluminum nitride layer, the carrier comprising carbon, the carrier defining a ledge on which the substrate rests; 10. The method for forming an LED structure of claim 1, further comprising:

3. 3. The method of forming an LED structure of claim 2, wherein a first cover wafer is disposed above the substrate on the carrier and a second cover wafer is disposed below the substrate on the carrier, and each of the first cover wafer and the second cover wafer includes a substrate having an aluminum nitride layer.

4. 4. The method of claim 3, wherein the first cover wafer and the second cover wafer are oriented in substantially the same direction as the substrate.

5. The method for forming an LED structure of claim 3 , wherein the substrate is placed face down on the carrier.

6. 4. The method for forming an LED structure of claim 3, wherein at least two substrates are placed in direct contact between the first cover wafer and the second cover wafer on the carrier.

7. 10. The method for forming an LED structure of claim 1, wherein the aluminum nitride layer is heated to a temperature of about 1600°C to about 1800°C.

8. 10. The method for forming an LED structure of claim 1, wherein the aluminum nitride layer is heated to above about 1000[deg.] C. for at least 100 minutes.

9. 10. The method for forming an LED structure of claim 1, wherein the full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer is less than or equal to about 300 arc seconds.

10. 10. The method for forming an LED structure of claim 1, wherein after heating the aluminum nitride layer, the substrate maintains about 85% or greater coverage of the aluminum nitride layer.

11. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer on the first substrate and the second substrate via a physical vapor deposition process; positioning the first substrate face down on a carrier; positioning the second substrate face down in contact with the first substrate; heating the first substrate and the second substrate to a temperature of about 1500° C. or greater; A method comprising:

12. forming an ultraviolet light emitting diode structure on said aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy; 12. The method for forming an LED structure of claim 11, further comprising:

13. 12. The method of forming an LED structure of claim 11, wherein the aluminum nitride layer is heated to a temperature of about 1600°C to about 1800°C.

14. 12. The method of forming an LED structure of claim 11, wherein the carrier comprises carbon, the carrier defining a ledge upon which both the first substrate and the second substrate rest.

15. Positioning the first substrate face down on the carrier includes: Positioning the first substrate on a first cover wafer.

12. The method of forming the LED structure of claim 11, comprising:

16. Positioning a second cover wafer over the second substrate on the carrier.

16. The method for forming an LED structure of claim 15, further comprising:

17. 17. The method for forming an LED structure of claim 16, wherein the first cover wafer and the second cover wafer each include a substrate having an aluminum nitride layer.

18. 20. The method for forming an LED structure of claim 17, wherein the first cover wafer, the second cover wafer, the first substrate, and the second substrate are each oriented in substantially the same direction.

19. 1. A method of forming an LED structure, comprising: depositing an aluminum nitride layer on a substrate via a physical vapor deposition process; positioning the substrate face down on a first cover wafer positioned on a carrier; positioning a second cover wafer over the substrate; heating the aluminum nitride layer to a temperature of about 1500°C or greater; forming an ultraviolet light emitting diode ("LED") structure on the aluminum nitride layer using metalorganic chemical vapor deposition or molecular beam epitaxy; A method comprising:

20. 20. The method for forming an LED structure of claim 19, wherein the full width at half maximum of an X-ray diffraction rocking curve along the (102) crystallographic direction of the aluminum nitride layer is less than or equal to about 300 arc seconds.

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