Semiconductor device

Abstract

To provide a semiconductor device capable of reducing conduction loss.SOLUTION: A semiconductor device 61 includes: a semiconductor layer 22 having a first main surface 3; a unit cell 15 including a p-type (second conductivity type) well region 25 formed on a surface layer portion of the first main surface 3 and an n-type (first conductivity type) impurity region 26 formed on a surface layer portion of the well region 25; a gate electrode layer 33 facing the well region 25 and the impurity region 26 across a gate insulation layer 32; and an embedded portion 80. The embedded portion 80 is in contact with the gate insulation layer 32. A thickness of the embedded portion 80 is larger than the that of the gate insulation layer 32.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] FIG. 14 of Patent Document 1 discloses a semiconductor device including a SiC epitaxial layer in which a gate trench is formed, and a Schottky cell and a pn diode cell formed in the SiC epitaxial layer so as to be separated from each other by the gate trench.

[0003] In this semiconductor device, a Schottky barrier diode is formed using a Schottky cell, and a metal insulator semiconductor field effect transistor (MISFET) is formed using a pn diode cell.

[0004] In the SiC epitaxial layer, one Schottky cell and a plurality of pn diode cells surrounding the one Schottky cell form one cell group, and multiple cell groups with this structure are arranged in a matrix in the SiC epitaxial layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2012 / 105611A1 Summary of the Invention [Problem to be solved by the invention]

[0006] As a result of extensive research into the semiconductor device disclosed in Patent Document 1, the inventors of the present application have discovered that there is room for reducing the conduction loss of the Schottky barrier diode. The conduction loss of a Schottky barrier diode decreases as the rate of increase in forward current relative to the rate of increase in forward voltage increases.

[0007] The semiconductor device disclosed in Patent Document 1 has a structure in which the Schottky cell and the pn diode cell are fabricated separately from each other. In such a structure, the current path for the Schottky cell and the current path for the pn diode cell are dispersed within the semiconductor layer.

[0008] Therefore, even if the forward voltage is increased, the forward current does not increase as expected. This problem is a hindrance to reducing the conduction loss of Schottky barrier diodes.

[0009] Therefore, one embodiment of the present invention provides a semiconductor device that can reduce the conduction loss of a Schottky barrier diode. Moreover, one embodiment of the present invention provides a semiconductor device that can reduce conduction loss. [Means for solving the problem]

[0010] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a unit cell including a first conductivity type diode region formed in a surface layer portion of the first main surface of the semiconductor layer; a second conductivity type well region formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a first conductivity type region formed in the surface layer portion of the well region; a gate electrode layer facing the well region and the first conductivity type region across a gate insulating layer; and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region and forming an ohmic junction with the first conductivity type region.

[0011] In this semiconductor device, the first principal surface electrode forms a Schottky junction with the diode region and an ohmic junction with the first conductivity type region of the transistor, thereby forming a Schottky barrier diode and an insulated gate transistor in one unit cell.

[0012] Therefore, the current path for the Schottky barrier diode and the current path for the transistor are formed in the region directly below the unit cell in the semiconductor layer. This prevents the current path for the Schottky barrier diode and the current path for the transistor from being dispersed within the semiconductor layer. As a result, the rate of increase in forward current relative to the rate of increase in forward voltage can be increased, thereby reducing the conduction loss of the Schottky barrier diode.

[0013] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a first major surface on one side and a second major surface on the other side; a unit cell including a well region of a second conductivity type formed in a surface layer portion of the first major surface; and an impurity region of a first conductivity type formed in a surface layer portion of the well region; a gate electrode facing the well region across a gate insulating layer; and a buried portion of an insulating material formed between the gate electrode and the impurity region and extending below the gate electrode. The buried portion may be in contact with the gate insulating layer. The thickness of the buried portion may be greater than the thickness of the buried portion. The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of region II shown in FIG. 1, with the structure above the first main surface of the semiconductor layer removed. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is an enlarged view of the main part of FIG. [Figure 5] FIG. 5 is a circuit diagram showing the electrical structure of the semiconductor device of FIG. [Figure 6]FIG. 6 is a diagram for explaining the structure of a semiconductor device according to a reference example from an electrical point of view. [Figure 7] FIG. 7 is a diagram for explaining the structure of the semiconductor device of FIG. 1 from an electrical point of view. [Figure 8] FIG. 8 is a graph showing the measurement results of the current-voltage characteristics of the SBD. [Figure 9] FIG. 9 is a diagram showing the results of a simulation of the current density distribution in the main part of the semiconductor device of FIG. [Figure 10] FIG. 10 is a plan view of a portion corresponding to FIG. 2, showing a structure in which the aspect ratio of the unit cell is "2." [Figure 11] FIG. 11 is a plan view of a portion corresponding to FIG. 2, showing a structure in which the aspect ratio of the unit cell is "3." [Figure 12] FIG. 12 is a graph showing the measurement results of the current-voltage characteristics of the SBD. [Figure 13] FIG. 13 is a plan view showing a part of the device formation region, and is a plan view of a semiconductor device according to a second embodiment of the present invention. [Figure 14] FIG. 14 is a plan view showing a part of the device formation region, and is a plan view of a semiconductor device according to a third embodiment of the present invention. [Figure 15] FIG. 15 is a plan view of a semiconductor device according to a fourth embodiment of the present invention. [Figure 16] FIG. 16 is a plan view of FIG. 15 with the surface electrodes removed, and is a view for explaining the structure on the first main surface of the semiconductor layer. [Figure 17] FIG. 17 is an enlarged view of region XVII shown in FIG. 16, with the structure above the first main surface of the semiconductor layer removed. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is an enlarged view of the region XIX shown in FIG. [Figure 20] FIG. 20 is a graph showing the impurity concentration profile. [Figure 21A] FIG. 21A is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 21B] FIG. 21B is a cross-sectional view showing a step subsequent to that shown in FIG. 21A. [Figure 21C] FIG. 21C is a cross-sectional view showing a step subsequent to FIG. 21B. [Figure 21D] FIG. 21D is a cross-sectional view showing a step subsequent to FIG. 21C. [Figure 21E] FIG. 21E is a cross-sectional view showing a step subsequent to FIG. 21D. [Figure 21F] FIG. 21F is a cross-sectional view showing a step subsequent to FIG. 21E. [Figure 21G] FIG. 21G is a cross-sectional view showing a step subsequent to FIG. 21F. [Figure 21H] FIG. 21H is a cross-sectional view showing a step subsequent to FIG. 21G. [Figure 21I] FIG. 21I is a cross-sectional view showing a step subsequent to FIG. 21H. [Figure 21J] FIG. 21J is a cross-sectional view showing a step subsequent to FIG. 21I. [Figure 21K] FIG. 21K is a cross-sectional view showing a step subsequent to FIG. 21J. [Figure 21L] FIG. 21L is a cross-sectional view showing a step subsequent to FIG. 21K. [Figure 21M] FIG. 21M is a cross-sectional view showing a step subsequent to FIG. 21L. [Figure 21N] FIG. 21N is a cross-sectional view showing a step subsequent to FIG. 21M. [Figure 21O] FIG. 21O is a cross-sectional view showing a step subsequent to FIG. 21N. [Figure 21P] FIG. 21P is a cross-sectional view showing a step subsequent to that shown in FIG. 21O. [Figure 22] FIG. 22 is a cross-sectional view of a portion corresponding to FIG. 19, and is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention. [Figure 23] FIG. 23 is a plan view showing a part of the device formation region, and is a plan view of a semiconductor device according to a sixth embodiment of the present invention. [Figure 24]FIG. 24 is a plan view showing a part of the device formation region, and is a plan view of a semiconductor device according to a seventh embodiment of the present invention. [Figure 25] FIG. 25 is a plan view of a semiconductor device according to the eighth embodiment of the present invention. [Figure 26] FIG. 26 is a plan view of FIG. 25 with the surface electrodes removed, and is a view for explaining the structure on the first main surface of the semiconductor layer. [Figure 27] FIG. 27 is a cross-sectional view of a portion corresponding to FIG. 18, and is a cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention. [Figure 28] FIG. 28 is a plan view showing a part of the device formation region, and is a plan view of a semiconductor device according to a tenth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] FIG. 1 is a plan view of a semiconductor device 1 according to a first embodiment of the present invention.

[0016] The semiconductor device 1 includes a chip-shaped semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and four side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4.

[0017] The first main surface 3 and the second main surface 4 of the semiconductor layer 2 are formed in a quadrangular shape in a plan view seen from the normal direction thereof (hereinafter simply referred to as "plan view"). The side surface 5A and the side surface 5C face each other. The side surface 5B and the side surface 5D face each other.

[0018] The semiconductor layer 2 has a device formation region 6 and an outer region 7. The device formation region 6 is a region where an SBD (Schottky Barrier Diode) 8 and a MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9, which is an example of an insulated gate transistor, are formed. The device formation region 6 is also called an active region.

[0019] In plan view, the device formation region 6 is set in the central region of the semiconductor layer 2 with a gap between the periphery of the semiconductor layer 2 and the inner region of the semiconductor layer 2. In this embodiment, the device formation region 6 is set in a quadrilateral shape having four sides parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in plan view.

[0020] The outer region 7 is set in a region between the periphery of the semiconductor layer 2 and the periphery of the device formation region 6. The outer region 7 is set in an endless shape (quadratic ring shape) surrounding the device formation region 6 in a plan view.

[0021] The ratio SE / SF of the planar area SF of the device formation region 6 to the planar area SE of the first main surface 3 of the semiconductor layer 2 may be 70% or more and 85% or less. 2 More than 25mm 2 The width WO of the outer region 7 may be 0.1 mm or more and 0.3 mm or less. The width WO of the outer region 7 is defined as the width in a direction perpendicular to the direction in which the outer region 7 extends.

[0022] A gate electrode 10 and a source electrode 11 (first main surface electrode) are formed on the first main surface 3 of the semiconductor layer 2. The gate electrode 10 includes a gate pad 12 and gate fingers 13.

[0023] The gate pad 12 is formed along any one of the side surfaces (side surface 5A in this embodiment) in a plan view. The gate pad 12 is formed in a central region of the side surface 5A in a plan view. In this embodiment, the gate pad 12 is drawn from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6.

[0024] In this embodiment, the gate pad 12 is formed in a quadrangular shape in plan view. The gate pad 12 may be formed along one corner connecting two side surfaces 5A to 5D that extend in directions that intersect (are perpendicular to) each other in plan view.

[0025] The gate fingers 13 extend in a strip shape from the gate pad 12 along the periphery of the device formation region 6. In this embodiment, the gate fingers 13 are formed in an endless shape (quadratic ring shape) that surrounds the device formation region 6 in a plan view. The gate fingers 13 may be formed so as to partition the device formation region 6 from three directions.

[0026] The source electrode 11 is formed in a C-shaped region defined by the inner edge of the gate electrode 10 in plan view. In this embodiment, the source electrode 11 is formed in a C-shape that follows the inner edge of the gate electrode 10 in plan view.

[0027] The source electrode 11 covers most of the device formation region 6. The source electrode 11 may have a structure in which it has a plurality of electrode portions separated from one another and the device formation region 6 is covered by the plurality of electrode portions.

[0028] In this embodiment, a first bonding wire for the gate is connected to the gate pad 12. The first bonding wire may be an aluminum wire. In this embodiment, a second bonding wire for the source is connected to the source electrode 11. The second bonding wire may be an aluminum wire.

[0029] FIG. 2 is an enlarged view of region II shown in FIG. 1, with the structure above first main surface 3 of semiconductor layer 2 removed.

[0030] 2, unit cells 15 for forming SBDs 8 and MISFETs 9 are formed in device formation region 6. Fig. 2 shows an example in which a plurality of unit cells 15 are arranged in a matrix.

[0031] The unit cells 15 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. In this embodiment, the first direction X is a direction along any of the side surfaces 5A to 5D of the semiconductor layer 2 (side surfaces 5B and 5D in this embodiment). The second direction Y is a direction along a side surface (side surfaces 5A and 5C in this embodiment) perpendicular to the arbitrary side surface. In this embodiment, the second direction Y is a direction perpendicular to the first direction X.

[0032] The unit cell 15 is formed in a quadrangular shape in a plan view. The aspect ratio L2 / L1 of the unit cell 15 is 1. The aspect ratio L2 / L1 is defined as the ratio of the length L2 of one side of the unit cell 15 along the second direction Y to the length L1 of one side of the unit cell 15 along the first direction X.

[0033] That is, in this embodiment, the unit cell 15 is formed in a square shape in a plan view. The lengths L1 and L2 of one side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 10 μm).

[0034] A first line portion 16, a second line portion 17, and an intersection portion 18 are formed on the first main surface 3 of the semiconductor layer 2. The first line portion 16, the second line portion 17, and the intersection portion 18 are all formed by the first main surface 3 of the semiconductor layer 2 exposed from the unit cell 15.

[0035] The first line portions 16 extend along the first direction X through the regions between the unit cells 15 and partition the regions between the unit cells 15 adjacent to each other in the second direction Y. The second line portions 17 extend along the second direction Y through the regions between the unit cells 15 and partition the regions between the unit cells 15 adjacent to each other in the first direction X. The intersection portions 18 are portions where the first line portions 16 and the second line portions 17 intersect.

[0036] The width W1 of the first line portion 16 in the second direction Y may be 0.8 μm or more and 3.0 μm or less, and the width W2 of the second line portion 17 in the first direction X may be 0.8 μm or more and 3.0 μm or less.

[0037] An impurity region 19 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 at the intersection 18. The impurity region 19 reduces the electric field generated in the surface layer portion of the first main surface 3 of the semiconductor layer 2, particularly between adjacent unit cells 15. The impurity region 19 suppresses a decrease in the breakdown voltage of the semiconductor device 1.

[0038] In this embodiment, the impurity region 19 is a p-type impurity region or p + The impurity region 19 includes a semiconductor layer 2 (which will be described later as an n-type impurity region). - A pn junction is formed between the epitaxial layer 22 and the pn layer 21.

[0039] Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 is an enlarged view of a main part of Fig. 3. In the following, Fig. 2 will also be referred to as necessary.

[0040] Referring to FIG. 3, the semiconductor layer 2 is + a semiconductor substrate 21 and an n-type + formed on an n-type semiconductor substrate 21 - The n-type epitaxial layer 22 has a layered structure. - The first main surface 3 of the semiconductor layer 2 is formed by the n-type epitaxial layer 22. + The second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 21 .

[0041] n+ In this embodiment, the n-type semiconductor substrate 21 includes a wide bandgap semiconductor. + The n-type semiconductor substrate 21 may include SiC, diamond, or a nitride semiconductor. + The off-angle of the semiconductor substrate 21 may be 4°.

[0042] n - In this embodiment, the n-type epitaxial layer 22 comprises a wide bandgap semiconductor. - The epitaxial layer 22 may include SiC, diamond, or a nitride semiconductor. The SiC may be 4H—SiC. The nitride semiconductor may be GaN.

[0043] n - The epitaxial layer 22 is + The n-type semiconductor substrate 21 may be made of the same material. - The epitaxial layer 22 is + The insulating layer 22 may be formed of a material different from that of the semiconductor substrate 21 .

[0044] In the following, n + type semiconductor substrate 21 and n - An example in which the n-type epitaxial layers 22 all contain SiC (4H—SiC) will be described. + The semiconductor substrate 21 has a main surface that is misoriented from the <0001> plane to the <11-20> direction by 10° or less, more specifically, 2° or 4°.

[0045] n - The epitaxial layer 22 is + It is formed by epitaxially growing SiC from the main surface of the n-type semiconductor substrate 21. - The epitaxial layer 22 has a primary surface that is off-angled from the <0001> plane by 10° or less with respect to the <11-20> direction. More specifically, the off-angle is 2° or 4°.

[0046] In this embodiment, the first direction X is set to a direction perpendicular to the <11-20> direction, and the second direction Y is set to the <11-20> direction. Therefore, the unit cells 15 are arranged at intervals along the <11-20> direction and a direction perpendicular to the <11-20> direction.

[0047] When a plurality of unit cells 15 are arranged along the <11-20> direction using a 4H—SiC substrate having an off-angle of 10° or less, the electric field and crystal orientation relationships between adjacent unit cells 15 are equal to each other.

[0048] The pressure resistance of the unit cells 15 is reduced by local electric field concentration. Therefore, when an electric field is locally concentrated in a certain unit cell 15 among the plurality of unit cells 15, the pressure resistance of the plurality of unit cells 15 as a whole is limited by that certain unit cell 15.

[0049] Therefore, by arranging the plurality of unit cells 15 so that the relationship between the electric field and the crystal orientation is equal to one another, it is possible to prevent the electric field from concentrating locally in a certain unit cell 15 among the plurality of unit cells 15. This makes it possible to make the breakdown voltage strength of each unit cell 15 nearly uniform, thereby preventing a decrease in the breakdown voltage of the semiconductor device 1.

[0050] A drain electrode 23 (second principal surface electrode) is connected to the second principal surface 4 of the semiconductor layer 2. The drain electrode 23 covers the second principal surface 4 of the semiconductor layer 2 and has an n + An ohmic junction is formed between the semiconductor substrate 21 and the insulating layer 22 .

[0051] In the semiconductor layer 2, n + The n-type semiconductor substrate 21 is formed as a low resistance region (drain region). - The epitaxial layer 22 is formed as a high resistance region (drift region).

[0052] n - The thickness of the n-type epitaxial layer 22 may be 5 μm or more and 30 μm or less.- By increasing the thickness of the epitaxial layer 22, the breakdown voltage of the semiconductor device 1 can be improved.

[0053] For example, n - By setting the thickness of the n-type epitaxial layer 22 to 5 μm or more, a breakdown voltage of 600 V or more can be obtained. - By setting the thickness of the type epitaxial layer 22 to 20 μm or more, a breakdown voltage of 3000 V or more can be obtained.

[0054] 2 and 3, a plurality of unit cells 15 are formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2. Each unit cell 15 has n - a p-type diode region 24, a p-type well region 25, an n + type source region 26 (first conductivity type region) and p + The mold contact region 27 is included.

[0055] n - The n-type diode region 24 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. - The n-type diode region 24 is formed in a quadrangular shape in plan view. - In this embodiment, the n-type diode region 24 - The n-type epitaxial layer 22 is formed by utilizing a part of the region. - The n-type diode region 24 - The n-type impurity concentration is approximately equal to the n-type impurity concentration of the epitaxial layer 22.

[0056] n - The n-type diode region 24 - Alternatively, the n-type epitaxial layer 22 may be formed by further implanting n-type impurities into the surface layer of the n-type epitaxial layer 22. - The surface layer of the n-type diode region 24 - The n-type impurity concentration may be higher than the n-type impurity concentration of the n-type epitaxial layer 22.

[0057] n for the planar area SC of unit cell 15 - The area ratio SD / SC of the planar area SD of the diode region 24 may be 0.005 or more and 0.015 or less (for example, about 0.01). Hereinafter, the area ratio SD / SC will be referred to as "n - The area ratio SD / SC of the diode region 24 is called the "area ratio SD / SC of the diode region 24."

[0058] n - The aspect ratio L4 / L3 of the n-type diode region 24 may be equal to or greater than 1. - n with respect to the length L3 of one side of the diode region 24 along the first direction X - The ratio is defined as the ratio of the length L4 of one side of the diode region 24 along the second direction Y.

[0059] Here, n - In this example, the aspect ratio L4 / L3 of the shaped diode region 24 is 1. Therefore, n - Here, the n-type diode region 24 is formed in a square shape in a plan view. - The lengths L3 and L4 of one side of the diode region 24 may each be 1 μm or more and 1.5 μm or less (for example, approximately 1.2 μm).

[0060] The p-type well region 25 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. - The p-type well region 25 is formed along the periphery of the p-type diode region 24. More specifically, the p-type well region 25 is formed along the periphery of the p-type diode region 24. - The diode region 24 is formed in an endless shape (square ring shape).

[0061] The outer periphery of the p-type well region 25 forms the outer periphery of the unit cell 15. The p-type well region 25 is - type diode region 24 and n - A first pn junction is formed between the epitaxial layer 22 and the pn-type epitaxial layer 22 .

[0062] Referring to FIG. 4, the first pn junction has the p-type well region 25 as the anode and the n -A first diode 28 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0063] n + The n-type source region 26 is formed in the surface layer of the p-type well region 25. + The n-type source region 26 - The n-type impurity concentration is higher than that of the n-type diode region 24.

[0064] n + The n-type source regions 26 are formed at intervals from the inner and outer peripheries of the p-type well region 25. + In this embodiment, the p-type source region 26 is formed in an endless shape (square ring shape) along the p-type well region 25 in plan view.

[0065] p + The p-type contact region 27 is formed in the surface layer of the p-type well region 25. + The p-type contact region 27 is formed in the surface layer of the p-type well region 25. - type diode region 24 and n + The p-type source regions 26 are formed in the region between the p-type source regions 26. + The contact region 27 has a p-type impurity concentration higher than the p-type impurity concentration of the p-type well region 25 .

[0066] p + In this embodiment, the p-type contact region 27 is formed in an endless shape (a square ring shape) along the inner periphery of the p-type well region 25 in plan view. + In this embodiment, the p-type contact region 27 is exposed from the inner periphery of the p-type well region 25, and the n - A second pn junction is formed between the first pn-type diode region 24 and the second pn-type diode region 25 .

[0067] Refer to Figure 4, p + The contact region 27 includes a first region 29 and a second region 30. + The first region 29 of the p-type contact region 27 is formed in the p-type well region 25. +The second region 30 of the contact region 27 is n-type from the first region 29. - The diode region 24 is connected to the semiconductor substrate 10.

[0068] p + The second region 30 of the contact region 27 is connected to the p-type well region 25 and the n-type well region 26. - The p-type diode region 24 is located at the boundary of the p-type diode region 24. + The second region 30 of the contact region 27 is - A second pn junction is formed between the p-type diode region 24 and the p-type diode region 25. + The contact region 27 is the anode, and the n - A second diode 31 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0069] Each unit cell 15 has a JBS (Junction Barrier Schottky) structure. - The JBS structure includes a first pn junction formed between the p-type diode region 24 and the p-type well region 25. - type diode region 24 and p + The second pn junction is formed between the contact regions 27.

[0070] Furthermore, n - A JFET (Junction Field Effect Transistor) structure is formed on the surface of the epitaxial layer 22 by utilizing each unit cell 15 .

[0071] The JFET structure includes a first pnp structure and a second pnp structure. The first pnp structure has n - The second pnp structure is formed by the first line portion 16 of the n-type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the first line portion 16 interposed therebetween. - The p-type well region 25 is formed by the second line portion 17 of the p-type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the second line portion 17 interposed therebetween.

[0072] 3, a planar gate structure is formed on the first main surface 3 of the semiconductor layer 2. The planar gate structure has a laminated structure including a gate insulating layer 32 and a gate electrode layer 33. In this embodiment, the planar gate structure is formed in a lattice shape along the first line portions 16 and the second line portions 17 in a plan view.

[0073] The gate electrode layer 33 is electrically connected to the gate electrode 10. The gate electrode layer 33 is connected to the p-type well region 25, the n-type well region 26, and the n-type well region 27 with the gate insulating layer 32 sandwiched therebetween. + type source region 26 and n - The epitaxial layer 22 faces the silicon substrate 21 .

[0074] More specifically, the gate electrode layer 33 extends from the region above the first line portion 16, the second line portion 17, and the intersection portion 18 to the region above each unit cell 15, and is connected to the p-type well region 25 and the n-type well region 26 of each unit cell 15. + The source region 26 is selectively covered.

[0075] An insulating layer 34 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 34 covers the gate electrode layer 33. The insulating layer 34 has an n - n-type diode region 24 + type source region 26 and p + Contact holes 35 exposing the mold contact regions 27 are selectively formed.

[0076] The source electrode 11 is formed on the insulating layer 34. The source electrode 11 penetrates into the contact hole 35 from above the insulating layer 34. The source electrode 11 is connected to the n - n-type diode region 24 + type source region 26 and p + The mold contact region 27 is covered in its entirety.

[0077] The source electrode 11 is -A Schottky junction is formed between the source electrode 11 and the n-type diode region 24. As a result, referring to FIG. - An SBD 8 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0078] The source electrode 11 is + type source region 26 and p + An ohmic junction is formed between the semiconductor layer 2, the p-type well region 25, and the n-type contact region 27. + Type source region 26, p + A MISFET 9 is formed, which includes a contact region 27, a gate insulating layer 32, a gate electrode 10 (gate electrode layer 33), a source electrode 11, and a drain electrode 23.

[0079] FIG. 5 is a circuit diagram showing the electrical structure of the semiconductor device 1 of FIG.

[0080] 5, the semiconductor device 1 includes an SBD 8, a MISFET 9, a first diode 28, and a second diode 31. The SBD 8, the first diode 28, and the second diode 31 form a freewheeling diode of the MISFET 9.

[0081] The SBD 8 is connected in parallel to the MISFET 9. The anode of the SBD 8 is connected to the source electrode 11 of the MISFET 9. The cathode of the SBD 8 is connected to the drain electrode 23 of the MISFET 9.

[0082] The first diode 28 is connected in parallel to the MISFET 9. The anode of the first diode 28 is connected to the source electrode 11 of the MISFET 9. The cathode of the first diode 28 is connected to the drain electrode 23 of the MISFET 9.

[0083] The second diode 31 is connected in parallel to the MISFET 9. The anode of the second diode 31 is connected to the source electrode 11 of the MISFET 9. The cathode of the second diode 31 is connected to the drain electrode 23 of the MISFET 9.

[0084] The source electrode 11 of the MISFET 9 also serves as the anode electrode of the SBD 8, the anode electrode of the first diode 28, and the anode electrode of the second diode 31. The drain electrode 23 of the MISFET 9 also serves as the cathode electrode of the SBD 8, the cathode electrode of the first diode 28, and the cathode electrode of the second diode 31.

[0085] 6 is a diagram for explaining the structure of a semiconductor device 41 according to a reference example from an electrical point of view. Below, only the differences from the semiconductor device 1 will be explained, and explanations of other points will be omitted.

[0086] The semiconductor device 41 according to the reference example has a structure different from the semiconductor device 1 in that it does not include the unit cell 15. More specifically, the semiconductor device 41 according to the reference example has a structure in which an SBD cell 42 for the SBD 8 and a MISFET cell 43 for the MISFET 9 are arranged adjacent to each other.

[0087] The SBD cell 42 has n - The MISFET cell 43 has a p-type well region 25, an n-type diode region 24, and a n-type well region 26. + type source region 26 and p + A mold contact region 27 is formed.

[0088] The current density distribution obtained by the simulation is shown in Figure 6. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18 V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1 V.

[0089] In the semiconductor device 41 according to the reference example, current is concentrated in the MISFET cell 43. Therefore, the current path for the SBD cell 42 and the current path for the MISFET cell 43 are dispersed within the semiconductor layer 2. Furthermore, the common portion of the current path for the SBD cell 42 and the current path for the MISFET cell 43 is formed on the bottom side of the semiconductor layer 2 and is relatively small.

[0090] Therefore, in the semiconductor device 41 according to the reference example, even if the forward voltage VF is increased, the forward current I does not increase as expected. This problem is an obstacle to reducing the conduction loss of the SBD 8.

[0091] FIG. 7 is a diagram for explaining the structure of the semiconductor device 1 from an electrical point of view.

[0092] 7 shows the current density distribution of the semiconductor device 1 obtained by simulation. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18 V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1 V.

[0093] 7, in semiconductor device 1, the common portion of the current path for SBD 8 and the current path for MISFET 9 is larger than that of semiconductor device 41 according to the reference example.

[0094] The semiconductor device 1 has a structure in which the MISFET 9 and the SBD 8 are fabricated using one unit cell 15. Therefore, the current path for the SBD 8 and the current path for the MISFET 9 are formed in the region directly below the unit cell 15.

[0095] This prevents the current path for the SBD 8 and the current path for the MISFET 9 from being separated within the semiconductor layer 2. Furthermore, it is possible to share the current path for the SBD 8 and the current path for the MISFET 9. This increases the rate of increase in the forward current IF relative to the rate of increase in the forward voltage VF, thereby reducing the conduction loss of the SBD 8.

[0096] FIG. 8 is a graph showing the measurement results of the current-voltage characteristics of the SBD 8.

[0097] 8, the vertical axis represents the drain current ID [A], and the horizontal axis represents the voltage VDS [V] between the drain electrode 23 and the source electrode 11. The drain current ID is also the forward current IF of the SBD 8. The voltage VDS between the drain electrode 23 and the source electrode 11 is also the forward voltage VF of the SBD 8.

[0098] 8 shows a first characteristic A and a second characteristic B. The first characteristic A shows the current-voltage characteristic of the SBD 8 of the semiconductor device 1. The second characteristic B shows the current-voltage characteristic of the SBD 8 of the semiconductor device 41 according to the reference example.

[0099] With reference to the first characteristic A and the second characteristic B, the rate of increase of the drain current ID relative to the rate of increase of the voltage VDS between the drain electrode 23 and the source electrode 11 in the first characteristic A is higher than the rate of increase of the drain current ID in the second characteristic B. Thus, the semiconductor device 1 has achieved a conduction loss smaller than that of the semiconductor device 41 according to the reference example.

[0100] Furthermore, according to the semiconductor device 1, the unit cell 15 has a p-type well region 25 and an n - The diode has a JBS structure including a first pn junction formed between the first pn junction and the second pn junction. Therefore, a first depletion layer extending from the first pn junction forms an n - This can suppress current concentration and electric field concentration in the diode region 24.

[0101] Furthermore, this JBS structure has a pn junction in addition to the first pn junction. + type contact region 27 and n - The second pn junction is formed between the n-type diode region 24. Therefore, the second depletion layer extending from the second pn junction also - This can suppress current concentration and electric field concentration in the diode region 24.

[0102] In particular, the second pn junction is - type diode region 24 and p + The second depletion layer is formed in the boundary region between the second region 30 of the n-type contact region 27. This ensures that the second depletion layer can be expanded from the second pn junction. - This makes it possible to appropriately suppress current concentration and electric field concentration in the diode region 24.

[0103] 9 is a diagram showing the results of a simulation of the current density distribution in the main part of the semiconductor device 1 of FIG. 1. The voltage VGS between the gate electrode 10 and the source electrode 11 was 18 V. The voltage VDS between the drain electrode 23 and the source electrode 11 was 1 V.

[0104] Referring to FIG. 9, in semiconductor device 1, the JBS structure is used to suppress the concentration of current and electric field. However, n - The current is concentrated in the n-type diode region 24. - It can be seen that the resistance value increases in the diode region 24 due to current concentration.

[0105] Therefore, n - It is believed that the conduction loss of the SBD 8 can be further reduced by suppressing an increase in resistance due to current concentration in the diode region 24 and facilitating current flow.

[0106] Therefore, the aspect ratio L2 / L1 and the like were adjusted based on the unit cell 15 shown in FIG. 2, and the current-voltage characteristics of the SBD 8 were examined.

[0107] 10 is a plan view of a portion corresponding to FIG. 2, illustrating a structure in which the aspect ratio L2 / L1 of the unit cell 15 is 2. The aspect ratio L2 / L1 being 2 means that the aspect ratio L2 / L1 is twice the aspect ratio L2 / L1 (= 1) of the unit cell 15 shown in FIG.

[0108] 10, each unit cell 15 is formed in a rectangular shape in a plan view. Preferably, each unit cell 15 is formed in a rectangular shape extending along the second direction Y, i.e., the <11-20> direction. This structure can suppress localized electric field concentration in the unit cell 15, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0109] The length L1 of the short side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 12 μm), and the length L2 of the long side of the unit cell 15 may be 10 μm or more and 30 μm or less (for example, about 24 μm).

[0110] n - The n-type diode region 24 is formed in a rectangular shape in a plan view. - The area ratio SD / SC of the diode region 24 may be equal to or greater than 0.05 and equal to or less than 0.06 (for example, approximately 0.055).

[0111] n - The length L3 of the short side of the n-type diode region 24 may be 1 μm or more and 1.5 μm or less (for example, about 1.2 μm). - The length L4 of the long side of the diode region 24 may be 10 μm or more and 15 μm or less (for example, about 13.2 μm). - The aspect ratio L4 / L3 of the diode region 24 is greater than the aspect ratio L2 / L1 of the unit cell 15.

[0112] 11 is a plan view of a portion corresponding to FIG. 2, illustrating a structure in which the aspect ratio L2 / L1 of the unit cell 15 is 3. The aspect ratio L2 / L1 being 3 means that the aspect ratio L2 / L1 is three times the aspect ratio L2 / L1 (= 1) of the unit cell 15 shown in FIG.

[0113] 11, each unit cell 15 is formed in a rectangular shape in a plan view. Preferably, each unit cell 15 is formed in a rectangular shape extending along the second direction Y, i.e., the <11-20> direction. This structure can suppress localized electric field concentration in the unit cell 15, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0114] The length L1 of the short side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 12 μm), and the length L2 of the long side of the unit cell 15 may be 15 μm or more and 45 μm or less (for example, about 36 μm).

[0115] n - The n-type diode region 24 is formed in a rectangular shape in a plan view. - The area ratio SD / SC of the diode region 24 may be equal to or greater than 0.065 and equal to or less than 0.075 (for example, approximately 0.07).

[0116] n - The length L3 of the short side of the n-type diode region 24 may be 1 μm or more and 1.5 μm or less (for example, about 1.2 μm). - The length L4 of the long side of the diode region 24 may be 20 μm or more and 30 μm or less (for example, about 25.2 μm). - The aspect ratio L4 / L3 of the diode region 24 is greater than the aspect ratio L2 / L1 of the unit cell 15.

[0117] 12 is a graph showing the measurement results of the current-voltage characteristics of the SBD 8. In FIG. 12, the vertical axis represents the drain current ID [A], and the horizontal axis represents the voltage VDS [V] between the drain electrode 23 and the source electrode 11. The drain current ID is also the forward current IF of the SBD 8. The voltage VDS between the drain electrode 23 and the source electrode 11 is also the forward voltage VF of the SBD 8.

[0118] In addition to the first characteristic A and the second characteristic B, FIG. 12 also shows a third characteristic C and a fourth characteristic D (see also FIG. 8).

[0119] A third characteristic C shows the current-voltage characteristics of the SBD 8 of the semiconductor device 1 including a unit cell 15 with an aspect ratio L2 / L1 of 2 (see also FIG. 10). A fourth characteristic D shows the current-voltage characteristics of the SBD 8 of the semiconductor device 1 including a unit cell 15 with an aspect ratio L2 / L1 of 3 (see also FIG. 11).

[0120] With reference to the first characteristic A and the third characteristic C, the rate of increase of the drain current ID relative to the rate of increase of the voltage VDS between the drain electrode 23 and the source electrode 11 in the third characteristic C is higher than the rate of increase of the drain current ID in the first characteristic A.

[0121] Furthermore, referring to the first characteristic A and the fourth characteristic D, the rate of increase of the drain current ID relative to the rate of increase of the voltage VDS between the drain electrode 23 and the source electrode 11 in the fourth characteristic D is higher than the rate of increase of the drain current ID in the first characteristic A.

[0122] Furthermore, with reference to the third characteristic C and the fourth characteristic D, the rate of increase of the drain current ID relative to the rate of increase of the voltage VDS between the drain electrode 23 and the source electrode 11 does not differ significantly between the third characteristic C and the fourth characteristic D.

[0123] The first characteristic A, the third characteristic C, and the fourth characteristic D show that increasing the aspect ratio L2 / L1 of the unit cell 15 can improve the rate of increase of the drain current ID relative to the rate of increase of the voltage VDS between the drain electrode 23 and the source electrode 11. In other words, increasing the aspect ratio L2 / L1 of the unit cell 15 can reduce the conduction loss of the SBD 8.

[0124] On the other hand, the rate of increase in the drain current ID of the fourth characteristic D relative to the third characteristic C is smaller than the rate of increase in the drain current ID of the third characteristic C relative to the first characteristic A. Therefore, it was found that there is an upper limit to the aspect ratio L2 / L1.

[0125] The aspect ratio L2 / L1 of the unit cell 15 may be adjusted within the range of "1" to "4". - The area ratio SD / SC of the diode region 24 may be adjusted within a range of 0.005 to 0.01.

[0126] Any combination of the aspect ratio L2 / L1 within the above range and the area ratio SD / SC within the above range can reduce the conduction loss of the SBD 8, thereby increasing the degree of freedom in design.

[0127] 13 is a plan view showing a part of the device formation region 6, and is a plan view of a semiconductor device 51 according to a second embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals and will not be described again.

[0128] As shown in FIG. 13, in this embodiment, the plurality of unit cells 15 includes a plurality of unit cells 15A having a relatively large aspect ratio L2 / L1 and a plurality of unit cells 15B having a relatively small aspect ratio L2 / L1.

[0129] Each of the unit cells 15A extends in a strip shape along the second direction Y, i.e., the <11-20> direction. The aspect ratio L2 / L1 of the unit cells 15A is 2. That is, the unit cell 15 shown in FIG. 11 is used as the unit cells 15A.

[0130] Such a structure can suppress localized electric field concentration on the unit cells 15, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1. The unit cells 15A are arranged in a staggered pattern in a planar view, instead of in a matrix pattern in a planar view.

[0131] The aspect ratio L2 / L1 of the plurality of unit cells 15B is less than "2." The plurality of unit cells 15B are formed along the periphery of the device formation region 6. The plurality of unit cells 15B may be formed in an area defined by the periphery of the device formation region 6 and the plurality of unit cells 15A.

[0132] As described above, the semiconductor device 51 can also achieve the same effects as those described for the semiconductor device 1. Furthermore, the plurality of unit cells 15B are formed in an area defined by the periphery of the device formation region 6 and the plurality of unit cells 15A. This allows the plurality of unit cells 15A, 15B to be formed efficiently within the device formation region 6, thereby appropriately increasing the current path.

[0133] 14 is a plan view showing a part of the device formation region 6, that is, a plan view of a semiconductor device 52 according to a third embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0134] 14, the plurality of unit cells 15 are arranged so as to be connected to each other along the second direction Y, i.e., the <11-20> direction. As a result, the plurality of (two or more) unit cells 15 form one linear cell 53 extending in a strip shape along the second direction Y. This structure can suppress local electric field concentration in the linear cell 53, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0135] A plurality of linear cells 53 may be arranged at intervals along the first direction X. Fig. 14 shows a structure in which the unit cell 15 shown in Fig. 11, whose aspect ratio L2 / L1 is "2", is applied.

[0136] A plurality of n adjacent to each other along the second direction Y -Between the n-type diode regions 24, the p-type well regions 25 of one and / or the other unit cells 15 adjacent to each other along the second direction Y are interposed. - The semiconductor device has a structure in which the diode regions 24 are arranged at intervals from each other along the second direction Y.

[0137] As described above, the semiconductor device 52 can also achieve the same effects as those described for the semiconductor device 1.

[0138] The plurality of unit cells 15 may be arranged so as to be connected to each other along the first direction X instead of the second direction Y. Therefore, the plurality of unit cells 15 may form one linear cell extending along the first direction X. Furthermore, a plurality of linear cells having such a structure may be arranged at intervals along the second direction Y.

[0139] 15 is a plan view of a semiconductor device 61 according to a fourth embodiment of the present invention. In the following description, structures corresponding to those described for the semiconductor device 1 will be denoted by the same reference numerals.

[0140] The semiconductor device 61 includes a chip-shaped semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and four side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4.

[0141] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the normal direction thereof (hereinafter simply referred to as "plan view"). The side surface 5A and the side surface 5C face each other. The side surface 5B and the side surface 5D face each other.

[0142] The semiconductor layer 2 is defined with a device formation region 6 and an outer region 7. The device formation region 6 is a region where an SBD 8 and a MISFET 9 are formed. The device formation region 6 is also called an active region.

[0143] In plan view, the device formation region 6 is set in the central region of the semiconductor layer 2, spaced apart from the periphery of the semiconductor layer 2 toward the inner region of the semiconductor layer 2. In this embodiment, the device formation region 6 is set in a quadrilateral shape having four sides parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in plan view.

[0144] The outer region 7 is set in a region between the periphery of the semiconductor layer 2 and the periphery of the device formation region 6. The outer region 7 is set in an endless shape (quadratic ring shape) surrounding the device formation region 6 in a plan view.

[0145] The ratio SE / SF of the planar area SF of the device formation region 6 to the planar area SE of the first main surface 3 of the semiconductor layer 2 may be 70% or more and 85% or less. 2 More than 25mm 2 The width WO of the outer region 7 may be 0.1 mm or more and 0.3 mm or less. The width WO of the outer region 7 is defined as the width in a direction perpendicular to the direction in which the outer region 7 extends.

[0146] A gate electrode 10 and a source electrode 11 (first main surface electrode) are formed on the first main surface 3 of the semiconductor layer 2. For clarity, the gate electrode 10 and the source electrode 11 are shown by hatching in Figure 15. The gate electrode 10 includes a gate pad 12, gate fingers 13, and a gate line 62.

[0147] The gate pad 12 is formed along any one of the side surfaces (side surface 5A in this embodiment) in a plan view. The gate pad 12 is formed in a central region of the side surface 5A in a plan view. In this embodiment, the gate pad 12 is drawn from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6.

[0148] In this embodiment, the gate pad 12 is formed in a quadrangular shape in plan view. The gate pad 12 may be formed along one corner connecting two side surfaces 5A to 5D that extend in directions that intersect (are perpendicular to) each other in plan view.

[0149] The gate fingers 13 extend in a strip shape from the gate pad 12 along the periphery of the device formation region 6. In this embodiment, the gate fingers 13 are formed in an endless shape (quadratic ring shape) that surrounds the device formation region 6 in a plan view. The gate fingers 13 may be formed so as to partition the device formation region 6 from three directions.

[0150] The gate line 62 is drawn out from the drawn-out end of the gate pad 12 toward the center of the device formation region 6. In this embodiment, the gate line 62 is formed in a strip shape extending in a straight line from the gate pad 12 toward the side surface 5C of the semiconductor layer 2 in a plan view.

[0151] The source electrode 11 is formed in a C-shaped region defined by the inner edge of the gate electrode 10 in plan view. In this embodiment, the source electrode 11 is formed in a C-shape that follows the inner edge of the gate electrode 10 in plan view.

[0152] The source electrode 11 covers most of the device formation region 6. The source electrode 11 may have a structure in which it has a plurality of electrode portions separated from one another and the device formation region 6 is covered by the plurality of electrode portions.

[0153] In this embodiment, a first bonding wire for the gate is connected to the gate pad 12. The first bonding wire may be an aluminum wire. In this embodiment, a second bonding wire for the source is connected to the source electrode 11. The second bonding wire may be an aluminum wire.

[0154] FIG. 16 is a plan view in which the gate electrode 10 and the source electrode 11 are removed from FIG. 15, and is a diagram for explaining the structure on the first main surface 3 of the semiconductor layer 2. In FIG.

[0155] A gate pad layer 63, a gate finger layer 64, and a gate line layer 65 are formed on the first main surface 3 of the semiconductor layer 2. In FIG. 16, for clarity, the gate pad layer 63, the gate finger layer 64, and the gate line layer 65 are indicated by hatching.

[0156] The gate pad layer 63 is formed in a region directly below the gate pad 12. The gate pad layer 63 is electrically connected to the gate pad 12. Although not shown, the gate pad 12 is electrically connected to the gate pad layer 63 via a contact hole formed in the insulating layer 34.

[0157] In this embodiment, the gate pad layer 63 is drawn from the outer region 7 to the device formation region 6 so as to cross the boundary between the outer region 7 and the device formation region 6. In this embodiment, the gate pad layer 63 is formed in a quadrangular shape in plan view.

[0158] The gate finger layer 64 is formed in a region directly below the gate finger 13. The gate finger layer 64 is electrically connected to the gate finger 13. Although not shown, the gate finger 13 is electrically connected to the gate finger layer 64 via a contact hole formed in the insulating layer 34. The gate finger layer 64 is drawn out in a strip shape from the gate pad layer 63 along the periphery of the device formation region 6.

[0159] In this embodiment, the gate finger layer 64 is formed endlessly (in the shape of a quadrangular ring) in plan view so as to surround the device formation region 6. The gate finger layer 64 may be formed so as to partition the device formation region 6 from three directions.

[0160] The gate line layer 65 is formed in a region directly below the gate line 62. The gate line layer 65 is electrically connected to the gate line 62. Although not shown, the gate line 62 is electrically connected to the gate line layer 65 via a contact hole formed in the insulating layer 34.

[0161] The gate line layer 65 is drawn out from the drawn-out end of the gate pad layer 63 toward the center of the device formation region 6. In this embodiment, the gate line layer 65 is formed in a strip shape extending in a straight line from the gate pad layer 63 toward the side surface 5C of the semiconductor layer 2 in a plan view.

[0162] A gate electrode layer 33 (planar gate structure) is formed in a C-shaped region defined by the gate pad layer 63, the gate finger layer 64, and the gate line layer 65. In this embodiment, the gate electrode layer 33 is formed in a lattice shape in a planar view.

[0163] 16, the gate electrode layer 33 is indicated by grid lines. The gate electrode layer 33 is led out from a gate pad layer 63, a gate finger layer 64, and a gate line layer 65.

[0164] The gate electrode layer 33 is electrically connected to the gate pad 12 , the gate finger 13 and the gate line 62 via a gate pad layer 63 , a gate finger layer 64 and a gate line layer 65 .

[0165] FIG. 17 is an enlarged view of region XVII shown in FIG. 16, with the structure above first main surface 3 of semiconductor layer 2 removed.

[0166] 17, unit cells 15 for forming SBDs 8 and MISFETs 9 are formed in device formation region 6. Fig. 17 shows an example in which a plurality of unit cells 15 are arranged in a matrix.

[0167] The unit cells 15 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. In this embodiment, the first direction X is a direction along any one of the side surfaces 5A to 5D of the semiconductor layer 2 (side surfaces 5B and 5D in this embodiment). The second direction Y is a direction along a side surface perpendicular to the arbitrary one of the side surfaces 5A to 5D (side surfaces 5A and 5C in this embodiment). In this embodiment, the second direction Y is a direction perpendicular to the first direction X.

[0168] The unit cell 15 is formed in a quadrangular shape in plan view. The unit cell 15 has corners 15a that are curved outward in a convex shape in plan view. This allows the concentration of the electric field at the corners 15a of the unit cell 15 to be alleviated.

[0169] 10 and 11, the aspect ratio L2 / L1 of the unit cell 15 can be a value of 1 or more (for example, 1 to 4), but an example where the aspect ratio is 1 will be described here. The aspect ratio L2 / L1 is defined as the ratio of the length L2 of one side of the unit cell 15 along the second direction Y to the length L1 of one side of the unit cell 15 along the first direction X.

[0170] In this embodiment, the unit cell 15 is formed in a square shape in a plan view. The lengths L1 and L2 of one side of the unit cell 15 may be 5 μm or more and 15 μm or less (for example, about 10 μm).

[0171] A first line portion 16, a second line portion 17, and an intersection portion 18 are formed on the first main surface 3 of the semiconductor layer 2. The first line portion 16, the second line portion 17, and the intersection portion 18 are all formed by the first main surface 3 of the semiconductor layer 2 exposed from the unit cell 15.

[0172] The first line portions 16 extend along the first direction X through the regions between the unit cells 15 and partition the regions between the unit cells 15 adjacent to each other in the second direction Y. The second line portions 17 extend along the second direction Y through the regions between the unit cells 15 and partition the regions between the unit cells 15 adjacent to each other in the first direction X. The intersection portions 18 are portions where the first line portions 16 and the second line portions 17 intersect.

[0173] The width W1 of the first line portion 16 in the second direction Y may be 0.8 μm or more and 3.0 μm or less (for example, about 1.2 μm). The width W2 of the second line portion 17 in the first direction X may be 0.8 μm or more and 3.0 μm or less (for example, about 1.2 μm).

[0174] An impurity region 19 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 at the intersection 18. The impurity region 19 reduces the electric field generated in the surface layer portion of the first main surface 3 of the semiconductor layer 2, particularly between adjacent unit cells 15. The impurity region 19 suppresses a decrease in the breakdown voltage of the semiconductor device 61.

[0175] In this embodiment, the impurity region 19 is a p-type impurity region or p + The impurity region 19 includes a semiconductor layer 2 (which will be described later as an n-type impurity region). - A pn junction is formed between the impurity region 19 and the type epitaxial layer 22. The impurity region 19 has a corner 19a that is curved outward in a convex shape in plan view.

[0176] The impurity regions 19 overlap the unit cells 15 at the intersections 18. More specifically, corners 19a of the impurity regions 19 overlap corners 15a of the unit cells 15. Even more specifically, the four corners 19a of one impurity region 19 overlap corners 15a of four adjacent unit cells 15 at the intersections 18. This allows the concentration of electric field at the corners 15a of each unit cell 15 to be appropriately alleviated.

[0177] Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 17. Fig. 19 is an enlarged view of an area XIX shown in Fig. 18. In the following, Fig. 17 will also be referred to as necessary.

[0178] Referring to FIG. 18, the semiconductor layer 2 is + a semiconductor substrate 21 and an n-type + formed on an n-type semiconductor substrate 21 - The n-type epitaxial layer 22 has a layered structure. - The first main surface 3 of the semiconductor layer 2 is formed by the n-type epitaxial layer 22. + The second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 21 .

[0179] n + In this embodiment, the n-type semiconductor substrate 21 includes a wide bandgap semiconductor. + The n-type semiconductor substrate 21 may include SiC, diamond, or a nitride semiconductor. + The off-angle of the semiconductor substrate 21 may be 4°.

[0180] n - In this embodiment, the n-type epitaxial layer 22 comprises a wide bandgap semiconductor. - The epitaxial layer 22 may include SiC, diamond, or a nitride semiconductor. The SiC may be 4H—SiC. The nitride semiconductor may be GaN.

[0181] n - The epitaxial layer 22 is + The n-type semiconductor substrate 21 may be made of the same material. - The epitaxial layer 22 is + The n-type semiconductor substrate 21 may be made of a material different from that of the n-type semiconductor substrate 21. + type semiconductor substrate 21 and n - An example in which the type epitaxial layers 22 all contain SiC (4H—SiC) will be described.

[0182] That is, n+ The semiconductor substrate 21 has a main surface that is misoriented from the <0001> plane to the <11-20> direction by 10° or less, more specifically, 2° or 4°.

[0183] n - The epitaxial layer 22 is + It is formed by epitaxially growing SiC from the main surface of the n-type semiconductor substrate 21. - The epitaxial layer 22 has a primary surface that is off-angled from the <0001> plane by 10° or less with respect to the <11-20> direction. More specifically, the off-angle is 2° or 4°.

[0184] In this embodiment, the first direction X is set to a direction perpendicular to the <11-20> direction, and the second direction Y is set to the <11-20> direction. Therefore, the unit cells 15 are arranged at intervals along the <11-20> direction and a direction perpendicular to the <11-20> direction.

[0185] When a plurality of unit cells 15 are arranged along the <11-20> direction using a 4H—SiC substrate having an off-angle of 10° or less, the electric field and crystal orientation relationships between adjacent unit cells 15 are equal to each other.

[0186] The pressure resistance of the unit cells 15 is reduced by local electric field concentration. Therefore, when an electric field is locally concentrated in a certain unit cell 15 among the plurality of unit cells 15, the pressure resistance of the plurality of unit cells 15 as a whole is limited by that certain unit cell 15.

[0187] Therefore, by arranging the plurality of unit cells 15 so that the relationship between the electric field and the crystal orientation is equal to one another, it is possible to prevent the electric field from concentrating locally in a certain unit cell 15 among the plurality of unit cells 15. This makes it possible to make the breakdown voltage strength of each unit cell 15 nearly uniform, thereby preventing a decrease in the breakdown voltage of the semiconductor device 1.

[0188] A drain electrode 23 (second principal surface electrode) is connected to the second principal surface 4 of the semiconductor layer 2. The drain electrode 23 covers the second principal surface 4 of the semiconductor layer 2 and has an n + An ohmic junction is formed between the semiconductor substrate 21 and the insulating layer 22 .

[0189] In the semiconductor layer 2, n + The n-type semiconductor substrate 21 is formed as a low resistance region (drain region). - The epitaxial layer 22 is formed as a high resistance region (drift region).

[0190] n - The thickness of the n-type epitaxial layer 22 may be 5 μm or more and 70 μm or less. - By increasing the thickness of the epitaxial layer 22, the breakdown voltage of the semiconductor device 61 can be improved.

[0191] For example, n - By setting the thickness of the n-type epitaxial layer 22 to 5 μm or more, a breakdown voltage of 600 V or more can be obtained. - By setting the thickness of the n-type epitaxial layer 22 to 20 μm or more, a breakdown voltage of 3000 V or more can be obtained. - By setting the thickness of the epitaxial layer 22 to 40 μm or more, a breakdown voltage of 6000 V or more can be obtained.

[0192] 17 to 19, a plurality of unit cells 15 are formed in a surface layer portion of first main surface 3 of semiconductor layer 2. A recess portion 71 recessed toward second main surface 4 of semiconductor layer 2 is formed in the surface of each unit cell 15.

[0193] That is, a plurality of recesses 71 are arranged in a matrix at intervals in the first direction X and the second direction Y on the first main surface 3 of the semiconductor layer 2. The unit cells 15 are formed along the recesses 71. The depth of the recesses 71 may be 0.5 μm or more and 5 μm or less.

[0194] The recessed portion 71 has side walls 72, a bottom wall 73, and an edge portion 74 connecting the side walls 72 and the bottom wall 73. In this embodiment, the recessed portion 71 is set to have a quadrangular shape with four sides parallel to the sides of the unit cell 15 in a plan view.

[0195] The bottom wall 73 of the recessed portion 71 has a surface roughness Zr that is equal to or greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 (Zr≧Zs). More specifically, the surface roughness Zr of the bottom wall 73 of the recessed portion 71 is greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 (Zr>Zs). The surface roughnesses Zr and Zs may each be arithmetic mean roughnesses.

[0196] The bottom wall 73 of the recessed portion 71 has n - a p-type diode region 24, a p-type well region 25, an n + type source region 26 and p + A mold contact region 27 is formed.

[0197] n - The n-type diode region 24 is formed in the center of the bottom wall 73 of the recessed portion 71. - The n-type diode region 24 is formed in a quadrangular shape in plan view. - The diode region 24 has a corner 24a that is curved outward in a convex shape in plan view.

[0198] n - In this embodiment, the n-type diode region 24 - The n-type epitaxial layer 22 is formed by utilizing a part of the region. - The n-type diode region 24 - The n-type impurity concentration is approximately equal to the n-type impurity concentration of the epitaxial layer 22.

[0199] n - The n-type diode region 24 - Alternatively, the n-type epitaxial layer 22 may be formed by further implanting n-type impurities into the surface layer of the n-type epitaxial layer 22. -The surface layer of the n-type diode region 24 - The n-type impurity concentration may be higher than the n-type impurity concentration of the n-type epitaxial layer 22.

[0200] n for the planar area SC of unit cell 15 - The area ratio SD / SC of the planar area SD of the diode region 24 may be equal to or greater than 0.005 and equal to or less than 0.015 (for example, approximately 0.01).

[0201] n - The aspect ratio L4 / L3 of the n-type diode region 24 may be "1". - n with respect to the length L3 of one side of the diode region 24 along the first direction X - The ratio is defined as the ratio of the length L4 of one side of the diode region 24 along the second direction Y.

[0202] Therefore, n - In this embodiment, the n-type diode region 24 is formed in a square shape in a plan view. - The lengths L3 and L4 of one side of the diode region 24 may each be 0.8 μm or more and 3.0 μm or less (for example, approximately 1.2 μm).

[0203] The breakdown voltage of the semiconductor layer 2 is n - The width (lengths L3 and L4) of the narrowest part of the diode region 24 is limited by the width W1 of the first line portion 16 or the width W2 of the second line portion 17. - It is preferable that the width (lengths L3, L4) of the narrowest portion of the diode region 24 is approximately equal to the width W1 of the first line portion 16 and the width W2 of the second line portion 17.

[0204] For example, n for the first line portion 16 and the second line portion 17 - When the diode region 24 is small, the breakdown voltage of the semiconductor layer 2 is - The n-type diode region 24 is limited. -When the first line portion 16 and / or the second line portion 17 is small relative to the diode region 24, the breakdown voltage of the semiconductor layer 2 is limited by the first line portion 16 and / or the second line portion 17.

[0205] Therefore, n - By forming the width (lengths L3 and L4) of the narrowest part of the diode region 24 to be approximately equal to the width W1 of the first line portion 16 and the width W2 of the second line portion 17, the breakdown voltage of the semiconductor layer 2 is - Therefore, the limitation by the diode region 24, the first line portion 16 or the second line portion 17 can be suppressed.

[0206] The p-type well region 25 is formed at the bottom wall 73 of the recessed portion 71 by - The p-type well region 25 is formed along the periphery of the n-type diode region 24. More specifically, the p-type well region 25 is formed on the bottom wall 73 of the recessed portion 71. - The diode region 24 is formed in an endless shape (square ring shape).

[0207] The p-type well region 25 covers the sidewall 72 of the recessed portion 71 from the bottom wall 73 through the edge portion 74. In other words, the bottom wall 73 of the recessed portion 71 is located closer to the first main surface 3 of the semiconductor layer 2 than the bottom of the p-type well region 25.

[0208] The outer periphery of the p-type well region 25 forms the outer periphery of the unit cell 15. Therefore, the p-type well region 25 has corners 25a that are curved convexly outward in a plan view. The corners 25a of the p-type well region 25 correspond to the corners 15a of the unit cell 15. This makes it possible to alleviate the concentration of the electric field at the corners 25a of the p-type well region 25.

[0209] The bottom of p-type well region 25 is formed parallel to first main surface 3 of semiconductor layer 2. In other words, the bottom of p-type well region 25 is formed parallel to the

[0001] plane of semiconductor layer 2. With this structure, it is possible to alleviate electric field concentration in p-type well region 25, which is caused by the properties of the crystal.

[0210] The p-type well region 25 is - type diode region 24 and n - A pn junction is formed between the p-type epitaxial layer 22 and the p-type well region 25. This pn junction allows the p-type well region 25 to function as an anode and the n-type epitaxial layer 22 to function as an anode. - A first diode 28 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0211] n + The n-type source region 26 is formed in the surface layer of the p-type well region 25. + The n-type source region 26 - The n-type impurity concentration is higher than that of the n-type diode region 24.

[0212] n + The n-type source region 26 is formed on the bottom wall 73 of the recess 71 at a distance from the inner and outer peripheries of the p-type well region 25. + The source region 26 covers the sidewall 72 of the recessed portion 71 from the bottom wall 73 through the edge portion 74 .

[0213] n + In this embodiment, the n-type source region 26 is formed in an endless shape (a square ring shape) along the p-type well region 25 in a plan view. + The source region 26 has a corner 26a that is curved outward in a convex shape in plan view.

[0214] p + The p-type contact region 27 is formed in the surface layer of the p-type well region 25. + The contact region 27 has a p-type impurity concentration higher than the p-type impurity concentration of the p-type well region 25 .

[0215] p + The contact region 27 is formed on the bottom wall 73 of the recess 71 so as to contact the inner periphery of the p-type well region 25 and the n-type well region 26 . + The p-type source regions 26 are formed in the region between the p-type source regions 26. + type contact region 27 and n+ The boundary area between the source regions 26 abuts the bottom wall 73 of the recess 71 .

[0216] p + In this embodiment, the p-type contact region 27 is formed in an endless shape (a square ring shape) along the inner periphery of the p-type well region 25 in plan view. + The mold contact region 27 has a corner 27a that is curved outward in a convex shape in plan view.

[0217] FIG. 20 shows the p-type well region 25, n + type source region 26 and p + 20 is a graph showing the impurity concentration profile of the type-contact region 27. In Fig. 20, the vertical axis represents the impurity concentration [cm-3], and the horizontal axis represents the depth [µm] from the first main surface 3 of the semiconductor layer 2.

[0218] 20 shows a first curve L1, a second curve L2, and a third curve L3. The first curve L1 shows the impurity concentration profile of the p-type well region 25. The second curve L2 shows the impurity concentration profile of the n + The third curve L3 shows the impurity concentration profile of the p-type source region 26. + 2 shows the impurity concentration profile of the contact region 27.

[0219] With reference to the first curve L1, the p-type impurity concentration of the p-type well region 25 has a peak value (maximum value) at a depthwise position thereof. The p-type impurity concentration of the p-type well region 25 decreases from the peak value toward the first main surface 3 and the second main surface 4 of the semiconductor layer 2.

[0220] Referring to the second curve L2, n + The n-type impurity concentration of the n-type source region 26 is higher than the p-type impurity concentration of the p-type well region 25. + The n-type impurity concentration of the source region 26 has a concentration profile that gradually decreases from the first main surface 3 (bottom wall 73 of the recessed portion 71) toward the second main surface 4 of the semiconductor layer 2.

[0221] Referring to the dashed line portion of the second curve L2, n + In reality, the n-type impurity concentration of the source region 26 has a peak value (maximum value) at a midpoint in the depth direction, similar to the p-type well region 25.

[0222] The recessed portion 71 is n + The n-type impurity concentration is formed by removing a surface region of the n-type source region 26 where the n-type impurity concentration is relatively low. In this way, the n-type impurity concentration is gradually decreased from the first main surface 3 to the second main surface 4 of the semiconductor layer 2. + A source region 26 is formed.

[0223] Referring to the third curve L3, p + The p-type impurity concentration of the p-type contact region 27 is higher than the p-type impurity concentration of the p-type well region 25. + The p-type impurity concentration of the contact region 27 has a concentration profile that gradually decreases from the first main surface 3 (bottom wall 73 of the recess 71) toward the second main surface 4 of the semiconductor layer 2.

[0224] Referring to the dashed line of the third curve L3, p + The p-type impurity concentration of the contact region 27 actually has a peak value (maximum value) at a midpoint in the depth direction, like the p-type well region 25.

[0225] The recessed portion 71 is p + The recessed portion 71 is formed by removing a surface region of the semiconductor layer 27 where the p-type impurity concentration is relatively low. In this way, the p-type impurity concentration is gradually decreased from the first main surface 3 (bottom wall 73 of the recessed portion 71) to the second main surface 4 of the semiconductor layer 2. + A mold contact region 27 is formed.

[0226] In this way, the bottom wall 73 of the recessed portion 71 is provided with the p-type well region 25, the n-type well region 26, and the n-type well region 27. + type source region 26 and p +A portion with a relatively high impurity concentration is exposed in the contact region 27. This improves the electrical connection of the source electrode 11 to each semiconductor region, allowing the SBD 8 and MISFET 9 to be formed appropriately.

[0227] Each unit cell 15 has a JBS structure. - The pn junction is formed between the p-type diode region 24 and the p-type well region 25. - A JFET structure is formed on the surface of the epitaxial layer 22 by utilizing each unit cell 15 .

[0228] The JFET structure includes a first pnp structure and a second pnp structure. The first pnp structure has n - The second pnp structure is formed by the first line portion 16 of the n-type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the first line portion 16 interposed therebetween. - The p-type well region 25 is formed by the second line portion 17 of the p-type epitaxial layer 22 and the p-type well regions 25 adjacent to each other with the second line portion 17 interposed therebetween.

[0229] 18 again, a planar gate structure is formed on the first main surface 3 of the semiconductor layer 2. The planar gate structure has a stacked structure including a gate insulating layer 32 and a gate electrode layer 33. The planar gate structure is formed in a lattice shape along the first line portions 16 and the second line portions 17 in a plan view.

[0230] Gate insulating layer 32 may include an oxide film. The oxide film may include silicon oxide. Referring to FIG. 19 , gate insulating layer 32 has a gate through-hole 75 formed therein, which is in communication with recess portion 71. The inner wall of gate through-hole 75 is formed flush with sidewall 72 of recess portion 71.

[0231] The gate electrode layer 33 is formed between the p-type well region 25 and the n-type well region 26 with the gate insulating layer 32 sandwiched therebetween. + type source region 26 and n -The gate electrode layer 33 extends from the region above the first line portion 16, the second line portion 17, and the intersection portion 18 to the region above each unit cell 15, and is connected to the p-type well region 25 and the n-type epitaxial layer 22 of each unit cell 15. + The source region 26 is selectively covered.

[0232] More specifically, the gate electrode layer 33 includes a main body portion 76 and an overhang portion 77. The main body portion 76 of the gate electrode layer 33 is located on the gate insulating layer 32. The overhang portion 77 of the gate electrode layer 33 overhangs from the main body portion 76 of the gate electrode layer 33 into a region above the unit cell 15.

[0233] The protruding portion 77 of the gate electrode layer 33 has a facing portion 78 that faces the bottom wall 73 of the recessed portion 71 across a space. More specifically, the protruding portion 77 of the gate electrode layer 33 faces the bottom wall 73 of the recessed portion 71 across a space. + The source region 26 faces the source region 26 .

[0234] An upper surface insulating layer 79 is formed on the upper surface of the gate electrode layer 33. The upper surface insulating layer 79 covers almost the entire upper surface of the gate electrode layer 33. The upper surface insulating layer 79 is formed to improve the flatness of the region above the gate electrode layer 33. The upper surface insulating layer 79 may include a nitride film. The nitride film may include silicon nitride.

[0235] An insulating layer 34 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 34 covers the gate electrode layer 33. Although not shown, the insulating layer 34 also covers the gate pad layer 63, the gate finger layer 64, and the gate line layer 65.

[0236] The insulating layer 34 fills the space between the protruding portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recessed portion 71, and covers the outer surface of the gate electrode layer 33. The insulating layer 34 includes a buried portion 80 buried in the space. The buried portion 80 of the insulating layer 34 contacts the gate insulating layer 32 in the space.

[0237] The protruding portion 77 of the gate electrode layer 33 is n-type with the buried portion 80 of the insulating layer 34 sandwiched therebetween. + The buried portion 80 of the insulating layer 34 faces the source region 26. Therefore, the buried portion 80 of the insulating layer 34 functions as a part of the gate insulating layer 32.

[0238] The thickness of the embedded portion 80 of the insulating layer 34 may be equal to or greater than the thickness of the gate insulating layer 32. In other words, the insulating layer 34 can be considered to have a thin film portion in contact with the inner portion (main body portion 76) of the gate electrode layer 33, and a thick film portion that has a thickness greater than the thickness of the thin film portion and in contact with the peripheral portion (protruding portion 77) of the gate electrode layer 33.

[0239] In this embodiment, the insulating layer 34 has a laminated structure in which a plurality of insulating films are laminated. More specifically, the plurality of insulating films include an insulating film 81 and an insulating film 82 laminated in this order from the first main surface 3 side of the semiconductor layer 2. The insulating film 82 contains an insulating material with different properties from the insulating material of the insulating film 81.

[0240] The insulating film 81 may contain USG (Undoped Silica Glass). The insulating film 82 may contain PSG (Phosphosilicate Glass). The insulating film 82 may contain BPSG (Borophosphosilicate Glass) instead of PSG.

[0241] The insulating film 81 is formed on the first main surface 3 of the semiconductor layer 2 so as to cover the gate electrode layer 33. The insulating film 81 covers from the bottom wall 73 of the recessed portion 71 to the outer surface of the gate electrode layer 33. More specifically, the insulating film 81 includes a first covering portion 83 that covers the bottom wall 73 of the recessed portion 71 and a second covering portion 84 that covers the outer surface of the gate electrode layer 33.

[0242] The first covering portion 83 of the insulating film 81 is formed in the form of a film along the bottom wall 73 of the recessed portion 71. The first covering portion 83 of the insulating film 81 is embedded in the space between the protruding portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recessed portion 71. The first covering portion 83 of the insulating film 81 forms a buried portion 80 of the insulating layer 34.

[0243] The second covering portion 84 of the insulating film 81 is formed in the form of a film along the outer surface of the gate electrode layer 33. The second covering portion 84 of the insulating film 81 faces the upper surface of the gate electrode layer 33 with the upper surface insulating layer 79 interposed therebetween.

[0244] The insulating film 81 is - n-type diode region 24 + type source region 26 and p + A first contact hole 85 is formed to expose the mold contact region 27. More specifically, the first contact hole 85 is formed in the first covering portion 83 of the insulating film 81.

[0245] The inner wall of the first contact hole 85 is + The first contact hole 85 is formed directly above the source region 26. The opening edge of the first contact hole 85 has a convex curved surface that curves outward in a convex shape.

[0246] The insulating film 82 covers the insulating film 81. The insulating film 82 covers a second covering portion 84 of the insulating film 81 from above a first covering portion 83 of the insulating film 81. A second contact hole 86 communicating with the first contact hole 85 is formed in the insulating film 82.

[0247] In this embodiment, the second contact hole 86 forms one contact hole 35 with the first contact hole 85. The opening edge portion of the second contact hole 86 has a convex curved surface that is curved outward.

[0248] The opening width of the second contact hole 86 is equal to or greater than the opening width of the first contact hole 85. The inner wall of the second contact hole 86 surrounds the inner wall of the first contact hole 85. The inner wall of the first contact hole 85 is located in the inner region of the second contact hole 86. A step 87 including the opening edge portion of the first contact hole 85 is formed in the region between the inner wall of the first contact hole 85 and the inner wall of the second contact hole 86.

[0249] The source electrode 11 is formed on the insulating layer 34. The source electrode 11 penetrates into the contact hole 35 from above the insulating layer 34. The source electrode 11 is connected to the n - n-type diode region 24 + type source region 26 and p + The mold contact region 27 is covered in its entirety.

[0250] The source electrode 11 is - A Schottky junction is formed between the source electrode 11 and the n-type diode region 24. - An SBD 8 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0251] The source electrode 11 is + type source region 26 and p + An ohmic junction is formed between the semiconductor layer 2, the p-type well region 25, and the n-type contact region 27. + Type source region 26, p + A MISFET 9 is formed, which includes a contact region 27, a gate insulating layer 32, a gate electrode 10 (gate electrode layer 33), a source electrode 11, and a drain electrode 23.

[0252] In this embodiment, the source electrode 11 has a laminated structure including an electrode layer 91 and an electrode layer 92 .

[0253] The electrode layer 91 is formed in a film shape and extends from above the insulating layer 34 into the contact hole 35. The electrode layer 91 covers the step portion 87 in the contact hole 35, including the opening edge portion of the first contact hole 85. The electrode layer 91 covers the n - n-type diode region 24 + type source region 26 and p + The mold contact region 27 is covered in its entirety.

[0254] The electrode layer 91 covers the bottom wall 73 of the recessed portion 71, which has a relatively large surface roughness Zr. This increases the adhesion of the electrode layer 91 (source electrode 11) to the bottom wall 73 of the recessed portion 71. As a result, the electrode layer 91 (source electrode 11) and the n - The SBD 8 can be suitably formed in the region between the diode regions 24.

[0255] In this embodiment, the electrode layer 91 has a laminated structure including a first barrier electrode film 93 and a second barrier electrode film 94. The first barrier electrode film 93 includes a Ti (titanium) film. The second barrier electrode film 94 includes a TiN (titanium nitride) film. The electrode layer 91 may have a single-layer structure including only either a Ti (titanium) film or a TiN (titanium nitride) film.

[0256] The electrode layer 92 is formed on the electrode layer 91. The thickness of the electrode layer 92 is equal to or greater than the thickness of the electrode layer 91. The electrode layer 92 is formed in a film shape along the electrode layer 91, and extends from above the insulating layer 34 into the contact hole 35.

[0257] The electrode layer 91 is formed in the contact hole 35 by n - n-type diode region 24 + type source region 26 and p + The electrode layer 92 collectively covers the mold contact region 27. The electrode layer 92 may contain aluminum.

[0258] 18 and 19, source electrode 11 includes a first covering portion 95 that covers insulating layer 34 and a second covering portion 96 that covers bottom wall 73 of recess portion 71. First covering portion 95 bulges upward from above insulating layer 34. Second covering portion 96 has a thickness equal to or smaller than that of first covering portion 95.

[0259] The upper surface of the second covering portion 96 is located closer to the bottom wall 73 of the recessed portion 71 than the upper surface of the first covering portion 95. The upper surfaces of the second covering portion 96 and the first covering portion 95 are formed by the electrode layer 92.

[0260] In this embodiment, the upper surface of the second covering portion 96 is located at a height approximately equal to that of the upper surface of the insulating layer 34. As a result, a recess is defined in the source electrode 11 by the first covering portion 95 and the second covering portion 96.

[0261] In the source electrode 11, a recess 97 is formed at a corner of the upper surface of the second covering portion 96. More specifically, the corner of the second covering portion 96 is a connecting portion that connects the first covering portion 95 and the second covering portion 96.

[0262] The recess 97 is recessed toward the first main surface 3 side of the semiconductor layer 2. The recess 97 may be recessed toward a corner of the insulating layer 34 (insulating film 82). The recess 97 faces the bottom wall 73 of the recess portion 71. The recess 97 has a width of n + The recess 97 faces the p-type source region 26. + It faces the mold contact region 27 .

[0263] The recess 97 forms a thick film portion 98 in the center of the second covering portion 96, the thick film portion 98 having a thickness greater than or equal to the thickness of the other regions. - The semiconductor layer is formed in a portion that covers the diode region 24.

[0264] The width WT of the thick film portion 98 is n - The thickness of the second covering portion 96 may be equal to or greater than the lengths L3, L4 of the diode region 24 (WT≧L3, L4). The thick film portion 98 forms a protrusion 99 on the upper surface of the second covering portion 96, which protrudes upward beyond the recess 97.

[0265] The top of the protrusion 99 is located above the upper surface of the gate electrode layer 33. The top of the protrusion 99 may be located in a region between the upper surface of the insulating layer 34 and the upper surface of the first covering portion 95. The top of the protrusion 99 may be located on the bottom wall 73 side of the recess 71 with respect to the upper surface of the insulating layer 34.

[0266] Although not shown, a plurality of contact holes are selectively formed in the insulating layer 34 to expose the gate pad layer 63, the gate finger layer 64 and the gate line layer 65.

[0267] The gate pad 12, the gate finger 13, and the gate line 62 each extend into a corresponding contact hole (not shown) from above the insulating layer 34. The gate pad 12, the gate finger 13, and the gate line 62 are electrically connected to a gate pad layer 63, a gate finger layer 64, and a gate line layer 65, respectively, in the corresponding contact hole.

[0268] Like the source electrode 11, the gate pad 12, the gate finger 13 and the gate line 62 may each have a laminated structure including an electrode layer 91 and an electrode layer 92.

[0269] In the semiconductor device 61, as shown in FIGS. 10 and 11, the aspect ratio L2 / L1 of the plurality of unit cells 15 may be adjusted within a range of 1 to 4. - The area ratio SD / SC of the diode region 24 may be adjusted within a range of 0.005 to 0.01.

[0270] Any combination of aspect ratio L2 / L1 within the above range and area ratio SD / SC within the above range can reduce the conduction loss of SBD8, as described for semiconductor device 1, and increase the design freedom.

[0271] The specific structure of the unit cells 15 having an aspect ratio L2 / L1 of 1 to 4 is as explained in FIGS. 10 and 11, and therefore will not be explained again.

[0272] As described above, the semiconductor device 61 can also achieve the same effects as those described for the semiconductor device 1.

[0273] 21A to 21P are cross-sectional views for explaining an example of a method for manufacturing the semiconductor device 61 shown in Fig. 15. Figs. 21A to 21P are cross-sectional views of a portion corresponding to Fig. 18.

[0274] 21A, a semiconductor layer 2 is prepared. The semiconductor layer 2 is an n + a step of preparing an n-type semiconductor substrate 21; + On the main surface of the n-type semiconductor substrate 21 - The n-type epitaxial layer 22 is formed through the steps of forming the n-type epitaxial layer 22. - The epitaxial layer 22 is + The SiC layer is formed by epitaxially growing SiC on the main surface of the semiconductor substrate 21.

[0275] 21B, p-type well region 25 is formed in a surface layer portion of first main surface 3 of semiconductor layer 2. In the step of forming p-type well region 25, first, an ion implantation mask 101 having a predetermined pattern is formed on first main surface 3 of semiconductor layer 2. Ion implantation mask 101 has a plurality of openings 102 that expose regions where p-type well region 25 is to be formed.

[0276] Next, p-type impurities are introduced into the surface layer portion of the first main surface 3 of the semiconductor layer 2 through the ion implantation mask 101. As a result, a p-type well region 25 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. After the step of forming the p-type well region 25, the ion implantation mask 101 is removed.

[0277] Next, referring to FIG. 21C, n-type well regions 25 are formed in the surface layer thereof. + The n-type source region 26 is formed. + In the step of forming the n-type source region 26, first, an ion implantation mask 103 having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The ion implantation mask 103 is + It has a plurality of openings 104 exposing the areas where the source regions 26 are to be formed.

[0278] Next, n-type impurities are introduced into the surface layer of the p-type well region 25 through the ion implantation mask 103. As a result, n-type impurities are introduced into the surface layer of the p-type well region 25. + The n-type source region 26 is formed. + After the step of forming the source region 26, the ion implantation mask 103 is removed.

[0279] Next, referring to FIG. 21D, p + A contact region 27 is formed. + In the step of forming the type contact region 27, first, an ion implantation mask 105 having a predetermined pattern is formed on the first main surface 3 of the semiconductor layer 2. The ion implantation mask 105 is a p + It has a plurality of openings 106 that expose the areas where mold contact regions 27 are to be formed.

[0280] Next, p-type impurities are introduced into the surface layer of the p-type well region 25 through the ion implantation mask 105. As a result, p + A contact region 27 is formed. + After the step of forming the mold contact region 27, the ion implantation mask 105 is removed.

[0281] A process for forming a p-type well region 25 (see FIG. 21B), + The step of forming the p-type source region 26 (see FIG. 21C) and + The steps of forming the mold contact region 27 (see FIG. 21C) may be performed in any order and are not limited to the above order.

[0282] 21E, a base insulating layer 107 that serves as a base for gate insulating layer 32 is formed on first main surface 3 of semiconductor layer 2. Base insulating layer 107 may be formed by thermal oxidation treatment or CVD (Chemical Vapor Deposition). Base insulating layer 107 may contain silicon oxide.

[0283] Next, a base electrode layer 108 that serves as a base for the gate electrode layer 33 is formed on the base insulating layer 107. The base electrode layer 108 may be formed by a CVD method. The base electrode layer 108 may include polysilicon.

[0284] Next, a top base insulating layer 109 that serves as a base for the top insulating layer 79 is formed on the base electrode layer 108. The top base insulating layer 109 may be formed by a CVD method. The top base insulating layer 109 may contain silicon nitride.

[0285] 21F, a resist mask 110 having a predetermined pattern is formed on top base insulating layer 109. Resist mask 110 selectively covers the region where gate electrode layer 33 is to be formed.

[0286] 21G, unnecessary portions of top surface base insulating layer 109 and base electrode layer 108 are removed. The unnecessary portions of top surface base insulating layer 109 and base electrode layer 108 may be removed by etching via resist mask 110. The etching may be a dry etching method such as RIE (Reactive Ion Etching). As a result, gate electrode layer 33 and top surface insulating layer 79 are formed.

[0287] 21H, unnecessary portions of the top surface base insulating layer 109 are removed. The unnecessary portions of the top surface base insulating layer 109 may be removed by etching using a resist mask 110. The etching may be a dry etching method such as an RIE method. As a result, the gate insulating layer 32 is formed.

[0288] 21I, the surface portion of the first main surface 3 of the semiconductor layer 2 exposed from the gate insulating layer 32 is selectively removed. Unnecessary portions of the first main surface 3 of the semiconductor layer 2 may be removed by etching using a resist mask 110. The etching may be a dry etching method such as an RIE method.

[0289] The unnecessary portion of the first main surface 3 of the semiconductor layer 2 is n + The unnecessary portion of the first main surface 3 of the semiconductor layer 2 may be removed until a region where the n-type impurity concentration reaches a peak value (maximum value) is exposed in the n-type source region 26. + The n-type contact region 27 may be removed until a region where the n-type impurity concentration reaches a peak value (maximum value) is exposed.

[0290] In this step, a region located directly below the gate electrode layer 33 in the surface layer portion of the first main surface 3 of the semiconductor layer 2 is removed together with the gate insulating layer 32. As a result, the recessed portion 71 is formed, and at the same time, the gate electrode layer 33 including the main body portion 76 and the protruding portion 77 is formed on the gate insulating layer 32.

[0291] Furthermore, in this step, the surface roughness Zr of the bottom wall 73 of the recessed portion 71 becomes equal to or greater than the surface roughness Zs of the first main surface 3 of the semiconductor layer 2 due to the effect of dry etching.

[0292] The structure of the recessed portion 71 and the structure of the gate electrode layer 33 are as described above, and therefore a detailed description thereof will be omitted. After the recessed portion 71 is formed, the resist mask 110 is removed.

[0293] 21J, an insulating film 81 is formed on the first main surface 3 of the semiconductor layer 2. The insulating film 81 may be formed by a CVD method. The insulating film 81 may contain USG (Undoped Silica Glass). The insulating film 81 is formed to fill the space between the protruding portion 77 of the gate electrode layer 33 and the bottom wall 73 of the recessed portion 71 and to cover the gate electrode layer 33.

[0294] 21K, an insulating film 82 is formed on the insulating film 81. The insulating film 82 may be formed by a CVD method. The insulating film 82 contains an insulating material having properties different from the insulating material of the insulating film 81. The insulating film 82 may contain PSG (Phosphosilicate Glass). The insulating films 81 and 82 form the insulating layer 34.

[0295] 21L, a resist mask 111 having a predetermined pattern is formed on the insulating film 82. The resist mask 111 selectively exposes regions where contact holes (not shown) for the gate electrode 10 and contact holes 35 for the source electrode 11 are to be formed.

[0296] 21M, unnecessary portions of insulating film 82 and insulating film 81 are removed. The unnecessary portions of insulating film 82 and insulating film 81 are removed by etching via resist mask 111.

[0297] The etching method may be a dry etching method such as an RIE method, etc. As a result, a contact hole (not shown) for the gate electrode 10 and a contact hole 35 for the source electrode 11 are formed.

[0298] 21N, a heat treatment is performed on the insulating films 81 and 82. This improves the film-forming properties and strength of the insulating films 81 and 82.

[0299] At the same time, the corners of the insulating film 81 and the corners of the insulating film 82 are rounded. The specific shapes of the insulating film 81 and the insulating film 82 are as described above, and therefore a detailed description thereof will be omitted.

[0300] 21O, an electrode layer 91 serving as a base for the gate electrode 10 and the source electrode 11 is formed on the first main surface 3 of the semiconductor layer 2. In the step of forming the electrode layer 91, first, a first barrier electrode film 93 containing Ti is formed (also see FIG. 19).

[0301] The first barrier electrode film 93 may be formed by sputtering. The first barrier electrode film 93 is formed in a film shape along the first main surface 3 of the semiconductor layer 2 (the bottom wall 73 of the recessed portion 71) and the outer surface of the insulating layer 34.

[0302] Next, a second barrier electrode film 94 containing TiN is formed on the first barrier electrode film 93 (see also FIG. 19). The second barrier electrode film 94 may be formed by sputtering. The second barrier electrode film 94 is formed in a film shape along the surface of the first barrier electrode film 93.

[0303] 21P, an electrode layer 92 serving as a base for the gate electrode 10 and the source electrode 11 is formed on the electrode layer 91. The electrode layer 92 may contain aluminum. The electrode layer 92 may be formed by electrolytic plating (more specifically, electrolytic aluminum plating).

[0304] Next, the electrode layer 91 and the electrode layer 92 are collectively patterned to form the gate electrode 10 and the source electrode 11. Thereafter, the drain electrode 23 is formed on the second main surface 4 of the semiconductor layer 2. Through the steps including those described above, the semiconductor device 61 is formed.

[0305] 22 is a cross-sectional view of a portion corresponding to FIG. 19, that is, a cross-sectional view of a semiconductor device 121 according to a fifth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 61 are given the same reference numerals and descriptions thereof will be omitted.

[0306] Referring to Figure 22, p + The contact region 27 includes a first region 29 and a second region 30, similar to the semiconductor device 1. + The first region 29 of the p-type contact region 27 is formed in the p-type well region 25. + The second region 30 of the contact region 27 is n-type from the first region 29. - The diode region 24 is connected to the semiconductor substrate 10.

[0307] n - In this embodiment, the p-type diode region 24 + The second region 30 of the contact region 27 is defined as n - In this embodiment, the lengths L3 and L4 of the sides of the diode region 24 are + This corresponds to the size of the area surrounded by the second region 30 of the mold contact region 27.

[0308] p + The second region 30 of the contact region 27 is connected to the p-type well region 25 and the n-type well region 26. - The p-type diode region 24 is located at the boundary of the p-type diode region 24. + The second region 30 of the contact region 27 is - A pn junction is formed between the pn junction and the pn junction. + The contact region 27 is the anode, and the n - A second diode 31 is formed with the diode region 24 (drain electrode 23) as the cathode.

[0309] The JBS structure of each unit cell 15 is, in this form, n - In addition to the first pn junction formed between the p-type diode region 24 and the p-type well region 25, - type diode region 24 and p + A second pn junction is formed between the second regions 30 of the contact regions 27 .

[0310] As described above, according to the semiconductor device 121, the unit cell 15 has a JBS structure including the first pn junction and the second pn junction. Therefore, the first depletion layer extending from the first pn junction forms the n - This can suppress current concentration and electric field concentration in the pn-type diode region 24. In addition, the second depletion layer extending from the second pn junction also - This can suppress current concentration and electric field concentration in the diode region 24.

[0311] In particular, the second pn junction is - type diode region 24 and p+ The second depletion layer is formed in the boundary region between the second region 30 of the n-type contact region 27. This ensures that the second depletion layer can be expanded from the second pn junction. - This makes it possible to appropriately suppress current concentration and electric field concentration in the diode region 24.

[0312] 23 is a plan view showing a part of the device formation region 6, that is, a plan view of a semiconductor device 131 according to a sixth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 61 are given the same reference numerals and descriptions thereof will be omitted.

[0313] As shown in FIG. 23, in this embodiment, the plurality of unit cells 15 includes a plurality of unit cells 15A having a relatively large aspect ratio L2 / L1 and a plurality of unit cells 15B having a relatively small aspect ratio L2 / L1.

[0314] The plurality of unit cells 15A preferably extend in a strip shape along the second direction Y, i.e., the <11-20> direction. The aspect ratio L2 / L1 of the plurality of unit cells 15A is 2. In other words, the unit cell 15 shown in FIG. 11 is applied as the plurality of unit cells 15A.

[0315] Such a structure can suppress localized electric field concentration on the unit cell 15A, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1. The unit cells 15A are formed in a staggered arrangement in a planar view, instead of a matrix arrangement in a planar view.

[0316] The aspect ratio L2 / L1 of the plurality of unit cells 15B is less than "2." The plurality of unit cells 15B are formed along the periphery of the device formation region 6. The plurality of unit cells 15B may be formed in an area defined by the periphery of the device formation region 6 and the plurality of unit cells 15A.

[0317] As described above, the semiconductor device 131 can also achieve the same effects as those described for the semiconductor device 61. Furthermore, the plurality of unit cells 15B are formed in an area defined by the periphery of the device formation region 6 and the plurality of unit cells 15A. This allows the plurality of unit cells 15A, 15B to be formed efficiently within the device formation region 6, thereby appropriately increasing the current path.

[0318] 24 is a plan view showing a part of the device formation region 6, that is, a plan view of a semiconductor device 141 according to a seventh embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 61 are given the same reference numerals and descriptions thereof will be omitted.

[0319] 24, the unit cells 15 are arranged so as to be connected to each other along the second direction Y, i.e., the <11-20> direction, so that the unit cells 15 (two or more) form one linear cell 53 extending in a strip shape along the second direction Y.

[0320] A plurality of linear cells 53 may be arranged at intervals along the first direction X. Fig. 14 shows a structure in which the unit cell 15 shown in Fig. 11 has an aspect ratio L2 / L1 of "2". Such a structure can suppress localized electric field concentration on the linear cells 53, which is effective in suppressing a decrease in the breakdown voltage of the semiconductor device 1.

[0321] A plurality of n adjacent to each other along the second direction Y - Between the n-type diode regions 24, the p-type well regions 25 of one and / or the other unit cells 15 adjacent to each other along the second direction Y are interposed. - The semiconductor device has a structure in which the diode regions 24 are arranged at intervals from each other along the second direction Y.

[0322] As described above, the semiconductor device 141 can also achieve the same effects as those described for the semiconductor device 61.

[0323] 25 is a plan view of a semiconductor device 151 according to an eighth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 61 will be given the same reference numerals and descriptions thereof will be omitted.

[0324] 25, in a semiconductor device 151, a gate electrode 10 includes a gate pad 12, a gate finger 13, and a plurality of (four in this embodiment) gate lines 62A, 62B, 62C, and 62D.

[0325] The gate pad 12 is formed in a central portion of the first main surface 3 of the semiconductor layer 2 in a plan view. In this embodiment, the gate pad 12 is formed in a quadrangular shape having four side surfaces 12A, 12B, 12C, and 12D parallel to the side surfaces 5A, 5B, 5C, and 5D of the semiconductor layer 2 in a plan view.

[0326] The gate fingers 13 are formed in a strip shape extending along the periphery of the device formation region 6 in the outer region 7. In this embodiment, the gate fingers 13 are formed in an endless shape (quadratic ring shape) surrounding the device formation region 6 in a plan view. The gate fingers 13 may be formed so as to partition the device formation region 6 from three directions.

[0327] The plurality of gate lines 62A to 62D are each drawn out from the side surfaces 12A to 12D of the corresponding gate pads 12 toward the side surfaces 5A to 5D of the semiconductor layer 2. The plurality of gate lines 62A to 62D are each formed in a strip shape extending in a straight line toward the side surfaces 5A to 5D of the semiconductor layer 2.

[0328] More specifically, the multiple gate lines 62A to 62D include a gate line 62A drawn from the side 12A of the gate pad 12, a gate line 62B drawn from the side 12B of the gate pad 12, a gate line 62C drawn from the side 12C of the gate pad 12, and a gate line 62D drawn from the side 12D of the gate pad 12.

[0329] In this embodiment, the gate line 62A of the multiple gate lines 62A to 62D is connected to the gate finger 13. As a result, a C-shaped region is defined in the device formation region 6 by the inner edge of the gate electrode 10 in plan view.

[0330] The source electrode 11 is formed in a C-shaped region defined by the inner edge of the gate electrode 10. In this embodiment, the source electrode 11 is formed in a C-shape that follows the inner edge of the gate electrode 10.

[0331] FIG. 26 is a plan view in which the gate electrode 10 and the source electrode 11 are removed from FIG. 25, and is a view for explaining the structure on the first main surface 3 of the semiconductor layer 2. In FIG.

[0332] On the first main surface 3 of the semiconductor layer 2, a gate pad layer 63, a gate finger layer 64, and a plurality of (four in this embodiment) gate line layers 65A, 65B, 65C, and 65D are formed.

[0333] The gate pad layer 63 is formed in a region directly below the gate pad 12. The gate pad layer 63 is electrically connected to the gate pad 12. Although not shown, the gate pad 12 is electrically connected to the gate pad layer 63 via a contact hole formed in the insulating layer 34.

[0334] The gate pad layer 63 is formed in a central portion of the first main surface 3 of the semiconductor layer 2 in a plan view. In this embodiment, the gate pad layer 63 is set to a quadrangular shape having four side surfaces 63A, 63B, 63C, and 63D parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

[0335] The gate finger layer 64 is formed in a region directly below the gate finger 13. The gate finger layer 64 is electrically connected to the gate finger 13. Although not shown, the gate finger 13 is electrically connected to the gate finger layer 64 via a contact hole formed in the insulating layer 34.

[0336] The gate finger layer 64 is drawn out in a strip shape from the gate pad layer 63 so as to follow the periphery of the device formation region 6. In this embodiment, the gate finger layer 64 is formed in an endless shape (quadratic ring shape) surrounding the device formation region 6 in a plan view. The gate finger layer 64 may be formed so as to partition the device formation region 6 from three directions.

[0337] The gate line layers 65A to 65D are formed in regions directly below the gate lines 62A to 62D, respectively. The gate line layers 65A to 65D are electrically connected to the corresponding gate lines 62A to 62D. Although not shown, the gate lines 62A to 62D are electrically connected to the gate line layers 65A to 65D via contact holes formed in the insulating layer 34.

[0338] Each of the plurality of gate line layers 65A to 65D is drawn out from the side surface 63A to 63D of the corresponding gate pad layer 63 toward the side surface 5A to 5D of the semiconductor layer 2. Each of the plurality of gate line layers 65A to 65D is formed in a strip shape extending in a straight line toward the side surface 5A to 5D of the semiconductor layer 2.

[0339] More specifically, the multiple gate line layers 65A to 65D include a gate line layer 65A drawn from a side surface 63A of the gate pad layer 63, a gate line layer 65B drawn from a side surface 63B of the gate pad layer 63, a gate line layer 65C drawn from a side surface 63C of the gate pad layer 63, and a gate line layer 65D drawn from a side surface 63D of the gate pad layer 63.

[0340] In this embodiment, the gate line layer 65A of the multiple gate line layers 65A to 65D is connected to the gate finger layer 64. As a result, a C-shaped region is defined in the device formation region 6 by the inner edge of the gate electrode 10 in plan view.

[0341] A gate electrode layer 33 (planar gate structure) is formed in a C-shaped region defined by the gate pad layer 63, the gate finger layer 64, and the plurality of gate line layers 65A to 65D.

[0342] The gate electrode layer 33 is formed in a lattice shape in a plan view. In Fig. 26, the gate electrode layer 33 is shown by lattice lines. The gate electrode layer 33 is led out from a gate pad layer 63, a gate finger layer 64, and a plurality of gate line layers 65A to 65D.

[0343] As a result, the gate electrode layer 33 is electrically connected to the gate pad 12, the gate fingers 13 and the plurality of gate lines 62A to 62D via the gate pad layer 63, the gate finger layer 64 and the plurality of gate line layers 65A to 65D.

[0344] As described above, the semiconductor device 151 can also achieve the same effects as those described for the semiconductor device 61.

[0345] 27 is a cross-sectional view of a portion corresponding to FIG. 18, that is, a cross-sectional view of a semiconductor device 161 according to a ninth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 61 are given the same reference numerals and descriptions thereof will be omitted.

[0346] 27, in this embodiment, the source electrode 11 includes a nickel layer 162, a gold layer 163, and a solder layer 164 laminated in this order on the electrode layer 92. A palladium layer may be interposed in the region between the gold layer 163 and the solder layer 164.

[0347] Although not shown, the gate electrode 10 also includes a nickel layer 162, a gold layer 163, and a solder layer 164, which are stacked in this order on the electrode layer 92, similar to the source electrode 11. A palladium layer may be interposed in the region between the gold layer 163 and the solder layer 164.

[0348] As described above, the semiconductor device 161 can also achieve the same effects as those described for the semiconductor device 61.

[0349] Moreover, according to the semiconductor device 161, the gate electrode 10 and the source electrode 11 each include a solder layer 164. This allows the semiconductor device 161 to be mounted on a connection target with the first main surface 3 of the semiconductor layer 2 facing the connection target.

[0350] Fig. 28 is a plan view showing a part of the device formation region 6, and is a plan view of a semiconductor device 171 according to a tenth embodiment of the present invention. In Fig. 28, the cross-sectional view along line AA corresponds to the cross-sectional view shown in Fig. 18. In the following, structures corresponding to those described for the semiconductor device 61 are given the same reference numerals and will not be described again.

[0351] 28, in this embodiment, the unit cells 15 are formed in the shape of strips having ends extending along the second direction Y. In this embodiment, a plurality of unit cells 15 are formed at intervals along the first direction X.

[0352] As a result, the unit cells 15 are formed in a stripe pattern in a plan view. The areas between the adjacent unit cells 15 are partitioned by line portions 172 extending along the second direction Y. The line portions 172 correspond to the second line portions 17 of the semiconductor device 61 (see also FIG. 17).

[0353] Each unit cell 15, like the semiconductor device 61, has n - a p-type diode region 24, a p-type well region 25, an n + type source region 26 and p + The contact area 27 includes - a p-type diode region 24, a p-type well region 25, an n + type source region 26 and p + The mold contact regions 27 each extend in a strip shape with ends along the second direction Y in a plan view.

[0354] In this embodiment, the p-type well region 25 includes one p-type well region 25A and another p-type well region 25B. - The diode region 24 extends in a strip shape with ends along one end in the first direction X of the diode region 24 .

[0355] The other p-type well region 25B is n - The n-type diode region 24 extends in a strip shape with an end along the other end of the n-type diode region 24 in the first direction X. - In this embodiment, the p-type diode region 24 is defined by one p-type well region 25A and the other p-type well region 25B.

[0356] n + The n-type source regions 26 are formed in the surface layer of each p-type well region 25. + The n-type source regions 26 are formed at intervals from the inner and outer peripheries of the p-type well region 25. + The source region 26 extends in a strip shape with ends along the p-type well region 25 in plan view.

[0357] p + The p-type contact regions 27 are formed in the surface layer of each p-type well region 25. + The p-type contact region 27 is formed in the surface layer of the p-type well region 25. - type diode region 24 and n + The p-type source regions 26 are formed in the region between the p-type source regions 26. + In this embodiment, the contact region 27 extends in a strip shape with ends along the p-type well region 25 in plan view.

[0358] As described above, the semiconductor device 171 can also achieve the same effects as those described for the semiconductor device 61.

[0359] In the semiconductor device 171, the width of the unit cell 15 along the first direction X can be adjusted to adjust electrical characteristics such as breakdown voltage. On the other hand, in the semiconductor device 61, the width of the unit cell 15 along both the first direction X and the second direction Y can be finely adjusted to adjust electrical characteristics. Therefore, it can be said that the semiconductor device 61 has a higher degree of freedom in design than the semiconductor device 171.

[0360] The structure of the semiconductor device 121 described above (see FIG. 22) may be applied to the semiconductor device 171. That is, the p + A mold contact region 27 may be applied to the semiconductor device 171 .

[0361] Although the embodiment of the present invention has been described above, the present invention can also be embodied in other forms.

[0362] In each of the above-described embodiments, the unit cells 15 may have a polygonal shape such as a triangular shape, a hexagonal shape, or an octagonal shape in plan view. Also, in each of the above-described embodiments, the unit cells 15 may have a circular or elliptical shape in plan view.

[0363] In each of the above-described embodiments, the n-type ferrite cores are formed in a polygonal shape such as a triangular shape, a hexagonal shape, or an octagonal shape in a plan view. - In the above-described embodiments, the n-type diode region 24 may be formed in a circular or elliptical shape in a plan view. - A diode region 24 may be formed.

[0364] In each of the above-described embodiments, the impurity region 19 is formed in the semiconductor layer 2(n - The epitaxial layer 22 may include a crystal defect region containing crystal defects selectively introduced into the epitaxial layer 22. The crystal defects may include lattice defects represented by interstitial atoms and atomic vacancies.

[0365] The crystal defect region is n -The n-type epitaxial layer 22 may have a crystal defect density N2 higher than the n-type impurity density N1 (n-type impurity density N1<crystal defect density N2).

[0366] In each of the above-described embodiments, the impurity region 19 may include a high resistance region. - The high resistance region may have a resistivity ρ2 higher than the resistivity ρ1 of the semiconductor layer 2(n-type epitaxial layer 22) (resistivity ρ1<resistivity ρ2). - Alternatively, the crystal defect region may be formed by a crystal defect region containing crystal defects selectively introduced into the epitaxial layer 22.

[0367] In each of the above-described embodiments, the semiconductor layer 2 may have a structure in which the impurity region 19 is not formed in the intersection 18.

[0368] In each of the above-described embodiments, the n-type semiconductor layer is made of silicon (Si) instead of the wide band gap semiconductor. + A type semiconductor substrate 21 may be applied.

[0369] In each of the above-described embodiments, the n-type semiconductor layer is made of silicon (Si) instead of the wide band gap semiconductor. - A type epitaxial layer 22 may be applied.

[0370] In each of the above-described embodiments, the semiconductor layer 2 is a n-type silicon nitride film manufactured by the FZ method. - In this case, the n-type semiconductor substrate may be included. - The n-type semiconductor substrate - A high resistance region (drift region) corresponding to the n-type epitaxial layer 22 is formed. In addition, by implanting n-type impurities into the second main surface 4 of the semiconductor layer 2, the aforementioned n + A low resistance region (drain region) corresponding to the type semiconductor substrate is formed.

[0371] In each of the above-described embodiments, the first direction X and the second direction Y are not limited to directions along the side surfaces 5A to 5D of the semiconductor layer 2. For example, in each of the above-described embodiments, the relationship between the first direction X and the second direction Y may be reversed. That is, the first direction X may be set to the <11-20> direction, and the second direction Y may be set to a direction perpendicular to the <11-20> direction.

[0372] In this case, the unit cells 15 are preferably arranged at intervals along the <11-20> direction. When the unit cells 15 are formed into a rectangular shape in a plan view, they are preferably formed into a rectangular shape extending along the <11-20> direction.

[0373] In each of the above-described embodiments, the first direction X and the second direction Y may be directions along the diagonal direction of the semiconductor layer 2. In this case, the unit cells 15 are preferably arranged at intervals along the <11-20> direction. When the unit cells 15 are formed into a rectangular shape in a plan view, they are preferably formed into a rectangular shape extending along the <11-20> direction.

[0374] In each of the above-described embodiments, a trench gate structure may be adopted instead of the planar gate structure. The trench gate structure may be formed along the first line portion 16 and the second line portion 17 so as to partition the unit cells 15.

[0375] The trench gate structure may include a gate electrode layer 33 embedded in a gate trench formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2, with a gate insulating layer 32 sandwiched therebetween. The sidewalls of the gate trench may be formed perpendicular to the first main surface 3 of the semiconductor layer 2. The gate trench may be formed in a tapered shape in cross section, with an opening area larger than the area of ​​the bottom wall.

[0376] The gate insulating layer 32 may be formed along the sidewalls and bottom wall of the gate trench so as to define a recessed space within the gate trench. The gate electrode layer 33 may be embedded in the recessed space defined by the gate insulating layer 32.

[0377] n - a portion of the p-type epitaxial layer 22, the p-type well region 25 and the n + The n-type source region 26 may be formed to face the gate electrode layer 33 with the gate insulating layer 32 interposed therebetween. - a part of the epitaxial layer 22 and the n + The portion sandwiched between the source regions 26 becomes the channel of the MISFET 9 .

[0378] In this way, even with a structure employing a trench gate structure, it is possible to achieve the same effects as those described in the above-described embodiments.

[0379] In each of the above embodiments, n + Instead of the p-type semiconductor substrate 21 + That is, in each of the above-described embodiments, an IGBT (Insulated Gate Bipolar Transistor), which is an example of an insulated gate transistor, may be formed in place of the MISFET 9.

[0380] In this case, the "source" of the MISFET 9 is read as the "emitter" of the IGBT, and the "drain" of the MISFET 9 is read as the "collector" of the IGBT.

[0381] This application corresponds to Patent Application No. 2017-011609 filed with the Japan Patent Office on January 25, 2017, the entire disclosure of which is incorporated herein by reference.

[0382] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0383] Below, examples of features extracted from this specification and drawings are presented.

[0384] [A1] A semiconductor device comprising: a unit cell including a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first conductivity type diode region formed in a surface layer portion of the first main surface of the semiconductor layer; a second conductivity type well region formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a first conductivity type region formed in a surface layer portion of the well region; a gate electrode layer facing the well region and the first conductivity type region with a gate insulating layer sandwiched therebetween; and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region and forming an ohmic junction with the first conductivity type region.

[0385] [A2] The semiconductor device described in A1, wherein the well region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the well region and the diode region.

[0386] [A3] The semiconductor device according to A1 or A2, wherein the well region surrounds the diode region in a plan view.

[0387] [A4] The semiconductor device according to any one of A1 to A3, wherein the unit cell includes a second conductivity type contact region formed in a region between the diode region and the first conductivity type region in a surface layer portion of the well region, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region.

[0388] [A5] The semiconductor device described in A4, wherein the contact region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the contact region and the diode region.

[0389] [A6] A semiconductor device according to any one of A1 to A5, wherein a plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a portion of the well region of each of the unit cells.

[0390] [A7] The semiconductor device according to A6, wherein the plurality of unit cells are arranged at intervals along an arbitrary first direction and a second direction intersecting the first direction.

[0391] [A8] The semiconductor device according to A7, wherein the plurality of unit cells are arranged in a matrix.

[0392] [A9] The semiconductor device according to A7, wherein the plurality of unit cells are arranged in a staggered pattern.

[0393] [A10] The semiconductor device according to A6, wherein the plurality of unit cells are arranged adjacent to each other in any one direction to form one linear cell.

[0394] [A11] The semiconductor device according to A10, wherein the linear cells are arranged at intervals along an intersecting direction intersecting the one direction.

[0395] [A12] The semiconductor device according to any one of A1 to A11, wherein the unit cell is formed in a quadrangular shape in a plan view.

[0396] [A13] The semiconductor device according to any one of A1 to A12, wherein the unit cell is formed in a rectangular shape in a plan view.

[0397] [A14] The semiconductor device according to any one of A1 to A13, wherein the unit cell has a first side and a second side extending in directions intersecting each other, and an aspect ratio of the unit cell defined as the ratio of the length of the second side to the length of the first side is 1 or more and 4 or less.

[0398] [A15] The semiconductor device according to any one of A1 to A14, wherein the ratio of the planar area of ​​the diode region to the planar area of ​​the unit cell is 0.005 or more and 0.01 or less.

[0399] [A16] The semiconductor device according to any one of A1 to A15, wherein the semiconductor layer includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the first main surface of the semiconductor layer is formed by the epitaxial layer, and the second main surface of the semiconductor layer is formed by the semiconductor substrate.

[0400] [A17] The semiconductor device according to A16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0401] [A18] The semiconductor device according to A16 or A17, wherein the epitaxial layer has a thickness of 20 μm or more.

[0402] [A19] A semiconductor device according to any one of A1 to A18, wherein the semiconductor layer has a device formation region and an outer region that is an area outside the device formation region, the unit cell is formed in the device formation region, and the ratio of the planar area of ​​the device formation region to the planar area of ​​the semiconductor layer is 70% or more.

[0403] [A20] The semiconductor device according to any one of A1 to A19, further including a second principal surface electrode covering the second principal surface of the semiconductor layer and forming an ohmic junction with the semiconductor layer.

[0404] [B1] A unit cell including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first conductivity type diode region formed in a surface layer portion of the first main surface of the semiconductor layer; a second conductivity type well region formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a first conductivity type region formed in the surface layer portion of the well region; a gate electrode layer facing the well region and the first conductivity type region with a gate insulating layer interposed therebetween and having a sidewall located on the first conductivity type region; an insulating layer covering the gate electrode layer; and a first main surface electrode electrically connected to the diode region and the first conductivity type region on the first main surface of the semiconductor layer. the first main surface of the semiconductor layer includes a recess portion recessed toward the second main surface side to expose at least a part of the first conductivity type region in a region located to a side of the gate electrode layer, the insulating layer including a first portion covering the recess portion to extend from the sidewall of the gate electrode layer along the recess portion, and a second portion covering the sidewall of the gate electrode layer to extend along the sidewall of the gate electrode layer, and a thickness of the first portion along a parallel direction parallel to the first main surface of the semiconductor layer is greater than a thickness of the second portion along the parallel direction.

[0405] [B2] The semiconductor device according to B1, wherein the well region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the well region and the diode region.

[0406] [B3] The semiconductor device according to B1 or B2, wherein the well region surrounds the diode region in a plan view.

[0407] [B4] The semiconductor device according to any one of B1 to B3, wherein the unit cell includes a second conductivity type contact region formed in a region between the diode region and the first conductivity type region in a surface layer portion of the well region, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region.

[0408] [B5] The semiconductor device described in B4, wherein the contact region forms a pn junction with the diode region, and the unit cell has a JBS (Junction Barrier Schottky) structure including the pn junction formed between the contact region and the diode region.

[0409] [B6] A semiconductor device according to any one of B1 to B5, wherein a plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a portion of the well region of each of the unit cells.

[0410] [B7] The semiconductor device according to B6, wherein the plurality of unit cells are arranged at intervals along an arbitrary first direction and a second direction intersecting the first direction.

[0411] [B8] The semiconductor device according to B7, wherein the plurality of unit cells are arranged in a matrix.

[0412] [B9] The semiconductor device according to B7, wherein the plurality of unit cells are arranged in a staggered pattern.

[0413] [B10] The semiconductor device according to B6, wherein the plurality of unit cells are arranged adjacent to each other in any one direction to form one linear cell.

[0414] [B11] The semiconductor device according to B10, wherein a plurality of the linear cells are arranged at intervals along an intersecting direction intersecting the one direction.

[0415] [B12] The semiconductor device according to any one of B1 to B11, wherein the unit cell is formed in a quadrangular shape in a plan view.

[0416] [B13] The semiconductor device according to any one of B1 to B12, wherein the unit cell is formed in a rectangular shape in a plan view.

[0417] [B14] The semiconductor device according to any one of B1 to B13, wherein the unit cell has a first side and a second side extending in directions intersecting each other, and an aspect ratio of the unit cell defined as the ratio of the length of the second side to the length of the first side is 1 or more and 4 or less.

[0418] [B15] The semiconductor device according to any one of B1 to B14, wherein the ratio of the planar area of ​​the diode region to the planar area of ​​the unit cell is 0.005 or more and 0.01 or less.

[0419] [B16] The semiconductor device according to any one of B1 to B15, wherein the semiconductor layer includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the first main surface of the semiconductor layer is formed by the epitaxial layer, and the second main surface of the semiconductor layer is formed by the semiconductor substrate.

[0420] [B17] The semiconductor device according to B16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0421] [B18] The semiconductor device according to B16 or B17, wherein the epitaxial layer has a thickness of 20 μm or more.

[0422] [B19] A semiconductor device according to any one of B1 to B18, wherein the semiconductor layer has a device formation region and an outer region that is an area outside the device formation region, the unit cell is formed in the device formation region, and the ratio of the planar area of ​​the device formation region to the planar area of ​​the semiconductor layer is 70% or more.

[0423] [B20] The semiconductor device according to any one of B1 to B19, further comprising a second principal surface electrode covering the second principal surface of the semiconductor layer and forming an ohmic junction with the semiconductor layer.

[0424] [C1] A unit cell including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first conductivity type diode region formed in a surface layer portion of the first main surface of the semiconductor layer; a second conductivity type well region formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a first conductivity type impurity region formed in the surface layer portion of the well region; a gate electrode layer facing the well region and the impurity region with a gate insulating layer interposed therebetween and having a sidewall located on the impurity region; an insulating layer covering the gate electrode layer; and a first main surface electrode electrically connected to the diode region and the impurity region on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region. the first main surface of the semiconductor layer includes a recessed portion recessed toward the second main surface so as to expose at least a part of the impurity region in a region located to a side of the gate electrode layer, the insulating layer including a first portion extending from the sidewall of the gate electrode layer in a horizontal direction along the first main surface and covering the recessed portion, and a second portion formed on an upper portion of the first portion so as to extend along the sidewall of the gate electrode layer and cover the sidewall of the gate electrode layer, and a distance (length) of the first portion in the horizontal direction based on the sidewall of the gate electrode layer is greater than a distance (length) of the second portion in the horizontal direction based on the sidewall of the gate electrode layer.

[0425] [C2] The semiconductor device according to C1, wherein the first portion is thicker than the gate insulating layer.

[0426] [C3] The semiconductor device according to C1 or C2, wherein the first portion extends in the horizontal direction from the sidewall of the gate electrode layer in a region closer to the first main surface than an upper end of the gate electrode layer.

[0427] [C4] The semiconductor device according to any one of C1 to C3, wherein the well region forms a pn junction with the diode region.

[0428] [C5] The semiconductor device according to any one of C1 to C4, wherein the well region surrounds the diode region in a plan view.

[0429] [C6] The semiconductor device according to any one of C1 to C5, wherein the unit cell includes a second conductivity type contact region formed in a region between the diode region and the impurity region in a surface layer portion of the well region, and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region.

[0430] [C7] The semiconductor device according to C6, wherein the contact region forms a pn junction with the diode region.

[0431] [C8] A semiconductor device according to any one of C1 to C7, wherein a plurality of the unit cells are formed in a surface layer portion of the first main surface of the semiconductor layer, and the gate electrode layer faces a portion of the well region of each of the unit cells.

[0432] [C9] The semiconductor device according to C8, wherein the plurality of unit cells are arranged at intervals in an arbitrary first direction and a second direction intersecting the first direction.

[0433] [C10] The semiconductor device according to C9, wherein the plurality of unit cells are arranged in a matrix or a staggered pattern.

[0434] [C11] The semiconductor device according to C8, wherein the plurality of unit cells are arranged adjacent to each other in any one direction to form one linear cell.

[0435] [C12] The semiconductor device according to C11, wherein the linear cells are arranged at intervals in an intersecting direction intersecting the one direction.

[0436] [C13] The semiconductor device according to any one of C1 to C12, wherein the unit cell is formed in a quadrangular shape in a plan view.

[0437] [C14] The semiconductor device according to any one of C1 to C13, wherein the unit cell has a first side and a second side extending in directions intersecting each other, and an aspect ratio of the unit cell defined as the ratio of the length of the second side to the length of the first side is 1 or more and 4 or less.

[0438] [C15] The semiconductor device according to any one of C1 to C14, wherein the ratio of the planar area of ​​the diode region to the planar area of ​​the unit cell is 0.005 or more and 0.01 or less.

[0439] [C16] The semiconductor device according to any one of C1 to C15, wherein the semiconductor layer has a layered structure including a semiconductor substrate and an epitaxial layer, the first main surface is formed by the epitaxial layer, and the second main surface is formed by the semiconductor substrate.

[0440] [C17] The semiconductor device according to C16, wherein the epitaxial layer has a thickness of 5 μm or more.

[0441] [C18] The semiconductor device according to C16 or C17, wherein the epitaxial layer has an impurity concentration lower than an impurity concentration of the semiconductor substrate.

[0442] [C19] The semiconductor device according to any one of C1 to C18, further including a device region set in the semiconductor layer and an outer region set in the semiconductor layer outside the device region, wherein the unit cell is formed in the device region.

[0443] [C20] The semiconductor device according to any one of C1 to C19, further comprising a second principal surface electrode covering the second principal surface of the semiconductor layer and forming an ohmic junction with the semiconductor layer.

[0444] [D1] A semiconductor device comprising: a unit cell including a semiconductor layer having a first main surface on one side and a second main surface on the other side; a well region of a second conductivity type formed in a surface layer portion of the first main surface; and an impurity region of a first conductivity type formed in the surface layer portion of the well region, the unit cell including a recess portion recessed toward the second main surface side in the surface layer portion; a gate electrode facing the well region with a gate insulating layer sandwiched therebetween; and a buried portion of an insulating material formed between the gate electrode and the well region so as to be sandwiched between the gate electrode and a bottom wall of the recessed portion, the buried portion being in contact with the gate insulating layer, and having a thickness greater than a thickness of the gate insulating layer. Provided is a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a unit cell including a first conductivity type diode region formed in a surface layer portion of the first main surface of the semiconductor layer; a second conductivity type well region formed along a periphery of the diode region in the surface layer portion of the first main surface of the semiconductor layer; and a first conductivity type region formed in the surface layer portion of the well region; a gate electrode layer facing the well region and the first conductivity type region across a gate insulating layer; and a first main surface electrode covering the diode region and the first conductivity type region on the first main surface of the semiconductor layer, forming a Schottky junction with the diode region and forming an ohmic junction with the first conductivity type region.

[0445] [D2] The semiconductor device according to D1, wherein the impurity region is formed on the bottom wall of the recessed portion.

[0446] [D3] The semiconductor device according to D1 or D2, wherein the depth of the recess is 0.5 m or more and 5 m or less.

[0447] [D4] The semiconductor device according to any one of D1 to D3, wherein the semiconductor layer has a laminated structure including a semiconductor substrate on the second main surface side and an epitaxial layer on the first main surface side.

[0448] [D5] The semiconductor device according to D4, wherein the epitaxial layer has a thickness of 5 μm or more.

[0449] [D6] The semiconductor device according to D5, wherein the epitaxial layer has a thickness of 20 μm or more.

[0450] [D7] The semiconductor device according to D5, wherein the epitaxial layer has a thickness of 5 μm or more and 30 μm or less.

[0451] [D8] A semiconductor device according to any one of D1 to D7, wherein the unit cell includes a second conductivity type contact region formed in a surface layer portion of the well region and having a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the well region.

[0452] [D9] comprising a plurality of the unit cells, The semiconductor device according to any one of D1 to D8, wherein the plurality of unit cells are arranged in a matrix.

[0453] [D10] a plurality of said unit cells; The semiconductor device according to any one of D1 to D8, wherein the plurality of unit cells are arranged in a staggered pattern.

[0454] [D11] further including an insulating layer formed on the first major surface of the semiconductor layer; The semiconductor device according to any one of D1 to D10, wherein the embedded portion forms a part of the insulating layer.

[0455] [D12] The semiconductor device according to D11, wherein the insulating layer covers the gate electrode.

[0456] [D13] The semiconductor device according to D12, further comprising a first main surface electrode formed on the insulating layer and electrically connected to the impurity region.

[0457] [D14] The semiconductor device of D13, further comprising a second main surface electrode covering the second main surface.

[0458] [D15] the first principal surface electrode is a source electrode, The semiconductor device according to D14, wherein the second principal surface electrode is a drain electrode. [Explanation of symbols]

[0459] 1. Semiconductor device 2. Semiconductor layer 3. First principal surface of semiconductor layer 4. Second principal surface of semiconductor layer 6 Device formation area 7 Outer area 8 SBD 9. MISFETs 11 Source electrode (main surface electrode) 15 unit cells 21n + semiconductor substrate 22n - Type epitaxial layer 24n - Type diode region 25 p-type well region 26n + Type source region (first conductivity type region) 27 pages + Mold contact area 32 Gate insulating layer 33 gate electrode layer 51 Semiconductor devices 52 Semiconductor Devices 60 Linear Cells 61 Semiconductor devices 121 Semiconductor devices 131 Semiconductor devices 141 Semiconductor devices 151 Semiconductor devices 161 Semiconductor devices L1 length of the unit cell L2 length of the unit cell SE: Planar area of ​​the first principal surface of the semiconductor layer Planar area of ​​SF device formation area SC unit cell planar area SD n -Planar area of ​​the diode region

Claims

1. a semiconductor layer having a first major surface on one side and a second major surface on the other side; a unit cell including a well region of a second conductivity type formed in a surface layer portion of the first main surface and an impurity region of a first conductivity type formed in a surface layer portion of the well region, the unit cell having a recess portion formed in the surface layer portion that is recessed toward the second main surface; a gate electrode facing the well region with a gate insulating layer interposed therebetween; a buried portion of insulating material formed between the gate electrode and the well region so as to be sandwiched between the gate electrode and a bottom wall of the recessed portion, and extending to below the gate electrode; the buried portion is in contact with the gate insulating layer, The semiconductor device, wherein the buried portion has a thickness greater than a thickness of the gate insulating layer.

2. 2. The semiconductor device according to claim 1, wherein said impurity region is formed on a bottom wall of said recessed portion.

3. 3. The semiconductor device according to claim 1, wherein the depth of the recessed portion is not less than 0.5 m and not more than 5 m.

4. 4. The semiconductor device according to claim 1, wherein the semiconductor layer has a laminated structure including a semiconductor substrate on the second main surface side and an epitaxial layer on the first main surface side.

5. 5. The semiconductor device according to claim 4, wherein said epitaxial layer has a thickness of 5 [mu]m or more.

6. 6. The semiconductor device according to claim 5, wherein said epitaxial layer has a thickness of 20 [mu]m or more.

7. 6. The semiconductor device according to claim 5, wherein the epitaxial layer has a thickness of 5 [mu]m or more and 30 [mu]m or less.

8. 8. The semiconductor device according to claim 1, wherein the unit cell includes a second conductivity type contact region formed in a surface layer portion of the well region and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the well region.

9. a plurality of said unit cells; 9. The semiconductor device according to claim 1, wherein the plurality of unit cells are arranged in a matrix.

10. a plurality of said unit cells; 9. The semiconductor device according to claim 1, wherein the plurality of unit cells are arranged in a staggered pattern.

11. further including an insulating layer formed on the first major surface of the semiconductor layer; 11. The semiconductor device according to claim 1, wherein the buried portion forms a part of the insulating layer.

12. The semiconductor device according to claim 11 , wherein the insulating layer covers the gate electrode.

13. 13. The semiconductor device according to claim 12, further comprising a first main surface electrode formed on said insulating layer and electrically connected to said impurity region.

14. The semiconductor device according to claim 13 , further comprising a second principal surface electrode covering said second principal surface.

15. the first principal surface electrode is a source electrode, The semiconductor device according to claim 14 , wherein the second principal surface electrode is a drain electrode.

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