Semiconductor Devices

Abstract

To provide a semiconductor device that shifts the level of a negative voltage and / or a positive voltage.SOLUTION: A semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor and the output terminal. A second terminal of the second transistor is electrically connected to a first terminal of the third transistor. A first terminal of the fourth transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor. A second terminal of the first capacitor is electrically connected to the input terminal. The first transistor, the second transistor, the third transistor, and the fourth transistor have the same polarity.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, there has been a strong demand for electronic devices to consume less power during operation. For example, in order to reduce the power consumption of electronic devices, efforts have been made to reduce the power consumption of individual logic circuits included in the electronic devices.

[0004] Logic circuits can be classified into, for example, static logic circuits, dynamic logic circuits, and pseudo logic circuits. Dynamic logic circuits operate by temporarily storing data, so compared to static logic circuits, transistor leakage current is a problem. If the transistor leakage current is large, the data stored in the dynamic logic circuit will be destroyed. Leakage current is caused in part by the off-current that flows when the transistor is in the off state. For example, Patent Documents 1 and 2 disclose that the leakage current of a dynamic logic circuit can be reduced by providing a transistor whose channel is formed of an oxide semiconductor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-9311 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-9313 Summary of the Invention [Problem to be solved by the invention]

[0006] In some cases, the manufacturing process of a semiconductor device can be shortened by using the same material for the channel formation regions of multiple transistors in the semiconductor device. Specifically, for example, a metal oxide containing indium, gallium, zinc, or the like can be used as the material.

[0007] However, while n-type semiconductors can be fabricated using metal oxides containing indium (e.g., In oxide) or metal oxides containing zinc (e.g., Zn oxide), fabrication of p-type semiconductors is difficult due to mobility and reliability considerations. Therefore, when fabricating a semiconductor device, it is preferable to use a unipolar circuit composed of transistors containing n-type semiconductors (n-channel transistors). However, because such unipolar circuits do not include transistors containing p-type semiconductors (p-channel transistors), the circuit area tends to be large, unlike CMOS circuits.

[0008] Let us now consider a case where a level shifter (called a negative voltage level shifter) that shifts the input potential to a lower potential, VSSL, is configured as a unipolar circuit including an n-channel transistor. When VSSL is input to the source of the n-channel transistor and the input signal VSS is input to the gate, the gate-source voltage of the n-channel transistor may become higher than the threshold voltage, causing the n-channel transistor not to turn off. If the n-channel transistor does not turn off, the negative voltage level shifter will have a circuit configuration in which a steady current flows, which may increase power consumption.

[0009] Furthermore, it is preferable that the level shifter has not only the function of a negative voltage level shifter but also the function of a positive voltage level shifter that shifts the input potential to a higher potential. Furthermore, it is preferable that the level shifter has a circuit configuration that functions only as either a negative voltage level shifter or a positive voltage level shifter depending on the situation.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage, or to provide a semiconductor device with reduced power consumption, or to provide a semiconductor device with a reduced circuit area.

[0011] Another object of one embodiment of the present invention is to provide a novel semiconductor device, or an object of one embodiment of the present invention is to provide an imaging device including the semiconductor device.

[0012] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the output terminal. The second terminal of the second transistor is electrically connected to the first terminal of the third transistor. The first terminal of the fourth transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitor, and the second terminal of the first capacitor is electrically connected to the input terminal. Note that the first transistor, the second transistor, the third transistor, and the fourth transistor may each be transistors of the same polarity.

[0014] (2) Alternatively, in one aspect of the present invention, in the above-mentioned (1), when a first potential is input to the input terminal, a second potential is input to the second terminal of the first transistor, and a third potential is input to the second terminal of the third transistor and the second terminal of the fourth transistor, it is preferable that the first transistor has a function of precharging the output terminal to the second potential when the first transistor is on, and it is preferable that the second transistor has a function of turning on or off depending on the first potential input to the input terminal when the fourth transistor is off.Furthermore, it is preferable that the semiconductor device has a function of setting the potential of the output terminal to the second potential or the third potential by precharging the output terminal to the second potential and turning on the third transistor after the first transistor turns off.

[0015] (3) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. The first terminal of the first transistor is electrically connected to the first terminal of the third transistor and the output terminal, the second terminal of the third transistor is electrically connected to the first terminal of the second transistor, the first terminal of the fourth transistor is electrically connected to a gate of the second transistor and the first terminal of the first capacitor, and the second terminal of the first capacitor is electrically connected to the input terminal. A first potential may be input to the input terminal. Note that the first transistor, the second transistor, the third transistor, and the fourth transistor may be transistors of the same polarity.

[0016] (4) Alternatively, in one aspect of the present invention, in the configuration (3) above, when a first potential is input to the input terminal, a second potential is input to the second terminal of the first transistor, and a third potential is input to the second terminal of the second transistor and the second terminal of the fourth transistor, it is preferable that the first transistor has a function of precharging the output terminal to the second potential when the first transistor is on, and it is preferable that the second transistor has a function of turning on or off depending on the first potential input to the input terminal when the fourth transistor is off. Furthermore, it is preferable that the semiconductor device has a function of setting the potential of the output terminal to the second potential or the third potential by turning on the third transistor after the output terminal is precharged to the second potential and the first transistor is turned off.

[0017] (5) Alternatively, one embodiment of the present invention may be a semiconductor device having the structure of (1) or (4) above, which further includes a second capacitor, wherein a first terminal of the second capacitor is electrically connected to a first terminal of the first transistor, a first terminal of the second transistor, and an output terminal.

[0018] (6) Alternatively, in one embodiment of the present invention, in any one of the above structures (1) to (5), each of the first to fourth transistors may include metal oxide or silicon in a channel formation region.

[0019] (7) Alternatively, in one aspect of the present invention, in any one of the configurations (1) to (6) above, the first capacitor may include a fifth transistor. The fifth transistor has a channel formation region made of metal oxide or silicon. The gate of the fifth transistor functions as one of the first terminal and the second terminal of the first capacitor, and the first terminal and the second terminal of the fifth transistor function as the other of the first terminal and the second terminal of the first capacitor.

[0020] (8) Another embodiment of the present invention is an imaging device including the semiconductor device according to any one of (1) to (7) above and a photoelectric conversion element, wherein the photoelectric conversion element is preferably located above the first to fourth transistors.

[0021] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package or the like are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0022] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0023] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0024] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0025] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0026] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0028] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0029] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0030] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0031] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0032] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0033] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0037] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in defect level density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding hydrogen, and oxygen.

[0042] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided.

[0047] According to one embodiment of the present invention, a novel semiconductor device can be provided, or an imaging device including the semiconductor device can be provided.

[0048] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a timing chart showing an example of the operation of the semiconductor device. [Figure 3] FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 4] FIG. 4A is a circuit diagram showing an example of the configuration of a capacitor, and FIG. 4B is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 5] FIG. 5 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 8] 8A to 8C are cross-sectional views showing examples of the structure of a transistor. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 11] 11A and 11B are cross-sectional views showing examples of the structure of a transistor. [Figure 12] 12A and 12B are cross-sectional views showing examples of the structure of a transistor. [Figure 13] FIG. 13A is a top view showing an example of the configuration of a capacitor, and FIGS. 13B and 13C are cross-sectional perspective views showing the example of the configuration of a capacitor. [Figure 14] FIG. 14A is a top view showing an example of the configuration of a capacitor, FIG. 14B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 14C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 15] FIG. 15 is a cross-sectional view showing a configuration example of an imaging device. [Figure 16] FIG. 16 is a cross-sectional view showing a configuration example of an imaging device. [Figure 17] FIG. 17A is a diagram illustrating the classification of IGZO crystal structures, FIG. 17B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 17C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 18] FIG. 18A is a perspective view showing an example of a semiconductor wafer, FIG. 18B is a perspective view showing an example of a chip, and FIGS. 18C and 18D are perspective views showing an example of an electronic component. [Figure 19] 19A to 19F are perspective views of a package and a module that house an imaging device. [Figure 20] FIG. 20 is a perspective view illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0050] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply "OSs"). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when a metal oxide is referred to as an OS FET or an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0051] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0052] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0053] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0054] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0055] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0056] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0057] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0058] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0059] (Embodiment 1) In this embodiment, a level shifter, which is a semiconductor device of one embodiment of the present invention, will be described.

[0060] Note that the level shifter in this specification and the like refers to a potential level conversion circuit that converts an input voltage level to another voltage level. In this case, the other voltage may be lower or higher than the input voltage. Note that, depending on the input voltage, a voltage equal to the input voltage may be output without level shifting. For example, the level shifter in this specification and the like may have a function of level-shifting an input high-level potential to a first potential and level-shifting an input low-level potential to a second potential. Note that the first potential may be a potential higher than the high-level potential, a high-level potential, or a potential lower than the high-level potential, and the second potential may be a potential higher than the low-level potential, a low-level potential, or a potential lower than the low-level potential. Therefore, for example, the level shifter in this specification and the like may have a function of level-shifting one of the input high-level potential or low-level potential to a potential higher than the high-level potential and level-shifting the other of the input high-level potential or low-level potential to a potential lower than the low-level potential.

[0061] A level shifter, which is a semiconductor device according to one embodiment of the present invention, is a circuit using the architecture of a dynamic logic circuit. The dynamic logic circuit is, for example, a circuit that is driven by operations including temporarily holding data, precharging a potential, and evaluating the potential.

[0062] 1 shows an example of the configuration of the level shifter 100. The level shifter 100 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitor C1, and a capacitor CL.

[0063] For example, the transistors Tr1 to Tr4 are preferably OS transistors. In addition, the channel formation regions of the transistors Tr1 to Tr4 are more preferably oxides containing at least one of indium, gallium, and zinc. Alternatively, instead of the oxides, oxides containing at least one of indium, an element M (e.g., aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) and zinc may be used. The transistors Tr1 to Tr4 preferably have the structure of the transistor described in Embodiment 2.

[0064] Alternatively, the transistors Tr1 to Tr4 may be transistors having silicon in their channel formation regions (referred to as Si transistors in this specification), for example. As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like can be used.

[0065] Alternatively, the transistors Tr1 to Tr4 may be, other than OS transistors and Si transistors, transistors whose channel formation region includes Ge or the like, transistors whose channel formation region includes a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe, transistors whose channel formation region includes carbon nanotubes, transistors whose channel formation region includes an organic semiconductor, or the like.

[0066] The transistors Tr1 to Tr4 can be manufactured in the same process by using similar structures and materials (e.g., materials such as semiconductors, insulators, and conductors contained in channel formation regions), which shortens the manufacturing process of the level shifter 100. Note that the semiconductor device of one embodiment of the present invention is not limited thereto. For example, some of the transistors Tr1 to Tr4 may have different structures and materials. For example, the transistors Tr1, Tr3, and Tr4 may be OS transistors, and the transistor Tr2 may be a Si transistor.

[0067] 1, the back gates of the transistors Tr1 to Tr4 are illustrated, but the connection configuration of the back gates is not illustrated. However, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor Tr1 may be electrically connected, or the gate and the back gate of the transistor Tr2 may be electrically connected, or the gate and the back gate of the transistor Tr3 may be electrically connected, or the gate and the back gate of the transistor Tr4 may be electrically connected. For example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0068] The threshold voltages of the transistors Tr1 to Tr4 are V TH1 , V TH2 , V TH3 , V TH4 In addition, unless otherwise specified in this specification, VTH1 ~V TH4 Each of is a real number greater than 0.

[0069] 1 include back gates, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistors Tr1 to Tr4 shown in FIG. 1 may have a structure without a back gate, that is, a single-gate transistor. Some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0070] 1 are n-channel transistors, the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors Tr1 to Tr4 may be replaced with p-channel transistors.

[0071] The above-described examples of changes in the structure and polarity of the transistors are not limited to the transistors Tr1 to Tr4. For example, the same changes in the structure and polarity of the transistors may be made to the transistors described elsewhere in the specification or shown in other drawings.

[0072] Unless otherwise specified, the transistors Tr1 to Tr4 may operate in the saturation region when they are on. That is, when the transistors Tr1 to Tr4 are on, the gate voltages, source voltages, and drain voltages of the transistors Tr1 to Tr4 may be appropriately biased to voltages within the range in which they operate in the saturation region.

[0073] The first terminal of the transistor Tr1 is electrically connected to the wiring VDHE, the second terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr2 and the wiring BOTE, and the gate of the transistor Tr1 is electrically connected to the wiring PRCE. The second terminal of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr3, and the gate of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr4 and the first terminal of the capacitor C1. The second terminal of the transistor Tr3 is electrically connected to the wiring VLSE, and the gate of the transistor Tr3 is electrically connected to the wiring EVE. The second terminal of the transistor Tr4 is electrically connected to the wiring VLSE, and the gate of the transistor Tr4 is electrically connected to the wiring CLPE. The second terminal of the capacitor C1 is electrically connected to the wiring INE. The first terminal of the capacitor CL is electrically connected to the wiring BOTE, and the second terminal of the capacitor CL is electrically connected to the wiring VLSE.

[0074] The level shifter 100 also includes, for example, a memory unit AM. The memory unit AM includes, for example, a transistor Tr4 and a capacitor C1. In this specification and the like, an electrical connection point between the gate of the transistor Tr2, the first terminal of the capacitor C1, and the first terminal of the transistor Tr4 is referred to as a node FN.

[0075] The memory unit AM has a function of holding a potential at the node FN. Specifically, for example, when a high-level potential is input to the wiring CLPE and the transistor Tr4 is turned on, the memory unit AM brings the node FN and the wiring VLSE into a conductive state, and the potential of the node FN becomes the potential provided by the wiring VLSE. Here, when a low-level potential is input to the wiring CLPE and the transistor Tr4 is turned off, the memory unit AM can hold the potential provided by the wiring VLSE to the node FN.

[0076] The capacitor CL is provided to stabilize the output signal from the line BOTE. Specifically, for example, when a voltage is output to the line BOTE and the transistors Tr1 and Tr2 are in the off state, the capacitor CL can hold the voltage. On the other hand, if the capacitor CL is not provided, the voltage of the line BOTE may fluctuate due to leakage current from the transistors Tr1 and Tr2. For this reason, it is preferable that the level shifter 100 be provided with the capacitor CL. Note that if the output signal from the line BOTE does not undesirably change due to parasitic capacitance or the like, the level shifter 100 does not need to be provided with the capacitor CL.

[0077] The wiring VDHE functions as, for example, a wiring that applies a constant voltage. Note that this constant voltage is a high-level power supply voltage in the level shifter 100. In this specification and the like, this power supply voltage will be referred to as VDDH.

[0078] The wiring VLSE functions as a wiring that applies a constant voltage, for example. The constant voltage is a low-level power supply voltage in the level shifter 100. In this specification, the power supply voltage is referred to as VSSL. VSSL is a voltage lower than VDDH.

[0079] For example, the wiring INE is electrically connected to an input terminal of the level shifter 100, and functions as a wiring for applying an input voltage to the input terminal. For example, the input voltage may be a voltage output from a logic circuit or the like electrically connected to the level shifter 100 via the wiring INE. Note that the input voltage (output voltage of the logic circuit) may be, for example, a high-level potential or a low-level potential. In this specification, the high-level potential is referred to as VDD, and the low-level potential is referred to as VSS. It is assumed that VDD is a voltage higher than VSS and lower than VDDH. It is assumed that VSS is a voltage higher than VSSL.

[0080] In the level shifter 100, when the VDD input to the wiring INE is not level-shifted to VDDH, the constant voltage provided by the wiring VDHE may be set to VDDH=VDD. Alternatively, in the level shifter 100, when the VSS input to the wiring INE is not level-shifted to VSSL, the constant voltage provided by the wiring VLSE may be set to VSSL=VSS.

[0081] For example, the wiring PRCE functions as a wiring for controlling whether or not a potential is charged from the wiring VDHE to the wiring BOTE. Specifically, for example, the wiring PRCE is connected to a line TH1 Alternatively, it can be a wiring that supplies VSS. TH1 is the threshold voltage of the transistor Tr1. The high level potential given by the wiring PRCE is VDDH+V TH1 Alternatively, it can be VDDH, or VDDH+V TH1 The potential may be greater than .

[0082] The wiring EVE functions as a wiring for supplying an evaluation signal, for example. Specifically, for example, the wiring EVE is a wiring for supplying an evaluation signal. TH3 Alternatively, it can be a wiring that supplies VSS. TH3 is the threshold voltage of the transistor Tr3. The high-level potential given by the wiring EVE is VDDH+V TH3 Alternatively, it can be VDDH, or VDDH+V TH3 The high level potential given by the wiring EVE may be a potential exceeding V TH3 It may also be set to a higher potential below VDDH.

[0083] For example, the wiring CLPE functions as a wiring for controlling the switching between the on state and the off state of the transistor Tr4. Specifically, for example, the wiring CLPE can be a wiring for supplying VDD or VSSL. In addition, the high-level potential supplied by the wiring CLPE is not VDD but VDD+V. TH4 Or VDD+V TH4 It is also possible to set the potential to exceed V TH4is the threshold voltage of transistor Tr4.

[0084] For example, the wiring BOTE is electrically connected to the input terminal of the level shifter 100, and functions as a wiring that outputs the output voltage of the level shifter 100. As will be described in detail later, when VDD is input to the wiring INE, the level shifter 100 level-shifts VDD to VDDH, inverts the logic, and outputs VSSL to the wiring BOTE. Alternatively, when VSS is input to the wiring INE, the level shifter 100 level-shifts VSS to VSSL, inverts the logic, and outputs VDDH to the wiring BOTE.

[0085] <<Example of operation>> Next, an example of the operation of the level shifter 100 shown in FIG. 1 will be described.

[0086] FIG. 2 is a timing chart showing changes in voltage of the wirings CLPE, PRCE, EVE, INE, the node FN, and the wiring BOTE from time T1 to time T9 and around those times.

[0087] At a time before time T1, VSS is input to the wiring INE, VSSL is input to the wiring CLPE, VSSL is input to the wiring PRCE, and VSSL is input to the wiring EVE. Also, VSSL or VSS is held at the node FN of the memory unit AM, and VDDH or VSSL is output to the wiring BOTE.

[0088] [Writing period of potential to memory section AM] Between time T1 and time T3, VSSL is written to node FN of memory unit AM. Specifically, between time T1 and time T2, VDD is input to line CLPE as a high-level potential. As a result, VDD is input to the gate of transistor Tr4, and the gate-source voltage of transistor Tr4 becomes VDD-VSSL. Here, VDD-VSSL>V TH4 V so that TH4By determining the value, the transistor Tr4 can be turned on.

[0089] When the transistor Tr4 is turned on, electrical continuity is established between the wiring VLSE and the node FN, causing the potential of the node FN in the memory unit AM to become VSSL.

[0090] Between time T2 and time T3, VSSL is input to the line CLPE as a low-level potential. As a result, VSSL is input to the gate of the transistor Tr4, and the gate-source voltage of the transistor Tr4 becomes 0. At this time, 0 <V TH4 Therefore, the transistor Tr4 is turned off.

[0091] When the transistor Tr4 is turned off, the line VLSE and the node FN are disconnected from each other. As a result, VSSL is held at the node FN of the memory unit AM. Specifically, VSS-VSSL is held between the first terminal and the second terminal of the capacitor C1.

[0092] Since VSSL is input to the gate of the transistor Tr3, the gate-source voltage of the transistor Tr3 is 0. <V TH3 Therefore, transistor Tr3 is turned off. Because transistor Tr3 is turned off, no current flows between the source and drain of transistor Tr2.

[0093] [Precharge period (1), data input period (1)] Between time T3 and time T4, the wiring BOTE is precharged with a potential. Specifically, between time T3 and time T4, the wiring PRCE is precharged with a high-level potential of VDDH+V TH1 This causes the gate of transistor Tr1 to receive VDDH+V. TH1At this time, since VDDH is input to the first terminal of the transistor Tr1, the second terminal of the transistor Tr1 is charged until the potential reaches VDDH. When the second terminal of the transistor Tr1 reaches VDDH, the gate-source voltage of the transistor Tr1 becomes 0 and then returns to 0. <V TH1 Therefore, the transistor Tr1 is turned off, and the potential of the wiring BOTE becomes VDDH.

[0094] After the wiring BOTE is precharged with a potential, VSSL is input as a low level potential to the wiring PRCE.

[0095] Between time T3 and time T4, data is input to the level shifter 100. Specifically, between time T3 and time T4, VDD is input to the line INE as a high-level potential.

[0096] When VDD is input to the wiring INE, the potential of the node FN fluctuates due to the capacitive coupling at the capacitor C1. In this case, for example, the potential of the node FN becomes VSSL+α(VDD-VSS) due to the capacitive coupling at the capacitor C1. Note that α is a capacitive coupling coefficient determined by the circuit configuration around the node FN, etc.

[0097] The timing of inputting data to the level shifter 100 is preferably between time T3 and time T4, preferably while VDDH is being input to the line PRCE. In other words, it is preferable that VDD is input to the line INE while VDDH is being precharged to the line BOTE.

[0098] [Non-overlap period (1)] The period from time T4 to time T5 is a non-overlap period. This non-overlap period is provided to prevent the pre-charge period from time T3 to time T4 described above from overlapping with the evaluation period from time T5 to time T6 described below. Note that if the pre-charge period and evaluation period do not overlap, it is not necessary to provide a non-overlap period.

[0099] [Evaluation period (1)] Between time T5 and time T6, the signal input to the wiring INE is evaluated. Specifically, between time T5 and time T6, the wiring EVE is supplied with, for example, a high-level potential VDDH+V TH3 As a result, VDDH+V is input to the gate of transistor Tr3. TH3 is input to the gate of transistor Tr3. TH3 When this is input, the gate-source voltage of transistor Tr3 becomes VDDH+V TH3 -VSSL, where VDDH+V TH3 -VSSL>V TH3 , that is, VDDH-VSSL>0 is satisfied, so that the transistor Tr3 can be turned on. As a result, the second terminal of the transistor Tr2 and the wiring VLSE are electrically connected, and the potential VSSL provided by the wiring VLSE is input to the second terminal of the transistor Tr2. Note that the wiring EVE is connected to a high-level potential, for example, V TH3 V, which is a potential higher than V and lower than VDDH EVE In this case, the gate-source voltage of the transistor Tr3 is V EVE -VSSL, so V EVE -VSSL>V TH3 If VSSL is set so as to satisfy the above, the transistor Tr3 can be turned on.

[0100] At this time, the gate-source voltage of the transistor Tr2 is VSSL+α(VDD-VSS)-VSSL=α(VDD-VSS). TH2However, α(VDD-VSS)>V TH2 When the above condition is satisfied, the transistor Tr2 is turned on.

[0101] When the transistors Tr2 and Tr3 are turned on, the line BOTE and the line VLSE are electrically connected. As a result, the VDDH that was charged in the line BOTE is discharged to the VSSL provided by the line VLSE. As a result, the line BOTE outputs VSSL.

[0102] After VSSL is output from the wiring BOTE, VSSL is input to the wiring EVE as a low-level potential. As a result, VSSL is input to the gate of the transistor Tr3. By inputting VSSL to the gate of the transistor Tr3, the gate-source voltage of the transistor Tr3 becomes VSSL-VSSL=0. Also, 0 <V TH3 Therefore, the transistor Tr3 is turned off.

[0103] [Precharge period (2), data input period (2)] Between time T6 and time T7, the wiring BOTE is precharged with a potential. Specifically, between time T6 and time T7, the same operation as between time T3 and time T4 is performed. Therefore, the wiring PRCE is precharged with a high-level potential VDDH+V TH1 is input, and the potential of the wiring BOTE becomes VDDH.

[0104] After the wiring BOTE is precharged with a potential, VSSL is input as a low level potential to the wiring PRCE.

[0105] Between time T6 and time T7, data is input to the level shifter 100. Specifically, between time T6 and time T7, VSS is input to the line INE as a low-level potential.

[0106] When VSS is input to the wiring INE, the potential of the node FN fluctuates due to capacitive coupling at the capacitor C1. At this time, the potential of the wiring INE is VSS, so the potential of the node FN returns to the potential of the node FN between time T2 and time T3. In other words, the potential of the node FN becomes VSSL between time T6 and time T7.

[0107] The timing of inputting data to the level shifter 100 is preferably between time T6 and time T7, preferably while VDDH is being input to the line PRCE. In other words, it is preferable to input VSS to the line INE while VDDH is being precharged to the line BOTE.

[0108] [Non-overlapping period (2)] The period from time T7 to time T8 is a non-overlap period similar to the period from time T4 to time T5. Therefore, for the non-overlap period, please refer to the explanation of the operation from time T4 to time T5.

[0109] [Evaluation Period (2)] Between time T8 and time T9, the signal input to the wiring INE is evaluated. Specifically, between time T8 and time T9, the wiring EVE is supplied with a high-level potential of VDDH+V TH3 is input. As a result, similar to the operation from time T5 to time T6, transistor Tr3 is turned on. This also causes VSSL provided by line VLSE to be input to the second terminal of transistor Tr2.

[0110] At this time, the gate-source voltage of the transistor Tr2 is VSSL-VSSL=0. <V TH2 Therefore, the transistor Tr2 is turned off. As a result, the potential of the line BOTE remains at VDDH, to which it was charged between time T6 and time T7. As a result, the line BOTE outputs VDDH.

[0111] After VDDH is output from the line BOTE, VSSL is input to the line EVE as a low-level potential, which turns off the transistor Tr3.

[0112] According to the above-described operation example, the input VDD can be level-shifted to VSSL, which is lower than VSS, or the input VSS can be level-shifted to VDDH, which is higher than VDD.

[0113] Note that the semiconductor device of one embodiment of the present invention is not limited to the configuration shown in Fig. 1. The semiconductor device of one embodiment of the present invention may have a modified circuit configuration of the level shifter 100 shown in Fig. 1 depending on the situation.

[0114] For example, the level shifter 100 shown in Fig. 1 may be modified to have a circuit configuration of a level shifter 100A shown in Fig. 3. Specifically, the level shifter 100A has a configuration in which the transistors Tr2 and Tr3 in the level shifter 100 are interchanged.

[0115] Regarding the circuit configuration of the level shifter 100A in Fig. 3, only differences from the level shifter 100 in Fig. 1 will be described. A first terminal of the transistor Tr1 is electrically connected to a first terminal of the transistor Tr3, a second terminal of the transistor Tr3 is electrically connected to a first terminal of the transistor Tr2, and a second terminal of the transistor Tr2 is electrically connected to the wiring VLSE.

[0116] An example of the operation of the level shifter 100A in FIG. 3 can be the same as the timing chart in FIG. 2, which is an example of the operation of the level shifter 100 in FIG.

[0117] For example, the level shifter 100 shown in FIG. 1 may have a configuration in which the capacitance C1 and the capacitance CL each include a transistor. In FIG. 4A, the capacitance C1 (capacitance CL) includes a transistor Tc1 (transistor TcL). Specifically, the first and second terminals of the transistor Tc1 (transistor TcL) are one of the first and second terminals of the capacitance C1 (capacitance CL), and the gate of the transistor Tc1 (transistor TcL) is the other of the first and second terminals of the capacitance C1 (capacitance CL). In other words, the gate capacitance of the transistor Tc1 is used as a substitute for the capacitance C1, and similarly, the gate capacitance of the transistor TcL is used as a substitute for the capacitance CL. In the level shifter 100B shown in FIG. 4B, the capacitance C1 and the capacitance CL are replaced with the transistor Tc1 and the transistor TcL, respectively. Note that the threshold voltage of the transistor Tc1 (transistor TcL) is preferably lower than the voltage between the gate of the transistor Tc1 (transistor TcL) and the source or drain of the transistor Tc1 (transistor TcL). Furthermore, in the level shifter 100B shown in FIG. 4B, the transistor Tc1 (transistor TcL) can be fabricated as the capacitor C1 (capacitor CL) in the process of fabricating the transistor, so that the process of forming a planar type, trench type, or other capacitor can be omitted. In other words, the time required to fabricate the level shifter 100B can be shortened.

[0118] Furthermore, for example, the level shifter 100 shown in FIG. 1 may be configured such that the second terminal of the capacitor CL is electrically connected to another wiring instead of the wiring VLSE. For example, the level shifter 100C shown in FIG. 5 may be configured as such. The level shifter 100C differs from the level shifter 100 in that the second terminal of the capacitor CL is electrically connected to the wiring VAL. The wiring VAL, like the wiring VLSE, functions as a wiring that applies a constant voltage. Note that the constant voltage may be VSS, a ground potential (GND), or the like, instead of VSSL applied by the wiring VLSE. Alternatively, the wiring VAL may be a wiring that applies a voltage such as VDD or VDDH depending on the situation. Alternatively, the wiring VAL may be electrically connected to the wiring VDHE.

[0119] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0120] (Embodiment 2) In this embodiment, structural examples of the semiconductor device described in the above embodiment and structural examples of a transistor that can be applied to the semiconductor device will be described.

[0121] <Configuration example of semiconductor device> 6 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 8A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 8B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 8C is a cross-sectional view of the transistor 300 in the channel width direction.

[0122] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change even at high temperatures. By applying the transistor 500 to a semiconductor device, such as a transistor included in the level shifter 100, the level shifter 100A, the level shifter 100B, or the level shifter 100C described in the above embodiments, a semiconductor device whose operating capability is not degraded even at high temperatures can be realized. In particular, by utilizing the characteristics of the small off-state current, the transistor 500 can be applied to the transistor Tr4, thereby enabling the potential written to the node FN of the memory unit AM to be held for a long time.

[0123] 6, the transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example. The capacitor 600 can be a capacitor included in the level shifter 100, the level shifter 100A, the level shifter 100B, the level shifter 100C, or the like described in the above embodiments. Depending on the circuit configuration, the capacitor 600 shown in FIG. 6 is not necessarily provided.

[0124] The transistor 300 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 can be applied to, for example, the transistors included in the level shifter 100, the level shifter 100A, the level shifter 100B, and the level shifter 100C described in the above embodiments. Specifically, the transistor 300 can be, for example, the transistor Tr2 included in the level shifter 100 in FIG. 1. Note that Figure 6 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source or drain of the transistor 500 through one of a pair of electrodes of the capacitor 600. However, depending on the configuration of the level shifter 100, the level shifter 100A, the level shifter 100B, the level shifter 100C, etc., one of the source or drain of the transistor 300 may be electrically connected to one of the source or drain of the transistor 500 through one of a pair of electrodes of the capacitor 600, or one of the source or drain of the transistor 300 may be electrically connected to the gate of the transistor 500 through one of a pair of electrodes of the capacitor 600. Furthermore, each terminal of the transistor 300 may not be electrically connected to each terminal of the transistor 500 or each terminal of the capacitor 600.

[0125] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 311.

[0126] 8C , the transistor 300 has a top surface and side surfaces in the channel width direction of a semiconductor region 313 covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0127] The transistor 300 may be either a p-channel type or an n-channel type.

[0128] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0129] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0130] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0131] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0132] 6 is just an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 7. The details of the transistor 500 will be described later.

[0133] In FIG. 7, the transistor 300 is provided on a substrate 312. In this case, the substrate 312 may be a semiconductor substrate similar to the substrate 311 of the semiconductor device in FIG. 6. The substrate 312 may be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride, as well as polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper.

[0134] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order to cover the transistor 300.

[0135] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0136] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0137] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0138] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or the transistor 300 to a region where the transistor 500 is provided.

[0139] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0140] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0141] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0142] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0143] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0144] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 6, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0145] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0146] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0147] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 6, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0148] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0149] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 6, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using a material similar to that of the conductors 328 and 330.

[0150] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0151] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 6, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be formed using a material similar to that of the conductors 328 and 330.

[0152] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0153] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0154] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen and hydrogen.

[0155] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0156] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0157] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0158] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0159] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0160] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0161] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0162] Above the insulator 516 is the transistor 500 .

[0163] As shown in Figures 8A and 8B, the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.

[0164] 8A and 8B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. It is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIGS.

[0165] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0166] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 6, 8A, and 8B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0167] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0168] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0169] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0170] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0171] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0172] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0173] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0174] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, when the conductivity of the wiring can be maintained at a high level, the conductor 503a is not necessarily provided. While the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0175] The insulators 520, 522, and 524 function as a second gate insulating film.

[0176] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. That is, an excess oxygen region is preferably formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0177] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0178] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0179] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0180] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0181] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0182] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0183] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524, the oxide 530, and the like can be suppressed.

[0184] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0185] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0186] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0187] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0188] 8A and 8B, the second gate insulating film has a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0189] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0190] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0191] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V O H functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0192] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0193] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0194] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0195] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in the oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0196] Furthermore, oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, which may form a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure based on the MIS structure.

[0197] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b, and may be formed, for example, between the conductor 542a and the conductor 542b and the oxide 530c, between the conductor 542a and the conductor 542b and the oxide 530b, or between the conductor 542a and the conductor 542b and the oxide 530c.

[0198] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0199] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0200] The oxide 530 preferably has a stacked structure made up of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be made up of the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0201] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0202] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0203] In addition to the compositions described above, oxide 530b may be a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0204] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that, and oxide 530b is a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0205] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0206] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0207] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0208] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0209] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0210] 8A and 8B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0211] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0212] 8A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0213] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0214] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0215] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0216] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0217] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 544 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0218] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0219] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0220] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0221] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0222] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a stacked structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0223] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 8A and 8B, but may have a single-layer structure or a stacked structure of three or more layers.

[0224] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 550 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0225] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0226] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0227] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0228] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0229] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0230] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0231] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0232] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0233] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0234] Furthermore, the conductor 540a and the conductor 540b are placed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 and the conductor 548, which will be described later.

[0235] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0236] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0237] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0238] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0239] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0240] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 514 or the insulator 522 and form the insulator with high barrier properties in contact with the insulator 514 or the insulator 522, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522.

[0241] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0242] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0243] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0244] 6, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0245] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0246] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0247] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, fluctuation in electrical characteristics can be suppressed and reliability can be improved, or miniaturization or high integration can be achieved in a semiconductor device including a transistor having an oxide semiconductor.

[0248] Note that the semiconductor device of one embodiment of the present invention may have a structure in which, for example, another semiconductor substrate on which a circuit is formed is bonded below the substrate 311 on which the transistor 300 is formed. Figure 9 illustrates a structure in which a layer SA, which is part of the semiconductor device in Figure 6, is bonded to a layer SB on which a circuit is formed on another semiconductor substrate. Specifically, the semiconductor device illustrated in Figure 9 has a structure in which a substrate 211 on which a circuit and the like included in the layer SB are formed is bonded below the substrate 311 included in the layer SA. Note that in Figure 9, conductors, insulators, and the like above the insulator 360 in the layer SA are omitted.

[0249] As the substrate 211, for example, a substrate that can be used as the substrate 311 of the semiconductor device in FIG. 6 can be used.

[0250] As an example, similar to the transistor 300 on the substrate 311, an insulator 220, an insulator 222, an insulator 224, an insulator 226, and an insulator 230 are provided in this order on the substrate 211 so as to cover the transistor 200.

[0251] Furthermore, the insulators 220, 222, 224, 226, 230, and 231 can be made of materials that can be used for the insulators 320, 322, 324, 326, and 230, for example. The insulators 220, 222, 224, 226, 230, and 231 can be formed by the same processes as the insulators 320, 322, 324, 326, and 350, for example.

[0252] Furthermore, conductors 228 and 229 are embedded in the insulators 220, 222, 224, and 226. The conductors 228 and 229 function as plugs or wirings, similar to the conductors 328 and 330. The conductors 228 and 229 can be made of materials that can be used for the conductors 328 and 330.

[0253] The insulator 232 functions as a bonding layer for an insulator 341 provided below the substrate 311, which will be described later. Furthermore, a conductor 233 is embedded in the insulators 231 and 232 so as to be electrically connected to a part of the conductor 229, and the conductor 233 also functions as a part of the bonding layer.

[0254] The insulator 232 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or titanium nitride.

[0255] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used as the conductor 233. In view of ease of bonding with the conductor 342 described below, it is preferable to use copper, aluminum, tungsten, or gold.

[0256] The conductor 233 may have a multilayer structure including multiple layers. For example, a first conductor may be formed on the side walls of the openings of the insulators 231 and 232, and then a second conductor may be formed to fill the openings of the insulators 231 and 232. For example, a conductor having a barrier property against hydrogen, such as tantalum nitride, may be used as the first conductor, and for example, tungsten having high conductivity may be used as the second conductor.

[0257] An insulator 341 is formed below the substrate 311. The insulator 341 functions as a bonding layer for the insulator 232 on the substrate 211.

[0258] The insulator 341 can be made of, for example, a material that can be used for the insulator 232. In particular, in order to join the insulator 232 and the insulator 341, it is preferable that the insulators 232 and 341 be made of the same component.

[0259] In layer SA, conductor 342 is embedded in insulator 341, substrate 311, insulator 320, and insulator 322 so as to be electrically connected to part of conductor 330, and conductor 342 also functions as part of the bonding layer.

[0260] For example, a material that can be used for the conductor 233 can be used as the conductor 342. In particular, in order to join the conductor 342 and the conductor 233, it is preferable that the conductor 342 and the conductor 233 are made of the same metal material.

[0261] The conductor 342 may have a multilayer structure including multiple layers. For example, a first conductor may be formed on the side walls of the openings of the insulator 341, the substrate 311, the insulator 320, and the insulator 322, and then a second conductor may be formed to fill the openings of the insulator 341, the substrate 311, the insulator 320, and the insulator 322. The first conductor may be, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, and the second conductor may be, for example, tungsten, which has high conductivity.

[0262] Next, the bonding of the layer SA and the layer SB will be described.

[0263] In a pre-process for bonding the layer SA and the layer SB, the surfaces of the insulator 232 and the conductor 233 in the layer SB are planarized so that they are at the same height. Similarly, the surfaces of the insulator 341 and the conductor 342 in the layer SA are planarized so that they are at the same height.

[0264] In the bonding process, when bonding insulator 232 and insulator 341, that is, bonding insulating layers together, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydration through heat treatment.Hydrophilic bonding also produces bonds at the atomic level, resulting in excellent mechanical bonding.

[0265] Furthermore, for example, when bonding conductor 233 and conductor 342, that is, bonding conductors together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0266] By carrying out the above-described bonding process, the conductor 342 included in the layer SA can be electrically connected to the conductor 233 included in the layer SB. Furthermore, a connection having sufficient mechanical strength can be obtained between the insulator 341 included in the layer SA and the insulator 232 included in the layer SB.

[0267] When the layers SA and SB are bonded together, an insulating layer and a metal layer are mixed on each bonding surface, so that the bonding can be performed by, for example, a combination of a surface activated bonding method and a hydrophilic bonding method.

[0268] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0269] By using the above-described bonding process, it is possible to add further circuits to the semiconductor device. This makes it possible to suppress an increase in the circuit area of ​​the semiconductor device. Furthermore, the bonding process makes it possible to electrically connect another semiconductor device (e.g., a logic circuit, a signal conversion circuit, a potential level conversion circuit, a current source, a voltage source, a switching circuit, an amplifier circuit, a photoelectric conversion circuit, an arithmetic circuit, etc.) to the semiconductor device. This makes it possible to configure a novel semiconductor device.

[0270] For example, a transistor 200 is formed on a substrate 211 included in the layer SB. Although FIG. 9 illustrates the transistor 200 as having the same structure as the transistor 300, the transistor 200 may have a different structure from the transistor 300. For example, as illustrated in FIG. 10, the transistor 200 may have the structure of the transistor 500 shown in FIGS. 6, 7, 8A, and 8B as an OS transistor. For example, the substrate 212 illustrated in FIG. 10 can be a substrate that can be used for the substrate 312 of the semiconductor device illustrated in FIG. 7.

[0271] Next, other configuration examples of the OS transistor shown in FIGS. 6 and 7 will be described.

[0272] 8A and 8B, Fig. 11A is a cross-sectional view of the transistor 500 in the channel length direction, and Fig. 11B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the structures illustrated in Fig. 11A and 11B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0273] 11A and 11B differs from the transistor 500 shown in FIGS. 8A and 8B in that the transistor 500 includes the insulator 402 and the insulator 404. The transistor 500 also differs from the transistor 500 shown in FIGS. 8A and 8B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500 also differs from the transistor 500 shown in FIGS. 8A and 8B in that the insulator 520 is not provided.

[0274] 11A and 11B, the insulator 402 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 402.

[0275] 11A and 11B , the transistor 500 includes the insulators 514, 516, 522, 524, 544, 580, and 574, and the insulator 404 covers these. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 402.

[0276] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 402 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0277] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0278] The transistor 500 shown in FIGS. 11A and 11B may have a different configuration depending on the situation. For example, the transistor 500 shown in FIGS. 11A and 11B may be modified to the transistor shown in FIGS. 12A and 12B as a modified example. FIG. 12A is a cross-sectional view of the transistor in the channel length direction, and FIG. 12B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIGS. 12A and 12B differs from the transistor shown in FIGS. 11A and 11B in that the oxide 530c has a two-layer structure of oxides 530c1 and 530c2.

[0279] The oxide 530c1 contacts the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0280] Oxide 530c1 can be, for example, an In-Zn oxide. Oxide 530c2 can be made of the same material as that used for oxide 530c when oxide 530c has a single-layer structure. For example, oxide 530c2 can be made of a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0281] By forming the oxide 530c as a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as, for example, a power MOS transistor. The oxide 530c of the transistor having the configuration shown in FIGS. 8A and 8B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0282] 12A and 12B can be applied to, for example, the transistor 300 illustrated in FIGS. 6 and 7. As described above, the transistor 300 can be applied to, for example, the semiconductor device described in the above embodiment, such as the transistor included in the level shifter 100, the level shifter 100A, the level shifter 100B, or the level shifter 100C described in the above embodiment. Note that the transistors illustrated in FIGS. 12A and 12B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one embodiment of the present invention.

[0283] Next, a capacitive element that can be applied to the semiconductor device of FIGS. 6 and 7 will be described.

[0284] Fig. 13 shows a capacitive element 600A as an example of the capacitive element 600 that can be applied to the semiconductor device shown in Fig. 6 and Fig. 7. Fig. 13A is a top view of the capacitive element 600A, Fig. 13B is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line L3-L4, and Fig. 13C is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line W3-L4.

[0285] The conductor 610 functions as one of a pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes.

[0286] The insulator 630 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like, and can be formed as a stacked layer or a single layer.

[0287] Furthermore, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitive element 600A can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the insulator with high dielectric strength improves the dielectric strength, thereby suppressing electrostatic breakdown of the capacitive element 600A.

[0288] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0289] Alternatively, the insulator 630 may be a single layer or a stack of insulators containing high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). For example, when the insulator 630 is a stack, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially formed may be used, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are sequentially formed may be used. Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become smaller and more highly integrated, thinning of the dielectrics used in gate insulators and capacitors may cause problems such as leakage current in transistors and / or capacitors. By using high-k materials for the gate insulator and the insulator that functions as the dielectric used in the capacitor element, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor element while maintaining the physical film thickness.

[0290] The capacitor 600 is electrically connected to the conductor 546 and the conductor 548 below the conductor 610. The conductors 546 and 548 function as plugs or wiring for connecting to other circuit elements. In addition, in FIGS. 13A to 13C, the conductors 546 and 548 are collectively referred to as the conductor 540.

[0291] Also, in Figure 13, for clarity, the insulator 586 in which the conductors 546 and 548 are embedded, and the insulator 650 covering the conductor 620 and the insulator 630 are omitted.

[0292] 6, 7, 13A, 13B, and 13C are planar capacitors, but the shape of the capacitor is not limited to this. For example, the capacitor 600 may be a cylindrical capacitor 600B shown in FIGS. 14A to 14C.

[0293] 14A is a top view of the capacitive element 600B, FIG. 14B is a cross-sectional view of the capacitive element 600B taken along the dashed dotted line L3-L4, and FIG. 14C is a perspective view showing the cross-section of the capacitive element 600B taken along the dashed dotted line W3-L4.

[0294] In Figure 14B, the capacitor element 600B has an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0295] Also, in FIG. 14C, insulator 586, insulator 650, and insulator 651 are omitted for clarity.

[0296] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0297] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of the same material as the conductors 330 and 518, for example.

[0298] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0299] As described above, the insulator 651 has an opening that overlaps with the conductor 611.

[0300] The conductor 610 is formed on the bottom and side surfaces of the opening. That is, the conductor 610 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0301] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. Thereafter, the conductor 610 deposited on the insulator 651 may be removed by chemical mechanical polishing (CMP) or the like, leaving the conductor 610 deposited in the opening.

[0302] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. Note that the insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor element.

[0303] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled.

[0304] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0305] The cylindrical capacitive element 600B shown in FIG. 14 can have a higher capacitance value than the planar capacitive element 600A.

[0306] 6 and 7. In other words, one embodiment of the present invention may be an imaging device including the level shifter described in the above embodiment. For example, the imaging device converts a current induced by a photoelectric conversion element into a digital signal using a current-voltage conversion circuit, an analog-to-digital conversion circuit, or the like. By providing a level shifter in the imaging device, the level of the digital signal can be shifted.

[0307] 15 illustrates a configuration example of an imaging device in which a photoelectric conversion element 700 is provided above the capacitor 600 in the semiconductor device illustrated in FIG. 7. Note that the photoelectric conversion element 700 may be provided below the transistor 300 instead of above the capacitor 600.

[0308] The photoelectric conversion element 700 includes, for example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.

[0309] 15 is an example of an organic photoconductive film, in which layer 767a is a lower electrode, layer 767e is a light-transmitting upper electrode, and layers 767b, 767c, and 767d correspond to a photoelectric conversion unit. Note that, instead of photoelectric conversion element 700 shown in FIG. 15, for example, a pn junction photodiode, an avalanche photodiode, or the like may be used.

[0310] The layer 767a serving as the lower electrode can be either an anode or a cathode, and the layer 767b serving as the upper electrode can be either an anode or a cathode. In this embodiment, the layer 767a serves as the cathode, and the layer 767b serves as the anode.

[0311] Layer 767a is preferably a low-resistance metal layer, etc. Specifically, layer 767a may be made of, for example, aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0312] The layer 767e is preferably formed using, for example, a conductive layer that has a high light-transmitting property to visible light. Specifically, the layer 767e can be formed using, for example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like. Note that the layer 767e may be omitted.

[0313] One of the layers 767b and 767d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 767c can be a photoelectric conversion layer.

[0314] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0315] The photoelectric conversion layer may be a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor.

[0316] 15, the insulator 751 is provided over the insulator 650, and the layer 767a is provided over the insulator 751. The insulator 752 is provided over the insulator 751 and the layer 767a. The layer 767b is provided over the insulator 752 and the layer 767a.

[0317] Moreover, a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are stacked in this order on the layer 767b.

[0318] The insulator 751 functions as an interlayer insulating film, for example. For the insulator 751, an insulator having a barrier property against hydrogen, like the insulator 324, is preferably used. Using an insulator having a barrier property against hydrogen for the insulator 751 can suppress diffusion of hydrogen into the transistor 500. Therefore, for example, a material that can be used for the insulator 324 can be used for the insulator 751.

[0319] The insulator 752 functions as an element isolation layer, for example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent to the insulator 752. For example, an organic insulator or the like is preferably used as the insulator 752.

[0320] For example, the insulator 753 functions as a light-transmitting planarization film. The insulator 753 can be formed using a material such as silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0321] Above the insulator 753, for example, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided.

[0322] The light-shielding layer 771 provided on the insulator 753 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 771. The metal layer may be stacked with a dielectric film that functions as an anti-reflection film.

[0323] A color filter can be used for the optical conversion layer 772 provided on the insulator 753 and the light-shielding layer 771. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.

[0324] Furthermore, if a wavelength cut filter is used in the optical conversion layer 772, an imaging device that can obtain images in various wavelength regions can be obtained.

[0325] For example, an infrared imaging device can be formed by using a filter that blocks light having a wavelength shorter than that of visible light in the optical conversion layer 772. Alternatively, a far-infrared imaging device can be formed by using a filter that blocks light having a wavelength shorter than that of near-infrared light in the optical conversion layer 772. Alternatively, an ultraviolet imaging device can be formed by using a filter that blocks light having a wavelength longer than that of visible light in the optical conversion layer 772.

[0326] Furthermore, if a scintillator is used for the optical conversion layer 772, an imaging device can be provided that obtains an image that visualizes the intensity of radiation, such as for use in an X-ray imaging device. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion element 700. An imaging device having such a configuration may also be used for a radiation detector or the like.

[0327] Scintillators contain a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with such radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, or the like dispersed in resin or ceramics can be used.

[0328] A microlens array 773 is provided on the light-shielding layer 771 and the optical conversion layer 772. Light passing through each lens of the microlens array 773 passes through the optical conversion layer 772 directly below and is irradiated onto the photoelectric conversion element 700. By providing the microlens array 773, concentrated light can be incident on the photoelectric conversion element 700, thereby enabling efficient photoelectric conversion. The microlens array 773 is preferably formed from a resin or glass that is highly translucent to visible light.

[0329] 15 illustrates a structure of an imaging device in which the transistor 300 and the photoelectric conversion element 700 using an organic photoconductive film are provided above the transistor 500; however, the imaging device of one embodiment of the present invention is not limited to this. For example, the imaging device of one embodiment of the present invention may have a back-illuminated pn junction photoelectric conversion element instead of the photoelectric conversion element 700.

[0330] 16 illustrates a configuration example of an imaging device in which a back-illuminated pn junction photoelectric conversion element 700A is provided above the transistor 300 and the transistor 500. The imaging device illustrated in FIG. 16 has a configuration in which a structure SC having the photoelectric conversion element 700A is attached above a substrate 312 on which the transistor 300, the transistor 500, and the capacitor 600 are provided.

[0331] The structure SC includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773, and the above-mentioned explanations should be referred to for the explanations of these.

[0332] Photoelectric conversion element 700A is a pn junction photodiode formed on a silicon substrate, and has layer 765b corresponding to a p-type region and layer 765a corresponding to an n-type region. Photoelectric conversion element 700A is a buried photodiode, and a thin p-type region (part of layer 765b) provided on the surface side (current extraction side) of layer 765a can suppress dark current and reduce noise.

[0333] The insulator 701, the conductor 741, and the conductor 742 function as bonding layers. The insulator 754 functions as an interlayer insulating film and a planarizing film. The insulator 755 functions as an element isolation layer. The insulator 756 functions to suppress the outflow of carriers.

[0334] Grooves separating pixels are provided in the silicon substrate, and insulators 756 are provided on the upper surface of the silicon substrate and in the grooves. By providing the insulators 756, it is possible to prevent carriers generated in the photoelectric conversion element 700A from flowing into adjacent pixels. The insulators 756 also have the function of suppressing the intrusion of stray light. Therefore, the insulators 756 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulators 756.

[0335] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, the insulator 756 may be an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic. The insulator 756 may have a multilayer structure.

[0336] Layer 765a (n-type region, corresponding to the cathode) of photoelectric conversion element 700A is electrically connected to conductor 741. Layer 765b (p-type region, corresponding to the anode) is electrically connected to conductor 742. Conductor 741 and conductor 742 have regions embedded in insulator 701. Furthermore, the surfaces of insulator 701, conductor 741, and conductor 742 are flattened so that they are all at the same height.

[0337] An insulator 691 and an insulator 692 are stacked in this order above the insulator 650. Also, for example, in Fig. 16, an opening is provided in the insulator 692, and a conductor 743 is formed to fill the opening.

[0338] As the insulator 691, for example, a material that can be used for the insulator 751 can be used.

[0339] As the insulator 692, for example, a material that can be used for the insulator 650 can be used.

[0340] The insulators 693 and 701 each function as part of the bonding layer. The conductors 741, 742, and 743 each also function as part of the bonding layer.

[0341] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulators 693 and 701. In particular, in order to bond the insulators 693 and 701 to each other, the insulators 693 and 701 are preferably made of the same component.

[0342] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for the conductor 741, the conductor 742, and the conductor 743. In particular, to easily bond the conductor 741 and the conductor 743, and the conductor 742 and the conductor 743, it is preferable to use copper, aluminum, tungsten, or gold.

[0343] Note that the conductor 741, the conductor 742, and the conductor 743 may each have a multilayer structure including multiple layers. For example, a first conductor may be formed on a side surface of an opening where the conductor 741, the conductor 742, or the conductor 743 is to be provided, and then a second conductor may be formed to fill the opening. The first conductor may be, for example, a conductor having a barrier property against hydrogen, such as tantalum nitride, and the second conductor may be, for example, tungsten, which has high conductivity.

[0344] In a pre-process for bonding the bonding layer on the substrate 312 side to the bonding layer on the structure SC side, the surfaces of the insulator 693 and the conductor 743 on the substrate 312 side are planarized so that they are at the same height. Similarly, the surfaces of the insulator 701, the conductor 741, and the conductor 742 on the structure SC side are planarized so that they are at the same height.

[0345] In the bonding process, when bonding the insulator 693 and the insulator 701, that is, bonding insulating layers together, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to temporarily bond them, and then the final bonding is performed by dehydrating them through heat treatment. The hydrophilic bonding method also produces bonds at the atomic level, so it can obtain mechanically excellent bonds.

[0346] Furthermore, for example, when bonding conductors 741 and 743, and conductors 742 and 743, that is, when bonding conductors together, a surface activated bonding method can be used in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0347] By performing the above-described bonding process, the conductor 743 on the substrate 312 side can be electrically connected to the conductors 741 and 742 on the structure SC side. Also, a connection having sufficient mechanical strength can be obtained between the insulator 693 on the substrate 312 side and the insulator 701 on the structure SC side.

[0348] When bonding the substrate 312 and the structure SC, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0349] For example, a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0350] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0351] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0352] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0353] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 17A. Fig. 17A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0354] As shown in FIG. 17A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0355] The structure within the bold frame shown in Figure 17A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0356] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 17B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." (The horizontal axis represents 2θ [deg.], and the vertical axis represents intensity in arbitrary units (au).) The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 17B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 17B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 17B is 500 nm.

[0357] As shown in Figure 17B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 17B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0358] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 17C. Figure 17C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 17C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0359] As shown in FIG. 17C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0360] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 17A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0361] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0362] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0363] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0364] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0365] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0366] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0367] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0368] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0369] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and / or defects (such as oxygen vacancies). Therefore, oxide semiconductors having the CAAC-OS have stable physical properties. Therefore, oxide semiconductors having the CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using the CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0370] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0371] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0372] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0373] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0374] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0375] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0376] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0377] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0378] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0379] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0380] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0381] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0382] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0383] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0384] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0385] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0386] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0387] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0388] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon, carbon, etc. in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0389] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0390] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0391] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0392] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0393] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0394] (Fourth embodiment) This embodiment mode will describe an example of a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0395] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 18A.

[0396] 18A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0397] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0398] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0399] By performing a dicing process, chips 4800a as shown in FIG. 18B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. Note that spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0400] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 18A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0401] <Electronic components> FIG. 18C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 18C has chip 4800a in mold 4711. Note that, as shown in FIG. 18C, chip 4800a may have a configuration in which circuit section 4802 is stacked. FIG. 18C omits a portion to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. Mounting substrate 4704 is completed by combining a plurality of such electronic components and electrically connecting them on printed circuit board 4702.

[0402] 18D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0403] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, any of the semiconductor devices described in the above embodiments or a high bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0404] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0405] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0406] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0407] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0408] Furthermore, SiP, MCM, etc. that use silicon interposers are less likely to experience a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer. Furthermore, because the silicon interposer has a highly flat surface, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly preferable for 2.5D packages (2.5-dimensional packaging), which place multiple integrated circuits side-by-side on an interposer.

[0409] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0410] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 18D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0411] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0412] Next, an electronic component having an image sensor chip (image pickup device) including a photoelectric conversion element will be described.

[0413] 19A is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 4510 for fixing an image sensor chip 4550 (see FIG. 19C), a cover glass 4520, and an adhesive 4530 for bonding the two together.

[0414] 19B is a perspective view of the underside of the package. The underside of the package has a BGA (Ball Grid Array) with solder balls as bumps 4540. Note that the package is not limited to a BGA, and may have an LGA (Land Grid Array), PGA (Pin Grid Array), or the like.

[0415] 19C is a perspective view of the package, with the cover glass 4520 and part of the adhesive 4530 omitted. Electrode pads 4560 are formed on the package substrate 4510, and the electrode pads 4560 and bumps 4540 are electrically connected via through holes. The electrode pads 4560 are electrically connected to the image sensor chip 4550 by wires 4570.

[0416] 19D is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 4511 for fixing an image sensor chip 4551 (FIG. 19F), a lens cover 4521, and a lens 4535. An IC chip 4590 (FIG. 19F) having functions such as a drive circuit and a signal conversion circuit for the imaging device is also provided between the package substrate 4511 and the image sensor chip 4551, forming a SiP (System in Package) configuration.

[0417] 19E is a perspective view of the appearance of the bottom side of the camera module. The bottom and side surfaces of package substrate 4511 have a QFN (Quad Flat No-lead package) configuration with mounting lands 4541 provided. Note that this configuration is just one example, and a QFP (Quad Flat Package), the aforementioned BGA, or the like may also be provided.

[0418] 19F is a perspective view of the module omitting a portion of lens cover 4521 and lens 4535. Land 4541 is electrically connected to electrode pad 4561, and electrode pad 4561 is electrically connected to image sensor chip 4551 or IC chip 4590 by wire 4571.

[0419] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0420] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0421] (Embodiment 5) In this embodiment, an example of an electronic device including the semiconductor device described in the above embodiment will be described. Note that Fig. 20 illustrates how each electronic device includes an electronic component 4700 including the semiconductor device.

[0422] [mobile phone] 20 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0423] 20, the information terminal 5500 includes a semiconductor device such as a memory device and an imaging device. By applying the semiconductor device described in the above embodiment, the information terminal 5500 can reduce power consumption of the memory device, the imaging device, the display portion 5511, and the like. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0424] [Wearable devices] 20 illustrates a wristwatch-type information terminal 5900 as an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0425] Similar to the information terminal 5500 described above, the wearable terminal can reduce the power consumption of semiconductor devices such as a memory device, an imaging device, and a display portion 5902 included in the wearable terminal by applying the semiconductor device described in the above embodiment.

[0426] [Information terminal] 20 also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0427] Like the information terminal 5500 described above, the desktop information terminal 5300 can reduce the power consumption of the semiconductor device provided in the desktop information terminal 5300 by applying the semiconductor device described in the above embodiment.

[0428] In the above description, a smartphone, a desktop information terminal, and a wearable terminal are illustrated as examples of electronic devices in Fig. 20, but information terminals other than smartphones, desktop information terminals, and wearable terminals can also be applied. Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0429] [electric appliances] 20 also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0430] By applying the semiconductor device described in the above embodiment to the electric refrigerator-freezer 5800, the power consumption of the electric refrigerator-freezer 5800 can be reduced.

[0431] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0432] [Game consoles] 20 also shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0433] FIG. 20 also illustrates a home video game console 7500, an example of a video game console. The home video game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 20, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to that shown in FIG. 20, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. In a music game, for example, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0434] Furthermore, the images of the above-mentioned game machine can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0435] A low-power consumption portable game console 5200 can be realized by applying the semiconductor device described in the above embodiment to the portable game console 5200. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0436] 20 illustrates a portable game machine as an example of a game machine, but the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include a home-use stationary game machine, an arcade game machine installed in an entertainment facility (such as an arcade or amusement park), and a pitching machine for batting practice installed in a sports facility.

[0437] [Moving object] The semiconductor device described in the above embodiment modes can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0438] FIG. 20 shows an automobile 5700 as an example of a moving object.

[0439] An instrument panel capable of displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device showing such information may also be provided around the driver's seat.

[0440] In particular, the display device can compensate for the view obstructed by pillars and the blind spot of the driver's seat by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby improving safety. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, it is possible to compensate for the blind spot and improve safety.

[0441] The semiconductor device described in the above embodiment can be applied to the above-mentioned instrument panel, imaging device, etc. Therefore, power consumption of the instrument panel, imaging device, etc. provided in the automobile 5700 can be reduced. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0442] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). The semiconductor device of one embodiment of the present invention can be applied to these moving objects to reduce their power consumption.

[0443] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0444] 20 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0445] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment to an imaging device included in the digital camera 6240. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0446] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0447] 20 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, and the like. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0448] The video camera 6300 has an imaging device similar to the digital camera 6240. Therefore, by applying the semiconductor device described in the above embodiment to the imaging device included in the video camera 6300, the video camera 6300 can consume less power. Furthermore, the low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0449] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0450] AM: memory unit, Tr1: transistor, Tr2: transistor, Tr3: transistor, Tr4: transistor, Tc1: transistor, TcL: transistor, C1: capacitance, CL: capacitance, FN: node, INE: wiring, BOTE: wiring, VDHE: wiring, VLSE: wiring, PRCE: wiring, EVE: wiring, CLPE: wiring, VAL: wiring, SA: layer, SB: layer, SC: structure, 100: level shifter, 100A: level shifter, 100B: level shifter, 100C: level shifter, 200: transistor, 211: substrate, 212: substrate, 220: insulation body, 222: insulator, 224: insulator, 226: insulator, 228: conductor, 229: conductor, 230: insulator, 231: insulator, 232: insulator, 233: conductor, 300: transistor, 311: substrate, 312: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 341: insulator, 342: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator , 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 402: insulator, 404: insulator, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 530c: oxide, 530c1: Oxide, 530c2: oxide, 540: conductor, 540a: conductor, 540b: conductor, 542: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 546: conductor, 548: conductor, 550: insulator, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitance element, 600A: capacitance element, 600B: capacitance element, 610: conductor, 611: conductor, 612: conductor, 620: conductor,630: insulator, 631: insulator, 650: insulator, 651: insulator, 691: insulator, 692: insulator, 693: insulator, 701: insulator, 741: conductor, 742: conductor, 743: conductor, 751: insulator, 752: insulator, 753: insulator, 754: insulator, 755: insulator, 756: insulator, 765a: layer, 765b: layer, 767a: layer, 767b: layer, 767c: layer, 767d: layer, 767e: layer, 771: light-shielding layer, 772: optical conversion layer, 4510: package substrate, 4511: package substrate, 4520: cover glass, 4 521: lens cover, 4530: adhesive, 4535: lens, 4540: bump, 4541: land, 4550: image sensor chip, 4551: image sensor chip, 4560: electrode pad, 4561: electrode pad, 4570: wire, 4571: wire, 4590: IC chip, 4700: electronic component, 4702: printed circuit board, 4704: mounting board, 4710: semiconductor device, 4711: mold, 4712: land, 4713: electrode pad, 4714: wire, 4730: electronic component, 4731: interposer, 4732: pad Cage substrate, 4733: electrode, 4735: semiconductor device, 4800: semiconductor wafer, 4800a: chip, 4801: wafer, 4801a: wafer, 4802: circuit unit, 4803: spacing, 4803a: spacing, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display, 5303: keyboard, 5500: information terminal, 5510: housing, 5511: display unit, 5700: automobile, 5800: electric refrigerator-freezer, 5801: housing , 5802: refrigerator compartment door, 5803: freezer compartment door, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation button, 5904: operator, 5905: band, 6240: digital camera, 6241: housing, 6242: display unit, 6243: operation button, 6244: shutter button, 6246: lens, 6300: video camera, 6301: housing, 6302: housing, 6303: display unit, 6304: operation key, 6305: lens, 6306: connection unit, 7500: stationary game console, 7520: main unit, 7522: controller,

Claims

1. A semiconductor device comprising first to fifth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; the gate of the first transistor is always electrically connected to a third wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to a fourth wiring; the gate of the third transistor is always electrically connected to a fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to a sixth wiring; a period during which a first potential is applied to the sixth wiring, and a period during which a second potential lower than the first potential is applied to the sixth wiring; Semiconductor device.

2. A semiconductor device comprising first to fifth transistors, one of the source and the drain of the first transistor is always electrically connected to a first wiring; the other of the source and the drain of the first transistor is always electrically connected to a second wiring; the gate of the first transistor is always electrically connected to a third wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the one of the source and the drain of the third transistor; the other of the source and the drain of the third transistor is always electrically connected to a fourth wiring; the gate of the third transistor is always electrically connected to a fifth wiring; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the second transistor; the gate of the fifth transistor is always electrically connected to a sixth wiring; a potential at which the fourth transistor is brought into a conductive state or a potential at which the fourth transistor is brought into a non-conductive state is applied to a gate of the fourth transistor; when the fourth transistor is in a conductive state, a potential of the fourth wiring is applied to a gate of the second transistor via the fourth transistor; a period during which a first potential is applied to the sixth wiring, and a period during which a second potential lower than the first potential is applied to the sixth wiring; Semiconductor device.

3. In claim 1 or claim 2, each of the first to fifth transistors has the same polarity; Semiconductor device.

Images