Semiconductor device

Abstract

To provide a semiconductor device in which damage due to ESD is suppressed in a manufacturing process.SOLUTION: At a position overlapping with a dicing line, a layer with a bandgap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less is provided. Around a semiconductor device such as a transistor, a layer with an energy bandgap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less is provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the invention disclosed in the present specification etc. is a process, a machine, a manufacture In particular, this specification One embodiment of the invention disclosed in the document relates to a semiconductor device and an electronic device including the semiconductor device. This is what is done.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. For example, a transistor can be considered a type of semiconductor device. display devices, light-emitting display devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductors 2. Description of the Related Art Circuits, imaging devices, electronic devices, and the like may include semiconductor devices. [Background technology]

[0003] Electrostatic discharge (ESD) can damage semiconductors. Conductive elements, electrodes, or insulating layers may be damaged or destroyed (also known as "electrostatic breakdown"). Electrostatic discharge damage can occur during the manufacturing process of semiconductor devices, through inspection and use as a product. It is known that this is a serious problem that can lead to reduced reliability and productivity.

[0004] For example, in Patent Document 1, a resistor element and a diode are included between a semiconductor circuit and a connection terminal. By connecting a protection circuit including this, surge current generated by ESD can be smoothed and the discharge path can be shortened. This discloses a technique for preventing surge current from flowing into a semiconductor circuit by securing a sufficient current. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-58762 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the method disclosed in Patent Document 1 does not address the E It is difficult to prevent damage caused by SD. When exposed to the plasma atmosphere in a floating state (electrically isolated state), The accumulated charge can cause ESD, damaging semiconductor elements, electrodes, or insulators. The edge layer may be damaged.

[0007] Also, in the dicing process in which a substrate on which a semiconductor device is formed is cut into chips, Semiconductor devices can be damaged by ESD.

[0008] One embodiment of the present invention is a semiconductor device that is less susceptible to ESD damage during a manufacturing process of the semiconductor device. Another object of the present invention is to provide a semiconductor device or the like with high productivity. Another object of the present invention is to provide a semiconductor device or the like with low power consumption. Another object is to provide a highly reliable semiconductor device or the like. One of the objects of the present invention is to provide a novel semiconductor device or the like.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] The band gap is 2.5 eV at the position overlapping with the separation line (also called "dicing line"). A layer having an energy of 2.7 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less, is provided. A semiconductor device such as a photodiode having a band gap of 2.5 eV or more and 4.2 eV or less is preferably disposed around the device. A layer having an electric potential of 2.7 eV or more and 3.5 eV or less is provided.

[0011] One aspect of the present invention is a semiconductor device having a circuit area and a first layer, the circuit area being surrounded by the first layer, The first layer is a semiconductor having a band gap of 2.5 eV or more and 4.2 eV or less. It is a body device.

[0012] The first layer preferably includes an oxide semiconductor. The first layer is formed by the same process as the semiconductor layer of the first transistor. Therefore, the first layer and the semiconductor layer of the first transistor are in contact with the same layer. In addition, a semiconductor layer of the first transistor and a semiconductor layer of the second transistor may be provided. The semiconductor layers may have different bandgaps. [Effects of the Invention]

[0013] It is possible to provide a semiconductor device that is less susceptible to damage due to ESD during the manufacturing process of the semiconductor device. Alternatively, a semiconductor device or the like with high productivity can be provided. It is possible to provide a semiconductor device with little defect or a highly reliable semiconductor device. Alternatively, a novel semiconductor device or the like can be provided.

[0014] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. [Figure 2] 1 is a cross-sectional view of a semiconductor wafer according to one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a semiconductor wafer according to one embodiment of the present invention. [Figure 7] FIG. 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a top view of a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A and 1B are a top view and an equivalent circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A and 1B are a top view and an equivalent circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 2 is a diagram illustrating an energy band structure. [Figure 26] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 28] FIG. 2 is a block diagram showing an example of the configuration of a CPU. [Figure 29] FIG. 1 is a circuit diagram illustrating an example of a memory element. [Figure 30] FIG. 1 is a circuit diagram illustrating an example of an imaging device. [Figure 31] 1A and 1B are a flowchart and a schematic perspective view illustrating an example of a manufacturing process for an electronic component. [Figure 32] 1A to 1C illustrate examples of electronic devices. [Figure 33] 1A to 1C illustrate examples of electronic devices. [Figure 34] 1A to 1C illustrate examples of electronic devices. [Figure 35]1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 36] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 37] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 38] Cross-sectional TEM image of a-like OS. [Figure 39] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. DETAILED DESCRIPTION OF THE INVENTION

[0016] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. The repeated explanation may be omitted.

[0017] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc.

[0018] In addition, in the drawings, in order to facilitate understanding of the invention, the illustration of some components may be omitted. In addition, some hidden lines may be omitted.

[0019] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are used to indicate the order or priority of the processes or stacking steps. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is used to avoid confusion of the constituent elements. In order to clarify the scope of the invention, ordinal numbers may be used in the claims. Even if a term has an ordinal number in the first place, it may be given a different ordinal number in the claims. In addition, even if a term is given an ordinal number in this specification, etc., it may be used in the patent. Ordinal numbers may be omitted in claims, etc.

[0020] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0021] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "B", electrode B does not need to be formed directly on insulating layer A, The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0022] The source and drain functions may also be different when using transistors with different polarities or when using circuits When the direction of the current changes during circuit operation, they are interchanged depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's say.

[0023] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. do.

[0024] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. Therefore, even when it is expressed as "electrically connecting," in an actual circuit, In some cases, there are no physical connections and only wires running.

[0025] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). In the region where a channel is formed (also called a "channel forming region") , source (source region or source electrode) and drain (drain region or drain electrode) ) in one transistor. The channel length of a transistor is not necessarily the same value. Therefore, in this specification, the channel length is the area where the channel is formed. The value is any one of the values, the maximum value, the minimum value, or the average value.

[0026] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0027] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (also called the "effective channel width") and the The channel width (also called "apparent channel width") may differ from the When the gate electrode covers the side surface of the semiconductor layer, the effective channel width is For example, when the gate voltage is too high and the In a transistor in which the electrodes cover the side of the semiconductor, the portion of the channel region formed on the side of the semiconductor In this case, the effective channel width may be larger than the apparent channel width. The width of the rule becomes larger.

[0028] In such a case, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known exactly, it is difficult to estimate the effective chip size. Channel width is difficult to measure accurately.

[0029] Therefore, in this specification, the apparent channel width is referred to as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when simply referred to as a channel width, it may refer to the actual It may refer to the effective channel width. The width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0030] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0031] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistor is a normally-off type field effect transistor.

[0032] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent can be considered impurities. The DOS (Density of States) of the conductor increases and carrier mobility The semiconductor may be an oxide semiconductor, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main components of oxide semiconductors transition metals, especially hydrogen (which is also contained in water), lithium, sodium , silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen The inclusion of impurities can cause oxygen vacancies. In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0033] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. "Straight" refers to two straight lines that form an angle of 60° or more and 120° or less.

[0034] In this specification, the terms "identical," "same," and "equal" are used to refer to counting values ​​and measurement values. " or "uniform" (including their synonyms) unless expressly stated otherwise. The calculations are subject to a margin of error of plus or minus 20%.

[0035] In this specification, a high power supply potential VDD (hereinafter referred to as "VDD" or "H potential") ) refers to a power supply potential that is higher than the low power supply potential VSS. SS (hereinafter also referred to as "VSS" or "L potential") is a potential lower than the high power supply potential VDD. It also refers to the ground potential (GND potential, hereinafter also referred to as "GND") can be used as VDD or VSS. For example, if VDD is the ground potential, VSS is a potential lower than the ground potential, and if VSS is at the ground potential, VDD is at the ground potential. It is at a higher potential.

[0036] Generally, "voltage" refers to the difference between a certain potential and a reference potential (for example, ground potential or source potential). In many cases, it refers to the potential difference between a reference point and a reference voltage. The potential applied to wiring etc. may change depending on the potential. " may be interchangeable. In this specification, etc., Except for the above, VSS is the reference potential.

[0037] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0038] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0039] In a circuit diagram or the like, a transistor using an oxide semiconductor is preferably used. The circuit symbol for the resistor should include the notation "OS".

[0040] (Embodiment 1) <Configuration Example of Semiconductor Wafer 100> A semiconductor wafer 100 according to one embodiment of the present invention includes a substrate 101, a circuit region 102, and a gate electrode. FIG. 1(A) shows a semiconductor wafer immediately before dicing. A top view of H100 is shown.

[0041] Specifically, a plurality of circuit regions 102 are provided on a substrate 101. The area 102 is provided with semiconductor devices such as transistors and diodes. (Also called "dicing line") By cutting the substrate 101 at the position 104, the circuit A chip 105 including the region 102 can be cut out from the substrate 101. An enlarged view of the cap 105 is shown.

[0042] The guard layer 103 is provided on the periphery of the circuit region 102. 03 has an area overlapping with the separation line 104. By providing the guard layer 103, This mitigates ESD that can occur during the dicing process and prevents a decrease in yield during the dicing process. In addition, the dicing process generally involves cooling the substrate, removing chips, and preventing static electricity. The purpose is to flow pure water that has dissolved carbon dioxide gas and other substances to reduce the resistivity into the cutting area. By providing the guard layer 103, the amount of pure water used can be reduced. This reduces the production cost of the semiconductor device. It can be done.

[0043] The guard layer 103 may be made of a conductive material such as a metal, but a band gap A material having a refractive index of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less, is used. Such materials allow the stored charge to be slowly discharged. This prevents the sudden transfer of charge due to ESD and makes it less likely to cause electrostatic damage. An example of such a material is an oxide semiconductor.

[0044] For example, a transistor using an oxide semiconductor in a semiconductor layer where a channel is formed is When an OS transistor (also called an OS transistor) is used, the semiconductor The guard layer 103 can be provided in the same process as the formation of the body layer.

[0045] The regions X1-X2, X3-X4, and Y1-Y are shown by dashed lines in FIG. 2 shows a cross-sectional view of the guard layer 103. The area X1-X2 is an area including the guard layer 103. The portion X3-X4 is connected to the transistor 201 provided in the circuit region 102. 1 is a cross-sectional view of the transistor 291 in the channel length direction, and the portion Y1-Y2 is a cross-sectional view in the channel width direction. In the circuit region 102 shown in this embodiment, a transistor 291 is provided on the transistor 292. A star 201 is formed.

[0046] 3A is an enlarged view of a transistor 291 shown in FIG. 2. 3C is an enlarged view of the transistor 201 shown in FIG. This is an enlarged view.

[0047] In this embodiment, a case where an n-type single crystal semiconductor substrate is used as the substrate 101 will be described. However, the material that can be used for the substrate 101 is not limited to this. A single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a silicon substrate made of silicon or the like is used as the substrate. Alternatively, a compound semiconductor substrate made of silicon germanium or the like may be used. Alternatively, a high electron mobility transistor (HEMT) may be used. Gallium arsenide applicable to electron mobility transistors , aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide Alternatively, silicon germanium or the like may be used.

[0048] Note that a flexible substrate may be used as the substrate 101. When using a flexible substrate, a transistor, a capacitor, or the like may be directly formed on the flexible substrate. Transistors, capacitors, and the like are fabricated on another fabrication substrate, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the film from the fabrication substrate to the flexible substrate, It is advisable to provide a peeling layer between the transistor, the capacitor, and the like.

[0049] The flexible substrate may be, for example, a metal, an alloy, a resin, a glass, or a fiber thereof. The lower the linear expansion coefficient of the flexible substrate used for the substrate 101, the more environmentally friendly it is. The flexible substrate used for the substrate 101 has a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less As the resin, for example, polyester, polyolefin, polyamide ( nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable for flexible substrates.

[0050] In this embodiment, the transistor 291 has a channel formed in a part of the substrate 101. 201, which is an OS transistor, is used as an example of a semiconductor device. However, one aspect of the present invention is not limited thereto.

[0051] [Transistor 291] The transistor 291 includes a channel forming region 283, a high concentration p-type impurity region 285, an insulating layer 286 and an electrode 287. The insulating layer 286 can function as a gate insulating layer. 7 can function as a gate electrode.

[0052] The transistor 291 is electrically isolated from other transistors by an element isolation layer 414. The element isolation layer is formed by the LOCOS method (Local Oxidation of Silicon Ionic method, STI (Shallow Trench Isolation) method, etc. can be used.

[0053] The transistor 291 can function as a p-channel transistor. An insulating layer 403 is formed on the capacitor 291 .

[0054] The insulating layer 403 is made of aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum nitride oxide. aluminum oxide, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, Silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide ammonium, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicon A material selected from the group consisting of oxides, etc. can be used in a single layer or in a laminated form. A material that is a mixture of multiple materials selected from the group consisting of alloy materials, nitride materials, oxynitride materials, and nitride oxide materials. Fees may also be used.

[0055] In this specification, the term "nitride oxide" refers to a compound containing more nitrogen than oxygen. Also, oxynitrides refer to compounds that contain more oxygen than nitrogen. The content of Measurements can be made using techniques such as kScattering Spectrometry. .

[0056] Note that the insulating layer 403 is formed using an insulating material that has a function of preventing diffusion of impurities. For example, insulating materials that are difficult for impurities to penetrate include boron, carbon, nitrogen, and oxide. silicon, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium , germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or An insulating material containing tantalum may be used in a single layer or a multilayer. For example, aluminum oxide Aluminum, aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Examples of the oxide include silicon dioxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0057] By using an insulating material that is difficult for impurities to penetrate for the insulating layer 403, impurities from the substrate 101 side can be prevented. The diffusion of impurities can be suppressed, and the reliability of the semiconductor device can be improved. The method is not particularly limited, and examples thereof include vapor deposition, CVD, sputtering, spin coating, and ALD. Various forming methods such as the above can be used.

[0058] The insulating layer 286 may be formed using the same material and method as the insulating layer 403. The edge layer 286 may be a layer formed by oxidizing the surface of the sample by thermal oxidation or the like. stomach.

[0059] Further, an insulating layer 405 having a flat surface is provided on the insulating layer 403. The insulating layer 405 is The insulating layer 405 can be formed from the same material and by the same method as the edge layer 403. Chemical Mechanical Polishin (CMP) g) treatment (hereinafter also referred to as "CMP treatment"). This reduces the unevenness of the sample surface and improves the coverage of the insulating layer and conductive layer that will be formed later. can be done.

[0060] The insulating layer 405 may be made of polyimide, acrylic resin, benzocyclobutene resin, Heat-resistant organic materials such as polyamide and epoxy resins may also be used. In addition to the electrical materials, low-k materials, siloxane resins, PSG (Lingala It is possible to use materials such as BPSG (borophosphorus glass) and BPSG (borophosphorus glass). The insulating layer 405 may be formed by stacking a plurality of insulating layers formed of a metal oxide film.

[0061] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0062] The method for forming the insulating layer 405 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), printing The insulating layer 405 may be baked by a baking method (screen printing, offset printing, etc.). By combining this process with other heat treatment processes, it becomes possible to efficiently manufacture transistors. .

[0063] In addition, an electrode 413a, an electrode 413b, and an electrode 413c are formed on the insulating layer 405. The electrodes 413a, 413b, and 413c are made of the same material as the electrode 287. It can be prepared using materials and methods.

[0064] Conductive layers for forming the electrodes 287, 413a, 413b, and 413c Materials include aluminum, chromium, iron, copper, silver, gold, platinum, tantalum, nickel, Barium, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese Contains one or more metal elements selected from the group consisting of silicon, magnesium, zirconium, and beryllium. In addition, instead of polycrystalline silicon containing impurity elements such as phosphorus, A semiconductor having high electrical conductivity, such as nickel silicide, may also be used. These materials are used as the electrode 287, the electrode 413a, the electrode 413b, and the electrode 413c. A plurality of conductive layers made of the material may be laminated.

[0065] In addition, the electrode 287, the electrode 413a, the electrode 413b, and the electrode 413c are formed of indium tin. Indium tin oxide (ITO), indium containing tungsten oxide Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium zinc oxide, indium gallium oxide Conductive materials containing oxygen, such as sodium zinc oxide and silicon-doped indium tin oxide Conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can also be used. The laminated structure is made by combining the material containing the metal element and the conductive material containing oxygen. In addition, it is possible to combine the material containing the metal element and the conductive material containing nitrogen. In addition, the material containing the metal element and the conductive material containing oxygen may be used. It is also possible to use a laminated structure in which a material and a conductive material containing nitrogen are combined.

[0066] The method for forming these conductive layers is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, a sintering method, or the like. Various formation methods such as pin coating and ALD can be used.

[0067] The electrode 413a is connected to the high concentration p-type impurity region 285 via the contact plug 406a. The electrode 413b is electrically connected to one of the electrodes 413a and 413b via a contact plug 406b. The electrode 413c is electrically connected to the other of the p-type impurity regions 285. The contact plug 406a is electrically connected to the electrode 287 via the contact plug 406c. , contact plug 406b, and contact plug 406c are formed in the insulating layer 4 05 and an opening formed by removing a part of the insulating layer 403.

[0068] The contact plug 406a, the contact plug 406b, and the contact plug 406 For c, a highly conductive material with high embedding properties, such as tungsten or polysilicon, is used. Although not shown, the side and bottom surfaces of the material may be covered with a titanium layer, a nitride layer, or the like. It may be covered with a barrier layer (diffusion prevention layer) made of a titanium layer or a laminate of these. The barrier layer may also be referred to as a contact plug.

[0069] An insulating layer 407 is formed on the electrodes 413a, 413b, and 413c. The insulating layer 407 can be formed using a material and method similar to those of the insulating layer 405. The insulating layer 407 may be subjected to CMP treatment.

[0070] An insulating layer 141 is formed on the insulating layer 407. The insulating layer 141 has the same structure as the insulating layer 403. The insulating layer 141 can be formed by using a material and a method. It is preferable to form the insulating layer 141 using an insulating material. By using a conductive material, the diffusion of impurities from the insulating layer 407 side to the transistor 201 side is suppressed. In addition, the diffusion of impurities from the insulating layer 142 side to the transistor 291 side can be suppressed. Therefore, the reliability of the semiconductor device can be improved.

[0071] [Transistor 201] The transistor 201 includes a semiconductor layer 242 (a semiconductor layer 242a, a semiconductor layer 242b, and a Semiconductor layer 242c), insulating layer 226, electrode 246, electrode 119, electrode 121a, electrode 12 1b. The insulating layer 226 can function as a gate insulating layer. The electrode 246 can be a gate electrode. The electrode 119 can function as a back gate electrode. The electrode 121a can function as a Electrode 121b can function as either a source electrode or a drain electrode. It can function as the other of the drain electrodes.

[0072] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is arranged so as to sandwich the channel forming region of the gate electrode. The back gate electrode is set to the same potential as the gate electrode. Alternatively, the back gate may be set to a ground potential (GND potential) or any other potential. By changing the electrode potential independently of the gate electrode, the threshold voltage of the transistor can be controlled. The value voltage can be changed.

[0073] Both the electrode 246 and the electrode 119 can function as gate electrodes. The insulating layer 226, the insulating layer 145, the insulating layer 144, and the insulating layer 143 are each a gate insulating layer. It can function as a gate insulating layer.

[0074] When one of the electrodes 246 and 119 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 201, the electrode 246 is called a "gate electrode." When the term "electrode" is used, the electrode 119 is referred to as a "back gate electrode." When the transistor 201 is used as a bottom gate electrode, In addition, either the electrode 246 or the electrode 119 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0075] By providing the electrode 246 and the electrode 119 with the semiconductor layer 242 sandwiched therebetween, the electrode 24 6 and the electrode 119 are set to the same potential, the region where carriers flow in the semiconductor layer 242 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 201 increases, the field effect mobility also increases.

[0076] Therefore, the transistor 201 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 201 is determined based on the required on-current. Therefore, a highly integrated semiconductor device can be realized.

[0077] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0078] The electrode 246 and the electrode 119 each have the function of shielding an external electric field. The charges of the charged particles generated above the electrode 246 and below the electrode 119 are transferred to the semiconductor layer 242. This does not affect the channel formation region. As a result, stress tests (e.g., applying a negative charge to the gate) -GBT (Gate Bias-Temperature) stress test In addition, the electrode 246 and the electrode 119 are resistant to the electric field generated from the drain electrode. Therefore, the voltage fluctuation caused by the drain voltage fluctuation can be prevented from affecting the semiconductor layer. As a result, fluctuations in the on-state current rise voltage can be suppressed. This is particularly noticeable when a potential is applied to electrode 246 and electrode 119 .

[0079] The BT stress test is a type of accelerated test that measures the transients that occur during long-term use. It is possible to evaluate the characteristic changes (aging) of the stator in a short time. The amount of change in the threshold voltage of a transistor before and after the test is an important indicator for examining reliability. The smaller the threshold voltage fluctuation before and after the BT stress test, the higher the reliability. It can be said that this is a high-performance transistor.

[0080] In addition, the electrode 246 and the electrode 119 are provided, and the electrode 246 and the electrode 119 are set to the same potential. This reduces the amount of variation in threshold voltage between multiple transistors. At the same time, the variation in electrical characteristics is reduced.

[0081] A transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0082] In addition, when light is incident from the back gate electrode side, the back gate electrode is By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents light degradation of the semiconductor layer and shifts the threshold voltage of the transistor. This can prevent deterioration of electrical characteristics such as

[0083] The insulating layer 145 has a protruding portion, and an island-shaped semiconductor layer 242a and an island-shaped semiconductor layer 242b are formed on the protruding portion. In addition, an electrode 121a and an electrode 121b are provided on the semiconductor layer 242b. A region of the semiconductor layer 242b that overlaps with the electrode 121a is the transistor 201. The semiconductor layer 242b overlaps with the electrode 121b. The other region can function as the source or drain of the transistor 201. The region 269 of the semiconductor layer 242b sandwiched between the electrodes 121a and 121b is a channel. It can function as a hole-forming region.

[0084] As shown in FIG. 2, the transistor 201 has an electrode 246 The insulating layer 145 covers the semiconductor layer 242b. The side surface of the conductor layer 242b can also be covered with the electrode 246. Therefore, the semiconductor layer 242b is electrically surrounded (the conductive film The structure of a transistor that electrically surrounds a semiconductor by an electric field is called surrounded This is called a channel (s-channel) structure. In the s-channel structure, the channel can be formed in the entire (bulk) of the semiconductor. The drain current of the transistor can be increased, and the on-current ( When the transistor is in the on state, the current that flows between the source and drain can be obtained. The entire region of the channel forming region formed in the semiconductor layer 242b is electrically connected to the electrode 246. Therefore, in the s-channel structure, the on-state of the transistor The off-state current (the current that flows between the source and drain when the transistor is off) is further reduced. By reducing the channel width, the s-channel structure can be This structure can enhance the effects of increasing the on-current and reducing the off-current.

[0085] [Semiconductor layer 242] In this embodiment, an oxide semiconductor is used for the semiconductor layer 242. Since the gap is 2 eV or more, when an oxide semiconductor is used for the semiconductor layer 242, the off-state current is extremely small. Furthermore, the OS transistor can realize a transistor with a small number of The dielectric strength between drains is high, which allows for the provision of highly reliable transistors. Furthermore, a highly reliable semiconductor device can be provided.

[0086] The semiconductor layer 242 is a stack of semiconductor layers 242a, 242b, and 242c. It has the following configuration.

[0087] The semiconductor layer 242b is, for example, an oxide containing indium (In). For example, when b contains indium, the carrier mobility (electron mobility) increases. The semiconductor layer 242b preferably contains the element M.

[0088] The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements that can be used for element M include boron, silicon, titanium, iron, and nickel. , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium However, the element M is the same as the above. In some cases, a combination of multiple elements may be used. For example, the element M has a bond energy with oxygen of 0. The element M has the function of widening the band gap of the oxide, for example. The oxide semiconductor preferably contains zinc. If it contains, it may be prone to crystallization.

[0089] However, the semiconductor layer 242b is not limited to an oxide containing indium. b is indium, for example, zinc tin oxide, gallium tin oxide, gallium oxide, etc. and may be oxides containing zinc, oxides containing gallium, oxides containing tin, etc. It's okay.

[0090] The semiconductor layer 242b is made of, for example, an oxide having a wide band gap. The band gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV The voltage is preferably from 3 eV to 3.8 eV, more preferably from 3 eV to 3.5 eV.

[0091] The semiconductor layer 242 is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. osition) method (MOCVD(Metal Organic Chemical V apor deposition) method, ALD (Atomic Layer Depos) method ition), thermal CVD or PECVD (Plasma Enhanced Chemical Vapor Deposition) (including but not limited to) chemical vapor deposition (CVD) techniques, MBE (Molecular Beam Epitaxy) method or PLD (Pulse It is recommended to use the PECVD method for film formation. High-quality films can be obtained at relatively low temperatures. If a film formation method that does not use plasma is used during film formation, damage to the surface to be formed is less likely to occur. Furthermore, a film with few defects can be obtained.

[0092] For example, the semiconductor layer 242 may be formed by thermal CVD using an oxide semiconductor containing In, Ga, and Zn. When forming a thin film, trimethylindium (In(CH3)3), trimethylgallium Zn(CH3)2) and dimethylzinc (Ga(CH3)3). The combination is not limited to these, and trimethylgallium may be replaced with triethylgallium (G Zn(C2H5)3) can also be used, and diethyl zinc (Zn(C 2H5)2) can also be used.

[0093] For example, the semiconductor layer 242 may be formed by an ALD method using an oxide semiconductor containing In, Ga, and Zn. When forming a thin film, In(CH3)3 gas and O3 gas are introduced in sequence. After forming an O2 layer, Ga(CH3)3 gas and O3 gas are introduced repeatedly in sequence to form Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. InGaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. It is also possible to form a mixed compound layer of these. Although H2O gas containing H may be used, it is preferable to use O3 gas that does not contain H. In addition, instead of In(CH3)3 gas, In(C2H5)3 gas or tris(acetylacetonate) Tris(acetylacetonato)indium may also be used. It is also called In(acac)3. Also, instead of Ga(CH3)3 gas, Ga(C2H5) 3 gas or tris(acetylacetonato)gallium may also be used. Gallium gallium acetonate is also called Ga(acac)3. It is also called Zn(CH3)2 gas. Alternatively, zinc acetate may be used, but the gas species is not limited to these.

[0094] When the semiconductor layer 242 is formed by sputtering, the number of particles is reduced by using an insulator. It is preferable to use a target containing M. Also, an oxide target with a high atomic ratio of element M is preferable. When using a target containing indium, the conductivity of the target may be reduced. When using a target, the conductivity of the target can be increased, making DC discharge and AC discharge easier. Therefore, it is easy to handle large-area substrates. Therefore, it is possible to improve the productivity of semiconductor devices. It is possible.

[0095] When the semiconductor layer 242 is formed by sputtering, the atomic ratio of the target is In:M :Zn is, for example, 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1 , 1:1:2, 1:4:4, 4:2:3, 4:2:4.1, 5:1:6 or close to these You can use "naka" or something similar.

[0096] When the semiconductor layer 242 is formed by sputtering, the atomic ratio of the target may be different from that of the target. In particular, zinc may form a film with a higher atomic ratio than the target. Specifically, the ratio of the number of atoms of zinc contained in the target to 4 may become smaller. It may be between 0 atomic% and 90 atomic%.

[0097] The semiconductor layer 242a and the semiconductor layer 242c are formed by adding elements other than oxygen that constitute the semiconductor layer 242b. It is preferable that the metal layer is made of a material containing one or more of the same metal elements. When such a material is used, the interface between the semiconductor layer 242a and the semiconductor layer 242b and the semiconductor layer 242a are The interface state can be made less likely to occur at the interface between the conductor layer 242c and the semiconductor layer 242b. Therefore, scattering and capture of carriers at the interface are unlikely to occur, and the field effect of the transistor is It is possible to improve the mobility. Also, the threshold voltage (Vth) of the transistor is Therefore, it is possible to reduce the variation in the electrical characteristics. It is possible to realize a semiconductor device.

[0098] The thickness of the semiconductor layer 242a and the semiconductor layer 242c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 242b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0099] The semiconductor layer 242b is an In-M-Zn oxide (an oxide containing In, element M, and Zn). When the semiconductor layer 242a and the semiconductor layer 242c are also made of In-M-Zn oxide, The conductor layer 242a and the semiconductor layer 242c are formed by In:M:Zn=x1:y1:z1 [atomic ratio] ], and the semiconductor layer 242b has an atomic ratio of In:M:Zn=x2:y2:z2, then y1 The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are Preferably, y1 / x1 is 1.5 times or more larger than y2 / x2. The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so that the semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are different from each other. Preferably, the semiconductor layer 242a, the semiconductor layer 242b, has a ratio y1 / x1 that is at least twice as large as y2 / x2. The conductive layer 242c and the semiconductor layer 242b are selected. The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer At this time, in the semiconductor layer 242b, if y1 is equal to or greater than x1, This is preferable because it can provide stable electrical characteristics to the transistor. However, if y1 is more than three times larger than x1, If the value is above 100, the field effect mobility of the transistor will decrease. Therefore, y1 should be less than three times x1. By configuring the semiconductor layer 242a and the semiconductor layer 242c as described above, As a result, the semiconductor layers 242a and 242c have less oxygen deficiency than the semiconductor layer 242b. It is possible to make the layer less susceptible to such defects.

[0100] When the semiconductor layer 242a is an In-M-Zn oxide, the sum of In and M is 100 at. When expressed as atomic %, preferably In is less than 50 atomic % and M is less than 50 atomic %. c% or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more When the semiconductor layer 242b is an In-M-Zn oxide, the sum of In and M is When the atomic percentage is 100, it is preferable that In is 25 atomic % or more and M is 75 atomic %, more preferably In is 34 atomic % or more and M is 66 atomic % or more. When the semiconductor layer 242c is an In-M-Zn oxide, In and When the sum of In and M is 100 atomic %, preferably In is less than 50 atomic % , M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is The semiconductor layer 242c is made of the same material as the semiconductor layer 242a. An oxide may also be used.

[0101] For example, the semiconductor layer 242a containing In or Ga and the semiconductor layer 242b containing In or Ga 242c, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4 , 1:9:6, or a target having an atomic ratio of about 1:9:6. Ga-Zn oxide, In:Ga=1:9, 7:93, or similar atomic numbers In-Ga oxide formed using a target with the same ratio can be used. The layer 242b may have a composition of In:Ga:Zn=1:1:1, 3:1:2, 4:2:4, In formed using a target with an atomic ratio of 4:2:4.1 or nearby The semiconductor layer 242a and the semiconductor layer 242b may be made of a Ga—Zn oxide. The atomic ratios of the semiconductor layer 242c and the semiconductor layer 242d are each plus or minus the above atomic ratios as an error. Includes a 20% variation in eggplant.

[0102] The semiconductor layer 242b has a larger electron affinity than the semiconductor layer 242a and the semiconductor layer 242c. For example, the semiconductor layer 242b is made of a thin oxide. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or less, than that of 242c. An oxide having a larger valence of 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less, is used. The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0103] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor layer 242c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and More preferably, it is 90% or more.

[0104] However, even if the semiconductor layer 242a and / or the semiconductor layer 242c is made of gallium oxide, For example, if gallium oxide is used as the semiconductor layer 242c, the electrode 121a or This can reduce the leakage current that occurs between the electrode 121b and the electrode 109. The off-state current of the transistor 201 can be reduced.

[0105] At this time, when a gate voltage is applied, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 2 Of the semiconductor layers 42c, a channel is formed in the semiconductor layer 242b having a large electron affinity.

[0106] In order to provide a transistor using an oxide semiconductor layer with stable electrical characteristics, The impurities and oxygen vacancies in the conductor layer are reduced to make it highly purified and intrinsic, and at least the semiconductor layer 242b It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. At least the channel forming region in the semiconductor layer 242b is a semiconductor that can be regarded as intrinsic or substantially intrinsic. It is preferable that the body layer be made of a material other than the polymer.

[0107] [Energy band structure of semiconductor layer 242] Here, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are stacked. The function and effect of the semiconductor layer 242 formed by the above method will be explained with reference to the energy band shown in FIG. The following explanation will be given using a structural diagram. Figure 25(A) shows the structure of the A1-A2 shown by the dashed line in Figure 3(B). 25(A) shows the energy band structure of transistor 2. 1 shows the energy band structure of the channel formation region of 01.

[0108] In Figure 25, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulating layer 145, the semiconductor layer 242a, the semiconductor layer 242b, the semiconductor layer 242c, and the insulating layer 145 are formed on the semiconductor layer 242a. The energy of the conduction band minimum of layer 226 is shown.

[0109] Here, the electron affinity is the energy difference between the vacuum level and the top of the valence band (the "ionization potential"). It is the value obtained by subtracting the band gap from the Using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300) The energy difference between the vacuum level and the top of the valence band can be measured by ultraviolet photoelectron spectroscopy ( UPS:Ultraviolet Photoelectron Spectrosco Measurement can be performed using a PHI VersaProbe device.

[0110] The In-Ga was formed using a target with an atomic ratio of In:Ga:Zn=1:3:2. The band gap of α-Zn oxide is approximately 3.5 eV and the electron affinity is approximately 4.5 eV. In addition, the In-Ga was formed using a target with an atomic ratio of In:Ga:Zn=1:3:4. The band gap of Zn-oxide is about 3.4 eV and the electron affinity is about 4.5 eV. , In-Ga- formed using a target with an atomic ratio of In:Ga:Zn=1:3:6 The band gap of ZnO is about 3.3 eV and the electron affinity is about 4.5 eV. In-Ga-Z formed using a target with an atomic ratio of In:Ga:Zn=1:6:2 The band gap of n-oxide is about 3.9 eV and the electron affinity is about 4.3 eV. In-Ga-Zn formed using a target with a molecular ratio of In:Ga:Zn=1:6:8 The band gap of the oxide is about 3.5 eV and the electron affinity is about 4.4 eV. In-Ga-Zn formed using a target with a numerical ratio of In:Ga:Zn=1:6:10 The band gap of the oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In-Ga-Zn oxide formed using a target with a numerical ratio of In:Ga:Zn=1:1:1 The band gap of the oxide is about 3.2 eV, and the electron affinity is about 4.7 eV. In-Ga-Zn oxide formed using a target with a ratio of In:Ga:Zn=3:1:2 The band gap of the material is approximately 2.8 eV and the electron affinity is approximately 5.0 eV.

[0111] Since the insulating layer 145 and the insulating layer 226 are insulators, Ec382 and Ec386 are It is closer to the vacuum level than 3a, Ec383b, and Ec383c (it has a smaller electron affinity). ).

[0112] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.07 eV or more and 1.3 eV or less than Ec383b, preferably 0.1 eV or more and 0.07 eV or less than Ec383b. 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level. preferable.

[0113] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.07 eV or more and 1.3 eV or less than Ec383b, preferably 0.1 eV or more and 0.07 eV or less than Ec383b. 0.7 eV or less, more preferably 0.15 eV to 0.4 eV, close to the vacuum level. preferable.

[0114] Here, between the semiconductor layer 242a and the semiconductor layer 242b, there is a semiconductor layer 242a and a semiconductor layer 242b. In some cases, the semiconductor layer 242b and the semiconductor layer 242c are mixed. There may be a mixed region of the semiconductor layer 242b and the semiconductor layer 242c between them. The interface state density is low in the overlap region. The stack of the semiconductor layer 242c and the semiconductor layer 242d has a structure in which energy is continuously distributed near the interfaces of the semiconductor layer 242c and the semiconductor layer 242d. This results in a band structure that changes (also called a continuous junction).

[0115] At this time, the electrons are not in the semiconductor layer 242a and the semiconductor layer 242c, but in the semiconductor layer 2 Therefore, the electrons move mainly through the semiconductor layer 242a and the semiconductor layer 242b. Interface state density at the interface, the interface between the semiconductor layer 242b and the semiconductor layer 242c By lowering the level density, the movement of electrons in the semiconductor layer 242b is inhibited. Therefore, the on-state current of the transistor 201 can be increased.

[0116] In addition, the interface between the semiconductor layer 242a and the insulating layer 145, and the interface between the semiconductor layer 242c and the insulating layer 226 Although trap levels 390 due to impurities and defects can be formed near the interface, The presence of the conductor layer 242a and the semiconductor layer 242c allows the semiconductor layer 242b and the This allows the rapping level to be kept away.

[0117] When the transistor 201 has an s-channel structure, the semiconductor layer 242b Therefore, the thicker the semiconductor layer 242b, the larger the channel region. That is, the thicker the semiconductor layer 242b, the higher the on-state current of the transistor 201. For example, it can be 20 nm or more, preferably 40 nm or more, and more preferably a semiconductor layer 242b having a region with a thickness of 60 nm or more, more preferably 100 nm or more; However, the productivity of the semiconductor device including the transistor 201 may decrease. Therefore, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably 15 The semiconductor layer 242b may have a region with a thickness of 0 nm or less.

[0118] In order to increase the on-state current of the transistor 201, the thickness of the semiconductor layer 242c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 The semiconductor layer 242c may have a region of 100 nm or less. The semiconductor layer 242b in which the channel is formed is doped with elements other than oxygen (water) that constitute the adjacent insulator. It has the function of blocking the penetration of elements such as silicon and silicon dioxide. It is preferable that 242c has a certain thickness. For example, it is preferable that it is 0.3 nm or more. a semiconductor layer 242c having a region with a thickness of at least 1 nm, more preferably at least 2 nm; In addition, the semiconductor layer 242c is formed by the outward diffusion of oxygen released from the insulating layer 145 and the like. In order to suppress diffusion, it is preferable that the material has oxygen blocking properties.

[0119] In order to increase reliability, the semiconductor layer 242a is thick and the semiconductor layer 242c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 If the semiconductor layer 242a has a region with a thickness of 60 nm or more, more preferably 60 nm or more, By increasing the thickness of the semiconductor layer 242a, the adjacent insulator and the semiconductor layer 242a The distance from the interface with the semiconductor layer 242b where the channel is formed can be increased. However, the productivity of the semiconductor device having the transistor 201 may decrease. For example, the thickness is 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The semiconductor layer 242a may have the above-mentioned region.

[0120] Note that silicon in an oxide semiconductor may become a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor layer 242b, the more preferable. Between the layer 242b and the semiconductor layer 242a, for example, secondary ion mass spectroscopy (SIMS: 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18 atoms / cm 3 It has a region where the silicon concentration is less than In addition, a 1×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Kuha 2 x 10 18 atoms / cm 3 The silicon concentration is less than 1000 .mu.m.

[0121] In order to reduce the hydrogen concentration in the semiconductor layer 242b, the semiconductor layer 242a and the semiconductor layer It is preferable to reduce the hydrogen concentration in the semiconductor layer 242a and the semiconductor layer 242c. , SIMS, 2 × 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 a toms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below are some more good ones: Preferably 5 x 10 18atoms / cm 3 The hydrogen concentration range is as follows: In order to reduce the nitrogen concentration in the conductor layer 242b, the semiconductor layer 242a and the semiconductor layer 242c It is preferable to reduce the nitrogen concentration in the semiconductor layer 242a and the semiconductor layer 242c. In S, 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0122] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may cause the threshold voltage of the transistor to shift in the positive direction. The copper concentration on the surface or inside of the semiconductor layer 242b is preferably as low as possible. Layer 242b, copper concentration 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 It is preferable to have a region where: .

[0123] The above-mentioned three-layer structure is an example. For example, a semiconductor layer without the semiconductor layer 242a or the semiconductor layer 242c Alternatively, a two-layer structure may be used. 242c, a semiconductor layer 242a, a semiconductor layer 242b, and a semiconductor layer 242c are provided above or below the semiconductor layer 242a, a semiconductor layer 242b, and a semiconductor layer 242c. Alternatively, a four-layer structure may be used, which includes any one of the semiconductors exemplified above. Above layer 242a, below semiconductor layer 242a, above semiconductor layer 242c, below semiconductor layer 242c The semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are disposed in two or more locations. It may also be an n-layer structure (n is an integer of 5 or more) having one of the semiconductors exemplified above. do not have.

[0124] In particular, the transistor 201 exemplified in this embodiment has a semiconductor The upper surface and side surfaces of the layer 242b are in contact with the semiconductor layer 242c, and the lower surface of the semiconductor layer 242b is in contact with the semiconductor layer 242a (see the Y1-Y2 cross section in FIG. 2). By covering the conductor layer 242b with the semiconductor layer 242a and the semiconductor layer 242c, The influence of the trap level can be further reduced.

[0125] The band gaps of the semiconductor layer 242a and the semiconductor layer 242c are It is preferable that the band gap is wider than that of b.

[0126] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment, a highly reliable transistor can be realized. Therefore, a semiconductor device with good performance can be realized.

[0127] In addition, the band gap of oxide semiconductors is 2 eV or more, so the semiconductor in which the channel is formed A transistor that uses an oxide semiconductor for its body layer can have an extremely small off-state current. Specifically, when the voltage between the source and drain is 3.5V and the temperature is 25°C, The off-state current per 1 μm of panel width is 1×10 -20 Less than A, 1 x 10 -22 Below A or is 1 x 10 -24 That is, the on / off ratio can be increased by 20 orders of magnitude to 150 Note that the oxide semiconductor will be described in detail in other embodiments. Reveal.

[0128] According to one embodiment of the present invention, a transistor with low power consumption can be provided. As a result, a semiconductor device with low power consumption can be realized.

[0129] Returning to the description of the transistor 201, an opening is provided in the region of the insulating layer 146 that overlaps the region 269. A semiconductor layer 242c is provided along the side and bottom surfaces of the opening. The insulating layer 2 is formed in the opening via the semiconductor layer 242c and along the side and bottom surfaces of the opening. 26 is provided in the opening. Electrodes 246 are provided along the sides and bottom of the opening.

[0130] The opening is formed between the semiconductor layer 242a and the semiconductor layer 24 in the cross section in the channel width direction. Therefore, in the region 269, the semiconductor layer 242a and The side surfaces of the semiconductor layer 242b are covered with the semiconductor layer 242c.

[0131] Moreover, an insulating layer 142, an electrode 118, and an electrode 119 are formed on the insulating layer 141. The insulating layer 142 can be formed using the same material and method as the insulating layer 403. Electrode 118 and electrode 119 can be formed using the same materials and methods as electrode 287. do.

[0132] An insulating layer 144 is formed on the insulating layer 142, the electrode 118, and the electrode 119. An insulating layer 145 is formed on the layer 144. The insulating layer 144 and the insulating layer 145 are insulating layers. It can be formed using the same materials and methods as layer 403 .

[0133] The insulating layer 144 may be made of hafnium oxide, aluminum oxide, tantalum oxide, or aluminum. By forming the insulating layer 144 from silicate or the like, it is possible to make the insulating layer 144 function as a charge trapping layer. By injecting electrons into the insulating layer 144, the threshold voltage of the transistor can be changed. Electrons can be injected into the insulating layer 144 by utilizing, for example, the tunnel effect. By applying a positive voltage to the electrode 119, tunnel electrons are injected into the insulating layer 144. It is possible.

[0134] The insulating layer 146 can be formed using the same material and method as the insulating layer 405 . The insulating layer 405 and the insulating layer 147 formed on the electrode 246 are made of the same material as the insulating layer 141. The insulating layer 147 can be formed using a material and a method that is impervious to impurities. It is preferable to form the insulating layer 147 using an insulating material. By using this material, the diffusion of impurities from the insulating layer 148 side to the transistor 201 side is suppressed. It is possible.

[0135] An insulating layer 148 is formed on the insulating layer 147, and an electrode 113a and an electrode The insulating layer 148 is formed on the insulating layer 113b, the electrode 113c, and the electrode 113d. The electrode 113a and the electrode 113b can be formed using the same material and method as the layer 405. , electrode 113c, and electrode 113d are formed using the same material and method as electrode 287. It is possible.

[0136] The electrode 113a is electrically connected to the electrode 121a via the contact plug 112a. The electrode 113b is electrically connected to the electrode 121b via the contact plug 112b. The electrode 113c is electrically connected to the electrode 246 via the contact plug 112c. The electrode 113d is electrically connected to the electrode 119 via the contact plug 112d. The electrode 113b is electrically connected to the electrode 118 via the contact plug 112e. are actively connected.

[0137] The contact plug 112a and the contact plug 112b are formed in the insulating layer 148. , and are provided in openings formed by removing parts of the insulating layer 147 and the insulating layer 146 . The contact plug 112c is formed by removing a part of the insulating layer 148 and the insulating layer 147. The contact plug 112d and the contact plug 112 e are the insulating layers 148, 147, 146, 145, and 146, respectively. 44 and in an opening formed by removing a portion of the insulating layer 143.

[0138] Furthermore, an insulating layer 149 is formed on the insulating layer 148. The insulating layer 149 is formed on the insulating layer 405. It can be formed using the same materials and methods as those described above.

[0139] When an oxide semiconductor is used for the semiconductor layer 242, the hydrogen concentration and the nitrogen concentration of the oxide semiconductor are To prevent this increase, the hydrogen concentration and nitrogen concentration of the insulating layer adjacent to the semiconductor layer 242 are reduced. Specifically, the insulating layer 145, the insulating layer 146, and the insulating layer 226 The hydrogen concentration in the sample was measured by SIMS at 2×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 The insulating layer 14 5, the nitrogen concentration in the insulating layer 146 and the insulating layer 226 was measured by SIMS to be 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0140] When an oxide semiconductor is used for the semiconductor layer 242, the insulating layers 145, 146, The insulating layer 226 is preferably formed using an insulating layer from which oxygen is released by heating. Specifically, the surface temperature of the insulating layer is 100°C or higher and 700°C or lower, preferably 100°C or lower. Thermal desorption spectroscopy (TDS) is used for heat treatment at temperatures above 500°C. Desorption Spectroscopy (DDS) was used to measure the desorption of oxygen converted to oxygen atoms. The separation is 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 × 1019 atom s / cm 3 More preferably, 1.0 × 10 20 atoms / cm 3 An insulating layer In this specification and elsewhere, the oxygen released by heating is referred to as "excess oxygen." An insulating layer that releases oxygen when heated is called an "insulating layer containing excess oxygen." Also called.

[0141] Alternatively, an insulating layer containing excess oxygen can be formed by adding oxygen to an insulating layer. The process of adding oxygen can be carried out by heat treatment under an oxygen atmosphere, ion implantation equipment, ion doping equipment, etc. This can be done using a doping device or a plasma treatment device. As a gas, 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas or ozone In this specification, the process of adding oxygen is referred to as "oxygen doping." Also called "processing."

[0142] [Guard Layer 103] The guard layer 103 shown in this embodiment has a structure in which a layer 103b is stacked on a layer 103a. The layer 103a is formed of the same material and by the same method as the semiconductor layer 242a. The layer 103b can be formed simultaneously with the semiconductor layer 242b using the same material and method. The gate insulating layer 242b can be formed at the same time by the same method as the semiconductor layer 242b. The drain layer 103 is formed on the protruding portion of the insulating layer 145. Either one of 103b may be omitted.

[0143] As mentioned above, the guard layer 103 may be made of a conductive material such as metal. Band gap: 2.5 eV or more and 4.0 eV or less, preferably 2.7 eV or more and 3.5 eV or less The following materials are preferably used: When such materials are used, the accumulated charge is slowly released. This prevents the sudden transfer of charge caused by ESD and prevents electrostatic damage. An example of such a material is an oxide semiconductor. This can be done.

[0144] Furthermore, impurities may be introduced into the guard layer 103 to reduce the resistance of the guard layer. The introduction of the impurity is performed using an ion implantation device, an ion doping device, or a plasma treatment device. The guard layer 103 can be formed in a plasma atmosphere of inert gas or nitrogen gas. The resistance of the guard layer 103 may be reduced by exposing it to air.

[0145] The guard layer 103 may be floating, or may be connected to VSS, GND, or A specific potential such as a common potential may be supplied to the guard layer 103. The guard layer 103 may be electrically connected to the substrate 101. The thickness 123t of the guard layer 103 may be 2 nm or more and 20 nm or less. Also, the wider the width 123w of the guard layer 103, the more preferable. The width 123w is at least two times, preferably at least five times, the cutting width (the width of the separation line 104). Or, it may be 10 times or more (see FIG. 3(C)).

[0146] As described above, by providing the guard layer 103 on the separation line 104, the dicing This can mitigate ESD that may occur during the process and prevent a decrease in yield during the dicing process. Furthermore, the amount of pure water with low resistivity used in the dicing process can be reduced. Therefore, the production cost of the semiconductor device can be reduced. It can be increased.

[0147] Furthermore, the guard layer 103 remains attached to the chip 105 even after the chip 105 is formed through the dicing process. It is preferable that the guard be left along the edge of the chip 105. The drain layer 103 prevents the semiconductor from being damaged by ESD even after the chip 105 is formed. Damage to body devices and the like can be prevented or reduced.

[0148] <Variation 1> As shown in the cross-sectional view of FIG. 4, the guard layer 103 is divided into layers 103a, 103b, and The layer 103c may be a laminate of the electrodes 121a and 121b. The electrodes 121a and 121b can be formed simultaneously using the same materials and methods. .

[0149] <Variation 2> As shown in the cross-sectional view of FIG. 5, the process before forming the transistor 201 and the process after forming the transistor 201 are the same. In the process after forming the stanchion 201, a guard layer is formed in the area overlapping the separation line 104. In FIG. 5, the guard layer 133 is formed on the insulating layer 141, and the insulating layer 147 An example of forming a guard layer 134 is shown above.

[0150] The guard layer 133 and the guard layer 134 are made of the same material as the guard layer 103 and In the configuration shown in Modification 2, the guard layer is formed by the transistor Therefore, the guard layer and the semiconductor layer of transistor 201 do not need to be formed at the same time. For example, the guard layer 133 and the semiconductor layer 134 may be made of different materials. The guard layer 134 is formed of an oxide semiconductor, and the semiconductor layer of the transistor 201 is formed of silicon. The transistor 201 can be formed of a semiconductor such as silicon or germanium. The semiconductor layer is made of silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, nitride The layer can be formed of a compound semiconductor such as a semiconductor, an organic semiconductor, or the like.

[0151] When an organic semiconductor is used as the semiconductor layer of the transistor 201, a low molecular weight compound having an aromatic ring is used. Organic materials and π-electron conjugated conductive polymers can be used. For example, rubrene, tetraethoxysilane, etc. thracene, pentacene, perylenediimide, tetracyanoquinodimethane, polythiophene , polyacetylene, polyparaphenylene vinylene, etc. can be used.

[0152] According to one embodiment of the present invention, the degree of freedom in designing a semiconductor device can be increased.

[0153] <Variation 3> 6, the guard layer 103 is not provided, and the part overlapping the separation line 104 is In the region 114 where the substrate 101 is exposed, a part of the substrate 101 may be exposed. This allows ESD generated during the dicing process to escape to the substrate 101 side. Reference numeral 14 corresponds to the area in which the guard layer 103 is provided in FIG. 1(A).

[0154] In addition, in the manufacturing process of the transistor 291 and the transistor 201, a part of the insulating layer When forming the opening by removing the insulating layer overlapping the region 114, the insulating layer is removed to expose the substrate 101. During the manufacturing process of the semiconductor device, it is preferable to provide an exposed region of the substrate 101. This prevents damage to the semiconductor device due to ESD that may occur during the manufacturing process of the semiconductor device. can be reduced.

[0155] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0156] (Embodiment 2) <Configuration example of circuit area 102> By providing the guard layer 203 in the circuit region 102, the This can prevent or reduce damage to the semiconductor device due to ESD.

[0157] The guard layer 203 is made of the same material and in the same manner as the guard layer 103 shown in the first embodiment. In this embodiment, the pads 202a to 202d are formed by the contact method. A transistor 211 connected to the gate electrode 212 and a guard for protecting the transistor 211 from electrostatic discharge damage are provided. The configuration of the drain layer 203 will be described with reference to the drawings.

[0158] [Plane configuration example] Enlarged views of the region 106 in FIG. 1(B) are shown in FIGS. 7 and 8. FIG. 7(A) shows the transistor A guard layer 203 is provided on the outside of the sta 211 and the pads 202a to 202d. This shows an example of how this can be done.

[0159] The pad 202a is electrically connected to the gate electrode of the transistor 211. In addition, the pad 202b is electrically connected to the back gate electrode of the transistor 211. The pad 202c is connected to one of the source electrode and the drain electrode of the transistor 211. The pad 202d is electrically connected to the source electrode of the transistor 211. is electrically connected to the other of the drain electrodes.

[0160] A potential is supplied to each electrode of the transistor 211 via the pads 202a to 202d. Also, by measuring the current flowing through the transistor 211, the electrical The properties can be evaluated.

[0161] In addition, in FIG. 7B, at least the guard layer 203 provided on the outer side of the transistor 211 At least a portion of the pads 202a to 202d is provided so as to overlap with at least a portion of the pads 202a to 202d. It is being done.

[0162] In addition, in FIG. 8A, between the transistor 211 and the pads 202a to 202d, A guard layer 203 is provided.

[0163] In addition, multiple guard layers 203 may be used in combination as appropriate (see FIG. 8(B)). In addition, in plan view, the guard layer 203 may have a circular shape as shown in FIG. 9(B) or a triangle as shown in FIG. It may be a rectangular shape or a polygonal shape as shown in FIG. 10(B).

[0164] The guard layer 203 may be electrically connected to the guard layer 103 .

[0165] [Cross-sectional structure example] As an example of the cross-sectional configuration of the circuit region 102, the portion L1-L2 shown by the dashed line in FIG. 11A is a cross-sectional view of the semiconductor device. For parts not specified, the explanations of other embodiments are used. Layers below the insulating layer 141 are omitted.

[0166] [Transistor 211] The transistor 211 has a structure similar to that of the transistor 201. An insulating layer 149 is formed on the electrodes 113a and 113b. The insulating layer 149 can be formed using the same material and method as the insulating layer 405. The pad 202c is formed by removing a part of the insulating layer 149. In the opening, the electrode 113a is electrically connected to the contact plug 115a. The pad 202c can be formed using the same material and method as the electrode 287.

[0167] [Guard Layer 203] An enlarged view of the guard layer 203 shown in Figure 11(A) is shown in Figure 11(B). Guard Layer The guard layer 103 has a structure in which a layer 203b is stacked on a layer 203a. Similarly, layer 203a is formed from the same material and in the same manner as semiconductor layer 242a. The layer 203b can be formed simultaneously using the same material and method as the semiconductor layer 242b. Therefore, the guard layer 242b can be formed at the same time as the semiconductor layer 242b. The layer 203 is formed on the protruding portion of the insulating layer 145. Either of the 03b's may be omitted.

[0168] Furthermore, impurities may be introduced into the guard layer 203 to reduce the resistance of the guard layer. The introduction of the impurity is performed using an ion implantation device, an ion doping device, or a plasma treatment device. The guard layer 203 can be formed in a plasma atmosphere of inert gas or nitrogen gas. The resistance of the guard layer 203 may be reduced by exposing it to air.

[0169] The guard layer 203 may be floating, or may be connected to VSS, GND, or A specific potential such as a common potential may be supplied to the guard layer 203. The guard layer 203 may be electrically connected to the substrate 101. The guard layer 203 may also be connected to the source of the transistor. The thickness of the layer 203 may be between 2 nm and 20 nm.

[0170] [Variation 1] As shown in the cross-sectional views of FIGS. 12(A) and 12(B), the guard layer 203 is formed on the layer 203 The conductive layer 121c may be a laminate of the electrode 1a, the layer 203b, and the conductive layer 121c. Electrodes 121a and 121b are formed using the same materials and methods as electrodes 21a and 121b. can be formed simultaneously.

[0171] Also, the resistivity of the conductive layer 121c is higher than the resistivity of the layer 203b and / or the layer 203a. By providing such a conductive layer 121c, the manufacturing process of the semiconductor device can be simplified. This can facilitate the conduction of charges generated during the process to layer 203b and / or layer 203a. Therefore, ESD occurring during the manufacturing process of the semiconductor device can be prevented or reduced.

[0172] [Variation 2] As shown in FIG. 13, the electrode 113e formed on the insulating layer 148 is connected to the contact plug 11 The electrode 113e may be electrically connected to the conductive layer 121c via the electrode 113a. The electrodes 113a and 113b can be formed simultaneously using the same materials and methods. The contact plug 112e is formed by the contact plug 112a and the contact plug 112b. They can be formed at the same time using the same materials and methods as those described above.

[0173] An electrode is independently formed on the layer where a conductive material such as wiring or an electrode is provided, and the layer 203b and and / or the layer 203a, thereby forming the guard layer 203 three-dimensionally. By forming the guard layer 203 three-dimensionally, the manufacturing process of the semiconductor device can be completed. This can make it easier to guide the charge generated therein to layer 203b and / or layer 203a. Therefore, the effect of preventing or reducing ESD occurring during the manufacturing process of a semiconductor device is improved. It is possible.

[0174] <Example of manufacturing method> A transistor 211, which is one of the semiconductor devices included in the circuit region 102, and a guard layer An example of a manufacturing method of 203 will be described with reference to the drawings. 1 is a cross-sectional view of the portion L1-L2 indicated by the dashed line in FIG. The manufacturing process after the formation of the insulating layer 141 will be illustrated.

[0175] First, the insulating layer 141 is formed using an insulating material that is difficult for impurities to permeate. Next, a conductive layer is formed over the insulating layer 141. A resist mask is formed on the surface (not shown). The resist mask is formed by photolithography. The resist mask can be formed by a suitable method such as a drawing method, a printing method, or an ink-jet method. When forming the pattern by printing or inkjet method, no photomask is used, so manufacturing costs are reduced. This can reduce the

[0176] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. The exposed area (or the unexposed area) is exposed to light through the mask and then developed. The light irradiated onto the photosensitive resist is KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. There is also the immersion technique, where exposure is performed by filling the space between the substrate and the projection lens with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used instead of the light. When an electron beam or an ion beam is used, a photomask is not required.

[0177] Using the resist mask as a mask, a part of the conductive layer is selectively removed. The removal (etching) can be done by dry etching or wet etching, or both. After that, the resist mask is removed and the electrode 119 is formed (FIG. 14( See A). ).

[0178] The resist mask is removed by dry etching such as ashing or by using a special remover. This can be done by wet etching using a dry etching method. Both the ion channeling method and the chiming method may be used.

[0179] Subsequently, the insulating layer 142 is formed to cover the electrode 119. In this embodiment, the insulating layer 142 Next, CMP processing is performed to remove the irregularities on the surface of the insulating layer 142. The CMP process may be performed until the surface of the electrode 119 is exposed (see FIG. 14). See (B). ).

[0180] Next, an insulating layer 143 is formed, an insulating layer 144 is formed on the insulating layer 143, and the insulating layer 144 In this embodiment, the insulating layer 143 is formed of silicon oxynitride. The insulating layer 145 is made of silicon oxynitride containing excess oxygen. Moreover, hafnium oxide is used as the insulating layer 144 (see FIG. 14(C)).

[0181] Next, the semiconductor layer 124a is formed on the insulating layer 145, and the semiconductor layer 124b is formed on the semiconductor layer 124a. Then, a conductive layer 125 is formed on the semiconductor layer 124b (see FIG. 14(D)).

[0182] In this embodiment, the semiconductor layer 124a is formed by sputtering. Using a target with an atomic ratio of n=1:3:4, oxides containing In, Ga, and Zn were The semiconductor layer 124b is formed using a material of In:Ga:Zn=1:1:1. An oxide semiconductor containing In, Ga, and Zn is formed using a target having a molecular ratio of In, Ga, and Zn. The oxygen doping treatment may be performed after the formation of the semiconductor layer 124a. After the formation of 4b, oxygen doping treatment may be carried out.

[0183] Next, impurities such as moisture or hydrogen contained in the semiconductor layer 124a and the semiconductor layer 124b are removed. In order to further reduce the amount of fluorine and to highly purify the semiconductor layers 124a and 124b, It is preferable to carry out a heat treatment.

[0184] For example, under a reduced pressure atmosphere, under an inert atmosphere such as nitrogen or a rare gas, under an oxidizing atmosphere, or under an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring-down laser spectroscopy) dew point meter) The moisture content when the air is cooled is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The oxide semiconductor layer 124a and the oxide semiconductor layer 124b are heated in an atmosphere of air, preferably 10 ppb or less. The conductor layer 124b is subjected to a heat treatment. The oxidizing atmosphere is oxygen, ozone, or nitriding acid. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases such as oxygen. The above oxidizing gases are less than 10 ppm, and the atmosphere is filled with nitrogen or rare gases. Be careful.

[0185] Furthermore, by performing a heat treatment, the impurities are released and the oxygen contained in the insulating layer 145 is also removed. The oxygen vacancies contained in the semiconductor layers 124a and 124b are diffused into the semiconductor layers 124a and 124b. After the heat treatment in an inert atmosphere, the desorbed oxygen is replenished. To prevent this, heat treatment is carried out in an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more. Note that the heat treatment may be performed after the formation of the semiconductor layers 124a and 124b. For example, after the semiconductor layer 242a and the semiconductor layer 242b are formed, A heat treatment may be performed.

[0186] The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will result in a decrease in productivity. Therefore, it is not desirable.

[0187] In this embodiment, the conductive layer 125 is formed of tungsten by a sputtering method. do.

[0188] Next, a resist mask (not shown) is formed over the conductive layer 125. The formation can be carried out by appropriately using a photolithography method, a printing method, an inkjet method, etc. If a resist mask is formed by printing or inkjet printing, it is not possible to use a photomask. Therefore, manufacturing costs can be reduced.

[0189] Using the resist mask as a mask, a part of the conductive layer 125 is selectively removed, and the conductive layer 125 is The conductive layer 121 and the conductive layer 121c are formed. Using this as a mask, parts of the semiconductor layer 124b and the semiconductor layer 124a are selectively removed. At this time, a part of the insulating layer 145 may be removed, and a protrusion may be formed on the insulating layer 145. The conductive layer 125, the semiconductor layer 124b, and the semiconductor layer 124a are removed (etched) by Either dry etching or wet etching may be used, or both may be used. The semiconductor layer 242a, the semiconductor layer 242b, the layer 203a, the layer 203b, the conductive layer 121, Furthermore, a conductive layer 121c is formed (see FIG. 15A).

[0190] Next, a resist mask 135 is formed to cover the conductive layer 121, and the conductive layer 121c is removed. (See FIG. 15(B)). Next, leaving the resist mask 135, the layers 203a and and / or layer 203b, by introducing impurities 225 into layer 203a and / or layer 203b. The impurity 225 may be introduced by an ion implantation device, an ion doping device, or the like. Alternatively, the layer 203a and / or the layer 203b may be formed by using a plasma treatment device. By exposing the layer 203a and the layer 203b to a plasma atmosphere of an inert gas or nitrogen gas, The resist mask is then removed.

[0191] Next, the insulating layer 127 is formed. In this embodiment, the insulating layer 127 is formed by plasma CVD. After the insulating layer 127 is formed, silicon oxynitride is formed by a method. In order to further reduce impurities such as moisture or hydrogen, a heat treatment may be carried out. The insulating layer 127 may be an insulating layer containing excess oxygen. A flopping process may also be performed.

[0192] Next, tungsten is formed as a layer 131 on the insulating layer 127 (see FIG. 15(C)). ) Also, a part of the layer 131 is selected using a photolithography process, an etching process, or the like. The hard mask 132 is formed by selectively removing the remaining film (see FIG. 15(D)).

[0193] Next, a portion of the insulating layer 127 is selectively removed using the hard mask 132 as a mask. , an opening 122 is formed (see FIG. 16(A)). The aspect ratio (here, the ratio of the depth of the opening 122 to the width of the opening 122) is In order to achieve a sufficient opening, it is preferable to use an anisotropic dry etching method.

[0194] Furthermore, when the opening 122 is formed, the area of ​​the conductive layer 121 that overlaps with the opening 122 is removed, and the electrode 12 As described above, the electrode 121a and the electrode 121b of the semiconductor layer 242b are formed. The region 269 sandwiched between the electrode 121a and the electrode 121b can function as a channel forming region. The region 269 overlaps with the opening 122. In the region 269, the surface of the semiconductor layer 242b and the Therefore, depending on the etching conditions, the side surface of the semiconductor layer 242a is exposed. These exposed portions may be etched away.

[0195] Furthermore, when the etching for forming the opening 122 is performed by dry etching, the exposed semiconductor The surface and side surfaces of the conductor layer 242b and the side surfaces of the semiconductor layer 242a are covered with residual etching gas. For example, if chlorine-based gas is used as an etching gas, impurity elements such as distillate components may adhere to the surface. If a hydrocarbon-based etching gas is used, chlorine may adhere to the surface. When gas is used, carbon, hydrogen, etc. may adhere.

[0196] Therefore, after the opening 122 is formed, impurities adhering to the surface and side surfaces of the exposed semiconductor layer It is preferable to reduce the amount of impurities. The reduction of impurities can be achieved by, for example, washing with diluted hydrofluoric acid. This can be done by cleaning, ozone cleaning, or ultraviolet cleaning. It is also possible to combine multiple cleaning treatments.

[0197] Next, a semiconductor layer 124c is formed on the semiconductor layer 242b and the hard mask 132, and the semiconductor layer 124c is In this embodiment, the insulating layer 128 is formed on the semiconductor layer 124c. The oxide semiconductor containing In, Ga, and Zn is used, similar to the semiconductor layer 242a. Then, silicon oxynitride is formed as the insulating layer 128 by using the plasma CVD method (FIG. 16( Also, the semiconductor layer 124c may be subjected to oxygen doping treatment. The insulating layer 128 may contain excess oxygen. Alternatively, the insulating layer 128 may be subjected to oxygen doping treatment. You may go.

[0198] The semiconductor layer 124c is formed along the bottom and side surfaces of the opening 122. The surface and side surfaces of the semiconductor layer 242b and the side surfaces of the semiconductor layer 242a are covered with the semiconductor layer 124c. .

[0199] By covering the side surfaces of the semiconductor layer 242a and the semiconductor layer 242b with the semiconductor layer 124c, insulation is achieved. The impurity elements generated during the formation of the layer 128 enter the semiconductor layers 242a and 242b. The diffusion of can be reduced.

[0200] Next, a conductive layer 129 for forming an electrode 246 is provided on the insulating layer 128 (FIG. 16( In this embodiment, the conductive layer 129 is a laminate of titanium nitride and tungsten. Specifically, titanium nitride is first formed on the insulating layer 128, and then titanium nitride is formed on the titanium nitride. The conductive layer 129 is formed by, for example, MOCVD. It is preferable to form a conductor by using the MOCVD method or the like, so that the asperity of the surface on which the conductor is formed is reduced. It is possible to fill a recess with a conductor even if the recess has a large area ratio.

[0201] Next, the sample surface is subjected to chemical mechanical polishing (CMP) processing (see FIG. 17(A)). According to the theory, the conductive layer 129, the insulating layer 128, the semiconductor layer 124c, and the insulating layer 127, A portion of each is removed, leaving the electrode 246, the insulating layer 226, the semiconductor layer 242c, and the insulating layer 1 In this way, the electrode 246 is formed using the damascene process. This can be done.

[0202] Next, an insulating layer 146 is formed on the electrode 246, the insulating layer 226, the semiconductor layer 242c, and the insulating layer 146. In this embodiment, the insulating layer 147 is formed by using a sputtering method. Aluminum oxide is formed by sputtering. A portion of the oxygen is introduced into the insulating layer 146 to form a region 207a containing excess oxygen.

[0203] By performing a heat treatment after forming the insulating layer 147, the oxygen (excess oxygen) contained in the region 207a is removed. ) can be introduced into the oxide semiconductor layer. When the insulating layer 147 is formed using an insulating layer containing the insulating material, the insulating layer 147 can be formed by performing a heat treatment after the formation of the insulating layer 147. A part of the oxygen contained in 46 can be introduced into the oxide semiconductor layer.

[0204] In addition, impurities such as aluminum oxide are formed above and below the transistor 211. By providing an insulating layer that is difficult to penetrate, the diffusion of impurities from the outside into the transistor 211 is prevented. This stabilizes the operation of the transistor 211 and improves its reliability. Above and below the sta 211, an insulating layer made of aluminum oxide or the like that is difficult for oxygen to penetrate is installed. By doing so, it is possible to prevent oxygen from being released. Furthermore, the electrical characteristics of the transistor can be improved. Cut.

[0205] Next, an insulating layer 148 is formed on the insulating layer 147. In this embodiment, the insulating layer 148 and Then, silicon oxynitride is formed by plasma CVD (see FIG. 17(B)).

[0206] Next, the insulating layer 148 and the insulating layer 149 are formed by photolithography, etching, etc. 47, selectively removing a portion of the insulating layer 146 to form openings 126a and 126b. (See FIG. 17(C)). The opening 126a overlaps with a part of the electrode 121a. 26b overlaps with a part of electrode 121b.

[0207] Next, the contact plugs 112a and 112b are inserted into the openings 126a and 126b, respectively. Then, a contact plug 112b is formed (see FIG. 17(D)). 2a and contact plug 112b can be fabricated in the same manner as electrode 246.

[0208] Next, a conductive layer is formed on the insulating layer 148, and then subjected to a photolithography process, an etching process, etc. The conductive layer is partially removed using a mask to form electrodes 113a and 113b. The electrode 113a is electrically connected to the electrode 121a via the contact plug 112a. The electrode 113b is electrically connected to the electrode 121b via the contact plug 112b. (See Figure 17(D)).

[0209] Next, an insulating layer 149 is formed on the insulating layer 148, the electrode 113a, and the electrode 113b (FIG. 18 See (A). ).

[0210] Next, a part of the insulating layer 149 is selected using a photolithography process, an etching process, or the like. The opening 137a is selectively removed to form an opening 137a (see FIG. 18(B)). It overlaps with part of 13a.

[0211] Next, a contact plug 115a is formed in the opening 137a (see FIG. 18(C)). The tact plug 136 a can be fabricated in the same manner as the electrode 246 .

[0212] Next, a conductive layer is formed on the insulating layer 149, and then subjected to a photolithography process, an etching process, etc. The conductive layer is selectively removed to form a pad 202c. c is electrically connected to the electrode 113a via a contact plug 115a (see FIG. 18). See (C). ).

[0213] In this way, the transistor 211 and the guard layer 203 can be created. In the manufacturing method described in this embodiment, the electrodes 121a and 121b and the opening 122 The position of the electrode 246 is determined by self-alignment. That is, the electrode 246 functions as a gate electrode, and the electrode 246 functions as either a source or a drain. and an electrode 121b that functions as the other of the source and drain. Therefore, the transistor fabricated by the fabrication method described in this embodiment is The transistor is an SA s-channel FET (Self Align S-channel FET). nnel FET), trench gate s-channel FET, TGSA FET It can also be called (Trench Gate Self Align FET).

[0214] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0215] (Embodiment 3) The transistor 211 shown in plan view in FIG. 7 to FIG. 10 is a TEG (Test Element). When fabricating a transistor as a FET (TFT) and measuring its electrical characteristics, first First, pad 1 is fabricated, and then pads 202a to 202d are fabricated.

[0216] The electrical characteristics are measured by connecting a measurement probe to the pads 202a to 202d. The pads 202a to 202d are connected to the respective terminals (gate terminals) of the transistor 211. Gate terminal (G), Source terminal (S), Drain terminal (D), Backgate terminal (B) In order to facilitate the connection of measurement probes and the like to the pads 202a to 202d, Therefore, the larger the pads 202a to 202d, the better.

[0217] However, if pads 202a to 202d are large, During the manufacturing process of the pad 202d, charges tend to concentrate on the pads 202a to 202d. If any of the pads 202a to 202d accumulates excessive charge, a transistor The excessive voltage across the terminals of transistor 211 can cause ESD damage to transistor 211. Also, depending on the level of electrical damage caused by ESD, In some cases, Zista 211 is completely destroyed.

[0218] In particular, as shown in FIG. 19(A), the sizes of the pads 202a to 202d are If the size of the transistor 211 is large, the transistor 211 may be easily damaged. Therefore, the size of the pad is large compared to the size of the transistor. When evaluating the electrical characteristics using G, the transistor 211 must be protected from electrical damage. It is preferable to provide a protection circuit for protection.

[0219] For example, a capacitance element is added between the gate terminal and the back gate terminal of the transistor 211. For example, if an excessive charge is applied to the pad connected to the gate terminal, Even if the voltage is accumulated, the capacitance element suppresses the voltage rise, and the transistor 211 Therefore, the electrical damage to the transistor 211 can be reduced. This can make it less likely to leak.

[0220] For example, between the gate terminal and the back gate terminal of the transistor 211 and A diode is added between the source terminal and back gate terminal of transistor 211 to form a protection circuit. For example, a diode can be used to connect the pad connected to the gate terminal. Even if excessive charge accumulates, the voltage rise is suppressed by dissipating the charge. This makes it possible to make the transistor 211 less likely to break down.

[0221] In this embodiment, a protection circuit is connected to the transistor 211 to prevent the transistor from being damaged by ESD. An example of a configuration for preventing or reducing the destruction or damage of 211 will be described with reference to the drawings. The protection circuit is connected to transistor 211 before the formation of pads 202a to 202d. It is essential that:

[0222] [Protection circuit configuration example 1] First, an example in which a capacitor is used as a protection circuit will be described. An example will be described in which the gate capacitance of a transistor is used as the element. 2 shows an example of connections between the transistor 211, the pads 202a to 202d, and the capacitance elements. 19(B) shows an equivalent circuit diagram of FIG. 19(A). 19(A) is a cross-sectional view of the portion M1-M2 and the portion N1-N2 indicated by the dashed line in FIG. 19(A). .

[0223] The electrode 246 (gate electrode) of the transistor 211 is connected to the pad 202a via the electrode 113c. The electrode 119 (back gate electrode) of the transistor 211 is electrically connected to the ) is electrically connected to pad 202b via electrode 113d. The first electrode 121a (either the source electrode or the drain electrode) is padded via the electrode 113a. The electrode 121b (source electrode or drain electrode) is electrically connected to the electrode 202c. The other electrode is electrically connected to pad 202d via electrode 113b.

[0224] The electrode 546 (gate electrode) of the transistor 211C is connected to the transistor 211C via the electrode 113c. The electrode 5 of the transistor 211C is electrically connected to the electrode 246 of the transistor 211. 19 (back gate electrode) is connected to the electrode 119 of the transistor 211 via the electrode 113d. The electrode 521a (source electrode or is one of the drain electrodes) and electrode 521b (the other of the source electrode or drain electrode) The electrode 546 is electrically connected to the pad 202d via the electrode 113b. The electrodes 521a and 521b can be formed using the same materials and methods. It can be formed using the same materials and methods as the pole 121a.

[0225] The transistor 211C may be formed using the same materials and methods as the transistor 211. The transistor 211C can be formed through the same process as the transistor 211. Therefore, the pads 202a to 202d function as capacitor elements. Transistor 211C is formed after electrically connecting with transistor 211 (FIG. 20 reference.).

[0226] Note that by providing a capacitor in the transistor 211, The transistor 211 is not only destroyed or damaged during the fabrication of the transistor 211 but also after the fabrication is completed. Scratches can be prevented or reduced.

[0227] [Protection circuit configuration example 2] Next, an example in which a diode is used as a protection circuit will be described. An example using a diode-connected transistor as a diode will be described. A) shows the transistor 211, pads 202a to 202d, and the diode 21(B) is a top view showing a connection example, and FIG. 21(B) is an equivalent circuit diagram of FIG. 22 shows the area M3-M4, area N3-N4, and and a cross-sectional view of the portion N5-N6.

[0228] The electrode 246 (gate electrode) of the transistor 211 is connected to the pad 202a via the electrode 113c. The electrode 119 (back gate electrode) of the transistor 211 is electrically connected to the ) is electrically connected to pad 202b via electrode 113d. The first electrode 121a (either the source electrode or the drain electrode) is padded via the electrode 113a. The electrode 121b (source electrode or drain electrode) is electrically connected to the electrode 202c. The other electrode is electrically connected to pad 202d via electrode 113b.

[0229] The electrode 546a (gate electrode, symbol not shown) of the transistor 211D1 is connected to the electrode 51 3a and is electrically connected to the electrode 519a (back gate electrode) of the transistor 211D1. The electrode 519a of the transistor 211D1 is connected to the transistor 211D2 via the electrode 113d. It is electrically connected to the electrode 119 of the transistor 211. The electrode 521c (either the source electrode or the drain electrode, the symbol is not shown) of the first electrode 13a. Also, the electrode 521d (source electrode) of the transistor 211D1 is electrically connected to the The other of the source electrode and the drain electrode (the reference symbol is not shown) is electrically connected to the electrode 113c. It is being done.

[0230] The electrode 546b (gate electrode) of the transistor 211D2 is connected to the transistor 211D1 via the electrode 513b. It is electrically connected to the electrode 519b (back gate electrode) of the transistor 211D2. The electrode 519b of the transistor 211D2 is connected to the The electrode 521e ( The source electrode or the drain electrode of the transistor 211 is connected to the electrode 113b. The electrode 521f ( The other of the source electrode and the drain electrode is connected to the transistor 211D2 via the electrode 513b. The electrode 546a and the electrode 546b are electrically connected to the electrode 519b (back gate electrode). The electrode 546b can be formed using the same material and method as the electrode 246. c, electrodes 521d, 521e, and 521f are made of the same material as electrode 121a and It can be formed by the following method.

[0231] The transistor 211D1 and the transistor 211D2 are the same as the transistor 211. The transistor 211D1 and the transistor 211D2 can be formed by using the material and the method. The transistor 211D2 can be formed through the same process as the transistor 211. , pads 202a to 202d are connected to transistor 211, which functions as a diode. D1 and transistor 211D2 functioning as a diode are connected to transistor 211. This is formed after the electrodes are electrically connected (see FIG. 22(A)).

[0232] Note that by providing a diode in the transistor 211, the pads 202a to 202c can be Not only during the fabrication of 2d, but also after the fabrication is completed, destruction or Damage can be prevented or reduced.

[0233] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0234] (Fourth embodiment) <Example of transistor structure> In this embodiment, the transistor 201 and the transistor 21 shown in the above embodiment are An example of a transistor structure that can be used in the present invention is shown below. Various types of transistors, such as gate-type transistors and top-gate transistors, It can be prepared using

[0235] It should be noted that the parts not explained in this embodiment can be understood by taking into consideration the other embodiments. This can be done.

[0236] FIG. 23A is a top view of the transistor 221. FIG. 23B is a top view of the transistor 221. FIG. 23(C) is a cross-sectional view of the portion L1-L2 indicated by the dashed dotted line (cross-sectional view in the channel length direction). ) is a cross-sectional view of the portion W1-W2 indicated by the dashed line in FIG. 23(A) (cross-section in the channel width direction). Figure).

[0237] The transistor 221 has a semiconductor layer 242b formed on a semiconductor layer 242a. 242b, and the semiconductor layer 242a is covered with the semiconductor layer 242c. The transistor 221 has an electrode 246 that can function as a gate electrode, a back gate electrode, and a The electrode 119 can function as a

[0238] After the electrodes 121a and 121b are formed, the transistor 221 is formed by forming the semiconductor layer 242a and the The insulating layer 226 is laminated in an island shape. An electrode 246 is formed on the insulating layer 226. The insulating layer 146 is formed to cover the electrode 246. The transistor 221 is a It is a transistor with a channel structure.

[0239] FIG. 24(A) is a top view of the transistor 231. FIG. 24(B) is a top view of the transistor 231. FIG. 24(C) is a cross-sectional view of the portion L1-L2 indicated by the dashed dotted line (cross-sectional view in the channel length direction). ) is a cross-sectional view of the portion W1-W2 indicated by the dashed line in FIG. 24(A) (cross-section in the channel width direction). Figure).

[0240] The transistor 231 is a type of bottom-gate transistor having a back gate electrode. In the transistor 231, an electrode 246 is formed over the insulating layer 143. An insulating layer 226 is provided to cover the electrode 246. The semiconductor layer 242 included in the transistor 231 is a semiconductor A conductor layer 242a and a semiconductor layer 242b are stacked.

[0241] In addition, the electrode 113a and the electrode 113b are formed on the insulating layer 226 in contact with a part of the semiconductor layer 242. In addition, the electrode 113a and the electrode 113b are formed in contact with a part of the semiconductor layer 242. An insulating layer 146 is formed on the insulating layer 13b. An insulating layer 147 is formed on the insulating layer 146. An electrode 119 is formed on the insulating layer 147 in a region overlapping with the semiconductor layer 242. It is being done.

[0242] The electrode 119 provided on the insulating layer 147 is connected to the insulating layer 226, the insulating layer 146, and the insulating layer The openings 247a and 247b in the electrode 246 are electrically connected to the electrode 246. Therefore, the same potential is supplied to the electrode 119 and the electrode 246. It is not necessary to provide either the opening 247a or the opening 247b. It is not necessary to provide both the opening 247a and the opening 247b. If no electrode is provided, different potentials can be applied to the electrode 119 and the electrode 246 .

[0243] [Energy band structure of semiconductor layer 242] FIG. 25(B) shows the energy band structure of the portion indicated by the dashed line B1-B2 in FIG. 24(B). FIG. 25(B) shows the energy band of the channel formation region of the transistor 231. The structure is shown.

[0244] In FIG. 25(B), Ec384 indicates the energy of the bottom of the conduction band of the insulating layer 146. By forming the semiconductor layer 242 into two layers, the semiconductor layer 242a and the semiconductor layer 242b, a transistor In addition, since the semiconductor layer 242c is not provided, the trap level 390, but the semiconductor layer 242 is more susceptible to the influence of the electric field 390 than when the semiconductor layer 242 has a single layer structure. Effective mobility can be achieved.

[0245] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a highly integrated semiconductor device can be provided.

[0246] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0247] (Embodiment 5) In this embodiment, an example of a semiconductor circuit that can be provided in the circuit region 102 will be described. In this embodiment, the p-channel transistor is the same as that in the above embodiment. A transistor 291 shown in FIG. 1 can be used. The transistor 201 or the like described in the above embodiment can be used as the transistor.

[0248] <Example of semiconductor circuit configuration> The circuit area 102 includes logic circuits such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit. logic circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits , encoder circuits, decoder circuits, amplifier circuits, analog switch circuits, integrator circuits, differential circuits Various semiconductor circuits such as a semiconductor device, a memory device, etc. can be provided. A conductor circuit can also be considered a semiconductor device. An example of a semiconductor circuit is shown in FIGS. 26(A) to 26(C). show.

[0249] The CMOS circuit shown in FIG. 26(A) includes a p-channel transistor 281 and an n-channel transistor The transistors 282 are connected in series and the gates of the transistors 282 are connected together. 1 shows an example of a circuit configuration.

[0250] The CMOS circuit shown in FIG. 26(B) includes a p-channel transistor 281 and an n-channel transistor 2 shows an example of the configuration of an analog switch circuit in which the transistors 282 are connected in parallel.

[0251] The CMOS circuit shown in FIG. 26(C) includes a transistor 281a, a transistor 281b, 2 shows an example of the configuration of a NAND circuit using a transistor 282a and a transistor 282b. The NAND circuit is a combination of the potentials input to the input terminals IN_A and IN_B. The output potential changes depending on the combination.

[0252] [Storage device] A memory device can also be provided in the circuit area 102. An example is shown in Figure 27(A) and Figure 27(B). The circuit shown in Figure 27(A) is a transistor. Either the source or drain of the capacitor 289 is connected to the gate of the transistor 1281 and the capacitor element 27(B) shows an example of the configuration of a memory device connected to one electrode of the element 257. In the circuit shown, one of the source and drain of the transistor 289 is connected to one of the capacitors 257. 1 shows an example of the configuration of a memory device connected to one electrode.

[0253] The circuits shown in FIGS. 27(A) and 27(B) are connected to the source or drain of the transistor 289. The charge input from the other input can be held at node 256. By using a transistor using an oxide semiconductor as the first transistor, the It can hold a charge of 6.

[0254] In FIG. 27A, a p-channel transistor is shown as the transistor 1281. However, an n-channel transistor may be used. Therefore, the transistor 281 or the transistor 282 may be used. 1281, a transistor using an oxide semiconductor in a semiconductor layer where a channel is formed is used. It's fine.

[0255] Here, the semiconductor device (memory device) shown in FIGS. 27(A) and 27(B) will be described in detail. Let me explain in detail.

[0256] The semiconductor device shown in FIG. 27A includes a transistor 1281 using a first semiconductor and a second The semiconductor device includes a transistor 289 and a capacitor 257 .

[0257] The transistor 289 is a transistor including an oxide semiconductor disclosed in the above embodiment. Since the off-state current of the transistor 289 is small, It is possible to retain memory contents for a long period of time, i.e., no refresh operation is required. This reduces power consumption by eliminating or minimizing the frequency of refresh operations. This results in a low-power semiconductor device.

[0258] In FIG. 27A, a wiring 251 is connected to one of the source and drain of a transistor 1281. The wiring 252 is electrically connected to the other of the source and drain of the transistor 1281. The wiring 253 is electrically connected to the source or drain of the transistor 289. The wiring 254 is electrically connected to the gate of the transistor 289. The gate of transistor 1281, the source of transistor 289, or The other of the drain and one of the electrodes of the capacitor 257 are electrically connected to a node 256. In addition, the wiring 255 is electrically connected to the other electrode of the capacitor 257.

[0259] The semiconductor device shown in FIG. 27A has a characteristic of being able to hold charge applied to the node 256. By having this, it is possible to write, hold, and read information as shown below.

[0260] [Write operation, hold operation] Writing and holding of data will be described. First, the potential of the wiring 254 is set to the value of 289 is turned on. As a result, the potential of the wiring 253 is changed to the node 256. That is, a predetermined charge is applied to the node 256 (write). The charges that give two different potential levels (hereinafter referred to as "Low-level charge" and "High-level charge") Then, the potential of the wiring 254 is set to By setting the potential at which the transistor 289 is turned off, charge is held at the node 256 .

[0261] Note that the high level charge provides a higher potential to the node 256 than the low level charge. When a p-channel transistor is used as the transistor 1281, Both the high-level charge and the low-level charge are greater than the threshold voltage of the transistor. The transistor 1281 is an n-channel transistor. When a transistor is used, both the high-level charge and the low-level charge are stored in the transistor. The potential is lower than the threshold voltage of the transistor. Both of these charges provide a potential that turns the transistor off.

[0262] Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is maintained for a long period of time. It is held as such.

[0263] [Read operation] Next, the reading of information will be described. With a potential (constant potential) applied, the wiring 255 is supplied with a read potential V R Given node 256 The information stored in the

[0264] The potential given by the high-level charge is V H , the voltage given by the low level charge V place L Then, the readout potential V R is {(Vth-V H )+(Vth+V L )} / 2 When data is not being read, the potential of the wiring 255 is If a p-channel transistor is used in 1281, V H A higher potential is used, and the transistor When using an n-channel transistor for the 1281, V L If we use a lower potential, stomach.

[0265] For example, when a p-channel transistor is used as the transistor 1281, The Vth of the 1281 is -2V, and V H to 1V, V L If we set it to -1V, then V R -2V The potential written to node 256 is V H When V is connected to wire 255, R is given When this occurs, the gate of transistor 1281 is connected to V R +V H , i.e., -1V is applied. Since -1V is higher than Vth, the transistor 1281 is not turned on. The potential of the wiring 252 does not change. L When Wiring 255 to V R is applied to the gate of transistor 1281. R +V L , that is, Since -3V is lower than Vth, transistor 1281 is turned on. As a result, the potential of the wiring 252 changes.

[0266] In addition, when an n-channel transistor is used as the transistor 1281, The Vth of the 1281 is 2V, and V H to 1V, V L If we set it to -1V, then V R Let's set it to 2V. The potential written to node 256 is V H When V is connected to wire 255, R is given and V is applied to the gate of transistor 1281. R +V H , i.e., 3V is applied. 3V is V th, the transistor 1281 is turned on. The potential written to node 256 changes to V L When V is connected to wire 255, R is applied to the gate of transistor 1281. R +V L , i.e., 1 V is applied Since 1V is lower than Vth, the transistor 1281 does not turn on. The potential of the wiring 252 does not change.

[0267] By determining the potential of the wiring 252, the data stored in the node 256 can be read. can be done.

[0268] The semiconductor device shown in FIG. 27B differs from the semiconductor device shown in FIG. 27A in that it does not include the transistor 1281. In this case, the operation is the same as that of the semiconductor device shown in FIG. It is possible to write and retain more information.

[0269] The reading of data in the semiconductor device shown in FIG. 27B will be described. When a potential that turns on the transistor 289 is applied to the wiring 253 and the capacitor 257 are electrically connected, and charge is redistributed between the wiring 253 and the capacitor 257 . As a result, the potential of the wiring 253 changes. The amount of change in the potential of the wiring 253 is Depending on the potential (or charge stored at node 256), it takes on different values.

[0270] For example, the potential of the node 256 is V, the capacitance of the capacitor 257 is C, and the capacitance of the wiring 253 is If the component is CB and the potential of the wiring 253 before the charge redistribution is VB0, The potential of the wiring 253 after this is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is such that the potential of the node 256 is V1 and V0 (V1>V0). If the potential V1 is held in one state, the potential of the wiring 253 (=(CB × VB0+C×V1) / (CB+C)) is the voltage of the wiring 253 when the potential V0 is maintained. It can be seen that it is higher than the first place (=(CB×VB0+C×V0) / (CB+C)).

[0271] Then, by comparing the potential of the wiring 253 with a predetermined potential, information can be read out. .

[0272] The semiconductor device described above is a transistor using an oxide semiconductor and having extremely low off-state current. By applying this, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary, or the frequency of refresh operations can be reduced significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (but the potential is preferably fixed), It is possible to retain the stored contents.

[0273] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as a conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem, and the reliability of this semiconductor device has been dramatically improved. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0274] 〔CPU〕 A CPU can also be provided in the circuit area 102. FIG. 28 is a block diagram showing an example of the CPU configuration. Figure.

[0275] The CPU shown in FIG. 28 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and ROM interface 1189 are Of course, the CPU shown in FIG. 28 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 28 is considered as one core, and a configuration including multiple such cores is considered as one core. It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be a bit or the like.

[0276] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0277] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0278] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0279] In the CPU shown in FIG. 28, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0280] In the CPU shown in FIG. 28, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the storage elements in register 1196 are supplied with a power supply voltage. If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0281] FIG. 29 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 730 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A non-volatile circuit 702, a switch 703, a switch 704, a logic element 706, and The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708 includes a transistor 709 and a transistor 710. 730 may further include other elements such as diodes, resistors, inductors, etc., as needed. It may have.

[0282] Here, the above-described memory device can be used for the circuit 702. When the supply of the power supply voltage is stopped, the gate of the transistor 709 in the circuit 702 is supplied with the ground potential ( 0 V), or a potential at which the transistor 709 is turned off is continuously input. The gate of the transistor 709 is grounded via a load such as a resistor.

[0283] The switch 703 is configured using a transistor 713 of one conductivity type (for example, n-channel type). The switch 704 is of the opposite conductivity type to the transistor 713 (e.g., p-channel type ) transistor 714 is used. The terminal corresponds to one of the source and drain of the transistor 713 and the second terminal of the switch 703. The resistor 704 corresponds to the other of the source and drain of the transistor 713, and the switch 703 corresponds to the other of the source and drain of the transistor 713. A control signal RD input to the gate of the transistor 713 controls the voltage between the first terminal and the second terminal. Conduction or non-conduction (i.e., the on or off state of transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The switch 704 is controlled by a control signal RD input to the gate of the transistor 714. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on state of transistor 714) ON or OFF state) is selected.

[0284] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. The other end is electrically connected to the gate of the transistor 710. One of the source and drain of the transistor 710 is connected to a low power supply potential. The other end is electrically connected to a wiring (for example, a GND line) that can be connected to the switch 703. It is electrically connected to the first terminal (one of the source and drain of the transistor 713). The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is 704 (one of the source and drain of the transistor 714) The second terminal of the switch 704 (the other of the source and drain of the transistor 714) is The first switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. 2 terminal (the other of the source and drain of the transistor 713) and the first terminal of the switch 704. a terminal (either the source or drain of the transistor 714), an input terminal of the logic element 706, The connecting portion is electrically connected to one of the pair of electrodes of the capacitor 707. The other electrode of the capacitor 707 is connected to a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential (V DD, etc.) can be input. The other side is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other of the pair of electrodes of the capacitor 708 is supplied with a low power supply potential. The signal is electrically connected to a wiring (for example, a GND line) that can supply power.

[0285] The capacitors 707 and 708 are formed by actively reducing the parasitic capacitance of transistors and wirings. It is also possible to omit it by using it effectively.

[0286] A control signal WE is input to the gate electrode of the transistor 709. The switch 704 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. A conductive or non-conductive state between the terminals is selected, and the first terminal and the second terminal of one switch are connected to each other. When the terminals are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. become.

[0287] The other of the source and drain of the transistor 709 is connected to a data terminal corresponding to the data held in the circuit 701. In FIG. 29, the signal output from the circuit 701 is input to the transistor 709. The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other of the source and drain of the transistor 713 is input to the logic element 70 6, the logical value of which is inverted to become an inverted signal, and is input to the circuit 701 via the circuit 720. Be encouraged.

[0288] In FIG. 29, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input (the other input) is input to the circuit 701 via the logic element 706 and the circuit 720. The second terminal of the switch 703 (transistor The signal output from the other of the source and drain of the capacitor 713 can be inverted in logic value. For example, the signal input from the input terminal may be input to the circuit 701. If there is a node where a signal whose logic value is an inverted version of the signal inputted from the switch 703 is held, The signal output from the second terminal (the other of the source and drain of the transistor 713) is The node can be input.

[0289] The transistor 709 in FIG. 29 is the same as the transistor 201 or the like exemplified in the above embodiment. A control signal WE is input to the gate electrode. The control signal WE2 can be input to the back gate electrode. The signal may be a signal of a constant potential. The constant potential may be, for example, a ground potential GND or a transistor potential. A potential smaller than the source potential of the transistor 709 is selected. This is a potential signal for controlling the threshold voltage of the transistor 709. This can further reduce the drain current when the gate voltage is 0V. The transistor 709 may be a transistor without a second gate.

[0290] In addition, in FIG. 29, among the transistors used in the memory element 730, the transistor The transistors other than 709 are formed on a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a silicon layer or a silicon-based transistor may be used. The memory element 73 can be a transistor in which the channel is formed in the conductive substrate. All transistors used in this device are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the storage element 730 may be a transistor other than the transistor 709. The transistors are classified into two types: a transistor in which the channel is formed in an oxide semiconductor layer and a transistor in which the channel is formed in a semiconductor layer other than an oxide semiconductor. In combination with a transistor in which a channel is formed in a conductive layer or substrate 1190 It may be used.

[0291] For example, a flip-flop circuit can be used for the circuit 701 in FIG. In addition, the logic element 706 may be, for example, an inverter or a clocked inverter. can be done.

[0292] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 730, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. The data can be stored in node M2.

[0293] As described above, a transistor in which a channel is formed in an oxide semiconductor layer has a low off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is extremely small. The off-state current is significantly higher than that of a transistor whose channel is formed in crystalline silicon. Therefore, by using this transistor as the transistor 709, Even while the power supply voltage is not supplied to the memory element 730, the signal held in the capacitor 708 is retained for a long time. In this way, the memory element 730 retains its stored contents even when the supply of power supply voltage is stopped. It is possible to retain data.

[0294] In addition, by providing the switches 703 and 704, after the power supply voltage is restarted, Furthermore, the time required for the circuit 701 to hold the original data again can be shortened.

[0295] In the circuit 702, the signal held at the node M2 ​​is applied to the gate of the transistor 710. Therefore, after the supply of the power supply voltage to the storage element 730 is resumed, the node M 2, the state (on or off) of transistor 710. is determined and can be read out from the circuit 702. Therefore, the signal held at node M2 Even if the potential corresponding to the signal fluctuates slightly, the original signal can be read out accurately.

[0296] Such a storage element 730 may be used as a storage device such as a register or cache memory of a CPU. By using this in a device, it is possible to prevent the loss of data in the storage device due to a power outage. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire CPU, or one or more logical circuits that make up the CPU, This allows for short-term power outages on roads, increasing the frequency of power outages. , power consumption can be reduced.

[0297] In this embodiment, the storage element 730 is used as a CPU. 0 is DSP (Digital Signal Processor), custom LSI LSIs such as PLDs (Programmable Logic Devices), RF- Can also be applied to ID (Radio Frequency Identification) is.

[0298] [Imaging device] An imaging device can also be provided in the circuit area 102. An example is shown in Figures 30(A) to 30(C).

[0299] An imaging device 610 having the circuit shown in FIG. 30(A) includes a photoelectric conversion element 601, a transistor 602, a transistor 604, and a capacitor 606. One of the source and drain of the transistor 60 is electrically connected to the photoelectric conversion element 601. The other of the source or drain of transistor 602 is connected to transistor 604 via node 607 (charge storage section). It is electrically connected to the gate of 04.

[0300] The transistor 602 is preferably an OS transistor. Since the off-state current of the capacitor can be made extremely small, the capacitor 606 can be made small. Alternatively, as shown in FIG. 30B, the capacitor 606 can be omitted. When an OS transistor is used as the transistor 602, the potential of the node 607 Therefore, it is possible to realize an imaging device that is less susceptible to noise. The transistor 604 may be an OS transistor.

[0301] The photoelectric conversion element 601 is a diode in which a pn-type or pin-type junction is formed on a silicon substrate. Alternatively, an amorphous silicon film or a microcrystalline silicon film may be used. Alternatively, a pin-type diode element or the like may be used. Also, variable resistors utilizing the photoelectric effect may be used. It may also be formed using silicon, selenium, or the like.

[0302] In addition, the photoelectric conversion element uses a material that can absorb radiation and generate electric charges. The material capable of absorbing radiation and generating a charge may be iodide. Examples include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0303] The imaging device 610 having the circuit shown in FIG. 30(C) uses a photodiode as the photoelectric conversion element 601. The imaging device 610 shown in FIG. transistor 601, transistor 602, transistor 603, transistor 604, The transistor 602 has a source or drain of a capacitor 605 and a capacitor 606. One of the electrodes is electrically connected to the cathode of the photoelectric conversion element 601, and the other is electrically connected to the node 607. The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. One of the source and drain of the transistor 603 is electrically connected to a node 607. The other end is electrically connected to a wiring 608. The source or drain is electrically connected to the wiring 609. The other end is electrically connected to one of the source and drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to a wiring 608. One electrode of the capacitor 606 is electrically connected to a node 607, and the other electrode is electrically connected to the wiring 611.

[0304] Transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the transistor 603. The transistor 603 functions as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. Transistor 604 can function as an amplifying transistor. Transistor 605 can function as a selection transistor. The gate of the transistor 605 is supplied with a selection signal SEL. Moreover, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

[0305] Next, the operation of the imaging device 610 having the circuit shown in FIG. Transistor 603 is turned on to supply VDD to node 607 (reset operation After that, when the transistor 603 is turned off, VDD is held at the node 607. Next, when the transistor 602 is turned on, a voltage is applied to the photoelectric conversion element 601 in accordance with the amount of light received. Then, the potential of the node 607 changes (storage operation). When the transistor 605 is turned on, the potential of the node 607 is maintained. Then, a potential corresponding to the potential of the node 607 is output to the wiring 609 (selection operation). By detecting the potential of 609, the amount of light received by the photoelectric conversion element 601 can be known.

[0306] The transistors 602 and 603 are preferably OS transistors. As described above, the off-state current of an OS transistor can be made extremely small. Therefore, the capacitor 606 can be made smaller. Alternatively, the capacitor 606 can be omitted. In addition, the transistors 602 and 603 can be OS transistors. When this is used, the potential of the node 607 is less likely to fluctuate. An imaging device can be realized.

[0307] The imaging device 610 having any of the circuits shown in FIGS. 30(A) to 30(C) is By arranging them in a box-like pattern, a high-resolution imaging device can be realized.

[0308] For example, if the image pickup devices 610 are arranged in a 1920 x 1080 matrix, Resolution of HDTV (also called "2K resolution", "2K1K", "2K") For example, the imaging device 610 can be configured to capture images at 40 When arranged in a 96 x 2160 matrix, it produces what is known as ultra high definition (4K resolution). It is also called "4K2K" or "4K" resolution. In addition, for example, the imaging device 610 can be realized as a 8192×4320 matrix. When arranged in a grid, it produces what is known as super high-definition ("8K resolution," "8K4K," It is possible to realize an imaging device capable of capturing images at a resolution of 8K. By increasing the number of imaging devices 610, an imaging device capable of capturing images at 16K or 32K resolution can be realized. It is also possible.

[0309] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0310] (Sixth embodiment) In this embodiment, examples of applying the semiconductor device described in the above embodiments to electronic components, and Examples of electronic devices equipped with the electronic components will be described with reference to FIGS. 31 and 32. Electronic components are also called semiconductor packages or IC packages. There are multiple standards and names depending on the terminal extraction direction and terminal shape. In this embodiment, an example of an electronic component will be described.

[0311] The electronic component is a semiconductor device according to the above embodiment that is used in an assembly process (post-process). The device is completed by combining components other than the semiconductor device.

[0312] The post-process will be explained using the flowchart shown in Figure 31(A). After the element substrate having the semiconductor device shown in the above embodiment is completed, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step S1). By thinning the element substrate through grinding, warping of the element substrate can be reduced, and electronic components can be It is possible to reduce the size of the device.

[0313] Next, a "dicing process" is performed to separate the element substrate into a plurality of chips (chips 105). Step S2). Then, the separated chips are individually picked up and attached to the lead frame. Then, a "die bonding process" is carried out (step S3). The chip and lead frame are bonded using resin or tape, etc. The appropriate method is selected depending on the product. Note that an interposer substrate is used instead of a lead frame. A chip may be bonded on top.

[0314] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. The wire bonding process is then carried out to connect the wires to the substrate (step S4). Silver wire or gold wire can be used. Wire bonding is also called ball bonding. Alternatively, wedge bonding can be used.

[0315] The wire-bonded chip is sealed with epoxy resin in the "encapsulation process (molding)" The sealing process is then carried out (step S5). It is filled with oil and mechanically connects the circuitry built into the chip and the wires connecting the chip and leads. It can protect the device from external forces and reduce deterioration of characteristics (reduced reliability) caused by moisture and dust. It is possible.

[0316] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step The plating process prevents the leads from rusting and makes it easier to mount the leads on a printed circuit board. The soldering can be done more reliably. Then, the leads are cut and shaped. Then, a "forming process" is carried out (step S7).

[0317] Next, a "marking process" is carried out, in which printing (marking) is applied to the surface of the package. (Step S8) Then, the "inspection process" ( After step S9), the electronic component is completed.

[0318] Using a chip 105 with guard layer 103 and / or guard layer 203 This makes it possible to prevent or reduce ESD damage in the post-processing of electronic components. do.

[0319] A perspective view of the completed electronic component is shown in FIG. 31(B). As an example of a product, a perspective view of a QFP (Quad Flat Package) is shown below. The electronic component 750 shown in FIG. 31(B) has leads 755 and a semiconductor device 753. The semiconductor device 753 may be a semiconductor device described in any of the above embodiments. can be done.

[0320] The electronic component 750 shown in FIG. 31(B) is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined and each is electrically connected to a printed circuit board 752. By connecting the components together, a substrate (mounting substrate 754) on which electronic components are mounted is completed. The mounting board 754 is used in electronic devices and the like.

[0321] Next, referring to FIG. 32, a vehicle (such as a bicycle) driven by power from a fixed power source is provided with a power supply. Examples of applications in which the above electronic components are applied to drive circuits that drive inverters, motors, etc. We will explain about this.

[0322] FIG. 32(A) shows an electric bicycle 1010 as an application example. The electric bicycle is powered by passing an electric current through the motor 1011. 1010 is a storage device 1012 for supplying current to a motor 1011, and In FIG. 32(A), the pedal is Although illustrated, it is not necessary.

[0323] The driver circuit 1013 is provided with an electronic component including the semiconductor device described in the above embodiment. The mounting board is installed. Therefore, it is possible to make an electric bicycle equipped with miniaturized electronic components. It will also be possible to realize electric bicycles with low power consumption and long range. Furthermore, it is possible to realize an electric bicycle with good reliability.

[0324] FIG. 32(B) shows an electric vehicle 1020 as another application example. 20 obtains power by passing current through the motor 1021. The electric vehicle 1020 includes a power storage device 1022 for supplying current to the motor 1021, and and a drive circuit 1023 for driving the motor.

[0325] The driver circuit 1023 is provided with an electronic component including the semiconductor device described in the above embodiment. This allows for the development of electric vehicles with low power consumption and long driving range. Furthermore, it is possible to realize an electric vehicle with good reliability.

[0326] Further, electronic components including the semiconductor device described in the above embodiment can be used not only in electric vehicles (EVs). It is used in hybrid vehicles (HEV) and plug-in hybrid vehicles (PHEV), etc. It is also possible.

[0327] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0328] (Embodiment 7) One embodiment of the present invention can be used in various electronic devices. Specific examples of electronic devices using such semiconductor devices will be described below.

[0329] Examples of electronic devices using a semiconductor device according to one embodiment of the present invention include display devices such as televisions and monitors. , lighting equipment, desktop or notebook personal computers, word processors stored on recording media such as DVD (Digital Versatile Disc) Image playback devices that play still or moving images, portable CD players, radios, tapes Recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets , transceivers, mobile phones, car phones, portable game consoles, tablet terminals, pachinko machines large game consoles such as PCs, calculators, personal digital assistants, electronic organizers, e-book readers, electronic translators, High frequency devices such as voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. Wave heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air Air conditioning equipment such as conditioners, humidifiers, dehumidifiers, dishwashers, dish dryers, and clothes dryers electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, pocket refrigerators Examples include electric lights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots , energy storage systems, industrial equipment such as energy storage devices for power leveling and smart grids Examples include:

[0330] In addition, moving objects propelled by electric motors using power from a power storage device are also included in the category of electronic devices. The above-mentioned mobile units include, for example, electric vehicles (EVs), vehicles with internal combustion engines and electric vehicles (EVs), and Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), These tires and wheels are converted into tracks, and motorized vehicles including electrically assisted bicycles are also available. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples include aircraft, rockets, satellites, space probes, planetary probes, and spacecraft. .

[0331] An example of an electronic device is shown in FIG. 33. In FIG. 33, a display device 8000 is an embodiment of the present invention. 8 is an example of an electronic device using the semiconductor device 8004 according to the present invention. 8000 corresponds to a display device for receiving TV broadcasts, and includes a housing 8001, a display unit 8002, and a speaker unit. 8003, a semiconductor device 8004, a power storage device 8005, and the like. The semiconductor device 8004 is provided inside the housing 8001. This controls the driving of the cooling fan inside the display device 8000 and the adjustment of the light emission brightness. The display device 8000 can also be supplied with power from a commercial power source. Alternatively, power stored in the power storage device 8005 can be used.

[0332] The display unit 8002 includes a liquid crystal display device, an emitting device having a light emitting element such as an organic EL element in each pixel, and Device, electrophoretic display device, DMD (Digital Micromirror Device) ce), PDP (Plasma Display Panel), FED (Field A display device such as a Fluorescence Emission Display can be used.

[0333] In addition to TV broadcast reception, display devices are also used for personal computers and advertising displays. , including all display devices for displaying information.

[0334] In FIG. 33, a stationary lighting device 8100 includes a semiconductor device 8 according to one embodiment of the present invention. 8103. Specifically, the lighting device 8100 includes a housing 8101, It includes a light source 8102, a semiconductor device 8103, a power storage device 8105, and the like. The body device 8103 is installed inside a ceiling 8104 where a housing 8101 and a light source 8102 are installed. However, the semiconductor device 8103 may be provided inside the housing 8101. The semiconductor device 8103 controls the luminance of the light source 8102. The lighting device 8100 can also be supplied with power from a commercial power source. Alternatively, power stored in a power storage device can be used.

[0335] In addition, FIG. 33 shows an example of a fixed lighting device 8100 provided on a ceiling 8104. However, in the semiconductor device according to one embodiment of the present invention, the sidewall 8405, the floor 8406, and the like are not included in the ceiling 8104. 8406, windows 8407, etc., or It can also be used as a tabletop lighting device.

[0336] The light source 8102 may be an artificial light source that artificially obtains light using electricity. Specifically, incandescent lamps, fluorescent lamps and other discharge lamps, and light-emitting devices such as LEDs and organic EL elements The element is an example of the artificial light source.

[0337] In FIG. 33, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is 8A and 8B are examples of electronic devices using a semiconductor device 8203 according to one embodiment of the present invention. The internal unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, a power storage device 820 33, the semiconductor device 8203 is provided in an indoor unit 8200. However, the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can be used in the compressor of an air conditioner. The air conditioner can also be powered by commercial power. The power can be supplied from the power storage device 8205 or can be stored in the power storage device 8205. It is also possible.

[0338] In Figure 33, a separate type air conditioner consisting of an indoor unit and an outdoor unit is shown. As an example, it is an all-in-one air conditioner that has the functions of both the indoor unit and the outdoor unit in a single housing. The semiconductor device according to one embodiment of the present invention can be used for the conditioner.

[0339] In FIG. 33, an electric refrigerator-freezer 8300 includes a semiconductor device 8304 according to one embodiment of the present invention. Specifically, an electric refrigerator-freezer 8300 includes a housing 8301, Refrigerator door 8302, freezer door 8303, semiconductor device 8304, power storage device 8305, etc. In FIG. 33, a power storage device 8305 is provided inside a housing 8301. A motor used in a compressor of an electric refrigerator-freezer 8300 by a conductor device 8304 The electric refrigerator-freezer 8300 can also control the operation of the The power can be supplied or stored in the power storage device 8305 can be used. .

[0340] The portable game machine 2900 shown in FIG. 34(A) includes a housing 2901, a housing 2902, a display unit 2903, and a display unit 2904. 903, display unit 2904, microphone 2905, speaker 2906, operation key 2907 The portable game machine shown in FIG. 34(A) has two display units 2903 and a display The display unit 2903 has a display unit 2904, but the number of display units is not limited to this. A touch screen is provided as an input device, and is operated by a stylus 2908 or the like. The housing 2901 is also provided with a storage device, a CPU, and the like.

[0341] The information terminal 2910 shown in FIG. 34(B) includes a housing 2911, a display unit 2912, a microphone 2913, and a microphone unit 2914. 17, speaker unit 2914, camera 2913, external connection unit 2916, and operation buttons The display unit 2912 includes a display panel using a flexible substrate and It is equipped with a touch screen. In addition, a storage device and a CPU are installed inside the housing 2911. The information terminal 2910 is, for example, a smartphone, a mobile phone, or a tablet-type information terminal. Ultimately, it can be used as a tablet personal computer, an electronic book reader, etc.

[0342] A notebook personal computer 2920 shown in FIG. 34(C) includes a housing 2921, a display unit 2922, a keyboard 2923, and a pointing device 2924. In addition, a storage device, a CPU, etc. are provided inside the housing 2921.

[0343] The video camera 2940 shown in FIG. 34(D) includes a housing 2941, a housing 2942, a display unit 29 43, operation keys 2944, a lens 2945, and a connection part 2946. 2944 and a lens 2945 are provided in the housing 2941, and the display unit 2943 is provided in the housing The housing 2941 and the housing 2942 are connected to a connection portion 2946. The angle between the housing 2941 and the housing 2942 is determined by the connection 2946. The angle of the housing 2942 relative to the housing 2941 can be changed. You can change the orientation of the image displayed on the display unit 2943 and switch between displaying and hiding the image. The housing 2941 also includes a storage device, a CPU, and the like.

[0344] An example of a bangle-type information terminal is shown in FIG. 34(E). The information terminal 2950 has a housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. The display unit 2952 is provided with a display panel using a flexible substrate, It is possible to provide a flexible, lightweight, and easy-to-use information terminal 2950. A storage device, a CPU, etc. are provided inside the housing 2951.

[0345] An example of a wristwatch-type information terminal 2960 is shown in FIG. 34(F). The information terminal 2960 includes a housing 2961, Display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal 2966. In addition, a storage device, a CPU, etc. are provided inside the housing 2961. The information terminal 2960 can be used for mobile phone calls, e-mail, viewing and creating documents, playing music, and internet access. - It can run various applications such as internet communication and computer games. do.

[0346] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by touching the The operation button 2965 is used to set the time. In addition to the settings, it can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation button 2965 You can also set the function.

[0347] The information terminal 2960 is also capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, you can make hands-free calls. The information terminal 2960 is also provided with an input / output terminal 2966, and can be connected to other information terminals. Data can be exchanged directly through the connector. Charging can also be performed via the input / output terminal 2966. It may also be powered by a line.

[0348] FIG. 34(G) shows an electric refrigerator as an example of a household electrical appliance. The electric refrigerator 2970 is It has a housing 2971, a refrigerator door 2972, a freezer door 2973, and the like.

[0349] 34(H) is an external view showing an example of an automobile. The automobile 2980 includes a body 2981, It has wheels 2982, a dashboard 2983, and lights 2984, etc.

[0350] The electronic devices described in this embodiment include the above-described transistors or the above-described semiconductor devices. It is equipped with:

[0351] An electronic device using a semiconductor device according to one embodiment of the present invention can prevent degradation of performance due to ESD and reliability. According to one aspect of the present invention, a highly reliable Electronic devices can be realized.

[0352] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0353] (Embodiment 8) In this embodiment, a structure of an oxide semiconductor will be described.

[0354] <Structure of oxide semiconductors> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned oxide semiconductor (CAAC-OS) crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0355] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0356] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0357] That is, the stable oxide semiconductor is completely amorphous. ) and cannot be called an oxide semiconductor. On the other hand, a-li oxide semiconductors cannot be called completely amorphous oxide semiconductors. The ke OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0358] [CAAC-OS] First, let me explain about CAAC-OS.

[0359] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0360] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in FIG. 35(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0361] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). Even if the peak is increased, no clear peak appears, as shown in Figure 35(B). When φ is scanned with 2θ fixed at around 56° for nO4, the results are as shown in Figure 35(C). As shown in Fig. 1, six peaks are observed that are attributed to the crystal plane equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0362] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in Figure 35(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly is shown in Figure 35(E). As shown in Figure 35(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of pellets in CAAC-OS. It can be seen that the a-axis and b-axis of the dots do not have any orientation. The ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is thought that the second ring in Figure 35(E) is due to the (110) plane, etc. It is possible.

[0363] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0364] Figure 36(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0365] From Figure 36(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0366] 36(B) and 36(C) show the CAAC images observed from a direction approximately perpendicular to the sample surface. Figures 36(D) and 36(E) show Cs-corrected high-resolution TEM images of the -OS surface. These are the images obtained by image processing of Figure 36(B) and Figure 36(C), respectively. First, the fast Fourier transform (FFT) of FIG. Then, the FFT image is obtained by Fourier Transform (FFT). In the FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). Inverse Fast Fourier Transform (FFT) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0367] In Figure 36(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0368] In FIG. 36(E), a lattice pattern is formed between an area with a uniform lattice arrangement and an area with a different uniform lattice arrangement. The dotted lines indicate the change in the orientation of the array, and the dashed lines indicate the change in the orientation of the lattice array. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points to the center, distorted hexagons, pentagons, and / or heptagons are formed. In other words, it was found that the formation of grain boundaries was suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because it is possible to

[0369] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0370] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects ( It can also be said to be an oxide semiconductor with few oxygen vacancies.

[0371] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0372] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0373] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0374] [nc-OS] Next, we will explain nc-OS.

[0375] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0376] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region in parallel to the surface to be formed, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (B) is shown in Figure 37(B). Therefore, nc-OS has a probe diameter of 50 nm. Although the order is not confirmed by irradiating an electron beam, the order is confirmed by irradiating an electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0377] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 37(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0378] Figure 37(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor with a diameter of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (fine microcrystalline oxide semiconductor) For example, in high-resolution TEM images, the grain boundaries of nc-OS can be clearly seen. In addition, the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as a pellet below.

[0379] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0380] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0381] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0382] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0383] Figure 38 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation 38(A) and 38(B) show that the a-like OS It can be seen that bright striped regions extending in the vertical direction are observed from the start of electron irradiation. It can be seen that the bright areas change shape after electron irradiation. It is estimated to be in the degree range.

[0384] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0385] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0386] First, high-resolution cross-sectional TEM images of each sample are acquired. Each of these has a crystalline portion.

[0387] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that it has a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is estimated to be 0.29 nm from crystal structure analysis. Below, the area where the lattice spacing is between 0.28 nm and 0.30 nm is InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0388] Figure 39 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 39, it can be seen that in the early stages of TEM observation, the size of the particles was about 1.2 nm. The crystal part (also called the initial nucleus) that was - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, in the case of nc, the size of the crystals grows to about 1.9 nm. The cumulative electron dose for the -OS and CAAC-OS was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of The size of the crystalline parts of nc-OS and CAAC-OS was It can be seen that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0389] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, compared with nc-OS and CAAC-OS, It is clear that this is an unstable structure.

[0390] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0391] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0392] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0393] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0394] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0395] 101 Substrate 102 Circuit area 103 Guard Layer 104 Separation line 105 chips 106 parts 109 Electrode 114 areas 118 Electrode 119 Electrode 121 Conductive layer 122 Aperture 125 Conductive Layer 127 Insulating Layer 128 Insulating Layer 129 Conductive Layer 131 layers 132 Hard Mask 133 Guard Layer 134 Guard Layer 135 Resist Mask 141 Insulating layer 142 Insulating layer 143 Insulating Layer 144 Insulating Layer 145 Insulating Layer 146 Insulating Layer 147 Insulating Layer 148 Insulating Layer 149 Insulating Layer 201 Transistor 203 Guard Layer 211 Transistor 221 Transistor 225 Impurities 226 Insulating Layer 231 Transistor 242 Semiconductor layer 246 Electrode 251 Wiring 252 Wiring 253 Wiring 254 Wiring 255 Wiring 256 nodes 257 Capacitor 269 ​​areas 281 Transistor 282 transistors 283 Channel formation region 285 High concentration p-type impurity region 286 Insulating Layer 287 Electrode 289 Transistor 291 Transistors 382 Ec 384 Ec 386 Ec 390 trap levels 403 Insulation Layer 405 Insulation Layer 407 Insulating Layer 414 Element isolation layer 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitor element 607 nodes 608 Wiring 609 Wiring 610 Imaging device 611 Wiring 701 circuits 702 circuits 703 Switch 704 Switch 706 Logic Elements 707 Capacitor 708 Capacitor 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 circuits 730 Memory Element 750 Electronic Components 752 Printed Circuit Board 753 Semiconductor Devices 754 Mounting board 755 leads 1010 Electric Bicycle 1011 Motor 1012 Electricity storage device 1013 Drive circuit 1020 Electric Vehicle 1021 Motor 1022 Electricity storage device 1023 drive circuit 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1281 Transistor 2900 handheld game console 2901 Case 2902 Case 2903 Display section 2904 Display section 2905 Microphone 2906 Speaker 2907 Operation Key 2908 Stylus 2910 Information terminal 2911 Case 2912 Display section 2913 Camera 2914 Speaker section 2915 Button 2916 External connection part 2917 Mike 2920 Notebook Personal Computer 2921 Case 2922 Display section 2923 keyboard 2924 Pointing Device 2940 video camera 2941 Case 2942 Case 2943 Display section 2944 Operation Key 2945 Lens 2946 Connection 2950 Information terminal 2951 Case 2952 Display section 2960 Information Terminal 2961 Case 2962 Display section 2963 bands 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 icons 8000 display device 8001 Case 8002 Display section 8003 Speaker section 8004 Semiconductor devices 8005 Electricity storage devices 8100 Lighting equipment 8101 Housing 8102 Light source 8103 Semiconductor devices 8104 Ceiling 8105 Electricity storage devices 8200 indoor unit 8201 Housing 8202 Ventilation outlet 8203 Semiconductor devices 8204 Outdoor unit 8205 Energy storage devices 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigerator door 8303 Freezer door 8304 Semiconductor devices 8305 Energy storage devices 8405 Side wall 8406 floors 8407 Window 103a layer 103b layer 103c layer 112a contact plug 112b contact plug 112c contact plug 112d Contact Plug 112e contact plug 113a electrode 113b Electrode 113c electrode 113d electrode 113e electrode 115a contact plug 121a electrode 121b Electrode 121c conductive layer 124a Semiconductor layer 124b Semiconductor layer 124c Semiconductor layer 126a aperture 126b aperture 136a contact plug 137a aperture 202a Pad 202b Pad 202c pad 202d Pad 203a layer 203b layer 207a area 211C transistor 211D1 transistor 211D2 transistor 242a Semiconductor layer 242b Semiconductor layer 242c Semiconductor layer 247a aperture 247b aperture 281a Transistor 281b transistor 282a Transistor 282b transistor 383a Ec 383b Ec 383c Ec 406a contact plug 406b contact plug 406c contact plug 413a electrode 413b Electrode 413c electrode

Claims

1. a circuit area and a first layer; the first layer is provided around the circuit area; the circuit region includes a first transistor and a second transistor; the first transistor includes a first oxide semiconductor, a first gate insulating film, a first gate electrode, a first source electrode, and a first drain electrode; a channel formation region of the first transistor is provided in the first oxide semiconductor; the second transistor has silicon, a second gate insulating film, a second gate electrode, a second source electrode, and a second drain electrode; the first layer includes a second oxide semiconductor; a channel formation region of the second transistor is provided in the silicon; the second gate insulating film is provided on the silicon; the second gate electrode is provided on the second gate insulating film, a first interlayer insulating film is provided on the second gate electrode; the first oxide semiconductor and the second oxide semiconductor are provided on the first interlayer insulating film and in contact with an upper surface of the same layer; the first gate insulating film is provided on the first oxide semiconductor; the first gate electrode is provided on the first gate insulating film, a second interlayer insulating film is provided on the first gate electrode; a first conductive layer provided on the second interlayer insulating film and a second conductive layer provided on the first interlayer insulating film, the first source electrode or the first drain electrode being electrically connected to the second gate electrode via the first conductive layer and the second conductive layer being provided on the first interlayer insulating film, the second gate electrode being electrically connected to the first oxide semiconductor;

2. In claim 1, The second gate electrode is electrically connected to a capacitance element.

3. In claim 1 or 2, The semiconductor device, wherein the resistance of the second oxide semiconductor is lower than the resistance of the first oxide semiconductor.

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