Image sensor and manufacturing method of the same

Abstract

To provide an image sensor advantageous for a pixel miniaturization and a manufacturing method of the same.SOLUTION: An image sensor includes: a substrate having a first surface and a second surface facing each other; an anti-reflection structure disposed on the second surface; a substrate isolation part separating the substrate; and a backside contact disposed in a backside contact trench penetrating the anti-reflection structure and contacting the substrate isolation part. The backside contact includes: a contact conductive pattern on a sidewall of the backside contact trench; and a contact metal pattern disposed on the contact conductive pattern. The anti-reflection structure includes: a first insulating layer; a high refractive layer on the first insulating layer; and a contact break provided between the high refractive layer and the backside contact.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for manufacturing the same, and more particularly to a CMOS image sensor and a method for manufacturing the same. [Background technology]

[0002] An image sensor is a semiconductor device that converts optical images into electrical signals. With the recent development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in various fields, including digital cameras, video cameras, PCS (Personal Communication Systems), game consoles, security cameras, and medical micro cameras.

[0003] As semiconductor devices become more highly integrated, image sensors are also becoming more highly integrated. As a result, the size of each pixel is becoming smaller. Therefore, image sensors with low crosstalk and high sensitivity in a small area are required.

[0004] The structure uses a highly refractive material for the bottom anti-reflective layer (BARL) of the image sensor, and requires a reduction in leakage current from the adjacent wiring. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent No. 11,362,130 B2 Summary of the Invention [Problem to be solved by the invention]

[0006] A technical problem to be solved by the present invention is to provide an image sensor that is advantageous for pixel miniaturization and a method for manufacturing the same.

[0007] SUMMARY OF THE INVENTION One technical object of the present invention is to provide an image sensor having improved sensitivity and a method for manufacturing the same.

[0008] Another technical problem to be solved by the present invention is to provide an image sensor that can be easily highly integrated and a method for manufacturing the same. [Means for solving the problem]

[0009] The image sensor according to the present invention includes a substrate having a first surface and a second surface facing each other, the substrate including a pixel array region and an edge region; an anti-reflection structure disposed on the second surface; a substrate isolation portion disposed in the substrate and isolating the substrate; a microlens on the anti-reflection structure; and a back contact disposed in a back contact trench penetrating the anti-reflection structure and in contact with the substrate isolation portion, the back contact including a contact conductive pattern on a sidewall of the back contact trench and a contact metal pattern disposed on the contact conductive pattern. The anti-reflection structure may include a first insulating film, a high refractive index layer on the first insulating film, and a contact disconnection portion interposed between the high refractive index layer and the back contact.

[0010] The image sensor according to the present invention includes a substrate having a first surface and a second surface facing each other, the substrate including a pixel array region and an edge region, an anti-reflection structure disposed on the second surface, a microlens on the anti-reflection structure, a first back via pattern penetrating the anti-reflection structure and the substrate in the edge region, a first interlayer insulating film disposed on the first surface of the substrate, a first wiring layer disposed in the first interlayer insulating film, a second interlayer insulating film disposed below the first interlayer insulating film, and a second wiring layer disposed in the second interlayer insulating film, and the anti-reflection structure may include a first insulating film, a high refractive index layer on the first insulating film, and a via cutoff portion disposed between the high refractive index layer and the first back via pattern.

[0011] an anti-reflection structure disposed on the second surface; a substrate isolation portion disposed within the substrate to isolate the substrate; a microlens on the anti-reflection structure; and a back contact disposed in a back contact trench penetrating the anti-reflection structure and in contact with the substrate isolation portion, the back contact including a contact conductive pattern on a sidewall of the back contact trench and a contact metal pattern disposed on the contact conductive pattern; the anti-reflection structure including a first insulating film, a high refractive index layer on the first insulating film, and a contact discontinuity portion disposed between the high refractive index layer and the back contact, the back contact including a contact protrusion protruding from the contact discontinuity portion. [Effects of the Invention]

[0012] According to the concept of the present invention, the image sensor may have a cutout between the rear contact and the high refractive index layer, in which case the rear contact and the high refractive index layer of the image sensor may be spaced apart, forming an electrical short structure.

[0013] According to the concept of the present invention, by disposing a discontinuity between the back contact and the high refractive index layer, electrical leakage paths can be blocked and the optical performance of the image sensor can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Figure 2] 1 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the present invention. [Figure 3] 1 is a plan view of an image sensor according to some embodiments of the present invention; [Figure 4]FIG. 4 is a cross-sectional view taken along line AA' in FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of X in FIG. 4. [Figure 6] FIG. 5 is an enlarged cross-sectional view of Y in FIG. 4. [Figure 7A] 5 is a cross-sectional view illustrating an image sensor according to some embodiments, corresponding to an enlarged cross-sectional view of X in FIG. 4. FIG. [Figure 7B] 5 is a cross-sectional view illustrating an image sensor according to some embodiments, corresponding to an enlarged cross-sectional view of Y in FIG. 4. FIG. [Figure 8] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 9] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 10] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 11] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 12A] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 12B] 12A, which is an enlarged view of X in FIG. 12A corresponding to X in FIG. 4, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 12C] 12A, which corresponds to Y in FIG. 4, and is an enlarged view of Y in FIG. 12A, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 13A] 4A to 4C are cross-sectional views corresponding to AA' in FIG. 3, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 13B]13A, which corresponds to X in FIG. 4, and is an enlarged view of X in FIG. 13A, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. [Figure 13C] 13A, which corresponds to Y in FIG. 4, and is an enlarged view of Y in FIG. 13A, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail by describing embodiments of the present invention with reference to the accompanying drawings.

[0016] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

[0017] Referring to FIG. 1, the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog to digital converter (ADC) 1007, and an input / output buffer 1008.

[0018] The active pixel sensor array 1001 includes a plurality of unit pixels arranged two-dimensionally and can convert optical signals into electrical signals. The active pixel sensor array 1001 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 1003. The converted electrical signals can be provided to a correlated double sampler 1006.

[0019] The row driver 1003 can provide a number of drive signals to the active pixel sensor array 1001 for driving a number of unit pixels according to the results decoded by the row decoder 1002. If the unit pixels are arranged in a matrix, a drive signal can be provided for each row.

[0020] A timing generator 1005 may provide timing and control signals to the row decoder 1002 and the column decoder 1004 .

[0021] The correlated double sampler (CDS) 1006 can receive and sample and hold the electrical signal generated by the active pixel sensor array 1001. The correlated double sampler 1006 can double sample a specific noise level and a signal level based on the electrical signal, and output a differential level corresponding to the difference between the noise level and the signal level.

[0022] An analog-to-digital converter (ADC) 1007 can convert an analog signal corresponding to the differential level output from the correlated double sampler 1006 into a digital signal and output the digital signal.

[0023] The input / output buffer 1008 can latch digital signals and sequentially output the latched digital signals to a video signal processor (not shown) according to the decoding results of the column decoder 1004 .

[0024] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to some embodiments of the present invention.

[0025] 1 and 2, the active pixel sensor array 1001 includes a plurality of pixel regions PX, which may be arranged in a matrix. Each pixel region PX may include a transfer transistor TX. Each pixel region PX may further include logic transistors RX, SX, and DX. The logic transistor may be a reset transistor RX, a selection transistor SX, or a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each pixel region PX may further include a photoelectric conversion unit PD and a floating diffusion region FD. The logic transistors RX, SX, and DX may be shared by a plurality of pixel regions PX.

[0026] The photoelectric conversion unit PD can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion unit PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX can transfer the charges generated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD can transfer and cumulatively store the charges generated in the photoelectric conversion unit PD. The source follower transistor DX can be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0027] The reset transistor RX can periodically reset the charge accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode of the reset transistor RX can be connected to a power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX can be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be discharged, resetting the floating diffusion region FD.

[0028] The source follower transistor DX including the source follower gate electrode SF can act as a source follower buffer amplifier, amplifying the potential change at the floating diffusion region FD and outputting it to the output line Vout.

[0029] A selection transistor SX including a selection gate electrode SEL can select a pixel region PX to be read out row by row. When the selection transistor SX is turned on, a power supply voltage VDD can be applied to the drain electrode of the source follower transistor DX.

[0030] Figure 3 is a plan view of an image sensor according to some embodiments of the present invention. Figure 4 is a cross-sectional view taken along line A-A' in Figure 3. Figure 5 is an enlarged cross-sectional view taken along line X in Figure 4. Figure 6 is an enlarged cross-sectional view taken along line Y in Figure 4.

[0031] 3 and 4, the image sensor 500 according to an embodiment of the present invention may have a structure in which first and second sub-chips CH1 and CH2 are bonded together. The first sub-chip CH1 may be disposed on the second sub-chip CH2. The first sub-chip CH1 includes a substrate 100. The substrate 100 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The substrate 100 may be doped with impurities of a first conductivity type. For example, the first conductivity type may be P-type.

[0032] The substrate 100 may include a first surface 100A and a second surface 100B facing each other. The first surface 100A may face a second direction D2, and the second surface 100B may face a first direction D1. The first direction D1 and the second direction D2 may face opposite each other. The substrate 100 may include a pixel array region APS, an optical black region OB, and an edge region ER.

[0033] The pixel array region APS and the optical black region OB may each include a plurality of unit pixels UP. The unit pixels UP may be arranged along a third direction D3 and a fourth direction D4. The optical black region OB may surround the pixel array region APS. The edge region ER may surround the pixel array region APS and the optical black region OB. The edge region ER may include a contact region BR1, a via region BR2, and a pad region PR. The via region BR2 may be located between the contact region BR1 and the pad region PR. The pad region PR may be located at the outermost position within the edge region ER.

[0034] A substrate isolation portion DTI is disposed within the substrate 100 in the pixel array region APS and the optical black region OB, and may isolate / define unit pixels UP in the pixel array region APS and may isolate / define regions of the substrate in the optical black region OB. The substrate isolation portion DTI may extend to the contact region BR1 in the edge region ER. The substrate isolation portion DTI may have a mesh shape in plan view.

[0035] Back contacts BCA, back via patterns BVS1 and BVS2, and back conductive pads PAD may be arranged on the second surface 100B of the substrate 100 in the edge region ER. The back via patterns BVS1 and BVS2 may include a first back via pattern BVS1 and a second back via pattern BVS2. Column signals and / or row signals may be transmitted between the first and second sub-chips CH1 and CH2 through the back via patterns BVS1 and BVS2.

[0036] A substrate isolation portion DTI may be disposed within the substrate 100. The substrate isolation portion DTI may separate the unit pixels UP. The substrate isolation portion DTI may penetrate the substrate 100 between the unit pixels UP along the second direction D2.

[0037] The substrate isolation portion DTI may penetrate only a portion of the substrate 100. In this case, the substrate 100 may include a region aligned with the substrate isolation portion DTI and oppositely doped to the photoelectric conversion region PD, through which pixels may be defined.

[0038] The substrate separation portion DTI may extend from the first surface 100A toward the second surface 100B. In a plan view, the substrate separation portion DTI may have a mesh shape in which lines extending in the third and fourth directions D3 and D4 intersect. The substrate separation portion DTI may have a width that narrows as it extends from the first surface 100A toward the second surface 100B of the substrate.

[0039] The substrate separating portion DTI may extend from the second surface 100B toward the first surface 100A. The substrate separating portion DTI may have a width that narrows as it extends from the second surface 100B toward the first surface 100A of the substrate.

[0040] The substrate isolation parts DTI may each include a buried insulating pattern 115, an isolated insulating pattern 111, and an isolated conductive pattern 113. The buried insulating pattern 115 may be interposed between the isolated conductive pattern 113 and the first interlayer insulating film ILD1. The isolated insulating pattern 111 may be interposed between the isolated conductive pattern 113 and the substrate 100 and between the buried insulating pattern 115 and the substrate 100.

[0041] The buried insulating pattern 115 and the isolated insulating pattern 111 may be formed of an insulating material having a different refractive index from that of the substrate 100. The buried insulating pattern 115 and the isolated insulating pattern 111 may include, for example, silicon oxide. The isolated conductive pattern 113 may be separated from the substrate 100. The isolated conductive pattern 113 may include a polysilicon layer or a silicon germanium layer doped with impurities. The impurities doped into the polysilicon or silicon germanium layer may be, for example, one of boron, phosphorus, and arsenic. Alternatively, the isolated conductive pattern 113 may include a metal layer.

[0042] Shallow isolation patterns STI may be positioned within the substrate 100. The shallow isolation patterns STI may extend from the second surface 100B into the substrate 100 and be disposed within corresponding unit pixels UP among the plurality of unit pixels UP. The shallow isolation patterns STI may define active regions ACT adjacent to the second surface 100B of the substrate 100 in the pixel array region APS. The active regions ACT may be provided for the transistors TX, RX, DX, and SX of FIG. 2 .

[0043] In each unit pixel UP, a photoelectric conversion unit PD may be disposed within the substrate 100. The photoelectric conversion unit PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N-type. The N-type impurities doped in the photoelectric conversion unit PD may form a PN junction with P-type impurities doped in the surrounding substrate 100 to provide a photodiode.

[0044] Referring to FIG. 4, a transfer gate TG may be disposed on a first surface 100A of the substrate 100 in the unit pixel UP. A portion of the transfer gate TG may extend into the substrate 100. The transfer gate TG may be a vertical type. Alternatively, the transfer gate TG may be a planar type that does not extend into the substrate 100 and is flat. A gate insulating film GI may be interposed between the transfer gate TG and the substrate 100. A floating diffusion region FD may be disposed in the substrate 100 on one side of the transfer gate TG. The floating diffusion region FD may be doped with, for example, impurities of the second conductivity type.

[0045] A first unit pixel UP1 and a second unit pixel UP2 may be disposed in the optical black area OB of the substrate 100. A black photoelectric conversion unit PD' may be provided in the substrate 100 in the first unit pixel UP1. A dummy area PD" may be provided in the first substrate 1 in the second unit pixel UP2. The black photoelectric conversion unit PD' may be doped with impurities of a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, n-type. The black photoelectric conversion unit PD' has a similar structure to the photoelectric conversion unit PD, but may not perform the same operation as the photoelectric conversion unit PD (i.e., an operation of receiving light and generating an electrical signal). A signal generated in the black photoelectric conversion unit PD' may be used to generate a reference signal for a dark level. The dummy area PD" may not be doped with impurities. The signal generated in the dummy area PD" may be used as information for removing noise in subsequent processes.

[0046] A first interlayer insulating film ILD1 and a first interlayer wiring MCL may be provided on a first surface 100A of the substrate 100.

[0047] A first interlayer dielectric film ILD1 may be provided on and cover the first surface 100A of the substrate 100. The first interlayer dielectric film ILD1 may be a composite film including at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a porous low-k film, or a combination thereof. A first interlayer wiring MCL may be provided in the first interlayer dielectric film ILD1. A floating diffusion region FD may be connected to the first interlayer wiring MCL.

[0048] A second interlayer insulating film ILD2 may be provided under the first interlayer insulating film ILD1. A second interlayer wiring 217 may be provided in the second interlayer insulating film ILD2. A peripheral transistor PTR may be disposed in the second interlayer insulating film ILD2.

[0049] A sub-substrate BSB may be provided under the second interlayer insulating film ILD2, and circuits constituting blocks other than the active pixel array of FIG.

[0050] An anti-reflection structure AL may be provided on the second surface 100b of the substrate 100. The anti-reflection structure AL may cover the second surface 100B.

[0051] A light-shielding pattern 48 may be disposed on the anti-reflection structure AL. A low-refractive index pattern 50 may be disposed on each of the light-shielding patterns 48. The light-shielding pattern 48 and the low-refractive index pattern 50 may overlap the substrate separating unit DTI and have a grid shape in plan view. The light-shielding pattern 48 may include, for example, titanium. The low-refractive index patterns 50 may have the same thickness and may include the same organic material. The low-refractive index patterns 50 may have a lower refractive index than the color filters CF1 and CF2 described below. The light-shielding pattern 48 and the low-refractive index pattern 50 may prevent crosstalk between adjacent pixel regions PX.

[0052] A protective film 56 may be provided on the low refractive index pattern 50. The protective film 56 may conformally cover the low refractive index pattern 50.

[0053] In the pixel array region APS, color filters CF1 and CF2 may be disposed between the low refractive index patterns 50. Each of the color filters CF1 and CF2 may have one of blue, green, and red. As another example, the color filters CF1 and CF2 may include different colors such as cyan, magenta, or yellow. In the image sensor according to this example, the color filters CF1 and CF2 may be arranged in a Bayer pattern. As another example, the color filters CF1 and CF2 may be arranged in a 2x2 Tetra pattern, a 3x3 Nona pattern, or a 4x4 Hexadeca pattern.

[0054] In the pixel array region APS, microlenses ML may be disposed on the color filters CF1 and CF2, and the edges of the microlenses ML may be in contact with each other or may be connected to each other.

[0055] An optical black liner 52p may be disposed in the optical black region OB. The optical black liner 52p may include a conductive material. The optical black liner 52p may have a single layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

[0056] An optical black pattern CFB may be provided in the edge region ER. The optical black pattern CFB may include the same material as the blue color filter, for example.

[0057] A lens remainder layer MLR may be disposed on the optical black pattern CFB in the edge region ER. The lens remainder layer MLR may include the same material as the microlenses ML. In the pad region PR, an opening 35 exposing the rear conductive pad PAD may be formed in the lens remainder layer MLR.

[0058] The anti-reflection structure AL may include a first insulating film 31, a high refractive index layer 32 on the first insulating film 31, a second insulating film 33 on the high refractive index layer 32, a third insulating film 34 on the second insulating film 33, a contact cutoff portion VC1 between the high refractive index layer 32 and the back contact BCA, a first via cutoff portion VC2 disposed between the high refractive index layer 32 and the first back via pattern BVS1, a pad cutoff portion VC3 between the back conductive pad PAD and the high refractive index layer 32, and a second via cutoff portion VC4 between the second back via pattern BVS2 and the high refractive index layer 32. The first insulating film 31, the second insulating film 33, and the third insulating film 34 may each include different materials.

[0059] The first insulating film 31 may be in contact with the second surface 100B of the substrate 100. The first insulating film 31 may include, for example, aluminum oxide. The second insulating film 33 may include, for example, silicon, silicon oxide, or plasma enhanced silicon oxide (PEOX). The third insulating film 34 may include, for example, hafnium oxide. The third insulating film 34 may function as an etch stop layer.

[0060] The high refractive index layer 32 can include titanium oxide, for example, TiO2.

[0061] The substrate 100 may have a substrate refractive index n0, the first insulating film 31 may have a first refractive index n1, the high refractive index layer 32 may have a second refractive index n2, and the second insulating film 33 may have a third refractive index n3.

[0062] The refractive index n0 of the substrate may be greater than the first refractive index n1. The second refractive index n2 of the high refractive index layer 32 may be greater than the third refractive index n3 of the second insulating film 33.

[0063] The substrate refractive index n0 may be, for example, 4.0 to 4.4. The first refractive index n1 may be 2.0 to 3.0. The second refractive index n2 may be 2.2 to 2.8. The third refractive index n3 may be 1.0 to 1.9.

[0064] In the contact region BR1, a back contact BCA may be disposed in a back contact trench 46 that penetrates the anti-reflection structure AL and a portion of the substrate. The back contact BCA may be in contact with the substrate isolation portion DTI. The back contact BCA may include a contact conductive pattern 52A on a sidewall of the back contact trench 46 and a contact metal pattern 54A disposed on the contact conductive pattern 52A.

[0065] The contact conductive pattern 52A may conformally cover the inner wall of the back contact trench 46. The contact conductive pattern 52A may be in contact with the first insulating film 31, the second insulating film 33, and the third insulating film 34. The contact conductive pattern 52A may be spaced apart from the high refractive index layer 32.

[0066] The contact metal pattern 54A may fill the back contact trenches 46. The contact metal pattern 54A may comprise, for example, aluminum.

[0067] The back contact BCA may be in contact with the isolated conductive pattern 113 of the substrate isolation unit DTI. A negative bias may be applied to the isolated conductive pattern 113 of the substrate isolation unit DTI through the back contact BCA. The isolated conductive pattern 113 may serve as a common bias line. Therefore, holes that may be present on the surface of the substrate 100 in contact with the substrate isolation unit DTI may be captured, thereby improving dark current characteristics.

[0068] A contact disconnection portion VC1 may be provided between the contact conductive pattern 52A and the high refractive index layer 32.

[0069] In one embodiment, the contact disconnecting portion VC1 may have a shape with an empty space therein. The contact disconnecting portion VC1 may have an empty space therein.

[0070] In one embodiment, the contact disconnection portion VC1 may include an insulating material, such as SiO2 or Al2O3.

[0071] Referring to FIG. 5, the contact disconnection portion VC1 and the back contact BCA are shown in more detail.

[0072] The contact conductive pattern 52A of the back contact BCA may include a first contact conductive pattern 521A in contact with the inner wall of the back contact trench 46 and a second contact conductive pattern 522A on the first contact conductive pattern 521A. The first contact conductive pattern 521A may be in contact with the first insulating film 31, the second insulating film 33, and the third insulating film 34. The first contact conductive pattern 521A may be in direct contact with the substrate isolation part DTI. The second contact conductive pattern 522A may be in contact with the contact metal pattern 54A. The second contact conductive pattern 522A may be in contact with the protective film 56.

[0073] The first contact conductive pattern 521A and the second contact conductive pattern 522A may include different materials, such as titanium or titanium nitride, and the second contact conductive pattern 522A may include tungsten.

[0074] The first contact conductive pattern 521A and the high refractive index layer 32 may be spaced apart. A contact disconnection portion VC1 may be provided between the first contact conductive pattern 521A and the high refractive index layer 32.

[0075] When the contact cutoff portion VC1 includes an empty space therein, one sidewall 32SS of the high refractive index layer 32 can be exposed.

[0076] The contact disconnection portion VC1 may be surrounded by the high refractive index layer 32, the second insulating film 33, the first insulating film 31, and the first contact conductive pattern 521A.

[0077] 4, first back vias BVS1 may be arranged on the second surface 100b of the substrate 100 in the via region BR2. Back conductive pads PAD and second back vias BVS2 may be arranged on the second surface 100b of the substrate 100 in the pad region PR. The second back vias BVS2 may be arranged in a predetermined number of groups around the back conductive pads PAD. External signals may be input / output through the back conductive pads PAD. The back conductive pads PAD may serve as an interface for external signals.

[0078] The back conductive pad PAD is disposed in the back pad trench 60. The back conductive pad PAD includes a pad conductive pattern 52c and a pad metal pattern 54c. The pad conductive pattern 52c can conformally cover the side and bottom surfaces of the back pad trench 60.

[0079] The pad conductive pattern 52c may include the same material and have the same thickness as the contact conductive pattern 52a. The pad conductive pattern 52c may have a single-layer or multi-layer structure made of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The pad metal pattern 54c may include, for example, aluminum. The pad metal pattern 54c fills the back pad trench 60.

[0080] A pad cutoff portion VC3 may be provided between the pad conductive pattern 52c and the high refractive index layer 32. The pad cutoff portion VC3 may be similar to the contact cutoff portion VC1. The pad conductive pattern 52c and the high refractive index layer 32 may be spaced apart by the pad cutoff portion VC3.

[0081] A first via cutoff portion VC2 may be provided between the first back via pattern BVS1 and the high refractive index layer 32. The first via cutoff portion VC2 may be similar to the contact cutoff portion VC1. The first back via pattern BVS1 and the high refractive index layer 32 may be separated by the first via cutoff portion VC2.

[0082] A second via cutoff portion VC4 may be provided between the second back via pattern BVS2 and the high refractive index layer 32. The second via cutoff portion VC4 may be similar to the contact cutoff portion VC1. The second back via pattern BVS2 and the high refractive index layer 32 may be separated by the second via cutoff portion VC4.

[0083] The back contact BCA and the first back via pattern BVS1 may be connected by a connecting conductive pattern 52B.

[0084] A first back via pattern BVS1 may be provided on the second surface 100b of the substrate 100. The first back via pattern BVS1 may be disposed in a first back via hole H1 that penetrates the anti-reflection structure AL and a portion of the substrate. The first back via pattern BVS1 may conformally cover a sidewall of the first back via hole H1.

[0085] The first back via pattern BVS1 may be in contact with the first insulating film 31, the second insulating film 33, and the third insulating film 34. The first back via pattern BVS1 may be spaced apart from the high refractive index layer 32.

[0086] A first low-refractive index protection pattern 51b may be disposed on the first rear via pattern BVS1. The first low-refractive index protection pattern 51b may have a refractive index lower than that of the color filters CF1 and CF2. For example, the first low-refractive index protection pattern 51b may have a refractive index of about 1.3 or less.

[0087] Although not shown, a low-refractive capping pattern (not shown) may be disposed on the first low-refractive protection pattern 51b, and in this case, the top surface of the first low-refractive protection pattern 51b may be recessed.

[0088] The first back via pattern BVS1 and the contact conductive pattern 52A may be electrically connected by a connecting conductive pattern 52B. The connecting conductive pattern 52B may be disposed on the third insulating pattern 34 and may be disposed between the first back via pattern BVS1 and the contact conductive pattern 52A. The first back via pattern BVS1, the connecting conductive pattern 52B, and the contact conductive pattern 52A may be continuous. The first interlayer wiring MCL and the second interlayer wiring 217 may be electrically connected by the first back via pattern BVS1.

[0089] The first back via pattern BVS1 may include a staircase portion STP. The first back via pattern BVS1 may be connected to the first interlayer wiring MCL through the staircase portion STP. The bottom surface of the first back via pattern BVS1 may be connected to the second interlayer wiring 217.

[0090] The second back via pattern BVS2 may be disposed in a second back via hole H2 penetrating the anti-reflection structure AL and a portion of the substrate. The second back via pattern BVS2 may partially penetrate the anti-reflection structure AL, the substrate 100, the first interlayer dielectric film ILD1, and the second interlayer dielectric film ILD2. The second back via pattern BVS2 may be connected to a portion of the second interlayer wiring 217. Although not shown, the second back via pattern BVS2 may be connected to a portion of the first interlayer wiring MCL. The second back via BVS2 may conformally fill the inner wall and bottom surface of the second back via hole H2. The second back via pattern BVS2 may include the same material and have the same thickness as the first contact conductive pattern 52a. The second back via pattern BVS2 may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. One of the second back via patterns BVS2 may be electrically connected to one of the back conductive pads PAD by one of the via connecting wires 52D.

[0091] 6, the first back via pattern BVS1 is illustrated in more detail. The first back via pattern BVS1 may include a first outer via pattern BVS11 conformally covering the inner wall of the first back via hole H1, and a first inner via pattern BVS12 on the first outer via pattern BVS11.

[0092] The connecting conductive pattern 52B may include a first connecting conductive pattern 521B connected to the first outer via pattern BVS11 and a second connecting conductive pattern 522B connected to the first inner via pattern BVS12.

[0093] The first connecting conductive pattern 521B may include the same material as the first outer via pattern BVS11 and the first contact conductive pattern 521 A. The first connecting conductive pattern 521B may include, for example, a titanium or titanium nitride layer.

[0094] The second connection conductive pattern 522B may include the same material as the first inner via pattern BVS12 and the second contact conductive pattern 522A. The second connection conductive pattern 522B may include, for example, tungsten.

[0095] The first outer via pattern BVS11 may be in direct contact with the first interlayer wiring MCL and the second interlayer wiring 217. The first outer via pattern BVS11 may electrically connect the first interlayer wiring MCL and the second interlayer wiring 217.

[0096] A first via cutoff portion VC2 may be provided between the first outer via pattern BVS11 and the high refractive index layer 32. The first outer via pattern BVS11 and the high refractive index layer 32 may be spaced apart by the first via cutoff portion VC2.

[0097] As described above, the high refractive index layer 32 may be spaced apart from the back contact BCA, the first back via pattern BVS1, the back conductive pad PAD, and the second back via pattern BVS2.

[0098] The contact cutoff portion VC1 between the high refractive index layer 32 and the back contact BCA, the first via cutoff portion VC2 between the high refractive index layer 32 and the first back via pattern BVS1, the pad cutoff portion VC3 between the back conductive pad PAD and the high refractive index layer 32, and the second via cutoff portion VC4 between the second back via pattern BVS2 and the high refractive index layer 32 may include an empty space or an insulating material therein, thereby forming an electrical short structure between the high refractive index layer 32 and the back contact BCA, the back conductive pad PAD, and the back via patterns BVS1 and BVS2, and improving the optical performance of the image sensor.

[0099] Figure 7A is a cross-sectional view illustrating an image sensor according to some embodiments, which corresponds to the cross-sectional view of enlarged X in Figure 4. Figure 7B is a cross-sectional view illustrating an image sensor according to some embodiments, which corresponds to the cross-sectional view of enlarged Y in Figure 4. For simplicity of explanation, descriptions that overlap with those described above will be omitted.

[0100] 7A and 7B, enlarged X and Y cross sections of the image sensor of FIG. 4 are illustrated in more detail, according to some embodiments.

[0101] 7A, the contact conductive pattern 52A of the rear contact BCA may include a contact protrusion 52APS protruding toward the high refractive index layer 32. The contact metal pattern 54A of the rear contact BCA may include a protrusion protruding toward the high refractive index layer 32. A contact disconnection side surface VC1S of the contact disconnection portion VC1, where the contact disconnection portion VC1 and the contact conductive pattern 52a meet, may include a curved surface.

[0102] The contact conductive pattern 52A may include a first contact conductive pattern 521A in contact with the inner wall of the back contact trench 46, and a second contact conductive pattern 522A on the first contact conductive pattern 521A.

[0103] A portion of the sidewall of the contact metal pattern 54A protrudes toward the high refractive index layer 32, so that the side surface of the contact metal pattern 54A can include a curved contact metal surface 54ACS.

[0104] A portion of the sidewall of the first contact conductive pattern 521A protrudes toward the high refractive index layer 32, so that the side of the first contact conductive pattern 521A may include a curved first contact conductive side surface 521ACS. The first contact conductive side surface 521ACS may be in direct contact with the contact cutoff portion VC1. If the contact cutoff portion VC1 includes an empty space therein, the first contact conductive side surface 521ACS may be exposed.

[0105] A portion of the sidewall of the second contact conductive pattern 522A protrudes toward the high refractive index layer 32, so that the side surface of the second contact conductive pattern 522A can include a curved second contact conductive side surface 522ACS. The second contact conductive side surface 522ACS can contact the first contact conductive pattern 521A.

[0106] Referring to FIG. 7B, the first rear via pattern BVS1 may include a first via protrusion 52BPS protruding toward the high refractive index layer 32.

[0107] The first outer via pattern BVS11 of the first back via pattern BVS1 may include a protrusion protruding toward the high refractive index layer 32. A first via cutoff side surface VC2S of the first via cutoff portion VC2 where the first via cutoff portion VC2 and the first back via pattern BVS1 meet may include a curved surface.

[0108] The first backside via pattern BVS1 may include a first outer via pattern BVS11 conformally covering the inner wall of the first backside via hole H1, and a first inner via pattern BVS12 on the first outer via pattern BVS11.

[0109] A part of the sidewall of the first back via pattern BVS1 protrudes toward the high refractive index layer 32, so that the side surface of the first back via pattern BVS1 can include a curved surface.

[0110] A portion of the sidewall of the first outer via pattern BVS11 protrudes toward the high refractive index layer 32, so that the side surface of the first outer via pattern BVS11 may include a curved surface. The first outer via pattern BVS11 may be in direct contact with the first via cutoff portion VC2. If the first via cutoff portion VC2 includes an empty space therein, the side surface of the first outer via pattern BVS11 may be exposed.

[0111] A part of the sidewall of the first inner via pattern BVS12 protrudes toward the high refractive index layer 32, so that the side surface of the first inner via pattern BVS12 can include a curved surface.

[0112] Since the image sensor according to the embodiment of the present invention includes the contact cutoff portion VC1 and the first via cutoff portion VC2, the sidewalls of the contact conductive pattern 52A and the first back via pattern BVS1 can protrude toward the high refractive index layer 32. The same can be true for the pad cutoff portion VC3 between the back conductive pad PAD and the high refractive index layer 32 and the second via cutoff portion VC4 between the second back via pattern BVS2 and the high refractive index layer 32.

[0113] 8 to 13C are cross-sectional views corresponding to AA' in FIG. 3 and enlarged views corresponding to X and Y in FIG. 4, illustrating a method for manufacturing an image sensor according to some embodiments of the present invention.

[0114] 8, a second sub-chip CH2 having the structure described with reference to FIG. 4 and a first sub-chip CH1 bonded on the second sub-chip CH2 may be prepared. Bonding the first sub-chip CH1 to the second sub-chip CH2 may include connecting the first sub-chip CH1 to the second sub-chip CH2 such that the first interlayer insulating film ILD1 contacts the second interlayer insulating film ILD2.

[0115] 9, a grinding process can be performed on the second surface 100B of the substrate 100 in the state shown in FIG. 8 to reduce the thickness of the substrate 100 to a desired thickness. At this time, the upper surface of the substrate isolation portion DTI can be exposed. A first insulating film 31, a high refractive index layer 32, a second insulating film 33, and a third insulating film 34 can be conformally formed on the second surface 100B of the substrate 100. An anti-reflection structure AL can be formed on the second surface 100B of the substrate 100.

[0116] 10, the first insulating film 31, the high refractive index layer 32, the second insulating film 33, the third insulating film 34, and a portion of the substrate 100 may be etched to form a back contact trench 46 and a back pad trench 60. The back contact trench 46 may expose the substrate isolation portion DTI. The back pad trench 60 may expose the substrate 100.

[0117] The first insulating film 31, the high refractive index layer 32, the second insulating film 33, the third insulating film 34, the substrate 100, the first interlayer insulating film ILD1, and the second interlayer insulating film ILD2 may be partially etched to form the first rear via hole H1 and the second rear via hole H2.

[0118] The first back via hole H1 may expose the first interlayer wiring layer MCL and the second interlayer wiring layer 217. The second back via hole H2 may expose the second interlayer wiring layer 217.

[0119] 11, a portion of the high refractive index layer 32 may be selectively recessed through the back contact trench 46. Thus, a first recess RS1 may be formed.

[0120] A portion of the high refractive index layer 32 may be selectively recessed through the first rear via hole H1, thereby forming a second recess RS2.

[0121] A portion of the high refractive index layer 32 may be selectively recessed through the back pad trench 60. Through this, a third recess RS3 may be formed.

[0122] A portion of the high refractive index layer 32 may be selectively recessed through the second rear via hole H2, thereby forming a fourth recess RS4.

[0123] 12A, 12B, and 12C, a conductive layer may be conformally deposited on the third insulating layer 34 and etched to form an optical black liner 52p, a contact conductive pattern 52A, a connecting conductive pattern 52B, a first rear via pattern BVS1, a second rear via pattern BVS2, a pad conductive pattern 52c, and a via connecting wiring 52D.

[0124] At this time, the conductive layer can be deposited while the first to fourth recesses RS1, RS2, RS3, and RS4 remain empty.

[0125] Therefore, a contact cutoff portion VC1, a first via cutoff portion VC2, a pad cutoff portion VC3, and a second via cutoff portion VC4 can be formed.

[0126] 13A, 13B, and 13C, a light-shielding film and a low-refractive film are conformally stacked in this order on the third insulating film 34 and etched to form a light-shielding pattern 48 and a low-refractive pattern 50.

[0127] A protective film 56 is formed to cover the third insulating film 34, the optical black liner 52p, the contact conductive pattern 52A, the connecting conductive pattern 52B, the first back via pattern BVS1, the second back via pattern BVS2, the pad conductive pattern 52c and the via connecting wiring 52D, the light-shielding pattern 48, and the low-refractive pattern 50.

[0128] 4, color filters CF1 and CF2 may be formed between the low refractive index patterns 50. An optical black pattern CFB may be formed on the optical black liner 52p. Microlenses ML may be formed on the color filters CF1 and CF2. A lens remainder layer MLR may be formed on the optical black pattern CFB. An opening 35 exposing the rear conductive pad PAD may be formed in the lens remainder layer MLR in the pad region PR. The image sensor of FIGS. 3 to 4 may be formed.

[0129] The above description of the embodiments of the present invention provides examples to explain the present invention, and therefore the present invention is not limited to the above embodiments. It is clear that various modifications and changes, such as combining and implementing the above embodiments, can be made by a person skilled in the art within the technical scope of the present invention. [Explanation of symbols]

[0130] 31, 33, 34 Insulating film 32 High refractive index layer 46 Rear contact trench 52A contact conductive pattern 54A Contact metal pattern 100 boards 217 Second layer wiring AL anti-reflection structure APS Array Area BCA rear contact BVS1 1st backside via pattern DTI board separation section ER marginal region ILD1 First interlayer insulating film ILD2 Second interlayer insulating film MCL 1st interlayer wiring layer ML Micro Lens OB Optical Black Area PAD Back conductive pad VC1 Contact cut-off section VC2 1st via cutoff

Claims

1. a substrate having a first surface and a second surface facing each other, the substrate including a pixel array region and an edge region; an anti-reflection structure disposed on the second surface; a substrate separation unit disposed within the substrate to separate the substrate; a microlens on the anti-reflection structure; a back contact disposed in a back contact trench that penetrates the anti-reflection structure and that contacts the substrate isolation portion; The back contact is a contact conductive pattern on a sidewall of the back contact trench; a contact metal pattern disposed on the contact conductive pattern; The anti-reflection structure comprises: a first insulating film; a high refractive index layer on the first insulating film; a contact break provided between the high refractive index layer and the back contact.

2. the high refractive index layer includes titanium oxide; The image sensor according to claim 1 , wherein the contact disconnection portion includes an empty space therein.

3. The image sensor of claim 1 , wherein the refractive index of the substrate is greater than the refractive index of the high refractive index layer.

4. The anti-reflection structure comprises: a second insulating film on the high refractive index layer; a third insulating film on the second insulating film, The image sensor of claim 1 , wherein the refractive index of the second insulating film is smaller than the refractive index of the high refractive index layer and is greater than 1.

5. the high refractive index layer includes titanium oxide; The contact disconnection portion is made of SiO ２ or Al ２ O ３ 10. The image sensor of claim 1, comprising:

6. a first interlayer insulating film disposed on the first surface of the substrate; a first interlayer wiring layer disposed in the first interlayer insulating film; a second interlayer insulating film disposed under the first interlayer insulating film; a second interlayer wiring layer disposed in the second interlayer insulating film; a first backside via pattern that penetrates the anti-reflection structure at the edge region; a connecting conductive pattern that continuously connects the first back surface via pattern and the contact conductive pattern, The image sensor of claim 1 , wherein the first backside via pattern electrically connects the first interlayer wiring layer and the second interlayer wiring layer.

7. a first backside via pattern that penetrates the anti-reflection structure at the edge region; The image sensor of claim 1 , further comprising a first via cutoff provided between the high refractive index layer and the first backside via pattern.

8. The image sensor according to claim 1 , wherein a contact-disconnecting side surface of the contact-disconnecting portion that meets the contact conductive pattern includes a curved surface.

9. a substrate having a first surface and a second surface facing each other, the substrate including a pixel array region and an edge region; an anti-reflection structure disposed on the second surface; a microlens on the anti-reflection structure; a first backside via pattern penetrating the anti-reflection structure and the substrate in the edge region; a first interlayer insulating film disposed on the first surface of the substrate; a first interlayer wiring layer disposed in the first interlayer insulating film; a second interlayer insulating film disposed under the first interlayer insulating film; a second interlayer wiring layer disposed in the second interlayer insulating film, The anti-reflection structure comprises: a first insulating film; a high refractive index layer on the first insulating film; a first via cut-off portion disposed between the high refractive index layer and the first back surface via pattern.

10. The image sensor of claim 9 , wherein the first back surface via pattern includes a first via protrusion protruding toward the high refractive index layer.

11. 10. The image sensor of claim 9, wherein the refractive index of the high refractive index layer is between 2.0 and 2.

3.

12. a substrate separation unit disposed within the substrate to separate the substrate; a back contact disposed in a back contact trench that penetrates the anti-reflection structure and that contacts the substrate isolation portion; The back contact is a contact conductive pattern on a sidewall of the back contact trench; a contact metal pattern disposed on the contact conductive pattern; The image sensor of claim 9 , wherein a contact break is disposed between the high refractive index layer and a sidewall of the contact conductive pattern.

13. The image sensor of claim 12 , wherein the back contact includes a contact protrusion that protrudes toward the contact break.

14. The image sensor of claim 12 , further comprising a connecting conductive pattern that continuously connects the first rear via pattern and the contact conductive pattern.

15. the high refractive index layer includes titanium oxide; The image sensor of claim 9 , wherein the first via cutoff portion comprises an open space.

16. The first via cutoff portion is made of SiO ２ or Al ２ O ３ 10. The image sensor of claim 9, comprising:

17. a back contact disposed in a back contact trench that extends through the anti-reflective structure; the anti-reflection structure includes a second insulating film on the high refractive index layer, The image sensor of claim 9 , wherein the second insulating film is continuously interposed between the back contact and the first back via pattern.

18. a substrate having a first surface and a second surface facing each other, the substrate including a pixel array region and an edge region; a transfer gate disposed on the first surface; an anti-reflection structure disposed on the second surface; a substrate separation unit disposed within the substrate to separate the substrate; a microlens on the anti-reflection structure; a back contact disposed in a back contact trench that penetrates the anti-reflection structure and that contacts the substrate isolation portion; The back contact is a contact conductive pattern on a sidewall of the back contact trench; a contact metal pattern disposed on the contact conductive pattern; The anti-reflection structure comprises: a first insulating film; a high refractive index layer on the first insulating film; a contact break disposed between the high refractive index layer and the back contact; The rear contact includes a contact protrusion protruding from the contact cutoff portion.

19. 20. The image sensor of claim 18, wherein the contact break includes an empty space therein.

20. The contact conductive pattern is a first contact conductive pattern in contact with the substrate; a second contact conductive pattern on the first contact conductive pattern; the first contact conductive pattern includes titanium; 20. The image sensor of claim 18, wherein the second contact conductive pattern comprises tungsten.

Images