Imaging apparatus

Abstract

To provide an imaging apparatus without requiring a lens.SOLUTION: An imaging apparatus includes a first layer, a second layer, and a third layer. The second layer is provided between the first layer and the third layer. The first layer includes a diffraction grating, the second layer includes a photoelectric conversion element and a third layer includes a transistor which has an oxide semiconductor in an active layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to an imaging device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductors are widely used in transistors. However, oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, Patent Document 3 discloses a pixel transistor using an oxide semiconductor transistor with extremely low off-state current. Used as part of the circuit, CMOS (Complementary Metal Oxide Semiconductor (Semiconductor) circuits can be fabricated using silicon-based transistors. An imaging device configured for road use is disclosed.

[0007] In addition, Patent Document 4 discloses a transistor having silicon and a transistor having an oxide semiconductor. The imaging device has a structure in which a photodiode having a crystalline silicon layer and a photodiode having a crystalline silicon layer are stacked. It has been done.

[0008] In addition, Patent Document 5 discloses an imaging device that uses a technology that uses a diffraction grating instead of a lens. is shown. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 4] Japanese Patent Application Laid-Open No. 2013-243355 [Patent Document 5] U.S. Patent Publication 2014 / 0253781 Summary of the Invention [Problem to be solved by the invention]

[0010] The imaging device emits light onto a chip on which pixels are integrated, and converts the light into a signal. The light is generally incident on the chip through a lens. The lens is a telephoto lens that is used in accordance with the specifications of the electronic device (such as a camera). lens, wide-angle lens, zoom lens, or a bright lens with a small F-number (focal length / effective aperture) Examples include "zu".

[0011] On the other hand, lens components account for a large proportion of the manufacturing costs of electronic devices or camera modules. The problem is that the proportion of lenses that are removed from electronic devices or camera modules is high. By eliminating the above, they can be manufactured more cheaply. The technology being discussed is one aspect of an imaging device that does not use a lens.

[0012] Therefore, one aspect of the present invention provides an imaging device that does not require an off-chip lens. Another object of the present invention is to provide an imaging device suitable for high-speed operation. Another object is to provide an imaging device with high resolution. One of the objects is to provide an imaging device with a high degree of integration. Another object of the present invention is to provide an imaging device capable of capturing images under low illumination. Another object of the present invention is to provide an imaging device with a wide dynamic range. Another object is to provide an imaging device that can be used in a wide temperature range. Another object is to provide an imaging device with a high aperture ratio. Another object is to provide a highly reliable imaging device. One of the objects is to provide a novel imaging device or the like. One of the aims is to provide

[0013] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0014] One embodiment of the present invention relates to an imaging device including a transistor formed using an oxide semiconductor. do.

[0015] One aspect of the present invention is an imaging device having a first layer, a second layer, and a third layer, The second layer is disposed between the first layer and the third layer, the first layer having a diffraction grating, and the second layer The first layer has a photoelectric conversion element, and the third layer has a transistor having an oxide semiconductor in the active layer. The imaging device is characterized by having:

[0016] Another aspect of the present invention is a method for manufacturing a semiconductor device having a first layer, a second layer, a third layer, and a fourth layer. wherein the first layer, the second layer, the third layer and the fourth layer are multiplied in this order. The first layer has a diffraction grating, the second layer has a photoelectric conversion element, and the third layer The layer has a transistor having an oxide semiconductor in the active layer, and the fourth layer is an active region or The imaging device is characterized by having a transistor having silicon in its active layer.

[0017] The third layer includes a first transistor, a second transistor, a third transistor, and , a fourth transistor, and a source electrode or a drain electrode of the first transistor. One of the electrodes is electrically connected to one of the electrodes of the photoelectric conversion element, and the other of the electrodes is connected to the source of the first transistor. The other of the electrode and the drain electrode is electrically connected to the gate electrode of the second transistor. The other of the source electrode or the drain electrode of the first transistor is connected to the third transistor. a source electrode of the second transistor electrically connected to one of the source electrode and the drain electrode; One of the source electrode and drain electrode of the fourth transistor is a source electrode or a drain electrode of the fourth transistor. The first and second electrodes may be electrically connected to one of the electrodes.

[0018] The other of the source electrode and the drain electrode of the first transistor is connected to one of the capacitors. It may be configured to be electrically connected to the electrode.

[0019] The oxide semiconductor is composed of In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, It is preferable that the alloy contains at least one of the following elements: La, Ce, Nd, or Hf.

[0020] In addition, the photoelectric conversion element can use selenium or a compound containing selenium in the photoelectric conversion layer. Cut. [Effects of the Invention]

[0021] Therefore, by using one embodiment of the present invention, an imaging device that does not require a lens outside the chip can be obtained. Alternatively, it is possible to provide an imaging device suitable for high-speed operation. Alternatively, it is possible to provide an imaging device with high resolution. It is possible to provide an imaging device. Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, an imaging device capable of capturing images under low illumination can be provided. This makes it possible to provide an imaging device with a wide dynamic range. It is possible to provide an imaging device that can be used in the above-mentioned applications. It is possible to provide a highly reliable imaging device. It is possible to provide a novel imaging device or the like. Alternatively, it is possible to provide a novel semiconductor device or the like. This can be done.

[0022] Note that the effects of one embodiment of the present invention are not limited to these. Depending on the circumstances, the effect may be different from those mentioned above. Alternatively, for example, one aspect of the present invention may be In some cases, these effects may not be present. [Brief explanation of the drawings]

[0023] [Figure 1] 1A and 1B are a cross-sectional view and a top view illustrating an imaging device. [Figure 2] 1A and 1B are diagrams for explaining the operations of a global shutter system and a rolling shutter system. [Figure 3] FIG. [Figure 4] FIG. 2 illustrates a circuit included in the imaging device. [Figure 5] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 6] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 7] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 8] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 9]FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 10] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 11] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 12] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 13] FIG. 2 is a top view illustrating the shape of a diffraction grating. [Figure 14] FIG. 3 is a cross-sectional view illustrating the shape of a diffraction grating. [Figure 15] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 16] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 17] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 18] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 19] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 20] FIG. 1 is a diagram illustrating a curved imaging device. [Figure 21] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 22] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 23] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 24] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 25] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 26] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 27] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 28] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 29] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 30] 4 is a timing chart illustrating the operations of the global shutter system and the rolling shutter system. [Figure 31] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 32] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 33] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 34] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 35] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 36] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 37] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 38] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 39] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 40] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 41] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 42] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 43] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 44] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 45] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 46] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 47] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 48] FIG. 1 is a top view illustrating a transistor. [Figure 49] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0025] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0026] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0027] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0028] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0029] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0030] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0031] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0032] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0033] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0034] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0035] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0036] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0037] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0038] 1A is a cross-sectional view of an imaging device according to one embodiment of the present invention. 00, layer 1200 and layer 1500, and layer 1200 is a layer between layer 1100 and layer 1500. It is set up in between.

[0039] The layer 1100 includes a transistor, and the layer 1200 includes a photoelectric conversion element. The transistor and the photoelectric conversion element form a circuit 90. The circuit 90 functions as a pixel circuit. As shown in the top view of FIG. 1(B), the circuit 90 can have a matrix. The pixels are arranged in a grid to form a pixel array 91. Signals can be extracted from the individual circuits 90. In FIG. 1(B), the layer 1500 is omitted for clarity. It is.

[0040] The layer 1500 is transparent and has a plurality of grooves or protrusions on the side opposite to the layer 1200. The layer 1500 has an area where the grooves or protrusions are provided, It can act as a diffraction grating.

[0041] In the imaging device according to one aspect of the present invention, an image of a subject (diffraction image) is captured by pixels through a diffraction grating. The input image (image of the subject) is constructed by arithmetic processing from the captured image at the pixels. Therefore, in this calculation process, the inverse conversion of the conversion from the input image to the diffraction image by the diffraction grating is performed. .

[0042] The input image is defined as a collection of countless point light sources, and the light emitted from each point light source is reflected by the corresponding diffraction grating. When the diffracted light is detected by each pixel of the imaging device, the pixel array 91 The pattern that will be generated is calculated using ray tracing and electromagnetic field simulation. .

[0043] This allows the data acquired by the pixels of the imaging device and the intensity of the light emitted from the point light source to be By calculating the coefficients for all pixels, , the conversion coefficients from the input image to the diffraction image by the diffraction grating can be constructed.

[0044] The input image can also be defined as a set of weighted light intensities of a plurality of point light sources. Therefore, the image captured by the imaging device is a vector image having components each of which is a weighting coefficient corresponding to the input image. It can be calculated by matrix operations using vectors and matrices whose elements are variable coefficients. A vector whose components are the data of each pixel of an image captured by an imaging device and the inverse of the aforementioned matrix By performing a matrix operation using the matrices and, a vector corresponding to the input image is obtained.

[0045] In the above imaging device, the diffracted light from the diffraction grating is detected by pixels, so a point light source is used as the input image. Even if the image is captured, calculations using data from all pixels of the image capture device are required. If the point light source moves, the diffracted light from the diffraction grating will have a completely different pattern. The image obtained by combining parts of the images taken before and after the movement and performing calculations is The resulting image is completely different from the input image.

[0046] Generally, in an imaging device in which pixels are arranged in a matrix as shown in the top view of Figure 1(B), 2A, the driving operation for performing an imaging operation 21, a holding operation 22, and a readout operation 23 for each row. When using the rolling shutter method, In this case, the image capture synchronism is lost, so if the subject moves, the input is processed Composing an image is difficult.

[0047] Therefore, one embodiment of the present invention is an imaging device using a diffraction grating, in which the , an imaging operation 21 and a holding operation 22 are performed simultaneously for all rows, and a readout operation 23 is performed for each row. The global shutter method is used. By using the global shutter method, This ensures simultaneous imaging at each pixel of the imaging device, even when the subject is moving. Even if the captured image has a high quality, it is possible to construct a high quality input image from the captured image.

[0048] Here, imaging when the subject moves will be described with reference to FIGS. At times T1 and T2, the position of the target, which is a point light source, moves to X1 and X2. For simplicity, the pixels of the imaging device are Y1 and Y2. The light from the subject enters the imaging device through the lens. For simplicity, when the object is at X1 and X2, the light is incident on pixels Y1 and Y2. Assume that incidence onto 2 is dominant.

[0049] The vectors corresponding to the input images at time T1 and time T2 are t (1,0), t (0,1) and the vector corresponding to the incident light on the imaging device is t (1,0), t (0,1). When the imaging device is driven by the global shutter method, the imaging operation is performed at time T1. When all rows are scanned at once, the vector corresponding to the captured image is t (1,0). This is This corresponds to the fact that the subject can be captured without distortion at time T1.

[0050] On the other hand, when the imaging device is driven by the rolling shutter method, the imaging operation is performed at time T1. When this is done sequentially for the pixel Y1 row at time T1 and the pixel Y2 row at time T2, a vector corresponding to the captured image is obtained. Lu is t (1,1). This is because the images of the object at time T1 and time T2 are mixed evenly. This corresponds to a distorted image.

[0051] FIG. 3B corresponds to the case of an imaging device using a diffraction grating. Let us assume that light passing through a grating is incident on the imaging device. Here, the matrix corresponding to the diffraction grating is A ={(a,b),(c,d)}, and the vectors corresponding to the input images at time T1 and time T2 are Kutlu is t (1,0), t If (0,1) is used, the vector corresponding to the incident light on the imaging device is teeth t (a,c), t (b, d). The inverse transformation matrix of the above matrix is ​​A -1 ={(d, -b),(-c,a)} (for simplicity, let ad-bc=1).

[0052] When the imaging device is driven by the rolling shutter method, the imaging operation is performed at time T1. When the pixel Y1 row is scanned at time T2, and the pixel Y2 row is scanned at time T3, the vector corresponding to the captured image is t (a,d). Therefore, the inverse transformation matrix is ​​A -1 · t (a,d)= t ((ab)d ,d 2 This is because the images of the subject at time T1 and time T2 are simply mixed together. The image of the subject at time T1 and time T2 is not the same as the image of the subject at time T2. This means that an input image of the body cannot be easily constructed by computational processing.

[0053] On the other hand, when the imaging device is driven by the global shutter method, the imaging operation is performed at time T1. When all the rows are scanned at once, the vector corresponding to the captured image is t (a,c). The inverse transformation matrix is ​​A -1 · t (a,c)= t (1,0). This is the This corresponds to the fact that the input image of the subject can be constructed by arithmetic processing. By driving the lens using a dual shutter system, it is possible to capture images of moving subjects. An apparatus can be provided.

[0054] To realize the global shutter method, the circuit that constitutes the pixel must be made of a transistor using an oxide semiconductor. For example, the circuit 90 is , the configuration shown in FIG. 4(A) can be used.

[0055] In the circuit 90, one of the source and drain electrodes of the transistor 51 is connected to a photoelectric conversion The source voltage of the transistor 51 is electrically connected to one electrode 66 of the conversion element 60. The other of the electrode and drain electrode is electrically connected to the gate electrode of the transistor 52 . The other of the source electrode and the drain electrode of the transistor 51 is connected to the The transistor 52 is electrically connected to one of the source electrode and the drain electrode. One of the source and drain electrodes is the source or drain electrode of transistor 54. The capacitor 59 is electrically connected to one of the electrodes.

[0056] In addition, the source electrode or the drain electrode of each transistor may function as a wiring. For example, one of the wires 71 and 79 functions as a power line and the other as an output line. The wiring 72 can function as a power supply line. The wiring 77 can function as a power supply line (low potential). , 78 can function as a signal line that controls the on / off of the transistor. In addition, the wiring 74 can function as a connecting wiring.

[0057] Here, the transistor 51 controls the charge accumulation section (FD) in response to the output of the photoelectric conversion element 60. It can function as a transfer transistor to control the voltage level. The transistor 52 functions as an amplifying transistor that outputs an output according to the potential of the charge storage section (FD). The transistor 53 initializes the potential of the charge storage section (FD). The transistor 54 can function as a reset transistor. It can function as a selection transistor for making a selection.

[0058] It is particularly preferable to use OS transistors for the transistors 51 to 54. It's nice.

[0059] OS transistors have extremely low off-state current characteristics, which expands the dynamic range of imaging. In the circuit configuration shown in FIG. When the light intensity is high, the potential of the charge storage section (FD) becomes small. Since the off-state current is extremely low, even when the gate potential is extremely small, Therefore, the range of illuminance that can be detected is This allows for a wider dynamic range.

[0060] Furthermore, the low off-state current characteristics of the transistors 51 and 53 reduce the charge storage capacity. (FD) can hold a charge for an extremely long period of time. Global shutter technology allows charge accumulation in all pixels simultaneously without complicating the operation method. Therefore, even if the subject is moving, it is possible to obtain an image with little distortion. It can be easily obtained.

[0061] An OS transistor is a transistor that uses silicon in the active region or active layer (hereafter referred to as Because the temperature dependency of the electrical characteristics is smaller than that of Si transistors, it can be used over an extremely wide temperature range. Therefore, the OS transistor can be used in an imaging device and a semiconductor device. The conductor device is also suitable for installation in automobiles, aircraft, spacecraft, and the like.

[0062] In addition, an OS transistor has a higher drain breakdown voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, the avalanche phenomenon is likely to occur. It is preferable to apply a relatively high voltage (for example, 10 V or more) to the Combining an S transistor with a photoelectric conversion element that uses a selenium-based material as the photoelectric conversion layer This makes it possible to provide a highly reliable imaging device.

[0063] FIG. 5A is an example of a cross-sectional view of an imaging device of one embodiment of the present invention, and shows the pixel shown in FIG. The photoelectric conversion element 60, the transistor 51, the transistor 52, and the capacitance element 5 in the circuit 9 shows an example of a specific connection form. is an example.

[0064] In this embodiment, each wiring, each electrode, and each conductor 81 is illustrated as an individual element. However, when they are electrically connected, they may be provided as the same element. In addition, the gate electrode, source electrode, or drain electrode of a transistor may be a conductor. The form in which the gate electrode and source of the transistor are connected to the respective wirings via 81 is an example. In some cases, the drain electrode or the drain electrode may function as a wiring. In some cases, some of the wirings shown on the surface may not be provided, or wirings and transistors other than those mentioned above may be provided. It may be included in the layer.

[0065] Moreover, an insulating layer 41 having a function as a protective film, an interlayer insulating film or a planarizing film is formed on each element. For example, the insulating layers 41 and 42 are made of a silicon oxide film, an oxide film, or the like. An inorganic insulating film such as a silicon nitride film can be used. Alternatively, an acrylic resin, a polyimide film, or the like can be used. Alternatively, an organic insulating film such as an imide resin may be used. Depending on the situation, CMP (Chemical Mechanical Polishing) method, etc. It is preferable to perform the planarization treatment by

[0066] In addition, there are cases where some of the above wirings are not provided, or where wirings or transistors other than those described above are provided in each layer. In some cases, layers other than those mentioned above may be included. In other cases, some of the above may be included. In some cases, no layers are included.

[0067] In the layer 1500, an area with a step on the upper surface is illustrated. The grooves or protrusions that are formed have various shapes, and there are steps at the positions shown in Figure 5(A). However, this is not necessarily the case, and there may be no step in the layer 1500 above a pixel.

[0068] In FIG. 5A, each transistor has a back gate. However, as shown in FIG. 5(B), a configuration without a back gate is also possible. As shown in (C), only some of the transistors, for example, transistor 51, are provided with a back gate. The back gate may be formed on the opposite side of the transistor. In some cases, the back gate may be electrically connected to the front gate of the In some cases, a fixed potential different from that of the back gate may be supplied. This configuration can also be applied to the configuration of other imaging devices described in this embodiment.

[0069] The photoelectric conversion element 60 provided in the layer 1200 can be an element of various types. FIG. 5A illustrates a configuration in which a selenium-based material is used for the photoelectric conversion layer 61. The photoelectric conversion element 60 using this material has the characteristic of high external quantum efficiency for visible light. In the photoelectric conversion element, the electrons are amplified significantly with respect to the amount of incident light due to avalanche multiplication. In other words, when a selenium-based material is used for the photoelectric conversion layer 61, a highly sensitive sensor can be obtained. This allows a sufficient amount of photocurrent to be obtained even if the pixel area is reduced. Therefore, photoelectric conversion elements using selenium-based materials are suitable for imaging in low-light environments. In addition, since the selenium-based material has a high light absorption coefficient, it is easy to make the photoelectric conversion layer 61 thin. It has many advantages.

[0070] The selenium-based material can be amorphous selenium or crystalline selenium. For example, amorphous selenium can be obtained by forming a film of amorphous selenium and then heat treating it. By making the grain size of the crystalline selenium smaller than the pixel pitch, the characteristic variations between pixels are reduced. Crystalline selenium also has a higher spectral sensitivity to visible light than amorphous selenium. It has the characteristics of high optical absorption coefficient.

[0071] Although the photoelectric conversion layer 61 is illustrated as a single layer, the hole injection layer 61 is formed on the light receiving surface side of the selenium-based material. Gallium oxide or cerium oxide is provided as a blocking layer, and an electron injection blocking layer is provided on the electrode 66 side. Alternatively, nickel oxide or antimony sulfide may be provided as the insulating layer.

[0072] The photoelectric conversion layer 61 is a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, avalanche multiplication can be utilized, similar to a single layer of selenium. It is possible to form a photoelectric conversion element that can

[0073] The photoelectric conversion element 60 using a selenium-based material has an electrode 66 formed of, for example, a metal material. The photoelectric conversion layer 61 can be disposed between the C IS and CIGS are p-type semiconductors, and cadmium sulfide, an n-type semiconductor, is used to form the junction. Alternatively, zinc or zinc sulfide may be provided in contact with the surface.

[0074] To generate the avalanche phenomenon, a relatively high voltage (for example, 10 It is preferable to apply a voltage (V or more) to the OS transistor. High breakdown voltage characteristics make it easy to apply relatively high voltage to the photoelectric conversion element. Therefore, we have developed an OS transistor with a high drain breakdown voltage and a selenium-based material for photoelectric conversion. By combining this with a photoelectric conversion element with a layer of SiO2, a highly sensitive and reliable imaging device can be achieved. It is possible.

[0075] In FIG. 5A, the photoelectric conversion layer 61 and the light-transmitting conductive layer 62 are not separated between the pixel circuits. However, it may be configured as shown in FIG. 6A in which the circuits are separated from each other. In the area between the pixels where there is no electrode 66, a partition wall 67 made of an insulator is provided, and the photoelectric conversion layer 6 It is preferable to prevent cracks from occurring in the transparent conductive layer 62. As shown in Fig. 6(C) and (D), the partition wall 67 may not be provided. Alternatively, the light-transmitting conductive layer 62 and the wiring 77 may be in direct contact with each other.

[0076] The electrodes 66 and the wiring 77 may be multi-layered. For example, as shown in FIG. The electrode 66 is made up of two layers of conductive layers 66a and 66b, and the wiring 77 is made up of two layers of conductive layers 77a and 77b. In the configuration of FIG. 7A, for example, the conductive layers 66a and 77a The conductive layers 66b and 77b are formed by selecting a low-resistance metal or the like, and are connected to the photoelectric conversion layer 61. It is advisable to select a metal or the like with good tactile characteristics. The electrical characteristics of the conversion element can be improved. Contact with such a metal may cause electrolytic corrosion. Even in this case, electrolytic corrosion can be prevented by providing the conductive layer 77b.

[0077] The conductive layer 66b and the conductive layer 77b are made of, for example, molybdenum or tungsten. The conductive layer 66a and the conductive layer 77a may be made of, for example, aluminum or titanium. A laminate such as titanium sandwiched between aluminum or titanium can be used.

[0078] The insulating layer 41 may also have a multi-layer structure. For example, as shown in FIG. The insulating layer 41 has an insulating layer 41a and an insulating layer 41b, and the insulating layer 41a and the insulating layer 41b If the etching rate and the like are different, the conductor 81 will have steps. In the case where other insulating layers used for the insulating film or the planarizing film are multi-layered, the conductor 81 also has a step. Although an example in which the insulating layer 41 has two layers is shown here, the insulating layer 41 The other insulating layers may be configured as three or more layers. The upper surface of the insulating layer 41 may be processed to be flat.

[0079] The partition wall 67 can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition wall 67 is used for blocking light from the transistors and the like and / or for reducing the light receiving capacity per pixel. The area of ​​the portion may be colored black or the like to define the area.

[0080] The photoelectric conversion element 60 is made of a pin film using an amorphous silicon film or a microcrystalline silicon film. A diode element or the like may also be used.

[0081] For example, FIG. 8 shows an example in which a pin-type thin film photodiode is used as the photoelectric conversion element 60. The photodiode is made up of an n-type semiconductor layer 65, an i-type semiconductor layer 64, and a p-type semiconductor layer The i-type semiconductor layer 64 is made of amorphous silicon. It is preferable to use the p-type semiconductor layer 63 and the n-type semiconductor layer 65. Amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type is used. Photodiodes that use amorphous silicon as a photoelectric conversion layer can emit light with wavelengths of visible light. It has high sensitivity in the visible light region and is easy to detect weak visible light.

[0082] In the photoelectric conversion element 60 shown in FIG. 8, the n-type semiconductor layer 65 acting as a cathode is Electrode 66 is electrically connected to transistor 51. The p-type semiconductor layer 63 acting as a semiconductor layer is electrically connected to the wiring 78 via the conductor 81. .

[0083] In the circuit 90 shown in FIG. 4A, the anode and cathode of the photoelectric conversion element 60 In some cases, the connection form of the wiring etc. connected to each other may be reversed from that shown in FIG. 4(A).

[0084] In either case, the photoelectric conversion element 61 is arranged so that the p-type semiconductor layer 63 serves as the light receiving surface. It is preferable to form a p-type semiconductor layer 60 as the light receiving surface. The output current of the transistor 60 can be increased.

[0085] The photoelectric conversion element 60 has a pin-type thin-film photodiode configuration, and The photoelectric conversion element 60 and the wiring connection configuration are shown in FIGS. The examples shown in (E) and (F) may also be used. The connection form between the 0 and the wiring is not limited to these, and other forms may be used.

[0086] FIG. 9A shows a photoelectric conversion element 60 having a p-type semiconductor layer 63 and a transparent conductive layer 62 in contact therewith. The transparent conductive layer 62 acts as an electrode and increases the output current of the photoelectric conversion element 60. It can be done.

[0087] The transparent conductive layer 62 is made of, for example, indium tin oxide or silicon-containing indium tin oxide. zinc oxide, zinc oxide, zinc oxide containing gallium, aluminum oxide zinc oxide, tin oxide, fluorine-containing tin oxide, antimony-containing tin oxide, or graphene The transparent conductive layer 62 is not limited to a single layer, but may be a laminate of different films. That's fine.

[0088] FIG. 9B shows a structure in which the p-type semiconductor layer 63 of the photoelectric conversion element 60 and the wiring 78 are directly connected to each other. This is the configuration.

[0089] FIG. 9C shows a photoelectric conversion element 60 having a p-type semiconductor layer 63 and a transparent conductive layer 62 in contact therewith. The wiring 78 and the light-transmitting conductive layer 62 are electrically connected.

[0090] FIG. 9(D) shows an insulating layer covering the photoelectric conversion element 60 having an opening through which the p-type semiconductor layer 63 is exposed. The transparent conductive layer 62 covering the opening and the wiring 78 are electrically connected. be.

[0091] 9(E) shows a configuration in which a conductor 81 is provided to penetrate the photoelectric conversion element 60. In this structure, the wiring 77 is electrically connected to the p-type semiconductor layer 63 via a conductor 81. In the drawing, the wiring 77 and the electrode 66 are apparently electrically connected via the n-type semiconductor layer 63. However, since the lateral resistance of the n-type semiconductor layer 63 is high, If an appropriate distance is provided between the wiring 77 and the electrode 66, the resistance between them will be extremely high. Therefore, the photoelectric conversion element 60 functions as a diode without short-circuiting the anode and cathode. The conductor 81 electrically connected to the p-type semiconductor layer 63 can have the following properties. There may be more than one.

[0092] FIG. 9(F) shows a transparent layer in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60 of FIG. 9(E). A photoconductive layer 62 is provided.

[0093] In the photoelectric conversion element 60 shown in FIGS. 9(D), 9(E), and 9(F), the light receiving area This has the advantage that a wide light receiving area can be secured because the area and wiring do not overlap.

[0094] As shown in FIG. 10, the photoelectric conversion element 60 has a silicon substrate 40 as a photoelectric conversion layer. A photodiode may also be used.

[0095] The photoelectric conversion element 60 formed using the above-mentioned selenium-based material or amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as a process for forming a semiconductor substrate, a lithography process, and an etching process. In addition, selenium-based materials have high resistance, and as shown in Figure 5(A), It is also possible to configure the layer 61 so that it is not separated between the circuits. The imaging device can be manufactured with high yield and low cost. When forming a photodiode as the photoelectric conversion layer 61, a polishing process, a bonding process, etc. What kind of difficult process is required?

[0096] The imaging device according to one aspect of the present invention has a structure in which silicon substrates 40 on which circuits are formed are stacked. For example, as shown in FIG. 11, a transistor having an active region on a silicon substrate 40 may be used. The layer 1400 having the transistors 55 and 56 overlaps the pixel circuit. It is possible.

[0097] The circuit formed on the silicon substrate 40 has a function of reading out the signal output from the pixel circuit and a function of detecting the signal. For example, the circuit diagram shown in FIG. The transistor 55 (nc The gate electrodes of the transistor 56 (p-ch type) and the transistor 57 (p-ch type) are electrically connected. , one of the source electrode or drain electrode of one transistor is connected to the other transistor The source electrode and the drain electrode are electrically connected to each other. The other of the source electrode and the drain electrode is electrically connected to a separate wiring.

[0098] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be a germanium or silicon gel substrate. aluminum, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, Substrates made of gallium nitride or organic semiconductor materials can also be used.

[0099] As shown in FIG. 11(B), the transistors 55 and 56 are made of silicon. The active layer 58 may be a polycrystalline thin film transistor. Silicon or SOI (Silicon on Insulator) single crystal silicon It is possible.

[0100] In the stacked layer, a layer having the transistors 55 and 56 and a layer having the transistors An insulating layer 80 is provided between the layer having the transistor 51 and the layer having the transistor 52. 11A, the region in which a transistor including an oxide semiconductor is formed is between the area where the Si transistor (Si photodiode in Figure 10) is formed and the area where the Si transistor (Si photodiode in Figure 10) is formed. An insulating layer 80 is provided.

[0101] The hydrogen in the insulating layer provided near the active regions of the transistors 55 and 56 The hydrogen terminates the dangling bonds of silicon. This has the effect of improving the reliability of the transistor 56. The hydrogen in the insulating layer provided near the oxide semiconductor layer, which is a conductive layer, is trapped in the oxide semiconductor. Therefore, the hydrogen reduces the reliability of the transistor 51. Therefore, transistors using silicon-based semiconductor materials When one layer having an OS transistor and another layer having an OS transistor are stacked, It is preferable to provide an insulating layer 80 between the layers, which has the function of preventing hydrogen diffusion. By confining hydrogen in one layer, the transistors 55 and 56 The reliability can be improved. In addition, the diffusion of hydrogen from one layer to another is suppressed. This also improves the reliability of the transistor 51 and the like.

[0102] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0103] In the configuration shown in FIG. 11, the circuit (for example, the driving The photoelectric conversion element 60 can be formed so as to overlap with the transistor 51 and the like. This allows for a higher pixel density, which means that the resolution of the imaging device can be increased. For example, the number of pixels can be 4K2K, 8K4K, or 16K8K. It is appropriate to be

[0104] The imaging device shown in FIG. 11 has a configuration in which no photoelectric conversion element is provided on the silicon substrate 40. Therefore, the photoelectric conversion element 60 is not affected by various transistors and wiring. This allows a light path to be secured, and pixels with a high aperture ratio can be formed.

[0105] An imaging device according to one embodiment of the present invention can have a structure shown in FIG.

[0106] The imaging device shown in FIG. 12 is a modified example of the imaging device shown in FIG. 11(A), and includes an OS transistor. The figure shows an example of configuring a CMOS inverter using a silicon transistor and a silicon transistor.

[0107] Here, the transistor 56, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 55 provided in the layer 1100 is an n-channel transistor. By providing only the −ch type transistor on the silicon substrate 40, well formation and n-type impurity Steps such as layer formation can be omitted.

[0108] The imaging device shown in FIG. 12 uses selenium for the photoelectric conversion element 60. Similarly, a pin type thin film photodiode may be used.

[0109] In the imaging device shown in FIG. 12, the transistor 55 is a transistor formed in the layer 1100. The transistor 51 and the transistor 52 can be fabricated in the same process. The manufacturing process of the device can be simplified.

[0110] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. Therefore, for example, one or more of the transistors 51 to 54 It can also be configured as a transistor having silicon or the like in the active region or active layer. The transistor 55 and / or the transistor 56 are formed with an oxide semiconductor layer as an active layer. The transistor may also have the following structure.

[0111] 13(A) through 13(F) are examples of top views of a layer 1500 that acts as a diffraction grating. The hatched portions in the drawings may be either convex or concave portions. A plurality of patterns shown in FIGS. 13(A) to 13(F) are arranged on the pixel array. That's fine.

[0112] Furthermore, the cross section of the convex or concave portion is not limited to a shape with vertical side faces as shown in FIG. 1(A). 14(A) to 14(D). The shape of the recess may be any of the shapes shown in FIG. ) may also be used.

[0113] The layer 1500 can be formed of a light-transmitting material, such as a silicon oxide film. An inorganic insulating film such as a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an inorganic insulating film and an organic insulating film such as a polyethyleneimide resin may be used. It may be laminated with a film.

[0114] The layer 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed by using a lithography process and an etching process. It can also be formed by using imprint lithography, laser scribing, or the like.

[0115] FIG. 15(A) is a cross-sectional view of an example of an imaging device to which a color filter or the like is added. The cross-sectional view shows a part of an area having pixel circuits for three pixels. An insulating layer 2500 is formed on the formed layer 1200. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A dielectric film such as fluorine may be laminated.

[0116] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may be formed on the upper The light-shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. Metal layers such as aluminum and tungsten, and dielectric layers that function as anti-reflection films The film may be laminated.

[0117] An organic resin layer 2520 is provided as a planarization film on the insulating layer 2500 and the light-shielding layer 2510. In addition, a color filter 2530 is formed for each pixel. , color filter 2530a, color filter 2530b, and color filter 2530 c, R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0118] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. Alternatively, the layer 1500 may be formed without providing the insulating layer 2560.

[0119] Also, as shown in FIG. 15(B), an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. By using such a configuration, images in various wavelength regions can be obtained. The imaging device can be configured as follows.

[0120] For example, if a filter that blocks light shorter than the wavelength of visible light is used in the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter such as this is used, it can be used as a far-infrared imaging device. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0121] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as that used in an X-ray imaging device. It can be used as an imaging device to obtain an image that visualizes the strength of rays. When radiation strikes a scintillator, it emits light through a phenomenon called photoluminescence. The light is converted into light (fluorescence) such as visible light or ultraviolet light. Image data is acquired by detecting the radiation. A position may also be used.

[0122] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. It is made of a substance that emits visible or ultraviolet light or a material that contains such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and The material dispersed in resin or ceramics can be used.

[0123] In the photoelectric conversion element 60 using a selenium-based material, radiation such as X-rays is directly converted into an electric charge. Since the conversion can be performed, a configuration can be made in which a scintillator is not required.

[0124] Color filter 2530a, color filter 2530b, and color filter 2530c A microlens array 2540 may be provided on top. The light passing through each lens passes through the color filter directly below and is irradiated onto the photoelectric conversion element 60. In addition, the area other than the layer 1200 shown in FIGS. 15(A), (B), and (C) Let's say there are 1600 layers.

[0125] The specific configuration of the imaging device shown in FIG. 15(A) is as follows: 6. Taking the imaging device shown in FIG. 10 as an example, the imaging device shown in FIG. 17 do.

[0126] The specific configuration of the imaging device shown in FIG. 15C is as follows, taking the imaging device shown in FIG. 5 as an example: 18. Taking the imaging device shown in FIG. 10 as an example, the imaging device shown in FIG. 19 It should be noted that even if a gap X is provided between the layer 1500 and the microlens array 2540, The interval X can be set to 1 mm or less, preferably 100 μm or less. The gap may be a space, or a light-transmitting material may be provided as a sealing layer or an adhesive layer. For example, an inert gas such as nitrogen or a noble gas can be enclosed in the gap; or Alternatively, acrylic resin, epoxy resin, polyimide resin, or the like may be provided in the gap. Alternatively, a liquid such as silicone oil may be used. Even if no gap is provided, a gap X is provided between the color filter 2530 and the layer 1500. That's fine.

[0127] The imaging device may also be curved as shown in FIG. 20(A1) and FIG. 20(B1). FIG. 20(A1) shows the state in which the imaging device is bent in the direction of the two-dot chain line X1-X2 in the same figure. FIG. 20(A2) shows the area indicated by the two-dot chain line X1-X2 in FIG. 20(A1). 20(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0128] FIG. 20(B1) shows the case where the imaging device is bent in the direction of the two-dot chain line X3-X4 in the same figure, and FIG. 20(B2) shows a state where the lens is bent in the direction of the two-dot chain line Y3-Y4 in the drawing. 20(B1) is a cross-sectional view of the portion indicated by the two-dot chain line X3-X4. 20(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG. 20(B1).

[0129] By curving the imaging device, it is possible to reduce field curvature and astigmatism. This makes it easier to design the optical system, such as lenses, that are used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, allowing for miniaturization of semiconductor devices that use imaging devices. It is possible to easily reduce the size and weight of the camera. In addition, it is possible to improve the quality of the captured image. Cut.

[0130] Note that one embodiment of the present invention has been described in this embodiment. However, the present invention is not limited to these. For example, although an example in which the present invention is applied to an imaging device has been shown as one embodiment of the present invention, One aspect of the present invention is not limited to this. The embodiment of the present invention does not necessarily have to be applied to an imaging device. For example, the embodiment of the present invention may be applied to a device having another function. For example, one embodiment of the present invention is a semiconductor device having a diffraction grating. However, one embodiment of the present invention is not limited to this. Depending on the circumstances, one aspect of the present invention may have other optical elements. In some cases, or depending on the situation, in one aspect of the present invention, a diffraction grating is not provided. Good too.

[0131] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0132] (Embodiment 2) In this embodiment, the circuit 90 described in the first embodiment will be described.

[0133] The circuit 90 shown in FIG. 4A and the details of the connection between the wirings are shown in FIG. 21A. The circuit shown in FIG. 1(A) includes a photoelectric conversion element 60, a transistor 51, a transistor 52, a transistor The circuit includes a transistor 53 and a transistor 54 .

[0134] The anode of the photoelectric conversion element 60 is connected to the wiring 316, and the cathode is connected to the source of the transistor 51. The source electrode or drain electrode of the transistor 51 is connected to the The other end of the drain electrode is connected to the charge storage section (FD), and the gate electrode is connected to the wiring 312 (TX). One of the source electrode and the drain electrode of the transistor 52 is connected to the wiring 314 ( GND), and the other of the source electrode and drain electrode is connected to the source of transistor 54. The gate electrode is connected to either the source or drain electrode, and the gate electrode is connected to the charge storage section (FD). One of the source electrode and the drain electrode of the transistor 53 is connected to the charge storage portion (FD). The other of the source electrode and the drain electrode is connected to a wiring 317, and the gate electrode is connected to a wiring 318. The source electrode or drain electrode of the transistor 54 is connected to the line 311 (RS). One side is connected to the wiring 315 (OUT), and the gate electrode is connected to the wiring 313 (SE). All of the above connections are electrical connections.

[0135] The wiring 314 may be supplied with a potential such as GND, VSS, or VDD. Therefore, the potential and voltage are relative. Therefore, the magnitude of the GND potential is not necessarily , is not necessarily 0 volts.

[0136] The photoelectric conversion element 60 is a light receiving element and has the function of generating a current corresponding to the light incident on the pixel circuit. The transistor 53 is configured to store charge in the charge storage section (FD) by the photoelectric conversion element 60. The transistor 54 has a function of controlling the signal according to the potential of the charge storage section (FD). The transistor 55 has a function of outputting a reset signal for the potential of the charge storage section (FD). The transistor 56 has a function of controlling the selection of the pixel circuit during readout. Has.

[0137] The charge storage section (FD) is a charge holding node, and the amount of light received by the photoelectric conversion element 60 It holds a charge that varies depending on

[0138] The transistor 52 and the transistor 54 are directly connected between the wiring 314 and the wiring 315. Therefore, the wiring 314, the transistor 52, the transistor 5 Alternatively, the wiring 314, the transistor 54, and the transistor 5 may be arranged in this order. 2, and the wiring 315 may be arranged in that order.

[0139] The wiring 311 (RS) functions as a signal line for controlling the transistor 53. The wiring 312 (TX) functions as a signal line for controlling the transistor 51. The wiring 313 (SE) functions as a signal line for controlling the transistor 54. The wiring 314 (GND) functions as a signal line that supplies a reference potential (for example, GND). The wiring 315 (OUT) is used to read out a signal output from the transistor 52. The wiring 316 functions as a signal line for the charge storage unit (FD). 21(A) has a function as a signal line for outputting charges via 60. The wiring 317 is a low potential line for resetting the potential of the charge storage section (FD). 21A. In the circuit of FIG. 21A, it is a high-potential line.

[0140] Here, the relationship between the wiring shown in FIG. 21(A) and the wiring shown in FIG. 4(A) is as follows. The line 76 corresponds to the wiring 311 (RS). The wiring 75 corresponds to the wiring 312 (TX). The line 78 corresponds to the wiring 313 (SE), and the wiring 79 corresponds to the wiring 314 (GND). The wiring 71 corresponds to the wiring 315 (OUT). The wiring 77 corresponds to the wiring 316.

[0141] The pixel circuit of one embodiment of the present invention may have a structure shown in FIG. The circuit shown in B) has the same components as the circuit shown in FIG. 10, but the arrangement of the photoelectric conversion element 60 is different. The node is electrically connected to one of the source electrode or the drain electrode of the transistor 51, The difference is that the cathode of the photoelectric conversion element 60 is electrically connected to the wiring 316. The wiring 316 is a signal line for supplying charges to the charge storage unit (FD) via the photoelectric conversion element 60. 21B. 7 is the low potential line.

[0142] Next, the configuration of each element shown in FIGS. 21(A) and 21(B) will be described.

[0143] As described in the first embodiment, the photoelectric conversion element 60 is made of a selenium-based material and a conductive layer. It is possible to use elements with a silicon layer or elements with pin-type junctions formed by silicon layers. .

[0144] The transistors 51, 52, 53, and 54 are Silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon Although it is possible to form the transistor using a silicon dioxide, it is preferable to form the transistor using an OS transistor. Transistors whose channel formation region is formed using an oxide semiconductor have extremely low off-state current. It has the following characteristics:

[0145] In particular, the transistors 51 and 53 connected to the charge storage unit (FD) If the leakage current is large, the charge stored in the charge storage section (FD) cannot be retained for a sufficient period of time. Therefore, it is necessary to use OS transistors for at least the two transistors. By doing so, it is possible to prevent unnecessary charges from flowing out from the charge storage section (FD).

[0146] Furthermore, if the leakage current is large in the transistors 52 and 54, Since unnecessary charge is output to the line 314 or the wiring 315, these transistors and It is preferable to use a transistor in which a channel formation region is formed using an oxide semiconductor. .

[0147] An example of the operation of the circuit in FIG. 21(A) will be explained using the timing chart in FIG. 22(A). I will explain.

[0148] For the sake of simplicity, the potential of each wiring is given as a binary signal in FIG. However, since each potential is an analog signal, in reality it is not limited to binary values ​​and can be various depending on the situation. In the figure, the signal 701 is the potential of the wiring 311 (RS), and the signal 702 is the potential of the wiring 311 (RS). The potential of the line 312 (TX), the signal 703 is the potential of the wiring 313 (SE), and the signal 704 is the charge storage potential. The potential of the integrated part (FD), signal 705, corresponds to the potential of the wiring 315 (OUT). The potential of the wiring 316 is always "Low", and the potential of the wiring 317 is always "High".

[0149] At time A, the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 ( When the signal 702) is set to "High", the potential (signal 704) of the charge storage section (FD) The potential of the wiring 317 is initialized to "High" and the reset operation is started. The potential of 15 (signal 705) is precharged to "High".

[0150] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", a reset operation is performed. At this point, a reverse bias is applied to the photoelectric conversion element 60. Therefore, the potential (signal 704) of the charge storage section (FD) begins to decrease due to the reverse current. When the photoelectric conversion element 60 is irradiated with light, the reverse current increases. The rate at which the potential (signal 704) of the charge storage section (FD) drops varies depending on the amount of light. The source electrode and the drain electrode of the transistor 54 are connected in accordance with the amount of light irradiated onto the electric conversion element 60. The channel resistance between the electrodes changes.

[0151] At time C, when the potential of the wiring 312 (signal 702) is set to "Low", the accumulation operation ends. The potential (signal 704) of the charge storage section (FD) is constant. It is determined by the amount of charge generated by the photoelectric conversion element 60 during operation. The transistors 51 and 53 change depending on the amount of light that has been incident on them. is a transistor with extremely low off-state current, in which the channel formation region is formed in an oxide semiconductor layer. Therefore, the charge storage section (FD) is not charged until the subsequent selection operation (read operation) is performed. The potential can be kept constant.

[0152] When the potential of the wiring 312 (signal 702) is set to "Low", the wiring 312 and the charge accumulation The potential of the charge storage section (FD) changes due to the parasitic capacitance between the charge storage section (FD) and the If the change in the potential is large, the photoelectric conversion element 60 generates a charge during the accumulation operation. Therefore, the amount of charge cannot be accurately obtained. In order to reduce the capacitance between the gate electrode and the source electrode (or the gate electrode and the drain electrode) of the capacitor 51, The gate capacitance of the transistor 52 is increased, and a storage capacitor is provided in the charge storage section (FD). In this embodiment, these measures are effective to prevent the change in the potential. It is assumed that the change can be ignored.

[0153] At time D, when the potential of the wiring 313 (signal 703) is set to “High”, the transistor 54 The wiring 314 and the wiring 315 are connected to the transistor 52 and the transistor 53. Then, the potential of the wiring 315 (signal 705) drops. The precharging of the wiring 315 should be completed before time D. The rate at which the potential of the wiring 315 (signal 705) drops depends on the voltage between the source electrode and the drain electrode of the transistor 52. That is, the amount of light irradiated onto the photoelectric conversion element 60 during the accumulation operation depends on the current between the rain electrodes. It changes depending on the amount of light present.

[0154] At time E, when the potential of the wiring 313 (signal 703) is set to “Low”, the transistor 54 is cut off, the selection operation ends, and the potential of the wiring 315 (signal 705) becomes a constant value. Here, the constant value changes depending on the amount of light irradiated onto the photoelectric conversion element 60. Therefore, by acquiring the potential of the wiring 315, the photoelectric conversion element 60 can be You can see the amount of light that was being emitted.

[0155] More specifically, when the light irradiating the photoelectric conversion element 60 is strong, the charge accumulation portion (FD) The potential, i.e., the gate voltage of transistor 52, decreases. The current flowing between the source electrode and the drain electrode of the wiring 315 becomes small, and the potential of the wiring 315 (signal 70 5) decreases slowly. Therefore, a relatively high potential can be read out from the wiring 315. This can be done.

[0156] Conversely, when the light irradiating the photoelectric conversion element 60 is weak, the potential of the charge storage portion (FD), i.e., That is, the gate voltage of transistor 52 becomes high. The current flowing between the electrode and the drain electrode increases, and the potential of the wiring 315 (signal 705) decreases rapidly. Therefore, a relatively low potential can be read out from the wiring 315.

[0157] Next, the timing chart shown in FIG. 22B will be used to explain an example of the operation of the circuit shown in FIG. 21B. The potential of the wiring 316 is always "High" and the potential of the wiring 317 is always "High". Set to "Low".

[0158] At time A, the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 ( When the signal 702) is set to "High", the potential (signal 704) of the charge storage section (FD) The potential of the wiring 31 is initialized to the potential of the wiring 317 ("Low"), and the reset operation is started. The potential of 5 (signal 705) is precharged to "High".

[0159] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", a reset operation is performed. At this point, a reverse bias is applied to the photoelectric conversion element 60. Therefore, the potential (signal 704) of the charge storage section (FD) begins to rise due to the reverse current. .

[0160] For the operation after time C, please refer to the explanation of the timing chart in FIG. 22(A). At time E, the potential of the wiring 315 is acquired, and the photoelectric conversion element 60 is charged during the accumulation operation. You can see the amount of light that was being emitted.

[0161] 21A includes transistors 52 to 54 as shown in FIG. The register 54 may be shared by multiple pixels. Although the configuration in which the transistors 52 to 54 are shared is illustrated, the horizontal direction or Alternatively, the transistors 52 to 54 may be shared by multiple pixels in the horizontal and vertical directions. By adopting such a configuration, the number of transistors per pixel can be reduced. In FIG. 26, the transistors 52 to 54 are shared by four pixels. However, the number of pixels may be two, three, five or more. The pixel circuit shown in FIG. 1(B) can also have a similar configuration.

[0162] Furthermore, the pixel circuit of one embodiment of the present invention may have a structure shown in FIGS.

[0163] The circuit shown in FIG. 23A is the same as the circuit shown in FIG. 21A except that the transistor 53 and the wiring The wiring 311 (RS) is a wiring for the photoelectric conversion element 60. The other configurations are the same as the circuit shown in Figure 21(A). .

[0164] The circuit shown in FIG. 23(B) has the same components as the circuit shown in FIG. 23(A), but the photoelectric conversion The anode of the switching element 60 is electrically connected to one of the source and drain electrodes of the transistor 52. The cathode of the photoelectric conversion element 60 is electrically connected to the wiring 311 (RS). They differ in points.

[0165] The circuit of FIG. 23(A) is similar to the circuit of FIG. 21(A), and is based on the timing chart shown in FIG. 22(A). It can be operated on the port.

[0166] At time A, the potential of the wiring 311 (signal 701) is set to "High" and the potential of the wiring 312 ( When the signal 702 is set to "High", a forward bias is applied to the photoelectric conversion element 60. The potential (signal 704) of the charge storage unit (FD) becomes "High." The potential of the (FD) is initialized to the potential ("High") of the wiring 311 (RS), and in the reset state This is the start of the reset operation. The potential of the wiring 315 (signal 705) is , precharge to "High".

[0167] At time B, when the potential of the wiring 311 (signal 701) is set to "Low", a reset operation is performed. At this point, a reverse bias is applied to the photoelectric conversion element 60. Therefore, the potential (signal 704) of the charge storage section (FD) begins to decrease due to the reverse current. .

[0168] For the operation after time C, the explanation of the circuit operation in FIG. 21(A) can be referred to. At time E, By acquiring the potential of the wiring 315, the light irradiated onto the photoelectric conversion element 60 during the accumulation operation can be detected. You can see the amount of light that was present.

[0169] The circuit of FIG. 23(B) can be operated according to the timing chart shown in FIG. 22(C). do.

[0170] At time A, the potential of the wiring 311 (signal 701) is set to "Low" and the potential of the wiring 312 (signal When signal 702 is set to "High", a forward bias is applied to the photoelectric conversion element 60, and the The potential (signal 704) of the charge storage unit (FD) is in the reset state of "Low". The potential of the wiring 315 (signal 705) is set to "High". Keep it in the jersey.

[0171] At time B, when the potential of the wiring 311 (signal 701) is set to “High”, the reset operation At this point, a reverse bias is applied to the photoelectric conversion element 60. Therefore, the potential (signal 704) of the charge storage section (FD) begins to rise due to the reverse current. do.

[0172] For the operation after time C, the explanation of the circuit operation in FIG. 21(A) can be referred to. At time E, By acquiring the potential of the wiring 315, the light irradiated onto the photoelectric conversion element 60 during the accumulation operation can be detected. You can see the amount of light that was present.

[0173] The pixel circuit shown in FIG. 23A includes a transistor 52 and a transistor The transistor 54 may be shared by multiple pixels. 1 illustrates a configuration in which the transistors 52 and 54 are shared, Alternatively, the transistors 52 and 54 may be shared by a plurality of pixels in the horizontal and vertical directions. In FIG. 27, the transistors 52 and 54 are shared by four pixels. However, the number of pixels may be two, three, five or more. The pixel circuit shown in FIG. 3(B) can also have a similar configuration.

[0174] In addition, in FIGS. 21(A), (B) and 23(A), (B), a transistor 51 is provided. 24A shows an example in which the ion implantation is performed, but one embodiment of the present invention is not limited to this. As shown in (B), the transistor 51 can be omitted.

[0175] The transistors used in the pixel circuits are as shown in FIG. 25(A) or 25(B). , the transistor 51, the transistor 52, and the transistor 54 are provided with back gates. FIG. 25(A) shows a configuration in which a constant potential is applied to the back gate. The threshold voltage can be controlled. Also, in Figure 25(B), the same potential as the front gate is This is a configuration in which voltage is applied to the back gate, which can increase the on-current. In the case of 5(A), the back gate is electrically connected to the wiring 314 (GND). However, it may be electrically connected to another wiring to which a constant potential is supplied. 5(A) and (B) are the same as those in the circuit shown in FIG. 23(A) except that a back gate is provided in the transistor. 21(A), (B), 23(B), 24(A), ( It can also be applied to the circuit shown in B). In contrast, a configuration in which the same potential as the front gate is applied to the back gate, and a constant voltage is applied to the back gate The structure with or without a back gate can be combined as needed. The circuit configuration may be the same.

[0176] The pixel circuit shown in FIG. 25A includes a transistor 51 and a transistor The transistor 54 may be shared by a plurality of pixels. As shown in FIG. 29, the circuit uses transistors 52 and 54 in common with multiple pixels. It may also be used in this form.

[0177] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0178] (Embodiment 3) In this embodiment, the global shutter system and the rolling shutter system described in the first embodiment are used. The details of the shutter method will now be described.

[0179] As described in the second embodiment, the operation of the pixel circuit is a reset operation, a storage operation, and a selection operation. The global imaging method is used to control the entire pixel matrix. The shutter system and the rolling shutter system are known.

[0180] FIG. 30(A) is a timing chart for the global shutter system. 30(A) has a plurality of pixel circuits arranged in a matrix, and the pixel circuits are provided with the circuit shown in FIG. As an example, an imaging device having a circuit is used, and the pixel count from the first row to the nth row (n is a natural number of 3 or more) The following explanation of the operation of the path is based on Figures 21(B) and 23(A). , (B), and also the circuits shown in FIGS. 24(A) and (B).

[0181] In FIG. 30A, signals 501, 502, and 503 are in the first row, the second row, This is a signal input to the wiring 311 (RS) connected to each pixel circuit in the nth row. Signals 504, 505, and 506 are supplied to the pixel circuits in the first, second, and n-th rows. The signals 507 and 508 are input to the connected wiring 312 (TX). The signal 509 is transmitted to the wiring 313 ( This is the signal input to the SE.

[0182] A period 510 is a period required for one image capture. A period 511 is a period required for the pixels in each row. The period 520 is a period in which the circuits are simultaneously performing reset operations. The selection operation is performed sequentially in the pixel circuits of each row. As an example, the period 531 is a period during which the pixel circuits in the first row are performing a selection operation. In this way, in the global shutter system, the reset operation is performed almost simultaneously in all pixel circuits. After this, accumulation operations are performed almost simultaneously in all pixel circuits, and readout operations are performed sequentially for each row. can be.

[0183] In other words, in the global shutter system, accumulation operations are performed in all pixel circuits almost simultaneously. Therefore, the image pickup is performed simultaneously in the pixel circuits of each row. Even if the object is moving, it is possible to obtain images with little distortion.

[0184] On the other hand, FIG. 30(B) is a timing chart when the rolling shutter method is used. For signals 501 to 509, please refer to the explanation in FIG. 30(A). 10 is the period required for one image capture. These are the reset periods for the first row, the second row, and the n-th row, respectively. Periods 622 and 623 are accumulation operation periods for the first row, second row, and nth row, respectively. Furthermore, a period 631 is a period during which the pixel circuits in the first row are performing a selection operation. In the rolling shutter method, the accumulation operation is not performed simultaneously in all pixel circuits, but for each row. Since the imaging is performed sequentially, the simultaneity of imaging in the pixel circuits of each row cannot be ensured. The timing of the image capture differs between the first and last lines, so there is a large amount of distortion when the subject is moving. This results in a large image.

[0185] To realize the global shutter system, the signal readout from each pixel must be completed sequentially. The potential of the charge storage section (FD) must be maintained for a long time until the charge storage section (FD) The long-term retention of the transistor 53 or the like is achieved by forming a channel formation region using an oxide semiconductor. This can be achieved by using a transistor with extremely low off-state current. When a transistor with a channel formation region made of silicon or the like is used, Because the current is high, the potential of the charge storage section (FD) cannot be maintained for a long time, and the global shutter method It becomes difficult to use the formula.

[0186] As described above, a transistor in which a channel formation region is formed using an oxide semiconductor is used in a pixel circuit. This makes it easy to realize the global shutter method.

[0187] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0188] (Fourth embodiment) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be made with reference to the drawings. For clarity, some elements may be enlarged, reduced, or omitted.

[0189] 31A and 31B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 31(A) is a top view, and a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to FIG. 31(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 31(A) is 37(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0190] The transistor 101 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 11 in contact with the conductive layer 150. 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Furthermore, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0191] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0192] Also, the region 231 shown in FIG. 31(B) is a source region, the region 232 is a drain region, and the region 2 The region 33 can function as a channel forming region. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0193] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The resistance becomes n-type.

[0194] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. The term "electrode layer" can also be used interchangeably with "wiring." can.

[0195] In addition, the conductive layer 170 is shown as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0196] Although the conductive layer 140 and the conductive layer 150 are shown as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may also be applied to other transistors described in this embodiment. can.

[0197] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 32A is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 32(B). The cross section in the direction of -C4 corresponds to FIG. 37(B). The direction of the dashed dotted line C3-C4 is called the channel width direction.

[0198] The transistor 102 is formed by connecting the edge of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the edge of the conductive layer 170 acting as a The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layers 140, 150, and 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0199] The transistor 101 and the transistor 102 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The top gate structure has a region where the gate electrode 150 overlaps the gate electrode 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this structure, no offset region is formed in the oxide semiconductor layer 130, and therefore, the on-current is high. This makes it easier to form a small transistor.

[0200] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 33A is a top view of the transistor 103, and the dashed line D in FIG. The cross section in the 1-D2 direction corresponds to FIG. 33(B). The cross section in the -D4 direction corresponds to FIG. 37(A). The direction of the dashed dotted line D3-D4 is called the channel width direction.

[0201] The transistor 103 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. The edge layer 175, the insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and the insulating layer 180 a conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. If necessary, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0202] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0203] Also, the region 231 shown in FIG. 33(B) is a source region, the region 232 is a drain region, and the region 2 The region 33 can function as a channel forming region. The region 231 and the region 232 are insulating layers. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0204] Specifically, the insulating layer 175 is formed in the regions 231 and 232 by the steps up to the formation of the insulating layer 175. The oxygen vacancies caused by the ion implantation and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232 interact with each other. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0205] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 34A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 34(B). The cross section in the -E4 direction corresponds to FIG. 37(A). The direction of the dashed dotted line E3-E4 is called the channel width direction.

[0206] The transistor 104 is configured such that the conductive layer 140 and the conductive layer 150 are disposed at the edge of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103 except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0207] The regions 331 and 334 shown in FIG. 34(B) are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0208] Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. As with 2, the resistance can be reduced.

[0209] Regions 334 and 335 are the same as regions 231 and 232 in transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. and when the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. In some cases, the resistance reduction step 5 is not performed.

[0210] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. Therefore, it is suitable for high-speed operation.

[0211] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 35A is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 35(B). The cross section in the -F4 direction corresponds to FIG. 37(A). The dashed line F1-F2 direction corresponds to the channel length The direction indicated by the dashed dotted line F3-F4 is referred to as the channel width direction.

[0212] The transistor 105 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151. the conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175; and an insulating layer 180 that is electrically conductive through openings in the insulating layers 175 and 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0213] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0214] The transistor 105 has a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening formed in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0215] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 36A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 36(B). The cross section in the -G4 direction corresponds to FIG. 37(A). The direction of the dashed line G3-G4 is called the channel width direction.

[0216] The transistor 106 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the insulating layer 160 in contact with the oxide semiconductor layer 130; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. , the conductive layer 141 and the conductive layer 142 are electrically connected to each other through openings provided in the insulating layer 175 and the insulating layer 180 . The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, the insulating layer 180, the conductive layer 142, and the insulating layer (planarization film) in contact with the conductive layer 152 are ) and the like.

[0217] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0218] Transistor 106 has the same structure as transistor 106 except that it has conductive layer 141 and conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has the same structure as the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 152) can act as a base electrode layer. 2) can act as a drain electrode layer.

[0219] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 50 is not in contact with the insulating layer 120, the oxygen in the insulating layer 120 is and the conductive layer 150 is less likely to take away the oxide from the insulating layer 120 into the oxide semiconductor layer 130. This makes it easier to supply the raw material.

[0220] Note that the regions 231 and 232 in the transistor 103, the transistor 104, In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed and the Impurities that increase the dielectric constant may be added. Examples of the elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. , helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, One or more selected from the group consisting of titanium, zinc, and carbon can be used. The methods of adding impurities include plasma treatment, ion implantation, ion doping, and plasma Zumaion ion implantation and the like can be used.

[0221] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide The conductivity of the semiconductor layer can be increased.

[0222] When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of an impurity element, Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Here, the oxide semiconductor that has been made conductive can be used as an oxide conductor. Note that an oxide conductor has light-transmitting properties similar to an oxide semiconductor.

[0223] Oxide conductors are degenerate semiconductors, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a The contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer functioning as the drain electrode layer can be reduced.

[0224] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 37(C) and (D) are cross-sectional views in the channel length direction shown in FIG. 37(F) and (F) are cross-sectional views in the channel length direction shown in FIG. 37(C) and (D). As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer 173 may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. The width may be shorter than that of the

[0225] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and the double In addition, to control the threshold voltage, A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 can be electrically connected via a contact hole.

[0226] In addition, in the transistors 101 to 106 in FIGS. Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 39B), (C), or 39D, (E). can be done.

[0227] FIG. 39(A) is a top view of the oxide semiconductor layer 130, and FIGS. 39(B) and 39(C) are views of the two-layer structure. 39(D) and (E) are cross-sectional views of the oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0228] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers or the like having different compositions can be used.

[0229] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 40A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 40(B). The cross section in the -H4 direction corresponds to Fig. 46(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, is called the channel width direction.

[0230] The transistor 107 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 140 and the conductive layer 150 that are connected, and the stacked layer, the conductive layer 140 and the conductive layer 15 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and a and an insulating layer 180 that functions as a planarizing film, if necessary. A function may be added.

[0231] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 140 and the conductive layer 150 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 101 .

[0232] Furthermore, the transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 41A is a top view of the transistor 108. The cross section in the direction of 1-I2 corresponds to FIG. 41(B). The cross section in the direction of -I4 corresponds to FIG. 46(B). The direction of the dashed line I1-I2 corresponds to the channel The longitudinal direction, the direction of the dashed dotted line I3-I4, is called the channel width direction.

[0233] The transistor 108 is formed such that the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the edge of 0.

[0234] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 42A is a top view of the transistor 109, and the dashed line J in FIG. The cross section in the 1-J2 direction corresponds to FIG. 42(B). The cross section in the -J4 direction corresponds to Fig. 46(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, is called the channel width direction.

[0235] The transistor 109 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. the oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, and the insulating layer 16 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covering the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and and a conductive layer 14 electrically connected to the stack through an opening provided in the insulating layer 180. 0 and conductive layer 150. In addition, an insulating layer 180, a conductive layer 140 and An insulating layer (planarizing film) or the like may be provided in contact with the conductive layer 150.

[0236] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 103 has the same configuration as the transistor 103 except that it is a compound semiconductor layer 130c.

[0237] Furthermore, the transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 43A is a top view of the transistor 110. The cross section in the direction of 1-K2 corresponds to FIG. 43(B). The cross section in the direction of -K4 corresponds to FIG. 46(A). The direction of the dashed line K1-K2 is the channel The longitudinal direction, the direction of the dashed dotted line K3-K4, is called the channel width direction.

[0238] The transistor 110 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 104 has the same configuration as the transistor 104 except that it is a compound semiconductor layer 130c.

[0239] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 44A is a top view of the transistor 111. The cross section in the direction of 1-K2 corresponds to FIG. 44(B). The cross section in the direction of -K4 corresponds to FIG. 46(A). The direction of the dashed line K1-K2 is the channel The longitudinal direction, the direction of the dashed dotted line K3-K4, is called the channel width direction.

[0240] The transistor 111 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 141 and the conductive layer 151 that are connected, and the stacked layer, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the stacked conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the compound semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 is in contact with the insulating layer 175, and openings are formed in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 is also provided. If necessary, an insulating layer 180, a conductive layer 142, and a conductive layer 1 An insulating layer (flattening film) or the like may be provided in contact with 52.

[0241] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 141 and the conductive layer 151 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 105 .

[0242] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 45A is a top view of the transistor 112, and the dashed line M The cross section in the 1-M2 direction corresponds to FIG. 45(B). The cross section in the direction of -M4 corresponds to Fig. 46(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, is called the channel width direction.

[0243] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c, oxide semiconductor layer 130d, oxide semiconductor layer 130e, oxide semiconductor layer 130f ...). The transistor 106 and the transistor 107 are the same except that the first and second layers are the organic semiconductor layer 130b and the oxide semiconductor layer 130c. They have a similar configuration.

[0244] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 46(C) and (D) are cross-sectional views in the channel length direction shown in FIG. 46(F) and FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive layer 170. It may be shorter than the width.

[0245] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is the oxide semiconductor layer 1 shown in the top view of FIG. 30, conductive layer 140, and conductive layer 150 are shown). (W OS ) of the conductive layer 140 and the conductive layer 150. SD ) is formed long It may be formed short. OS ≧W SD(W SD is W OS (below) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor The characteristics can be improved.

[0246] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction through the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel This is called the (s-channel) structure.

[0247] In addition, a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, etc. and oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c. In a transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By flowing current through the conductor layer 130b, the device is less susceptible to the influence of interface scattering and a high on-current can be obtained. It should be noted that increasing the thickness of the oxide semiconductor layer 130b can improve the on-state current. For example, when the thickness of the oxide semiconductor layer 130b is set to 100 nm to 200 nm, Good too.

[0248] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0249] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0250] (Embodiment 5) In this embodiment, components of the transistor shown in Embodiment 4 will be described in detail. do.

[0251] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. Alternatively, a metal substrate or a transistor or a photodiode can be used. A silicon substrate on which an insulating layer, wiring, contact plugs, etc. are formed, and The silicon substrate may be formed with a conductor or the like that functions as a gate. When forming a p-ch transistor on the substrate, n - Silicon substrate with conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-channel type, The plane on which the transistor is formed is preferably a (110) plane. ) surface, the mobility can be increased.

[0252] The insulating layer 120 serves to prevent the diffusion of impurities from elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The insulating layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom in an amount equivalent to an oxygen atom measured by the TDS method. The calculated oxygen release rate is 1.0 x 10 19 atoms / cm 3 It is preferable that the value is equal to or greater than The surface temperature of the film during the TDS analysis was 100°C or higher and 700°C or lower, or 1 The temperature range is 00° C. or more and 500° C. or less. In the case of a plate, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform a planarization process by CMP or the like to make the surface flat.

[0253] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. It is also possible.

[0254] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are formed from the insulating layer 120 side. The details will be mainly explained for the case of a three-layer structure stacked in order.

[0255] Note that when the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 13 Just use the layer corresponding to 0b.

[0256] In addition, when the oxide semiconductor layer 130 is a two-layer structure, the oxide semiconductor layer 13 A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be swapped with 130b.

[0257] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0258] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (ion The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the

[0259] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be formed of a thin oxide semiconductor.

[0260] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0261] The oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface states may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0262] The oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0263] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may contain, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf as an element having a higher conductivity than the oxide semiconductor layer 130b. Specifically, the atomic ratio is preferably 1.5 times or more. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from occurring in the oxide semiconductor layer. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0264] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also used. It is preferred that it contains

[0265] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

[0266] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0267] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0268] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0269] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 30a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c was In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0270] When Zn and O are removed from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0271] The oxide semiconductor layer 130b is formed by multiplying the oxide semiconductor layer 130a and the oxide semiconductor layer 130b by the same amount. It is preferable to have a higher indium content than the c content. In oxide semiconductors, the s orbital of heavy metals is mainly The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the oxide semiconductor layer 130b has a higher mobility than the oxide semiconductor layer 130b. By using oxides with a high content of sodium, transistors with high field-effect mobility can be realized. It is possible.

[0272] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. Preferably thicker than 30a.

[0273] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is 1 x10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 Being less than More preferably, 1 × 10 13 / cm 3 Less than 1 x 10 -9 / cm 3 That's all It shall be so decided.

[0274] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in the layer 130c and at the respective interfaces.

[0275] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. The silicon concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 1×10 19 atoms / cm3, preferably less than 5×10 18 atoms / cm 3 less than and 1×10 18 atoms / cm 3 The control is performed so that the area is equal to or larger than this. The hydrogen concentration is 2×10 20 atoms / cm3 or less, preferably 5×10 19 ato ms / cm 3 Less than or equal to 5 × 10 18 atoms / cm 3 is less than or equal to 1× 10 17 atoms / cm 3 The nitrogen concentration is controlled to have a region where the nitrogen concentration is equal to or greater than the above. , 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Below or less, more preferably 5 × 10 17 atoms / cm 3 Less than or equal to 5 x 10 16 ato ms / cm 3 The control is performed so as to have a region where the above is true.

[0276] Furthermore, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer is reduced. In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, for example, the silicon concentration is set to 1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10 18 atoms / cm 3 The control is performed so that the carbon The element concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / c m 3 Less than 6 x 10 17 atoms / cm 3 Controlled to have an area where do.

[0277] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0278] Note that, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating film, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. Therefore, it is preferable that the region of the oxide semiconductor layer that becomes the channel is separated from the gate insulating film. .

[0279] Therefore, the oxide semiconductor layer 130 is divided into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible to form a

[0280] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers with different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0281] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) The layers are fabricated so that a U-shaped well is formed. There are no impurities that form defect levels such as trap centers or recombination centers at the interface. If impurities are mixed between the stacked oxide semiconductor layers, When the energy band is not uniform, the continuity of the energy band is lost and carriers are trapped or recombined at the interface. It will disappear when combined.

[0282] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are made of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. When the above oxides are used as sputtering targets for film formation, the oxide semiconductor film formed is The atomic ratio of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c is not necessarily They are not necessarily identical and may vary by approximately ±20%.

[0283] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 becomes a well, and the oxide In the transistor using the semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. The oxide semiconductor layer 130 has a conduction band minimum that changes continuously. Therefore, it can also be called a U-shaped well. can also be called a buried channel.

[0284] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a film such as a silicon oxide film. Trap levels due to impurities and defects can be formed near the interface with the insulating layer. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c allows the oxide semiconductor layer 13 This can keep 0b away from the trap level.

[0285] However, the energy of the conduction band minimum of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the bottom of the conduction band of the oxide semiconductor layer 130b and the energy of the bottom of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap level, a negative charge is generated at the interface of the insulating layer, and the transistor The threshold voltage of the transistor shifts in the positive direction.

[0286] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, it is possible to form a transistor. In addition, the c-axis oriented crystal is resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0287] Conductive layer 140 acts as a source electrode layer and conductive layer 1 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Typical examples include Ti, which is particularly susceptible to bonding with oxygen, and materials that can be processed at relatively high temperatures afterward. For these reasons, it is more preferable to use W, which has a high melting point. Also, low-resistance Cu and Cu-M A stack of an alloy such as n and the above material may be used. In the transistors 106, 111, and 112, for example, the conductive layer 14 The conductive layers 141 and 151 are made of W, and the conductive layers 142 and 152 are made of a laminated film of Ti and Al. etc. can be used.

[0288] The above material has a property of extracting oxygen from the oxide semiconductor film. In a part of the oxide semiconductor layer, oxygen is released from the oxide semiconductor film, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0289] When W is used for the conductive layer 140 and the conductive layer 150, nitrogen doping is also effective. By doping with nitrogen, the oxygen-pulling property can be weakened appropriately, and n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding into the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the As the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0290] The insulating layer 160, which acts as a gate insulating film, may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. It may contain the following as impurities.

[0291] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0292] Hafnium oxide and aluminum oxide are relatively Therefore, the thickness of the insulating layer 160 can be made larger than when silicon oxide is used. Therefore, the leakage current due to the tunnel current can be reduced. It is possible to realize a transistor with a small current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to make a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

[0293] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the insulating layer 120 is in contact with a conductor, the density of levels caused by nitrogen oxides may increase. The insulating layer 160 may be made of, for example, a silicon oxynitride film or a silicon nitride film that emits a small amount of nitrogen oxide. An oxide insulating layer such as an aluminum oxynitride film can be used.

[0294] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it releases, typically 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower The amount released is the amount released by the

[0295] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0296] The conductive layer 170 acting as a gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or Ni. Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Furthermore, alloys of the above materials and conductive nitrides of the above materials may also be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are used. Typically, tungsten or a stack of tungsten and titanium nitride is used. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys, etc. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a silicon dioxide film.

[0297] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor transistor 106, transistor 109, transistor 110, and transistor 112 By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer becomes n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0298] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In transistors 107, 108, and 111, the insulating layer 175 is made of oxide. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Therefore, aluminum oxide has a high blocking effect, preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. to prevent oxygen from being mixed into the oxide semiconductor layer 130, to prevent oxygen from being released from the oxide semiconductor layer, and to prevent the insulating layer 1 Suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen from 20 In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0299] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0300] Here, the insulating layer 180 has a larger amount of oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that oxygen released from the insulating layer 180 travels through the insulating layer 160 to the oxide semiconductor. Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, which leads to the formation of a stable transistor. Electrical properties can be obtained.

[0301] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate with the miniaturization of the channel width. When the size is reduced, the on-current decreases.

[0302] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and reduces the on-state voltage of the transistor. The flow can be increased.

[0303] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from the direction perpendicular to the channel forming layer. Since the gate electric field is applied to the It can be improved.

[0304] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. In the first embodiment, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. This has the effect of making it difficult for an interface state to be formed. In a transistor having a three-layer oxide semiconductor layer 130, the oxide semiconductor layer 130b is located in the middle of the three-layer structure. By placing it in the layer above the ground, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor as described above, the threshold voltage is stabilized. Therefore, it is possible to reduce the S value (subthreshold value). The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. Furthermore, the transistor of one embodiment of the present invention can improve electrical characteristics with miniaturization. Since deterioration of the semiconductor device can be suppressed, it can be said that this method is suitable for forming a highly integrated semiconductor device.

[0305] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The film can be formed by sputtering or plasma CVD, but other methods, such as thermal The film may be formed by a CVD method. Examples of thermal CVD methods include MOCVD (Metal O Organic Chemical Vapor Deposition (ALD) and ALD There are also other methods such as the Atomic Layer Deposition (ALD) method.

[0306] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0307] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0308] In the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is introduced into the chamber. The film is formed by repeating this process. For example, two or more kinds of carrier gases (e.g., argon, nitrogen, etc.) may be introduced. The source gases may be supplied to the chamber in order. In this case, multiple source gases are not mixed. In this way, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced into the surface of the substrate to form a first layer by adsorbing and reacting with the surface of the substrate. The second source gas introduced later is adsorbed and reacted with the first layer, and the second layer is formed on the first layer. The order of gas introduction is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is introduced. This is suitable for fabricating miniaturized FETs.

[0309] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a Zn-O film, trimethylindium (In(CH3)3), Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and trimethylgallium may be replaced with triethylene. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0310] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0311] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas, which is vaporized from other materials, and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0312] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are supplied. is fed to react with the adsorbate.

[0313] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0314] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced sequentially to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0315] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0316] (Sixth embodiment) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0317] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0318] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0319] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0320] First, the CAAC-OS film will be described.

[0321] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0322] Transmission Electron Microscope (TEM) A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also reveal clear boundaries between crystalline parts, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0323] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. The CAAC-OS film is formed on a surface (also called a surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface thereof.

[0324] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0325] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0326] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0327] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0328] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0329] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may occur.

[0330] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0331] Next, a microcrystalline oxide semiconductor film will be described.

[0332] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0333] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the D device, the crystal plane is In addition, the peaks indicating the probes larger than the crystalline part were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. If you do this, you may observe a circular (ring-shaped) area of ​​high brightness. When nanobeam electron diffraction was performed on the nc-OS film, multiple spots were observed within the ring-shaped region. It may be observed.

[0334] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0335] Next, the amorphous oxide semiconductor film will be described.

[0336] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0337] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0338] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0339] The oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly, for amorphous-like oxidation. Amorphous-like semiconductors (amorphous-like OS:amorphous-like Ox This is called an ide semiconductor film.

[0340] Amorphous-like OS membranes appear as voids in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiation with a small amount of electrons, the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of high quality, However, crystallization due to the minute amount of electron irradiation, such as observed by TEM, is hardly observed.

[0341] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystal structure of InGaZnO4 is It has a layered structure with two Ga-Zn-O layers between In-O layers. The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is , which is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is estimated to be 0.29 nm. Therefore, we focused on the lattice fringes in the high-resolution TEM image. However, in the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0342] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film or an amorphous-like e. A stacked film including two or more of an OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. may be.

[0343] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. (Embodiment 7)

[0344] An imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are used in a display device, a personal computer ... personal computers, image playback devices equipped with recording media (typically DVDs: Digital l Versatile Disc and other recording media can be played and images can be displayed on the disc. In addition, the imaging device according to one embodiment of the present invention can be used in a device having a display. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) Examples of such electronic devices include electronic devices such as smartphones, tablets, and vending machines. Specific examples of such electronic devices are shown in Figure 49.

[0345] FIG. 49(A) shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 38(A) has two display units 903 and the like. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The lensless imaging device of one embodiment of the present invention can be used for the camera 909. .

[0346] FIG. 49(B) shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The lensless imaging device of one embodiment of the present invention can be used as the camera 919.

[0347] FIG. 49(C) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband 9 The display unit 932 may be a touch panel. The lensless imaging device of one embodiment of the present invention can be used as the lens 939.

[0348] FIG. 49(D) shows a mobile phone, which includes a housing 951, a display unit 952, a microphone 957, a speaker, and the like. The camera 954, the camera 959, the input / output terminal 956, the operation button 955, etc. The lensless imaging device of one embodiment of the present invention can be used as 959.

[0349] FIG. 49(E) shows an automobile, which includes a body 961, wheels 962, a dashboard 963, and lights. 964, and a camera 965. The camera 965 also has a function of detecting the position of a nearby object. In this case, the lensless imaging device of one embodiment of the present invention can be used.

[0350] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0351] 21 Imaging operation 22 Holding operation 23 Read operation 40 Silicon substrate 41 Insulating layer 41a Insulating layer 41b insulating layer 51 Transistor 52 transistors 53 Transistor 54 transistors 55 transistors 56 transistors 58 Active layer 59 Capacitor 60 Photoelectric conversion element 61 Photoelectric conversion layer 62 Transparent conductive layer 63 Semiconductor layer 64 Semiconductor layer 65 Semiconductor layer 66 electrode 66a conductive layer 66b Conductive layer 67 Bulkhead 71 Wiring 72 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 77a Conductive layer 77b Conductive layer 78 Wiring 79 Wiring 80 insulating layer 81 Conductors 90 circuits 91 pixel array 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 112 transistors 115 PCB 120 insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating Layer 170 Conductive Layer 171 Conductive layer 172 Conductive layer 173 Conductive Layer 175 Insulating Layer 180 insulating layer 231 areas 232 areas 233 areas 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 331 areas 332 areas 333 areas 334 areas 335 areas 501 signal 502 signal 503 signal 504 signal 505 signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 Signal 704 signal 705 signal 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 chassis 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 939 Camera 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera 961 body 962 wheels 963 Dashboard 964 Light 965 Camera 1100 layers 1200 layers 1400 layers 1500 layers 1600 layers 2500 insulating layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b color filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation Layer

Claims

[Claim 1] 1. An imaging device having a first layer, a second layer, and a third layer, the second layer is provided between the first layer and the third layer; the first layer has a diffraction grating; the second layer has a photoelectric conversion element, The imaging device, wherein the third layer includes a transistor having an oxide semiconductor in an active layer.

Images