Switching device and method for manufacturing the same

Abstract

To form electric field relaxation regions with high position accuracy.SOLUTION: A method for manufacturing a switching device (10) includes the steps of: forming source regions (30) and a body region (34) on a semiconductor substrate (12) having a drift region (38); forming a mask (50) having openings (52) on a top face of the semiconductor substrate having the drift region; injecting a p-type impurity into the semiconductor substrate through the openings after forming the mask to form electric field relaxation regions (36) in the drift region; forming gate trenches (14) inside the openings after forming the electric field relaxation regions so that the electric field relaxation regions remain below the gate trenches; and forming gate insulator films (16) and gate electrodes (18) after forming the gate trenches.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a switching device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a switching device having a trench-type gate electrode. This switching device has a p-type electric field relaxation region in contact with the bottom surface of the gate trench. The electric field relaxation region is surrounded by an n-type drift region. The electric field relaxation region suppresses electric field concentration near the bottom end of the gate trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-116986 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method for manufacturing a switching device described in Patent Document 1, a field relaxation region is formed by implanting p-type impurities into a portion of the drift region. Next, an n-type layer and a p-type layer are sequentially epitaxially grown on a semiconductor substrate. Next, a gate trench is formed on the upper surface of the semiconductor substrate. Here, the gate trench is formed so that its lower end is located within the field relaxation region. Then, a gate electrode is formed in the gate trench. In this manufacturing method, the gate trench must be formed by aligning it with the field relaxation region so that its bottom surface is located within the field relaxation region. However, because the alignment accuracy of photolithography is not very high, the gate trench may be laterally misaligned with respect to the field relaxation region. For example, as shown in FIG. 12, the gate trench 120 may be laterally misaligned with respect to the field relaxation region 130, causing the corner portion 120c at the lower end of the gate trench 120 to extend outside the field relaxation region 130. If the corner portion 120c of the gate trench 120 extends beyond the electric field relaxation region 130 in this manner, the electric field tends to concentrate near the corner portion 120c, reducing the breakdown voltage of the switching device. For this reason, in the manufacturing method of Patent Document 1, the width of the electric field relaxation region must be significantly wider than the width of the gate trench so that the bottom of the gate trench is located within the electric field relaxation region even if the gate trench is laterally shifted relative to the electric field relaxation region. If the width of the electric field relaxation region is wider, problems such as an increase in the on-resistance of the switching device and an increase in the size of the switching device may occur.

[0005] Another method involves forming a gate trench before forming the electric field relaxation region and then implanting p-type impurities into the bottom surface of the gate trench to form the electric field relaxation region. However, this manufacturing method has the problem of prone to variation in the vertical position of the lower end of the electric field relaxation region (i.e., its position in the thickness direction of the semiconductor substrate). That is, when a gate trench is formed on the upper surface of a semiconductor substrate, the depth of the gate trench generally varies greatly. Therefore, when a p-type impurity is implanted into the bottom surface of the gate trench to form the electric field relaxation region, the position of the lower end of the electric field relaxation region varies greatly in the vertical direction. For example, as shown in FIG. 13, if there is variation in the depth D140 of the gate trench 140, when the electric field relaxation region 130 is formed by implanting p-type impurities into the bottom surface of the gate trench 140, the position D130 of the lower end of the electric field relaxation region 130 also varies due to the influence of the variation in the depth D140 of the gate trench. Vertical variation in the position of the lower end of the electric field relaxation region causes variation in the characteristics of the switching device.

[0006] Therefore, this specification proposes a technique for forming an electric field relaxation region with high positional accuracy. [Means for solving the problem]

[0007] This specification proposes a method for manufacturing a switching device, the switching device comprising: a semiconductor substrate having a gate trench on an upper surface thereof; a gate electrode disposed in the gate trench and insulated from the semiconductor substrate by a gate insulating film; an n-type source region in contact with the gate insulating film on a side surface of the gate trench; a p-type body region below the source region in contact with the gate insulating film on the side surface of the gate trench; a p-type electric field relaxation region in contact with the gate insulating film on the bottom surface of the gate trench; and an n-type drift region below the body region in contact with the gate insulating film on the side surface of the gate trench and in contact with the side surface and bottom of the electric field relaxation region. The manufacturing method includes the steps of: forming the source region and the body region in the semiconductor substrate having the drift region; forming a mask having an opening on the top surface of the semiconductor substrate having the drift region; forming the electric field relaxation region in the drift region by implanting p-type impurities into the semiconductor substrate through the opening after forming the mask; forming the gate trench by etching the top surface of the semiconductor substrate within the opening after forming the electric field relaxation region, the gate trench being formed so that the electric field relaxation region remains below the gate trench; and forming the gate insulating film and the gate electrode after forming the gate trench.

[0008] The step of forming the source region and the body region may be performed at any time, for example, before the step of forming the mask, or after the step of forming the gate electrode.

[0009] In this manufacturing method, a field relaxation region is formed by implanting p-type impurities into a semiconductor substrate through an opening in a mask, and then a gate trench is formed by etching the upper surface of the semiconductor substrate within the same opening in the mask. This reduces lateral misalignment between the field relaxation region and the gate trench. Furthermore, in this manufacturing method, the gate trench is formed after the field relaxation region is formed, so the position of the lower end of the field relaxation region is not affected by variations in the depth of the gate trench. This reduces vertical variations in the position of the lower end of the field relaxation region. In this way, this manufacturing method reduces lateral misalignment of the field relaxation region relative to the gate trench and also reduces vertical variations in the position of the lower end of the field relaxation region. In other words, the field relaxation region can be formed with high positional accuracy. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of a MOSFET 10 according to an embodiment. [Figure 2] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 3] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 4] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 5] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 6] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 7] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 8] 3A to 3C are explanatory diagrams of a manufacturing method of the MOSFET 10 according to the embodiment. [Figure 9] FIG. 2 is an explanatory diagram of a current path of the MOSFET 10 according to the embodiment. [Figure 10] FIG. 10 is an explanatory diagram of a current path of a MOSFET according to a comparative example. [Figure 11] FIG. 10 is a cross-sectional view of a modified MOSFET. [Figure 12]10 is a cross-sectional view showing a lateral misalignment of the electric field reduction region with respect to the gate trench. FIG. [Figure 13] 10 is a cross-sectional view showing variations in the vertical position of the electric field relaxation region when p-type impurities are implanted into the bottom surface of the gate trench. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the exemplary manufacturing method disclosed in the present specification, in the step of forming the electric field buffer region, the electric field buffer region may be formed so that the width of the electric field buffer region increases toward the lower side.

[0012] According to this configuration, the width of the electric field relaxation region is increased near the bottom surface of the gate trench, so that the entire bottom surface of the gate trench is easily covered by the electric field relaxation region, and electric field concentration near the lower end of the gate trench can be effectively suppressed.

[0013] In the exemplary manufacturing method disclosed in this specification, in the step of forming the gate trench, the gate trench may be formed so that the width of the gate trench becomes narrower toward the bottom.

[0014] According to this configuration, the width of the bottom surface of the gate trench is narrowed, so that the entire bottom surface of the gate trench is easily covered with the electric field relaxation region, and electric field concentration near the lower end of the gate trench can be effectively suppressed.

[0015] In one example of the manufacturing method disclosed in this specification, after the step of forming the gate trench, the method may further include a step of etching the side surface of the gate trench.

[0016] According to this configuration, the width of the portion where the drift region contacts the gate insulating film above the electric field relaxation region is increased, and variations in the mirror capacitance of the switching element are suppressed.

[0017] In the example manufacturing method disclosed herein, a width of the bottom surface of the gate trench may be narrower than a width of the electric field relaxation region. In the step of forming the gate trench, the gate trench may be formed so that the electric field relaxation region contacts each corner portion between the bottom surface of the gate trench and the side surface of the gate trench.

[0018] This configuration effectively suppresses electric field concentration near the bottom end of the gate trench.

[0019] In one example of the manufacturing method disclosed herein, the drift region may have a low-concentration region and a high-concentration region having a higher n-type impurity concentration than the low-concentration region and disposed above the low-concentration region. In the step of forming the electric field buffer region, the electric field buffer region may be formed in the high-concentration region such that a lower end of the electric field buffer region is located within the high-concentration region.

[0020] With this configuration, the position of the lower end of the electric field buffer region is less likely to vary in the depth direction, making it easy to position the lower end of the electric field buffer region above the lower end of the high-concentration region. By positioning the lower end of the electric field buffer region above the lower end of the high-concentration region, the on-resistance of the switching element can be reduced.

[0021] This specification proposes a switching device. The switching device may include a semiconductor substrate having a plurality of gate trenches on its upper surface, a plurality of gate electrodes disposed in the gate trenches and insulated from the semiconductor substrate by gate insulating films, an n-type source region contacting the gate insulating film at the side surfaces of the gate trenches, a p-type body region below the source regions contacting the gate insulating film at the side surfaces of the gate trenches, a plurality of p-type electric field relaxation regions contacting the gate insulating film at the bottom surfaces of the gate trenches, and an n-type drift region contacting the gate insulating film at the side surfaces of the gate trenches below the body regions and contacting the side surfaces and bottom surfaces of the electric field relaxation regions. In each of the gate trenches, the deviation in the width direction between the center of the gate trench and the center of the electric field relaxation region below the gate trench may be 0.1 μm or less. Among the electric field relaxation regions, the variation in the distance from the top surface of the semiconductor substrate to the lower end of the electric field relaxation region in the thickness direction of the semiconductor substrate may be ±2% or less.

[0022] In this switching element, the lateral misalignment between the gate trench and the electric field buffer region is small, so electric field concentration near the bottom end of the gate trench can be effectively suppressed. Furthermore, in this switching element, the position of the bottom end of the electric field buffer region varies little in the depth direction (i.e., in the thickness direction of the semiconductor substrate). Therefore, this switching element is less likely to exhibit variations in characteristics. Furthermore, a switching element with such high positional accuracy of the electric field buffer region can be manufactured by any of the manufacturing methods described above.

[0023] In the switching device disclosed in the present specification, in each of the plurality of gate trenches, a width of the bottom surface of the gate trench may be narrower than a width of the electric field relaxation region below the gate trench, and in each of the plurality of gate trenches, the electric field relaxation region may contact each corner portion between the bottom surface of the gate trench and the side surface of the gate trench.

[0024] This configuration effectively suppresses electric field concentration near the bottom end of the gate trench. [Example]

[0025] FIG. 1 shows a metal oxide semiconductor field effect transistor (MOSFET) 10 according to an embodiment. The MOSFET 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC (i.e., silicon carbide). However, the semiconductor substrate 12 may be made of other materials such as silicon. In the following description, the thickness direction of the semiconductor substrate 12 is referred to as the z-direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, and a direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x-direction is referred to as the y-direction.

[0026] A plurality of gate trenches 14 are provided in the upper surface 12a of the semiconductor substrate 12. The gate trenches 14 are arranged at intervals in the x direction. Each gate trench 14 extends longitudinally in the y direction. The inner surface of each gate trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each gate trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the corresponding gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.

[0027] The MOSFET 10 has a source electrode 22 and a drain electrode 24. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The source electrode 22 contacts the semiconductor substrate 12 at the upper surface 12a. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The drain electrode 24 covers the entire lower surface 12b of the semiconductor substrate 12.

[0028] The semiconductor substrate 12 has a plurality of source regions 30 , a plurality of contact regions 32 , a body region 34 , a plurality of field relief regions 36 , a drift region 38 , and a drain region 40 .

[0029] Each source region 30 is an n-type region having a high concentration of n-type impurities. Each source region 30 is provided in an area facing the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the source electrode 22. Each source region 30 is in contact with the gate insulating film 16 at the upper end of the side surface of the gate trench 14.

[0030] Each contact region 32 is a p-type region having a high p-type impurity concentration. Each contact region 32 is provided in a range sandwiched between source regions 30 and facing the upper surface 12a of the semiconductor substrate 12. Each contact region 32 is in ohmic contact with the source electrode 22.

[0031] The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 is disposed below the source regions 30 and the contact regions 32. The body region 34 contacts the source regions 30 and the contact regions 32 from below. The body region 34 contacts the gate insulating film 16 on the side surface of each gate trench 14 below each source region 30.

[0032] Each electric field relaxation region 36 is a p-type region having a lower p-type impurity concentration than the contact region 32. Each electric field relaxation region 36 is disposed below the corresponding gate trench 14. Each electric field relaxation region 36 extends long in the y direction along the bottom surface of the corresponding gate trench 14. Each electric field relaxation region 36 is in contact with the gate insulating film 16 over the entire area of ​​the bottom surface of the corresponding gate trench 14. Each electric field relaxation region 36 is connected to the body region 34 by a p-type region provided at a position not shown. However, in other embodiments, each electric field relaxation region 36 may not be connected to the body region 34 and may be floating with respect to the body region 34.

[0033] The drift region 38 is an n-type region having a relatively low n-type impurity concentration. The drift region 38 is provided below the body region 34. The drift region 38 contacts the gate insulating film on the side surface of each gate trench 14 below the body region 34. The drift region 38 contacts the side surface and bottom surface of each electric field relaxation region 36. The drift region 38 has a high-concentration region 38a and a low-concentration region 38b. The high-concentration region 38a has a lower n-type impurity concentration than the source region 30. The low-concentration region 38b has a lower n-type impurity concentration than the high-concentration region 38a.

[0034] The high-concentration region 38a is distributed from the position of the lower surface of the body region 34 to a position below the lower end of each electric field relaxation region 36. The high-concentration region 38a contacts the body region 34 from below. The high-concentration region 38a contacts the gate insulating film 16 on the side surface of each gate trench 14 below the body region 34. That is, the high-concentration region 38a contacts the gate insulating film 16 in the range between the electric field relaxation region 36 and the body region 34 on the side surface of each gate trench 14 (i.e., the range of width W38 shown in FIG. 1). The high-concentration region 38a contacts the side surface and bottom surface of each electric field relaxation region 36. That is, the lower end of each electric field relaxation region 36 is located within the high-concentration region 38a.

[0035] The low-concentration region 38b is disposed below the high-concentration region 38a. The low-concentration region 38b contacts the high-concentration region 38a from below. The low-concentration region 38b is separated from each electric field relaxation region 36 by the high-concentration region 38a. In other words, the low-concentration region 38b does not contact each electric field relaxation region 36.

[0036] The drain region 40 is an n-type region having a higher n-type impurity concentration than the drift region 38 (i.e., a higher n-type impurity concentration than both the high-concentration region 38a and the low-concentration region 38b). The drain region 40 is disposed below the low-concentration region 38b. The drain region 40 contacts the low-concentration region 38b from below. The drain region 40 is disposed in an area facing the lower surface 12b of the semiconductor substrate 12. The drain region 40 is in ohmic contact with the drain electrode 24.

[0037] In FIG. 1, a center C14 indicates the center of the gate trench 14 in the width direction of the gate trench 14 (i.e., the x direction). Also, in FIG. 1, a center C36 indicates the center of the electric field relaxation region 36 in the width direction of the electric field relaxation region 36 (i.e., the x direction). In all gate trenches 14 included in the MOSFET 10, the deviation between the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 is 0.1 μm or less. That is, in the x direction, the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 substantially coincide with each other. Also, in all gate trenches 14 included in the MOSFET 10, the width W14 of the bottom surface of the gate trench 14 is narrower than the width W36 of the electric field relaxation region 36 at the position of the bottom surface of the gate trench 14. Therefore, each corner portion 14c connecting the bottom surface of the gate trench 14 and the side surface of the gate trench 14 is covered by the electric field relaxation region 36. That is, the electric field relaxation region 36 contacts the gate insulating film 16 at each corner 14 c of the gate trench 14 .

[0038] 1, distance L36 indicates the distance in the z direction from upper surface 12a of semiconductor substrate 12 to the lower end of electric field buffer region 36. The variation in distance L36 between the multiple electric field buffer regions 36 in MOSFET 10 is ±2% or less. In other words, the variation in distance L36 is extremely small.

[0039] Next, a method for manufacturing the MOSFET 10 of the embodiment will be described. First, a semiconductor substrate 12 (i.e., the semiconductor substrate 12 before processing) shown in FIG. 2 is prepared. The semiconductor substrate 12 shown in FIG. 2 is made of SiC. However, the semiconductor substrate 12 may be made of other materials such as silicon. The semiconductor substrate 12 shown in FIG. 2 has a drain region 40, a low-concentration region 38b, and a high-concentration region 38a. The low-concentration region 38b is disposed above the drain region 40, and the high-concentration region 38a is disposed above the low-concentration region 38b. The low-concentration region 38b and the high-concentration region 38a may be regions formed by epitaxial growth or by ion implantation. No electrodes, insulating films, or the like are provided on the upper surface 12a or the lower surface 12b of the semiconductor substrate 12 shown in FIG. 2.

[0040] First, epitaxial growth, ion implantation, and the like are performed on the semiconductor substrate 12 of FIG. 2 to form the source region 30, contact region 32, and body region 34 as shown in FIG.

[0041] 4, a mask 50 made of silicon oxide is formed on the upper surface 12a of the semiconductor substrate 12. Next, a plurality of openings 52 are formed in the mask 50 by photolithography, etching, or the like. Here, the mask 50 is formed so that each opening 52 is positioned above a portion of the semiconductor substrate 12 where the gate trench 14 and the electric field reduction region 36 are to be formed. In each opening 52, the upper surface 12a of the semiconductor substrate 12 is exposed.

[0042] Next, as shown in FIG. 5, p-type impurities are ion-implanted into the semiconductor substrate 12 through the mask 50. The mask 50 blocks the p-type impurities in the areas where the mask 50 is present. Therefore, the p-type impurities are implanted into the semiconductor substrate 12 through each opening 52. Here, the p-type impurities are implanted by adjusting the implantation energy of the p-type impurities so that the implanted p-type impurities reach the high-concentration region 38a but do not reach the low-concentration region 38b. That is, the p-type impurities are implanted into the shaded area shown in FIG. 5. The p-type impurities are implanted into the implantation range of the high-concentration region 38a at a higher concentration than in the high-concentration region 38a. Therefore, the p-type electric field relaxation region 36 is formed in the high-concentration region 38a. In this way, the p-type electric field relaxation region 36 is formed below the opening 52. The electric field relaxation region 36 is formed so that the lower end of the electric field relaxation region 36 is located within the high-concentration region 38a (that is, so that the lower end of the electric field relaxation region 36 does not contact the low-concentration region 38b). In the p-type impurity implantation range 30x of the source region 30, the n-type impurity concentration of the source region 30 is higher than the concentration of the implanted p-type impurity. Therefore, the p-type impurity implantation range 30x of the source region 30 is maintained as n-type. In the p-type impurity implantation range 34x of the body region 34, the p-type impurity concentration of the body region 34 increases.

[0043] The implantation depth of the p-type impurity can be controlled with relatively high precision. Therefore, the variation in the depth direction of the lower ends of the electric field relaxation regions 36 between the electric field relaxation regions 36 is extremely small. That is, the variation in the distance L36 between the electric field relaxation regions 36 is extremely small. In other words, according to this manufacturing method, the position of the lower ends of the electric field relaxation regions 36 in the z direction can be accurately controlled.

[0044] Furthermore, as the p-type impurities travel in the z direction through semiconductor substrate 12, they are scattered and diffuse in the x direction. Therefore, the width in the x direction of the p-type impurity implantation range (i.e., the shaded range) shown in FIG. 5 increases downward. Therefore, width W36 of the lower portion of electric field relaxation region 36 is slightly wider than width W52 of opening 52.

[0045] Next, the upper surface 12a of the semiconductor substrate 12 is etched using the same mask 50 used for the p-type impurity implantation. That is, the upper surface 12a of the semiconductor substrate 12 is etched within the openings 52 of the mask 50. As a result, as shown in FIG. 6, a gate trench 14 is formed in the upper surface 12a of the semiconductor substrate 12. Here, the gate trench 14 is formed by etching the semiconductor substrate 12 in the z-direction within the openings 52 using anisotropic etching such as reactive ion etching. Here, the gate trench 14 is formed so that it penetrates the source region 30 and the body region 34 and reaches the electric field relaxation region 36. Here, the gate trench 14 is formed so that the electric field relaxation region 36 remains below the gate trench 14. By forming the gate trench 14, most of the p-type impurity implantation region 30x in the source region 30 and the p-type impurity implantation region 34x in the body region 34 shown in FIG. 5 are removed. Because the ion implantation shown in FIG. 5 and the etching shown in FIG. 6 are performed using the same mask 50, the gate trench 14 is accurately formed at a position overlapping the electric field relaxation region 36. This allows the center C14 of the gate trench 14 to be aligned with the center C36 of the electric field relaxation region 36 with high accuracy. That is, according to this manufacturing method, the positional deviation in the x direction between the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 can be kept to 0.1 μm or less.

[0046] Furthermore, in the process of forming the gate trench 14, etching conditions are adjusted to form the gate trench 14 so that the width of the gate trench 14 in the x direction narrows toward the bottom. Therefore, the width W14k of the bottom surface of the gate trench 14 in the x direction is slightly narrower than the width W52 of the opening 52. As described above, the width W36 of the lower portion of the electric field relaxation region 36 is slightly wider than the width W52 of the opening 52. Therefore, the electric field relaxation region 36 is present on both sides of the bottom surface of the gate trench 14 in the x direction. In other words, the corner portions 14c of the gate trench 14 are covered with the electric field relaxation region 36.

[0047] Next, the mask 50 is removed. Next, a carbon film is formed to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the gate trench 14. Next, the semiconductor substrate 12 is annealed to activate the p-type impurities implanted into the semiconductor substrate 12. The carbon film prevents silicon atoms from diffusing outward from the semiconductor substrate 12 during the annealing step. After the annealing step, the carbon film is removed.

[0048] Next, as shown in FIG. 7 , the upper surface 12 a of the semiconductor substrate 12 and the inner surface of the gate trench 14 are etched by isotropic etching (e.g., CDE (chemical dry etching)). This removes damaged layers (i.e., layers damaged by ion implantation, etching, etc.) present on the upper surface 12 a and the inner surface of the gate trench 14. Furthermore, etching the side surfaces of the gate trench 14 in this manner slightly increases the width of the gate trench 14. For example, the width of the bottom surface of the gate trench 14 increases from width W14k shown in FIG. 6 to width W14 shown in FIG. 7. Since the increase in the width of the gate trench 14 is slight, an electric field relaxation region 36 remains adjacent to the side surface of the gate trench 14 near the bottom surface of the gate trench 14. Furthermore, the slight increase in the width of the gate trench 14 removes the upper portion of the electric field relaxation region 36 (i.e., portion 36u shown in FIG. 6 ). Therefore, as shown in FIG. 7, in the upper part of the electric field relaxation region 36, the high concentration region 38a is exposed on the side surface of the gate trench 14.

[0049] Next, as shown in FIG. 8, a gate insulating film 16 is formed to cover the inner surface of the gate trench 14. As a result, the source region 30 contacts the gate insulating film 16 at the upper end of the side surface of the gate trench 14. Furthermore, the body region 34 contacts the gate insulating film 16 on the side surface of the gate trench 14 below the source region 30. Furthermore, the high-concentration region 38a contacts the gate insulating film 16 below the body region 34 (i.e., in the range between the body region 34 and the electric field relaxation region 36). Furthermore, the electric field relaxation region 36 contacts the gate insulating film 16 on the bottom surface of the gate trench 14 and the side surface near the bottom surface. Next, as shown in FIG. 8, a gate electrode 18 is formed in the gate trench 14.

[0050] 1, an interlayer insulating film 20 is formed to cover the upper surface of the gate electrode 18. Next, a source electrode 22 is formed to cover the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. Next, a drain electrode 24 is formed to cover the lower surface 12b of the semiconductor substrate 12. As a result, the MOSFET 10 shown in FIG. 1 is completed.

[0051] Next, the operation of the MOSFET 10 will be described. The MOSFET 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 34 near the gate insulating film 16. As a result, as shown by arrow 92 in FIG. 9 , electrons flow from the drain region 40 to the source region 30 through the low-concentration region 38b, the high-concentration region 38a, and the channel in the body region 34. In other words, the MOSFET 10 is turned on. When the potential of the gate electrode 18 is reduced to a potential equal to or lower than the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off.

[0052] When the MOSFET 10 is turned off, a depletion layer spreads from the body region 34 to the drift region 38. Depletion of the drift region 38 allows the MOSFET 10 to sustain a high voltage applied between the drain electrode 24 and the source electrode 22. Furthermore, when the MOSFET 10 is turned off, a depletion layer spreads from the electric field relaxation region 36 to the high-concentration region 38a around the bottom end of the gate trench 14. The depletion layer spreading from the electric field relaxation region 36 to the high-concentration region 38a suppresses electric field concentration around the bottom end of the gate trench 14. Therefore, the MOSFET 10 has a high breakdown voltage. As shown in FIG. 12 , if the corners of the gate trench are positioned outside the electric field relaxation region due to misalignment between the gate trench and the electric field relaxation region, electric field concentration occurs around the corners. In contrast, in the above-described manufacturing method, the electric field relaxation region 36 and the gate trench 14 are formed using a common mask 50, thereby suppressing misalignment of the electric field relaxation region 36 with respect to the gate trench 14 (more specifically, misalignment of the center C36 of the electric field relaxation region 36 with respect to the center C14 of the gate trench 14). This suppresses the corner portion 14c from extending beyond the electric field relaxation region 36. Therefore, the above-described manufacturing method more reliably prevents electric field concentration near the bottom end of the gate trench 14. Furthermore, in the above-described manufacturing method, since there is almost no misalignment of the electric field relaxation region 36 with respect to the gate trench 14, the corner portion 14c can be suppressed from extending beyond the electric field relaxation region 36 even if the width W36 of the electric field relaxation region 36 is not very wide. Since the width W36 of the electric field relaxation region 36 can be made relatively narrow, the MOSFET 10 can be miniaturized. Furthermore, since the width W36 of the electric field relaxation region 36 can be made relatively narrow, electrons can flow through a relatively short path, as indicated by the arrow 92 in FIG. 9 . This reduces the on-resistance of the MOSFET 10.

[0053] The dashed line 90 in FIG. 9 indicates the depletion layer that spreads from the electric field relaxation region 36 to its periphery due to the built-in potential when the MOSFET 10 is on. As mentioned above, the arrows 92 in FIG. 9 indicate the path through which electrons flow when the MOSFET 10 is on. As shown in FIG. 9, when the MOSFET 10 is on, electrons flow while avoiding the depletion layer 90. Because the high-concentration region 38a adjacent to the electric field relaxation region 36 has a relatively high n-type impurity concentration, the range over which the depletion layer 90 spreads is narrow. Therefore, as shown by the arrows 92, electrons can flow through a relatively short path. Therefore, the on-resistance of the MOSFET 10 is low. Also, FIG. 10 shows, as a comparative example, the current path in a MOSFET in which the electric field relaxation region 36 extends from the high-concentration region 38a into the low-concentration region 38b. When the field relaxation region 36 contacts the low-concentration region 38b as shown in Figure 10, the low-concentration region 38b has a low n-type impurity concentration. Therefore, when the MOSFET 10 is on, a depletion layer 90 spreads widely from the high-concentration region 38a into the low-concentration region 38b due to the built-in potential. When the depletion layer 90 spreads widely into the low-concentration region 38b, electrons take a large detour to avoid the depletion layer 90, as shown by arrow 94. As a result, the electron flow path becomes longer, increasing the on-resistance of the MOSFET. For example, in the method of forming a field relaxation region by implanting p-type impurities into the bottom of the gate trench shown in Figure 13, the position of the bottom edge of the field relaxation region varies greatly due to variations in the depth of the gate trench. As a result, when the field relaxation region 36 is formed in the high-concentration region 38a as shown in Figure 9, the field relaxation region 36 may contact the low-concentration region 38b as shown in Figure 10. Therefore, forming a field relaxation diffusion region by implanting p-type impurities into the bottom of the gate trench increases the on-resistance of the MOSFET. In contrast, in the manufacturing method of the above embodiment, the gate trench 14 is formed after the electric field relaxation region 36 is formed, so the position of the lower end of the electric field relaxation region 36 (i.e., distance L36) is not affected by variations in the depth of the gate trench 14. Therefore, according to the manufacturing method of the embodiment, variations in the position of the lower end of the electric field relaxation region 36 can be suppressed, and the electric field relaxation region 36 can be prevented from being formed so as to contact the low-concentration region 38b.Therefore, by manufacturing the MOSFET 10 by the manufacturing method of the embodiment, the variation in the on-resistance of the MOSFET 10 can be suppressed.

[0054] Furthermore, in the manufacturing method of the above-described embodiment, the electric field relaxation region 36 is formed so that its width increases toward its lower side, and the gate trench 14 is formed so that its width decreases toward its lower side. Therefore, the width W36 of the electric field relaxation region 36 can be made wider than the width W14 of the gate trench 14 at the bottom of the gate trench 14. This allows the gate trench 14 and the electric field relaxation region 36 to be positioned so that the corner portions 14c of the gate trench 14 are reliably covered by the electric field relaxation region 36. This more reliably prevents electric field concentration near the bottom end of the gate trench 14. Note that in other embodiments, the electric field relaxation region 36 does not need to be formed so that its width increases toward its lower side, and the gate trench 14 does not need to be formed so that its width decreases toward its lower side. For example, if the electric field relaxation region 36 is formed so that its width increases toward its lower side, the gate trench 14 does not need to be formed so that its width decreases toward its lower side. Furthermore, when the gate trench 14 is formed so that its width narrows toward the bottom, the electric field relaxation region 36 does not need to be formed so that its width widens toward the bottom. As long as the corner portion 14c of the gate trench 14 can be covered with the electric field relaxation region 36, the electric field relaxation region 36 and the gate trench 14 may have any shape.

[0055] Furthermore, according to the manufacturing method of the above-described embodiment, the electric field buffer region 36 can be formed with high precision, thereby suppressing variations in the width W38 in the z direction of the portion where the high-concentration region 38a contacts the gate insulating film 16 (i.e., the portion between the body region 34 and the electric field buffer region 36). The width W38 affects the mirror capacitance of the MOSFET 10. According to the manufacturing method of the above-described embodiment, variations in the width W38 are suppressed, thereby suppressing variations in the mirror capacitance of the MOSFET 10. In particular, according to the manufacturing method of the above-described embodiment, the side surfaces of the gate trench 14 are etched after the gate trench 14 is formed. Etching the side surfaces of the gate trench 14 allows the width W38 to be wide. Ensuring a wide width W38 suppresses variations in the width W38, thereby more effectively suppressing variations in the mirror capacitance.

[0056] In the above-described embodiment, drift region 38 has high-concentration region 38a and low-concentration region 38b. However, as shown in Fig. 11, drift region 38 may be composed of a single-concentration n-type region. Even in this case, variation in the position of the bottom end of electric field relaxation region 36 (i.e., distance L36) is suppressed, thereby suppressing variation in the characteristics of the MOSFET.

[0057] In the manufacturing method of the above-described embodiment, the source region 30, the contact region 32, and the body region 34 are formed before forming the electric field relaxation region 36 and the gate trench 14. However, the source region 30, the contact region 32, and the body region 34 may be formed by ion implantation or the like after forming the electric field relaxation region 36 and the gate trench 14.

[0058] Furthermore, in the above-described embodiments, a MOSFET has been described, but the technology disclosed in this specification may be applied to other switching devices (for example, an IGBT (insulated gate bipolar transistor)).

[0059] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0060] 12: semiconductor substrate, 14: gate trench, 16: gate insulating film, 18: gate electrode, 30: source region, 32: contact region, 34: body region, 36: electric field relaxation region, 38: drift region, 38a: high concentration region, 38b: low concentration region, 40: drain region

Claims

1. A method for manufacturing a switching device (10), comprising: The switching device a semiconductor substrate (12) having a gate trench (14) on an upper surface thereof; a gate electrode (18) disposed in the gate trench and insulated from the semiconductor substrate by a gate insulating film (16); an n-type source region (30) in contact with the gate insulating film on the side surface of the gate trench; a p-type body region (34) contacting the gate insulating film on the side surface of the gate trench below the source region; a p-type electric field relaxation region (36) in contact with the gate insulating film at the bottom surface of the gate trench; an n-type drift region (38) in contact with the gate insulating film on the side surface of the gate trench below the body region and in contact with the side surface and bottom surface of the electric field relaxation region; and The manufacturing method comprises: forming the source region and the body region in the semiconductor substrate having the drift region; forming a mask (50) having an opening (52) on the top surface of the semiconductor substrate having the drift region; forming the electric field relaxation region in the drift region by implanting p-type impurities into the semiconductor substrate through the opening after forming the mask; forming the gate trench by etching the top surface of the semiconductor substrate within the opening after forming the electric field relief region, the gate trench being formed such that the electric field relief region remains below the gate trench; forming the gate insulating film and the gate electrode after forming the gate trench; A manufacturing method comprising the steps of:

2. The manufacturing method according to claim 1 , wherein in the step of forming the electric field buffer region, the electric field buffer region is formed so that the width of the electric field buffer region increases toward the lower side.

3. The manufacturing method according to claim 2 , wherein in the step of forming the gate trench, the gate trench is formed so that the width of the gate trench becomes narrower toward the bottom.

4. 4. The manufacturing method according to claim 1, further comprising the step of etching the side surface of the gate trench after the step of forming the gate trench.

5. the width of the bottom surface of the gate trench is narrower than the width of the electric field relaxation region, In the step of forming the gate trench, the gate trench is formed so that the electric field relaxation region contacts each corner portion (14c) between the bottom surface of the gate trench and the side surface of the gate trench. The method according to any one of claims 1 to 4.

6. the drift region has a low concentration region (38b) and a high concentration region (38a) having a higher n-type impurity concentration than the low concentration region and disposed above the low concentration region, In the step of forming the electric field buffer region, the electric field buffer region is formed in the high concentration region so that a lower end of the electric field buffer region is located within the high concentration region. The method according to any one of claims 1 to 5.

7. A switching device (10), comprising: a semiconductor substrate (12) having a plurality of gate trenches (14) on an upper surface thereof; a plurality of gate electrodes (18) disposed within the plurality of gate trenches and insulated from the semiconductor substrate by a gate insulating film (16); n-type source regions (30) in contact with the gate insulating film on the side surfaces of the plurality of gate trenches; a p-type body region (34) contacting the gate insulating film on the side surfaces of the gate trenches below the source regions; a plurality of p-type electric field relaxation regions (36) in contact with the gate insulating film at the bottom surfaces of the plurality of gate trenches; an n-type drift region (38) in contact with the gate insulating film on the side surfaces of the gate trenches below the body region and in contact with the side surfaces and bottom surfaces of the electric field relaxation regions; and In each of the plurality of gate trenches, a deviation between a center (C14) of the gate trench in the width direction and a center (C36) of the electric field relaxation region below the gate trench in the width direction is 0.1 μm or less, a variation in a distance (L36) from the upper surface of the semiconductor substrate to a lower end of each electric field relaxation region in a thickness direction of the semiconductor substrate is ±2% or less among the plurality of electric field relaxation regions; Switching device.

8. In each of the plurality of gate trenches, the width of the bottom surface of the gate trench is narrower than the width of the electric field relief region below the gate trench, In each of the plurality of gate trenches, the electric field relaxation region is in contact with each corner portion (14c) between the bottom surface of the gate trench and the side surface of the gate trench.

8. The switching device of claim 7.

Images