Semiconductor device, semiconductor package, and method for manufacturing these

Abstract

To provide a semiconductor device, a semiconductor package, and a method for manufacturing these capable of improving mechanical strength.SOLUTION: A semiconductor device includes a semiconductor layer having a first main surface on one side and a second main surface on the other side, a first main surface electrode comprising a first electrode covering the first main surface, and a second electrode having a higher hardness than the first electrode and covering the first electrode, and an oxide layer covering the first main surface electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-082702 filed with the Japan Patent Office on May 8, 2020, the entire disclosure of which is incorporated herein by reference. The present invention relates to a semiconductor device, a semiconductor package, and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a technique relating to a vertical semiconductor element using a SiC semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-79945 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device, a semiconductor package, and a method for manufacturing the same, which can improve mechanical strength. [Means for solving the problem]

[0005] One embodiment of the present invention provides a semiconductor device including a vertical power semiconductor element, the semiconductor layer having a first main surface and a second main surface opposite to the first main surface and containing SiC as a main component, a first electrode layer formed on the first main surface side of the semiconductor layer, a second electrode layer formed on the first electrode layer, electrically connected to a first terminal of the vertical power semiconductor element, and harder than the first electrode layer, a third electrode layer formed on the second main surface side of the SiC semiconductor layer, and electrically connected to a second terminal of the vertical power semiconductor element, and an oxide layer formed on a surface of the second electrode layer.

[0006] One embodiment of the present invention provides a method for manufacturing a semiconductor device including a vertical power semiconductor element, the method including the steps of: forming a first electrode layer on a first main surface side of a semiconductor layer containing SiC as a main component; forming a second electrode layer on the first electrode layer, the second electrode layer being electrically connected to a first terminal of the vertical power semiconductor element and being harder than the first electrode layer; and connecting a bonding wire to the second electrode layer.

[0007] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; a first main surface electrode including a first electrode covering the first main surface and a second electrode having a higher hardness than the first electrode and covering the first electrode; and an oxide layer covering the first main surface electrode.

[0008] One embodiment of the present invention includes the steps of: providing a semiconductor layer having a principal surface; forming a first electrode on the principal surface; and forming a second electrode on the first electrode, the second electrode having a higher hardness than the first electrode, thereby forming a first principal surface electrode including the first electrode and the second electrode on the principal surface; and forming an oxide layer covering an outer surface of the first principal surface electrode. A method for manufacturing a semiconductor device is provided.

[0009] One embodiment of the present invention provides a semiconductor device including: a semiconductor layer having a first main surface on one side and a second main surface on the other side; an interlayer insulating layer selectively covering the semiconductor layer on the first main surface; a first electrode covering the first main surface and the interlayer insulating layer; a first main surface electrode including a second electrode having a higher hardness than the first electrode and covering the first electrode; and an oxide layer covering the first main surface electrode, wherein the first main surface has a concave-convex structure due to the presence or absence of the interlayer insulating layer, and the surface of the first electrode includes a concave-convex portion formed according to the concave-convex structure. A difference between a highest position and a lowest position in a thickness direction of the second electrode may be smaller than a difference between a highest position and a lowest position in the thickness direction of the first electrode.

[0010] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device according to the embodiment. [Figure 3A] FIG. 3A is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3B] FIG. 3B is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3C] FIG. 3C is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3D] FIG. 3D is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3E] FIG. 3E is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 3F] FIG. 3F is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a modified example of the semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a perspective view of a semiconductor package according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view of the diode semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement positions, component connection forms, steps, step orders, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Among the components in the following embodiments, components not recited in independent claims will be described as optional components.

[0013] The accompanying drawings are schematic diagrams and are not necessarily precisely illustrated. Therefore, for example, the scales of the accompanying drawings are not necessarily the same. In the accompanying drawings, substantially identical components are assigned the same reference numerals, and duplicated explanations are omitted or simplified.

[0014] In this specification, terms indicating the relationship between elements, such as vertical and horizontal, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that mean to include a substantially equivalent range.

[0015] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Specifically, in this specification, the first main surface side of one semiconductor layer is described as the upper side (upper), and the second main surface side of the other semiconductor layer is described as the lower side (lower). When the semiconductor device (vertical transistor) is actually used, the first main surface side may be the lower side (lower) and the second main surface side may be the upper side (upper). Alternatively, the semiconductor device (vertical transistor) may be used with the first and second main surfaces inclined or perpendicular to a horizontal plane.

[0016] In addition, the terms "above" and "below" apply not only when two components are arranged with a gap between them so that another component is interposed between them, but also when two components are arranged so that they are in close contact with each other.

[0017] The configuration of a semiconductor device according to this embodiment will be described below. Fig. 1 is a plan view showing a semiconductor device 101 according to this embodiment. The semiconductor device 101 includes a power semiconductor device (power semiconductor element) as an example of a functional device. In the following, an example in which the semiconductor device 101 includes a vertical transistor will be shown.

[0018] Referring to FIG. 1, semiconductor device 101 has a SiC semiconductor layer 102 including a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. In this embodiment, SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip. SiC semiconductor layer 102 includes a first main surface 103 on one side and a second main surface 104 on the other side. First main surface 103 is a device surface on which a main structure of a functional device is formed. Second main surface 104 may be a mounting surface that faces a connection target when semiconductor device 101 is connected to the connection target.

[0019] The length of one side of the SiC semiconductor layer 102 may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The SiC semiconductor layer 102 has an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0020] The semiconductor device 101 includes a gate electrode 108, gate fingers 109, and a source electrode 110, each formed on a first main surface 103 of a SiC semiconductor layer 102. The gate electrode 108 and the source electrode 110 are each formed as an example of a first main surface electrode. The gate electrode 108 may also be referred to as a gate pad, and the source electrode 110 may also be referred to as a source pad. In FIG. 1, the gate electrode 108, the gate fingers 109, and the source electrode 110 are indicated by hatching for clarity. The gate electrode 108, the gate fingers 109, and the source electrode 110 may contain aluminum or copper.

[0021] The gate electrode 108 is formed in a quadrangular shape in a plan view. The gate electrode 108 is drawn from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view. The gate finger 109 is formed in the outer region 107. The gate finger 109 is drawn from the gate electrode 108 and extends in a strip shape in the outer region 107.

[0022] The source electrode 110 is formed in the active region 106 at a distance from the gate electrode 108 and the gate fingers 109. The source electrode 110 is formed in a concave shape in a plan view so as to cover the concave region defined by the gate electrode 108 and the gate fingers 109. A gate voltage is applied to the gate electrode 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source electrode 110. The source voltage may be a reference voltage (for example, a GND voltage).

[0023] 2 is a cross-sectional view of the SiC semiconductor layer 102, and is a cross-sectional view of the MISFET in the active region 106 in a first direction X. The first direction X is an arbitrary direction along the first main surface 103 (second main surface 104) of the SiC semiconductor layer 102. Referring to FIG. 2, the SiC semiconductor layer 102 in this embodiment has n +The MISFET has a layered structure including an n-type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122. The SiC semiconductor substrate 121 is formed as a drain region of the MISFET. The SiC epitaxial layer 122 is formed as a drift region of the MISFET.

[0024] The SiC semiconductor substrate 121 forms the second main surface 104 of the SiC semiconductor layer 102. The SiC epitaxial layer 122 forms the first main surface 103 of the SiC semiconductor layer 102. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The thickness of the SiC semiconductor substrate 121 may be equal to or greater than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate 121 is preferably equal to or less than 150 μm.

[0025] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably 15 μm or less or 10 μm or less. The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC epitaxial layer 122 is 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 It may be the following:

[0026] In this embodiment, the SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102. Specifically, the SiC epitaxial layer 122 includes a high-concentration region 122a having a relatively high n-type impurity concentration, and a low-concentration region 122b having a lower n-type impurity concentration than the high-concentration region 122a.

[0027] The high-concentration region 122a is formed in a region on the first main surface 103 side. The low-concentration region 122b is formed in a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the high-concentration region 122a. The n-type impurity concentration of the high-concentration region 122a is 1×10 16 cm -3More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 122b may be 1×10 15 cm -3 More than 1×10 16 cm -3 The thickness of the high-concentration region 122a may be equal to or less than the thickness of the low-concentration region 122b. Specifically, the thickness of the high-concentration region 122a is less than the thickness of the low-concentration region 122b.

[0028] The semiconductor device 101 includes a drain electrode 123 covering the second principal surface 104 of the SiC semiconductor layer 102. The drain electrode 123 is formed as an example of a second principal surface electrode and may be referred to as a drain pad. The maximum voltage that can be applied between the source electrode 110 and the drain electrode 123 in the off state may be 1000 V or more and 10000 V or less.

[0029] Drain electrode 123 may include at least one of a Ti (titanium) layer, a Ni (nickel) layer, an Au (gold) layer, or an Ag (silver) layer. Drain electrode 123 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from second main surface 104 of SiC semiconductor layer 102.

[0030] Drain electrode 123 may have a four-layer structure including a Ti layer, an Al (aluminum)Cu (alloy of Al and Cu) layer, a Ni layer, and an Au layer stacked in this order on second main surface 104 of SiC semiconductor layer 102. Drain electrode 123 may have a four-layer structure including a Ti layer, an AlSi (silicon)Cu (alloy of Al, Si, and Cu) layer, a Ni layer, and an Au layer stacked in this order on second main surface 104 of SiC semiconductor layer 102. Drain electrode 123 may have a TiN (titanium nitride) layer instead of a Ti layer, or a stacked structure including a Ti layer and a TiN layer.

[0031] The semiconductor device 101 includes a p-type body region 126 formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The body region 126 defines the active region 106. That is, in this embodiment, the body region 126 is formed over the entire area of ​​the first main surface 103 of the SiC semiconductor layer 102 that forms the active region 106. The p-type impurity concentration of the body region 126 is 1×10 17 cm -3 More than 1×10 20 cm -3 It may be the following:

[0032] The semiconductor device 101 includes a plurality of gate trenches 131 formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. The plurality of gate trenches 131 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 131 are formed in a band shape extending along a second direction Y intersecting the first direction X. The plurality of gate trenches 131 are formed in a stripe shape in a plan view. The length of each gate trench 131 may be 0.5 mm or more. In this embodiment, the length of each gate trench 131 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0033] Each gate trench 131 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 131 is located in the SiC epitaxial layer 122. Specifically, the bottom wall of each gate trench 131 is located in a high-concentration region 122a of the SiC epitaxial layer 122. With respect to the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102, the depth of the gate trench 131 may be 0.5 μm or more and 3 μm or less (for example, approximately 1 μm). The depth of the gate trench 131 is preferably 0.5 μm or more and 1.0 μm or less. The width of the gate trench 131 in the first direction X may be 0.1 μm or more and 2 μm or less (for example, approximately 0.5 μm). The width of the gate trench 131 in the first direction X is preferably 0.1 μm or more and 0.5 μm or less.

[0034] A gate insulating layer 134 and a gate electrode layer 135 are formed in each gate trench 131. The gate insulating layer 134 contains silicon oxide. The gate insulating layer 134 may also contain other insulating films such as silicon nitride. The gate insulating layer 134 is formed in the form of a film along the inner wall surface of the gate trench 131 so as to define a recessed space within the gate trench 131.

[0035] The gate insulating layer 134 includes a first region 134a, a second region 134b, and a third region 134c. The first region 134a is formed along the sidewall of the gate trench 131. The second region 134b is formed along the bottom wall of the gate trench 131. The third region 134c is formed along the first main surface 103 of the SiC semiconductor layer 102. The thickness of the first region 134a is smaller than the thicknesses of the second region 134b and the third region 134c. The thickness of the first region 134a may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 134b may be 0.05 μm or more and 0.5 μm or less. The thickness of the third region 134c may be 0.05 μm or more and 0.5 μm or less. Of course, the gate insulating layer 134 may have a uniform thickness.

[0036] The gate electrode layer 135 is embedded in the gate trench 131 with the gate insulating layer 134 sandwiched therebetween. Specifically, the gate electrode layer 135 is embedded in the gate trench 131 so as to fill the concave space defined by the gate insulating layer 134. The gate electrode layer 135 is controlled by a gate voltage. The gate electrode layer 135 is electrically connected to the gate electrode 108 and the gate fingers 109.

[0037] The gate electrode layer 135 is formed in a wall shape extending along the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view orthogonal to the direction in which the gate trench 131 extends (second direction Y). The gate electrode layer 135 may contain conductive polysilicon. The gate electrode layer 135 may contain n-type polysilicon or p-type polysilicon as an example of conductive polysilicon. The gate electrode layer 135 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy, instead of conductive polysilicon.

[0038] The semiconductor device 101 includes a plurality of source trenches 141 formed in the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. Each source trench 141 is formed in a region between two adjacent gate trenches 131. The plurality of source trenches 141 are each formed in a band shape extending along the second direction Y. The plurality of source trenches 141 are formed in a stripe shape in plan view. The pitch between the centers of adjacent source trenches 141 in the first direction X may be 1.5 μm or more and 3 μm or less.

[0039] Each source trench 141 penetrates the body region 126 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 141 is located in the SiC epitaxial layer 122. Specifically, the bottom wall of each source trench 141 is located in the high concentration region 122a. In this embodiment, the depth of the source trench 141 is equal to or greater than the depth of the gate trench 131. Specifically, the depth of the source trench 141 is greater than the depth of the gate trench 131.

[0040] The depth of source trench 141 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm) in normal direction Z to first main surface 103 of SiC semiconductor layer 102. The width of source trench 141 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). A source insulating layer 142 and a source electrode layer 143 are formed in each source trench 141.

[0041] The source insulating layer 142 may contain silicon oxide. The source insulating layer 142 is formed in the form of a film along the inner wall surface of the source trench 141 so as to define a recessed space within the source trench 141. The source insulating layer 142 includes a first region 142a and a second region 142b. The first region 142a is formed along the side wall of the source trench 141. The second region 142b is formed along the bottom wall of the source trench 141. The thickness of the first region 142a is smaller than the thickness of the second region 142b. The thickness of the first region 142a may be 0.01 μm or more and 0.2 μm or less. The thickness of the second region 142b may be 0.05 μm or more and 0.5 μm or less. Of course, the source insulating layer 142 may have a uniform thickness.

[0042] The source electrode layer 143 is embedded in the source trench 141 with the source insulating layer 142 sandwiched therebetween. Specifically, the source electrode layer 143 is embedded in the source trench 141 so as to fill the recessed space defined by the source insulating layer 142. The source electrode layer 143 is controlled by a source voltage. The thickness of the source electrode layer 143 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0043] The source electrode layer 143 preferably contains polysilicon, which has properties similar to those of SiC. This reduces stress generated in the SiC semiconductor layer 102. The source electrode layer 143 may contain the same conductive material type as the gate electrode layer 135. The source electrode layer 143 may contain conductive polysilicon. The source electrode layer 143 may contain n-type polysilicon or p-type polysilicon, which are examples of conductive polysilicon. The source electrode layer 143 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy, instead of conductive polysilicon.

[0044] As described above, the semiconductor device 101 has a trench gate structure and a trench source structure. The trench gate structure includes a gate trench 131, a gate insulating layer 134, and a gate electrode layer 135. The trench source structure includes a source trench 141, a source insulating layer 142, and a source electrode layer 143.

[0045] The semiconductor device 101 has an n-type semiconductor layer formed in a surface layer of the body region 126 along the sidewall of the gate trench 131. + In this embodiment, the plurality of source regions 153 are formed along one sidewall and the other sidewall of the gate trench 131 in the first direction X. The n-type impurity concentration of the source region 153 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0046] The source regions 153 are each formed in a strip shape extending along the second direction Y. The source regions 153 are formed in a stripe shape in a plan view. Each source region 153 is exposed from the sidewall of the gate trench 131 and the sidewall of the source trench 141.

[0047] The semiconductor device 101 includes a plurality of p-type semiconductor layers formed on the surface layer of the first main surface 103 of the SiC semiconductor layer 102. + The p-type impurity concentration of the contact region 154 is greater than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the contact region 154 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0048] A plurality of contact regions 154 are formed along the sidewalls of each source trench 141. The plurality of contact regions 154 are formed at intervals along the second direction Y. The plurality of contact regions 154 are formed at intervals from the gate trench 131 along the first direction X. Each contact region 154 covers the sidewalls and bottom wall of the source trench 141.

[0049] The semiconductor device 101 includes a plurality of p-type deep well regions 155 formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The deep well regions 155 are also referred to as breakdown voltage adjusting regions (breakdown voltage holding regions) that adjust the breakdown voltage of the SiC semiconductor layer 102 in the active region 106. Each deep well region 155 is formed along the inner wall of each source trench 141 so as to cover the contact region 154.

[0050] The p-type impurity concentration of the deep well region 155 may be approximately equal to the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be greater than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be less than the p-type impurity concentration of the body region 126. The p-type impurity concentration of the deep well region 155 may be equal to or less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 may be less than the p-type impurity concentration of the contact region 154. The p-type impurity concentration of the deep well region 155 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0051] The deep well region 155 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 122a of the SiC epitaxial layer 122). A depletion layer extends from this pn junction toward a region between adjacent gate trenches 131. This depletion layer extends toward a region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 131.

[0052] The semiconductor device 101 includes an interlayer insulating layer 191 formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 191 selectively covers the active region 106 and the outer region 107. The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may contain PSG (PhosphorSilicateGlass) and / or BPSG (BoronPhosphorSilicateGlass), which are examples of silicon oxide.

[0053] The semiconductor device 101 includes the aforementioned source electrode 110 formed on the interlayer insulating layer 191. The source electrode 110 has a layered structure including a first electrode layer 201, a second electrode layer 202, and a third electrode layer 203, which are layered in this order from the first main surface 103 side (the interlayer insulating layer 191 side) of the SiC semiconductor layer 102. The first electrode layer 201 may have a single-layer structure including a titanium layer or a titanium nitride layer. The first electrode layer 201 may have a layered structure including a titanium layer and a titanium nitride layer, which are layered in this order from the first main surface 103 side of the SiC semiconductor layer 102.

[0054] The thickness of the second electrode layer 202 is greater than the thickness of the first electrode layer 201. The second electrode layer 202 includes a conductive material having a resistance value lower than that of the first electrode layer 201. The second electrode layer 202 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy. The second electrode layer 202 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. In this embodiment, the second electrode layer 202 includes an aluminum-silicon-copper alloy. The first main surface 103 (wafer surface) of the SiC semiconductor layer 102 has an uneven structure due to the presence or absence of the interlayer insulating layer 191, and the surface of the second electrode layer 202 has an uneven structure (uneven portion) formed in accordance with the uneven structure.

[0055] The third electrode layer 203 includes at least one of nickel (Ni) and copper (Cu). The third electrode layer 203 may have a single-layer structure including a nickel layer or a copper layer. The third electrode layer 203 may have a laminated structure including a nickel layer and a copper layer. The third electrode layer 203 preferably includes a nickel layer. The third electrode layer 203 is harder than the second electrode layer 202. By providing the relatively hard third electrode layer 203 on the second electrode layer 202, it is possible to prevent the source electrode 110 from peeling off or the structure from being destroyed during wire bonding, for example. In other words, the mechanical strength can be improved.

[0056] For example, the thickness of the third electrode layer 203 may be 1 μm or more and 10 μm or less in the normal direction Z of the first main surface 103 of the SiC semiconductor layer 102. The surface of the third electrode layer 203 is flatter than that of the second electrode layer 202. Specifically, the difference between the highest and lowest positions in the thickness direction of the third electrode layer 203 is smaller than the difference between the highest and lowest positions in the thickness direction of the second electrode layer 202.

[0057] Specifically, the difference between the highest and lowest positions in the thickness direction of the third electrode layer 203 in one active cell (see FIG. 2) is smaller than the difference between the highest and lowest positions in the thickness direction of the second electrode layer 202. The highest position is typically the surface position of each layer at the center A of the interlayer insulating layer 191, and the lowest position is typically the surface position of each layer at the intermediate position B between two adjacent interlayer insulating layers 191. However, since there are various structures formed on the first main surface 103 (wafer surface) of the SiC semiconductor layer 102, the definitions of the highest and lowest positions are not limited to this.

[0058] The semiconductor device 101 includes an oxide layer 204 formed on the third electrode layer 203. The oxide layer 204 is a metal oxide layer containing a metal oxide. Specifically, the oxide layer 204 is formed by oxidizing the outer surface of the source electrode 110 (first principal surface electrode). That is, the oxide layer 204 contains an oxide of the source electrode 110. More specifically, the oxide layer 204 is formed by oxidizing the third electrode layer 203, and contains an oxide of at least one of nickel and copper. That is, the oxide layer 204 contains nickel oxide or copper oxide. The oxide layer 204 preferably has a thickness less than that of the source electrode 110. It is particularly preferable that the oxide layer 204 has a thickness less than that of the third electrode layer 203.

[0059] During wire bonding, oxide layer 204 is removed by connecting the bonding wire, and the bonding wire and third electrode layer 203 are directly connected. Oxidized layer 204 remains in areas other than the connection portion between the bonding wire and third electrode layer 203 even after wire bonding. Therefore, when the bonding wire is connected, third electrode layer 203 has a covered portion covered with oxide layer 204 and a connection portion connected to the bonding wire. The connection portion of third electrode layer 203 is made of a removed portion where at least a portion of oxide layer 204 has been removed, and the bonding wire is directly connected electrically and mechanically.

[0060] Although specific illustrations are omitted, the semiconductor device 101 includes the aforementioned gate electrode 108 and gate fingers 109 formed on the interlayer insulating layer 191. Like the source electrode 110, the gate electrode 108 has a layered structure including a first electrode layer 201, a second electrode layer 202, and a third electrode layer 203 layered in this order from the first main surface 103 side (the interlayer insulating layer 191 side) of the SiC semiconductor layer 102. The aforementioned oxide layer 204 is also formed on the outer surface (third electrode layer 203) of the gate electrode 108.

[0061] Next, a description will be given of a manufacturing process of the semiconductor device 101. Figures 3A to 3F are diagrams showing an example of a manufacturing method of the semiconductor device 101 shown in Figure 2.

[0062] First, referring to FIG. 3A, + The n-type SiC semiconductor substrate 121 is a base + A molded SiC semiconductor wafer 301 is prepared. The SiC semiconductor wafer 301 has a first wafer main surface 302 on one side and a second wafer main surface 303 on the other side. Next, a SiC epitaxial layer 122 is formed on the first wafer main surface 302 of the SiC semiconductor wafer 301. The SiC epitaxial layer 122 is formed by growing SiC from the first wafer main surface 302 of the SiC semiconductor wafer 301 by an epitaxial growth method.

[0063] In this step, the amount of n-type impurity added is adjusted to form a SiC epitaxial layer 122 having a high-concentration region 122a and a low-concentration region 122b. This results in a SiC semiconductor layer 102 including a SiC semiconductor wafer 301 and the SiC epitaxial layer 122. The SiC semiconductor layer 102 includes a first main surface 103 and a second main surface 104. The following description will be given using the SiC semiconductor layer 102, the first main surface 103, and the second main surface 104.

[0064] Next, a p-type body region 126 is formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. In this step, the body region 126 is formed over the entire surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 126 is formed by introducing a p-type impurity into the first main surface 103 of the SiC semiconductor layer 102.

[0065] Next, n +An n-type source region 153 is formed. The source region 153 is formed by introducing n-type impurities into a surface portion of the body region 126. In this step, the source region 153 is formed over the entire surface portion of the first main surface 103 of the SiC semiconductor layer 102. Next, a hard mask 304 is formed on the first main surface 103 of the SiC semiconductor layer 102. The hard mask 304 may contain silicon oxide. The hard mask 304 may be formed by a CVD (Chemical Vapor Deposition) method or a thermal oxidation method. In this step, the hard mask 304 is formed by a thermal oxidation method.

[0066] 3B, unnecessary portions of SiC semiconductor layer 102 are removed by etching (e.g., dry etching) using a resist mask. In this process, unnecessary portions of SiC epitaxial layer 122 are removed. As a result, gate trench 131 and source trench 141 are formed. Next, mask 307 is formed. Mask 307 fills gate trench 131, source trench 141, and outer region 107 and covers first main surface 103 of SiC semiconductor layer 102. Mask 307 has a layered structure including polysilicon layer 308 and insulating layer 309. Insulating layer 309 includes silicon oxide.

[0067] The polysilicon layer 308 may be formed by a CVD method. The insulating layer 309 may be formed by a CVD method or a thermal oxidation method. In this step, the insulating layer 309 is formed by a thermal oxidation method on the polysilicon layer 308.

[0068] Next, unnecessary portions of mask 307 are removed by etching (for example, dry etching) through a resist mask. As a result, source trench 141 and outer region 107 are exposed from mask 307. Next, unnecessary portions of SiC semiconductor layer 102 are removed by etching (for example, dry etching) through mask 307. As a result, source trench 141 and outer region 107 are further deepened.

[0069] Next, deep well region 155 is formed in a surface layer portion of first main surface 103 of SiC semiconductor layer 102. Deep well region 155 is formed by introducing p-type impurities into first main surface 103 of SiC semiconductor layer 102. The p-type impurities are introduced into first main surface 103 of SiC semiconductor layer 102 via mask 307.

[0070] 3D , mask 307 is removed. Next, contact region 154 is formed in a surface portion of first main surface 103 of SiC semiconductor layer 102. Contact region 154 is formed by introducing p-type impurities into first main surface 103 of SiC semiconductor layer 102. The p-type impurities are introduced into first main surface 103 of SiC semiconductor layer 102 via a resist mask.

[0071] Next, a base insulating layer serving as a base for gate insulating layer 134 and source insulating layer 142 is formed on first main surface 103 of SiC semiconductor layer 102. The base insulating layer may contain silicon oxide. The base insulating layer may be formed by a CVD method or a thermal oxidation treatment method. Next, a base conductor layer serving as a base for gate electrode layer 135 and source electrode layer 143 is formed on first main surface 103 of SiC semiconductor layer 102. The base conductor layer fills gate trench 131, source trench 141, and outer region 107 and covers first main surface 103 of SiC semiconductor layer 102.

[0072] The base conductor layer may include polysilicon. The base conductor layer may be formed by a CVD method. The CVD method may be a low pressure CVD (LP-CVD) method. Next, unnecessary portions of the base conductor layer are removed. The unnecessary portions of the base conductor layer are removed until the base insulating layer is exposed. The unnecessary portions of the base conductor layer may be removed by an etch-back method using the base insulating layer as an etching stop layer.

[0073] The unnecessary portions of the base conductor layer may be removed by etching (for example, wet etching) using a mask having a predetermined pattern, thereby forming the gate electrode layer 135 and the source electrode layer 143.

[0074] Next, referring to FIG. 3E, an interlayer insulating layer 191 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 191 collectively covers the active region 106 and the outer region 107. The interlayer insulating layer 191 may contain silicon oxide or silicon nitride. The interlayer insulating layer 191 may be formed by a CVD method. Next, unnecessary portions of the interlayer insulating layer 191 are removed. The unnecessary portions of the interlayer insulating layer 191 may be removed by an etching method (e.g., a dry etching method) using a resist mask.

[0075] Next, unnecessary portions of the base insulating layer exposed from interlayer insulating layer 191 are removed. The unnecessary portions of the base insulating layer may be removed by an etching method (e.g., dry etching). This separates the base insulating layer into gate insulating layer 134 and source insulating layer 142.

[0076] Next, a base electrode layer that serves as the base of the gate electrode 108 and the source electrode 110 is formed on the interlayer insulating layer 191. In this step, a first electrode layer 201 and a second electrode layer 202 are formed. In this step, the first electrode layer 201 is first formed on the interlayer insulating layer 191. The first electrode layer 201 includes a step of forming a titanium layer and a titanium nitride layer in this order on the interlayer insulating layer 191. The titanium layer and the titanium nitride layer may be formed by a sputtering method. The first electrode layer 201 may have a single-layer structure made of a titanium layer or a titanium nitride layer.

[0077] Next, the second electrode layer 202 is formed on the first electrode layer 201. The second electrode layer 202 may include an aluminum-silicon-copper alloy. The second electrode layer 202 may be formed by a sputtering method.

[0078] Next, drain electrode 123 is formed on second main surface 104 of SiC semiconductor layer 102. This step may include a step of forming at least one of a Ti layer, a Ni layer, an Au layer, or an Ag layer as drain electrode 123. The Ti layer, Ni layer, Au layer, or Ag layer may be formed by sputtering. The step of forming drain electrode 123 may include a step of forming a Ti layer, a Ni layer, an Au layer, and an Ag layer in this order on second main surface 104 of SiC semiconductor layer 102. The Ti layer, Ni layer, Au layer, and Ag layer may be formed by sputtering.

[0079] 3F, the third electrode layer 203 is formed on the second electrode layer 202. The third electrode layer 203 may include at least one of nickel and copper. The third electrode layer 203 may have a single-layer structure including a nickel layer or a copper layer. The third electrode layer 203 may have a laminated structure including a nickel layer and a copper layer.

[0080] In this step, first, back surface tape 205 is attached to the surface of drain electrode 123 on second main surface 104 of SiC semiconductor layer 102. Next, third electrode layer 203 is formed on second electrode layer 202 by plating. For example, the plating may be electroless plating. After third electrode layer 203 is formed, back surface tape 205 is peeled off. After third electrode layer 203 is formed, oxide layer 204 is formed on the surface of third electrode layer 203 by oxidation. The step of forming oxide layer 204 may be included in the step of forming third electrode layer 203.

[0081] Thereafter, the SiC semiconductor layer 102 (SiC semiconductor wafer 301) is selectively cut along dicing lines (dicing streets). As a result, a plurality of semiconductor devices 101 are cut out from one SiC semiconductor wafer 301. After dicing, the semiconductor device 101 is subjected to a step of connecting a conductor (conductive connecting member) such as a bonding wire to the third electrode layer 203. The semiconductor device 101 is formed through steps including those described above.

[0082] Here, the third electrode layer 203 is formed only on the first main surface 103 side by attaching the back surface tape 205, but the electroless plating method may be performed without attaching the back surface tape 205, and an electrode layer (third electrode layer 203) may be formed on both the first main surface 103 side and the second main surface 104 side. In other words, an electrode layer corresponding to the third electrode layer 203 may cover the drain electrode 123.

[0083] 4 is a cross-sectional view showing the configuration of semiconductor device 101 in this case. As shown in the figure, drain electrode 123 includes a fourth electrode layer 123a and a fifth electrode layer 123b formed in this order on second main surface 104 of SiC semiconductor layer 102. Fourth electrode layer 123a corresponds to drain electrode 123 shown in FIG.

[0084] The fourth electrode layer 123a is made of, for example, the same material as the second electrode layer 202. For example, the fourth electrode layer 123a and the second electrode layer 202 are made of aluminum. The fifth electrode layer 123b is made of the same material as the third electrode layer 203. The fifth electrode layer 123b is formed by electroless plating in the same process as the third electrode layer 203.

[0085] The fifth electrode layer 123b may contain at least one of nickel and copper. The fifth electrode layer 123b may have a single-layer structure including a nickel layer or a copper layer. The fifth electrode layer 123b may have a laminated structure including a nickel layer and a copper layer. The surface of the fifth electrode layer 123b may be covered with an oxide layer 204, similar to the surface of the third electrode layer 203. In other words, the semiconductor device 101 may include an oxide layer (oxide layer 204 on the second main surface 104 side) that covers the surface of the drain electrode 123 (surface of the fifth electrode layer 123b) on the second main surface 104 side.

[0086] Next, a description will be given of the configuration of a semiconductor package 401 including the semiconductor device 101. Fig. 5 is a perspective view showing the semiconductor package 401 incorporating the semiconductor device 101, with the sealing body 407 seen through.

[0087] The semiconductor package 401 includes a semiconductor chip 402, a pad portion 403, a heat spreader 404, a plurality of (three in this embodiment) terminals 405, a plurality of (three in this embodiment) conductive wires 406, and a sealing body 407. The semiconductor device 101 described above is applied as the semiconductor chip 402.

[0088] The pad portion 403 includes a metal plate. The pad portion 403 may include aluminum, copper, or the like. The pad portion 403 is formed in a quadrangular shape in a plan view. The pad portion 403 has a planar area equal to or larger than the planar area of ​​the semiconductor chip 402. The drain electrode 123 of the semiconductor chip 402 is electrically connected to the pad portion 403 by die bonding.

[0089] The heat spreader 404 is connected to one side of the pad portion 403. In this embodiment, the pad portion 403 and the heat spreader 404 are formed from a single metal plate. A through hole 404a is formed in the heat spreader 404. The through hole 404a is formed in a circular shape. The multiple terminals 405 are arranged along the side of the pad portion 403 opposite to the heat spreader 404. Each of the multiple terminals 405 includes a metal plate extending in a strip shape. The terminals 405 may include aluminum, copper, or the like. The multiple terminals 405 include a first terminal 405A, a second terminal 405B, and a third terminal 405C.

[0090] First terminal 405A, second terminal 405B, and third terminal 405C are arranged at intervals along the side of pad portion 403 opposite heat spreader 404. First terminal 405A, second terminal 405B, and third terminal 405C extend in a strip shape in a direction perpendicular to the direction of their arrangement. Second terminal 405B and third terminal 405C sandwich first terminal 405A from both sides.

[0091] The plurality of conductive wires 406 may be bonding wires or the like. In this embodiment, the plurality of conductive wires 406 include conductive wires 406A, 406B, and 406C. The conductive wire 406A is electrically connected to the gate electrode 108 of the semiconductor chip 402 and the first terminal 405A. The conductive wire 406B is electrically connected to the source electrode 110 of the semiconductor chip 402 and the second terminal 405B. The conductive wire 406C is electrically connected to the pad portion 403 and the third terminal 405C. When the bonding wires are made of aluminum, it is preferable that at least the surface of the third electrode layer (third electrode layer 203) is made of nickel.

[0092] The sealing body 407 seals the semiconductor chip 402, the pad portion 403, and the plurality of conductive wires 406 so as to expose the heat spreader 404 and a portion of the plurality of terminals 405. The sealing body 407 contains a sealing resin. The sealing body 407 is formed in a rectangular parallelepiped shape. The shape of the semiconductor package 401 is not limited to the shape shown in FIG.

[0093] The semiconductor package 401 may be a small outline package (SOP), a quad flat non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), or a small outline J-leaded package (SOJ), or various other similar semiconductor packages.

[0094] In the above description, an example has been given in which the functional device (semiconductor element) included in the semiconductor device 101 is a vertical transistor, but the semiconductor device 101 may also include a vertical diode. The semiconductor device 101 may include either a transistor or a diode, or may include both a transistor and a diode.

[0095] 6 is a cross-sectional view of a semiconductor device 101 including a diode. As shown in FIG. 6, the semiconductor device 101 includes a SiC semiconductor layer 501. The SiC semiconductor layer 501 has an n + The SiC semiconductor substrate 502 includes an n-type SiC semiconductor substrate 502 and an n-type SiC epitaxial layer 503. The impurity concentration of the SiC semiconductor substrate 502 is, for example, about 1×10 18 cm -3 ~Approx. 1×10 21 cm -3 The impurity concentration of the SiC epitaxial layer 503 is, for example, about 5×10 14 cm -3 ~Approx. 5×10 16 cm -3 The SiC epitaxial layer 503 may have a buffer layer formed on the SiC semiconductor substrate 502 and a drift layer formed on the buffer layer.

[0096] The semiconductor device 101 includes a cathode electrode 504 that covers the back surface ((000-1) C plane) of the SiC semiconductor substrate 502. The cathode electrode 504 is formed as an example of a second principal surface electrode. The cathode electrode 504 covers the entire back surface of the SiC semiconductor substrate 502. The cathode electrode 504 is connected to a cathode terminal.

[0097] The semiconductor device 101 includes a field insulating film 505 formed on the surface ((0001) Si face) of the SiC epitaxial layer 503. The field insulating film 505 is made of SiO2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN).

[0098] The semiconductor device 101 includes an anode electrode 506 formed on a field insulating film 505. The anode electrode 506 is formed as an example of a first principal surface electrode. The anode electrode 506 is connected to an anode terminal. The anode electrode 506 includes a first electrode layer 507 and a second electrode layer 508. The first electrode layer 507 is formed on the SiC epitaxial layer 503 and the field insulating film 505. The second electrode layer 508 is formed on the first electrode layer 507.

[0099] For example, the first electrode layer 507 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy. The first electrode layer 507 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy.

[0100] The second electrode layer 508 may contain at least one of nickel and copper. The second electrode layer 508 may have a single-layer structure including a nickel layer or a copper layer. The second electrode layer 508 may have a laminated structure including a nickel layer and a copper layer. The second electrode layer 508 preferably includes a nickel layer. The second electrode layer 508 is harder than the first electrode layer 507. By providing the relatively hard second electrode layer 508 on the first electrode layer 507, it is possible to prevent the anode electrode 506 from peeling off or the structure from being destroyed during wire bonding, for example. In other words, the mechanical strength can be improved.

[0101] The semiconductor device 101 includes an oxide layer 509 formed on the second electrode layer 508. The oxide layer 509 is a metal oxide layer containing a metal oxide. Specifically, the oxide layer 509 is formed by oxidizing the outer surface of the anode electrode 506 (first principal surface electrode). That is, the oxide layer 509 contains an oxide of the anode electrode 506. More specifically, the oxide layer 509 is formed by oxidizing the second electrode layer 508, and contains an oxide of at least one of a nickel layer and a copper layer. That is, the oxide layer 509 contains nickel oxide or copper oxide. The oxide layer 509 preferably has a thickness less than that of the anode electrode 506. It is particularly preferable that the oxide layer 509 has a thickness less than that of the second electrode layer 508.

[0102] During wire bonding, oxide layer 509 is removed by connecting the bonding wire, and the bonding wire and second electrode layer 508 are directly connected. Oxide layer 204 remains in areas other than the connection portion between the bonding wire and second electrode layer 508 even after wire bonding. Therefore, when the bonding wire is connected, second electrode layer 508 has a covered portion covered with oxide layer 509 and a connection portion connected to the bonding wire. The connection portion of second electrode layer 508 is made of a removed portion where at least a portion of oxide layer 509 has been removed, and the bonding wire is directly connected electrically and mechanically.

[0103] The semiconductor device 101 includes a p-type JTE (Junction Termination Extension) structure 510 (impurity region) formed near the surface (surface layer portion) of the SiC epitaxial layer 503. The JTE (Junction Termination Extension) structure 510 is formed so as to contact a first electrode layer 507 of an anode electrode 506.

[0104] As described above, the semiconductor device according to this embodiment has the following features. A semiconductor device 101 according to one aspect of the present invention is a semiconductor device including a vertical power semiconductor element, as shown in Fig. 2. The semiconductor device 101 includes a SiC semiconductor layer 102, a first electrode layer (second electrode layer 202), a second electrode layer (third electrode layer 203), a third electrode layer (drain electrode 123), and an oxide layer 204.

[0105] The SiC semiconductor layer 102 has a first main surface 103 and a second main surface 104 opposite to the first main surface 103, and contains SiC as a main component. The first electrode layer (second electrode layer 202) is formed on the first main surface 103 side of the SiC semiconductor layer 102. The second electrode layer (third electrode layer 203) is formed on the first electrode layer (second electrode layer 202) and is electrically connected to a first terminal of the vertical power semiconductor element. The second electrode layer (third electrode layer 203) is harder than the first electrode layer (second electrode layer 202).

[0106] The third electrode layer (drain electrode 123) is formed on the second main surface 104 side of the SiC semiconductor layer 102 and is electrically connected to the second terminal of the vertical power semiconductor element. The oxide layer 204 is formed on the surface of the second electrode layer (third electrode layer 203). With this structure, the second electrode layer (third electrode layer 203) can suppress damage to the structure during wire bonding, for example. This can improve mechanical strength.

[0107] For example, the second electrode layer (third electrode layer 203) is made of nickel (Ni) or copper (Cu), and the oxide layer 204 is made of an oxide of nickel or copper. For example, the vertical power semiconductor element may be a vertical transistor, with the first terminal being a source terminal and the second terminal being a drain terminal. The vertical power semiconductor element may be a vertical transistor, with the first terminal being a gate terminal and the second terminal being a drain terminal. As shown in FIG. 6, the vertical power semiconductor element may be a vertical diode, with one of the first terminal and the second terminal being an anode terminal and the other being a cathode terminal.

[0108] For example, the second electrode layer (third electrode layer 203) is formed of a plating layer. For example, as shown in FIG. 4, the semiconductor device 101 further includes a fourth electrode layer (fifth electrode layer 123b). The fourth electrode layer (fifth electrode layer 123b) is formed on the surface of the third electrode layer (fourth electrode layer 123a) opposite to the SiC semiconductor layer 102 side. The fourth electrode layer (fifth electrode layer 123b) is harder than the third electrode layer (fourth electrode layer 123a). For example, as shown in FIG. 5, a semiconductor package according to one embodiment of the present invention includes the semiconductor device 101 (semiconductor chip 402) and a bonding wire (conductor 406) connected to the second electrode layer (third electrode layer 203).

[0109] A semiconductor device manufacturing method according to one aspect of the present invention is a method for manufacturing a semiconductor device 101 including a vertical power semiconductor element. This semiconductor device manufacturing method includes a first step, a second step, and a third step. In the first step, a first electrode layer (second electrode layer 202) is formed on the first main surface 103 side of the SiC semiconductor layer 102. In the second step, a second electrode layer (third electrode layer 203) electrically connected to a first terminal of the vertical power semiconductor element and harder than the first electrode layer (second electrode layer 202) is formed on the first electrode layer (second electrode layer 202). In the third step, a bonding wire (conductor 406) is connected to the second electrode layer (third electrode layer 203). According to this manufacturing method, the second electrode layer (third electrode layer 203) can suppress damage to the structure during wire bonding. This improves mechanical strength.

[0110] For example, in the step (second step) of forming the second electrode layer (third electrode layer 203), the second electrode layer (third electrode layer 203) is formed by plating. In the manufacturing method, the step (third step) of connecting the bonding wire (conductor 406) may be included in the manufacturing method of the semiconductor package.

[0111] Although the semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art and modifications constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0112] Furthermore, the above-described embodiments may be modified, substituted, added, or omitted in various ways within the scope of the claims or their equivalents. The present invention is industrially applicable to semiconductor devices, semiconductor packages, and the like.

[0113] Below, examples of features extracted from this specification and drawings are shown. Below, we provide a semiconductor device, a semiconductor package, and a method for manufacturing the same that can improve mechanical strength. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments.

[0114] [A1] A semiconductor device (101) including a vertical power semiconductor element, the semiconductor layer (102, 501) having a first main surface (103) and a second main surface (104) opposite to the first main surface (103), the semiconductor layer (102, 501) containing SiC as a main component, a first electrode layer (202, 507) formed on the first main surface (103) side of the semiconductor layer (102, 501), and a first terminal of the vertical power semiconductor element formed on the first electrode layer (202, 507). a second electrode layer (203, 508) electrically connected to a second terminal of the vertical power semiconductor element and harder than the first electrode layer (202, 507); a third electrode layer (123, 123a, 123b, 504) formed on the second main surface (104) side of the SiC semiconductor layer (102, 501) and electrically connected to a second terminal of the vertical power semiconductor element; and an oxide layer (204, 509) formed on a surface of the second electrode layer (203, 508).

[0115] [A2] The semiconductor device (101) according to A1, wherein the second electrode layer (203, 508) is made of nickel or Cu, and the oxide layer (204, 509) is made of an oxide of nickel or Cu.

[0116] [A3] The semiconductor device (101) according to A1 or A2, wherein the vertical power semiconductor element is a vertical transistor, the first terminal is a source terminal, and the second terminal is a drain terminal.

[0117] [A4] The semiconductor device (101) according to any one of A1 to A3, wherein the second electrode layer (203, 508) is formed by plating.

[0118] [A5] The semiconductor device (101) according to any one of A1 to A4, further comprising a fourth electrode layer (123b) formed on a surface of the third electrode layer (123, 123a, 123b, 504) opposite to the SiC semiconductor layer (102, 501) side, the fourth electrode layer (123b) being harder than the third electrode layer (123, 123a, 123b, 504).

[0119] [A6] A semiconductor package (401) comprising the semiconductor device (101) according to any one of A1 to A5 and a bonding wire (406) connected to the second electrode layer (203, 508).

[0120] [A7] A method for manufacturing a semiconductor device (101) including a vertical power semiconductor element, the method comprising the steps of: forming a first electrode layer (202, 507) on a first main surface (103) side of a semiconductor layer (102, 501) containing SiC as a main component; forming a second electrode layer (203, 508) on the first electrode layer (202, 507) that is electrically connected to a first terminal of the vertical power semiconductor element and is harder than the first electrode layer (202, 507); and connecting a bonding wire (406) to the second electrode layer (203, 508).

[0121] [A8] The method for manufacturing a semiconductor device (101) according to A7, wherein in the step of forming the second electrode layer (203, 508), the second electrode layer (203, 508) is formed by plating.

[0122] [B1] A semiconductor device (101) comprising: a semiconductor layer (102, 501) having a first main surface (103) on one side and a second main surface (104) on the other side; a first electrode (202, 507) covering the first main surface (103); a second electrode (108, 110, 506) including a second electrode (203, 508) having a higher hardness than the first electrode (202, 507) and covering the first electrode (202, 507); and an oxide layer (204, 509) covering the second electrode (108, 110, 506).

[0123] [B2] The semiconductor device (101) according to B1, wherein the oxide layer (204, 509) is made of a metal oxide layer containing a metal oxide.

[0124] [B3] The semiconductor device (101) according to B1 or B2, wherein the oxide layer (204, 509) includes an oxide of the second electrode (108, 110, 506).

[0125] [B4] The semiconductor device (101) according to any one of B1 to B3, wherein the oxide layer (204, 509) is thinner than the second electrode (108, 110, 506).

[0126] [B5] The semiconductor device (101) according to any one of B1 to B4, wherein the oxide layer (204, 509) is thinner than the second electrode (203, 508).

[0127] [B6] The semiconductor device (101) according to any one of B1 to B5, wherein the oxide layer (204, 509) contains an oxide of the second electrode (203, 508).

[0128] [B7] The semiconductor device (101) according to B6, wherein the second electrode (203, 508) includes at least one of nickel and copper, and the oxide layer (204, 509) includes an oxide of at least one of nickel and copper.

[0129] [B8] The semiconductor device (101) according to any one of B1 to B7, wherein the second electrode (203, 508) is made of a plating layer.

[0130] [B9] The semiconductor device (101) according to any one of B1 to B8, wherein the semiconductor layer (102, 501) contains a wide band gap semiconductor as a main component.

[0131] [B10] The semiconductor device (101) according to any one of B1 to B9, wherein the semiconductor layer (102, 501) contains SiC as a main component.

[0132] [B11] The semiconductor device (101) according to any one of B1 to B10, further comprising a functional device formed in the semiconductor layer (102, 501), and the second electrode (108, 110, 506) is electrically connected to the functional device.

[0133] [B12] The semiconductor device (101) according to B11, wherein the functional device includes a transistor having a source, and the second electrode (108, 110, 506) includes a source electrode (110) electrically connected to the source of the transistor.

[0134] [B13] The semiconductor device (101) according to B11, wherein the functional device includes a transistor having a gate, and the second electrode (108, 110, 506) includes a gate electrode (108) electrically connected to the gate of the transistor.

[0135] [B14] The semiconductor device (101) according to B11, wherein the functional device includes a diode having an anode, and the second electrode (108, 110, 506) includes an anode electrode (506) electrically connected to the anode of the diode.

[0136] [B15] The semiconductor device (101) according to any one of B1 to B14, further comprising a second principal surface electrode (123, 123a, 123b, 504) covering the second principal surface (104).

[0137] [B16] The semiconductor device (101) according to B15, wherein the second principal surface electrode (123, 123a, 123b, 504) includes a third electrode (123a) covering the second principal surface (104), and a fourth electrode (123b) having a higher hardness than the third electrode (123a) and covering the third electrode (123a).

[0138] [B17] A semiconductor package (401) including the semiconductor device (101) according to any one of B1 to B16, and a bonding wire (406) electrically connected to the second electrode (108, 110, 506).

[0139] [B18] A semiconductor package (401) according to B17, wherein the bonding wire (406) penetrates the oxide layer (204, 509) and is electrically and mechanically connected to the second electrode (203, 508), and the second electrode (108, 110, 506) has a covering portion covered by the oxide layer (204, 509) and a connection portion directly connected to the bonding wire (406).

[0140] [B19] A method for manufacturing a semiconductor device (101), comprising: a step of preparing a semiconductor layer (102, 501) having a main surface (103); a step of forming a first electrode (202, 507) on the main surface (103), and a step of forming a second electrode (203, 508) having a higher hardness than the first electrode (202, 507) on the first electrode (202, 507), thereby forming a second electrode (108, 110, 506) including the first electrode (202, 507) and the second electrode (203, 508) on the main surface (103); and a step of forming an oxide layer (204, 509) covering an outer surface of the second electrode (108, 110, 506).

[0141] [B20] A method for manufacturing a semiconductor package (401), comprising the method for manufacturing a semiconductor device (101) according to B19, and a step of connecting a bonding wire (406) to the second electrode (108, 110, 506).

[0142] [C1] A semiconductor device comprising: a semiconductor layer having a first main surface on one side and a second main surface on the other side; an interlayer insulating layer selectively covering the semiconductor layer on the first main surface; a first electrode covering the first main surface and the interlayer insulating layer; a first main surface electrode including a second electrode having a higher hardness than the first electrode and covering the first electrode; an oxide layer covering the first main surface electrode; the first main surface having an uneven structure due to the presence or absence of the interlayer insulating layer, the surface of the first electrode including an uneven portion formed following the uneven structure; and the surface of the second electrode having a higher flatness than the surface of the first electrode.

[0143] [C2] The semiconductor device according to C1, wherein the oxide layer is a metal oxide layer containing a metal oxide.

[0144] [C3] The semiconductor device according to C1 or C2, wherein the oxide layer includes an oxide of the first principal surface electrode.

[0145] [C4] The semiconductor device according to any one of C1 to C3, wherein the oxide layer is thinner than the first principal surface electrode.

[0146] [C5] The semiconductor device according to any one of C1 to C4, wherein the oxide layer is thinner than the second electrode.

[0147] [C6] The semiconductor device according to any one of C1 to C5, wherein the oxide layer includes an oxide of the second electrode.

[0148] [C7] The semiconductor device according to C6, wherein the second electrode includes at least one of nickel and copper, and the oxide layer includes an oxide of at least one of nickel and copper.

[0149] [C8] The semiconductor device according to any one of C1 to C7, wherein the second electrode is made of a plating layer.

[0150] [C9] The semiconductor device according to any one of C1 to C8, wherein the semiconductor layer contains a wide band gap semiconductor as a main component.

[0151] [C10] The semiconductor device according to any one of C1 to C9, wherein the semiconductor layer contains SiC as a main component.

[0152] [C11] The semiconductor device according to any one of C1 to C10, further comprising a functional device formed on the semiconductor layer, the first principal surface electrode being electrically connected to the functional device.

[0153] [C12] The semiconductor device according to C11, wherein the functional device includes a transistor having a source, and the first principal surface electrode includes a source electrode electrically connected to the source of the transistor.

[0154] [C13] The semiconductor device according to C11, wherein the functional device includes a transistor having a gate, and the first principal surface electrode includes a gate electrode electrically connected to the gate of the transistor.

[0155] [C14] The semiconductor device according to C11, wherein the functional device includes a diode having an anode, and the first principal surface electrode includes an anode electrode electrically connected to the anode of the diode.

[0156] [C15] The semiconductor device according to any one of C1 to C14, further comprising a second principal surface electrode covering the second principal surface.

[0157] [C16] The semiconductor device according to C15, wherein the second principal surface electrode includes a third electrode covering the second principal surface, and a fourth electrode having a higher hardness than the third electrode and covering the third electrode.

[0158] [C17] A semiconductor package comprising the semiconductor device according to any one of C1 to C16 and a bonding wire electrically connected to the first principal surface electrode.

[0159] [C18] A semiconductor package as described in C17, wherein the bonding wire penetrates the oxide layer and is electrically and mechanically connected to the second electrode, and the first main surface electrode has a covering portion covered by the oxide layer and a connection portion directly connected to the bonding wire. [Explanation of symbols]

[0160] 101 Semiconductor device 102 SiC semiconductor layer 103 First main surface 104 Second main surface 108 gate electrode (first principal surface electrode) 110 Source electrode (first principal surface electrode) 123 Drain electrode (second principal surface electrode) 123a 4th electrode layer 123b 5th electrode layer 201 1st electrode layer 202 Second electrode layer 203 Third electrode layer 204 Oxide layer 401 Semiconductor Package 402 Semiconductor chips (semiconductor devices) 406 Conductor (bonding wire) 501 SiC semiconductor layer 504 Cathode electrode (second principal surface electrode) 506 Anode electrode (first principal surface electrode) 507 1st electrode layer 508 Second electrode layer 509 Oxide layer

Claims

1. a semiconductor layer having a first major surface on one side and a second major surface on the other side; an interlayer insulating layer selectively covering the semiconductor layer on the first main surface; a first electrode covering the first main surface and the interlayer insulating layer, and a second electrode having a hardness higher than that of the first electrode and covering the first electrode; an oxide layer covering the first principal surface electrode; the first main surface has an uneven structure due to the presence or absence of the interlayer insulating layer, and a surface of the first electrode includes an uneven portion formed in accordance with the uneven structure; a difference between the highest and lowest positions of the second electrode in the thickness direction is smaller than a difference between the highest and lowest positions of the first electrode in the thickness direction.

2. 2. The semiconductor device according to claim 1, wherein said oxide layer is a metal oxide layer containing a metal oxide.

3. 3. The semiconductor device according to claim 1, wherein said oxide layer includes an oxide of said first principal surface electrode.

4. 4. The semiconductor device according to claim 1, wherein said oxide layer is thinner than said first principal surface electrode.

5. 5. The semiconductor device according to claim 1, wherein said oxide layer is thinner than said second electrode.

6. 6. The semiconductor device according to claim 1, wherein the oxide layer includes an oxide of the second electrode.

7. the second electrode comprises at least one of nickel and copper; 7. The semiconductor device according to claim 6, wherein said oxide layer includes an oxide of at least one of nickel and copper.

8. 8. The semiconductor device according to claim 1, wherein the second electrode is made of a plating layer.

9. 9. The semiconductor device according to claim 1, wherein the semiconductor layer contains a wide band gap semiconductor as a main component.

10. 10. The semiconductor device according to claim 1, wherein the semiconductor layer contains SiC as a main component.

11. Further including a functional device formed in the semiconductor layer; 11. The semiconductor device according to claim 1, wherein the first principal surface electrode is electrically connected to the functional device.

12. the functional device includes a transistor having a source; The semiconductor device according to claim 11 , wherein the first principal surface electrode includes a source electrode electrically connected to the source of the transistor.

13. the functional device includes a transistor having a gate; The semiconductor device according to claim 11 , wherein the first principal surface electrode includes a gate electrode electrically connected to the gate of the transistor.

14. the functional device includes a diode having an anode; The semiconductor device according to claim 11 , wherein the first principal surface electrode includes an anode electrode electrically connected to the anode of the diode.

15. 15. The semiconductor device according to claim 1, further comprising a second principal surface electrode covering said second principal surface.

16. 16. The semiconductor device according to claim 15, wherein the second principal surface electrode includes a third electrode covering the second principal surface, and a fourth electrode having a hardness higher than that of the third electrode and covering the third electrode.

17. A semiconductor device according to any one of claims 1 to 16, a bonding wire electrically connected to the first principal surface electrode.

18. the bonding wire penetrates the oxide layer and is electrically and mechanically connected to the second electrode; 18. The semiconductor package according to claim 17, wherein the first principal surface electrode has a covering portion covered with the oxide layer and a connecting portion directly connected to the bonding wire.

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