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Abstract

To provide a semiconductor device with a transistor using oxide semiconductors that offer higher shock resistance. To provide a reliable semiconductor device that can accommodate increasingly diverse applications, enhancing convenience.SOLUTION: In a semiconductor device, a gate electrode, a first insulating layer, an oxide semiconductor layer, a second insulating layer and a conductive layer are formed on a substrate, the gate electrode and the conductive layer each extend beyond both ends of the oxide semiconductor layer in the channel width direction of the transistor, and in a cross-section of the transistor along the channel width direction, the oxide semiconductor layer is surrounded by the gate electrode, the first insulating layer, the second insulating layer, and the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Thin film transistors are used in integrated circuits (ICs) and image display devices ( It is widely applied in electronic devices such as LCDs.

[0004] Metal oxides have been attracting attention as materials that exhibit semiconducting properties that can be applied to thin-film transistors. A thin film transistor having a channel formation region made of a metal oxide exhibiting such semiconductor properties is It is known (see Patent Documents 1 and 2).

[0005] In addition, electronic devices using thin film transistors are used in a variety of places and for a variety of purposes. As a result, the required characteristics and shapes, such as light weight, thinness, and impact resistance, are becoming more diverse. Therefore, development of electronic devices with functionality suited to the purpose is underway.

[0006] For example, as a semiconductor device to be installed in a gaming machine, A display with a curved surface has been reported (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Publication No. 7-114347 Summary of the Invention [Problem to be solved by the invention]

[0008] When semiconductor devices are used in various shapes as described above, it is necessary to protect the semiconductor device from external shocks. It is necessary to provide high resistance to

[0009] In view of the above, one embodiment of the present invention is to provide a semiconductor device including a transistor including an oxide semiconductor. One of the purposes is to provide higher impact resistance.

[0010] Furthermore, one embodiment of the present invention can be adapted to a wider variety of uses, and is highly reliable with improved convenience. It is an object of the present invention to provide a semiconductor device having a high resistance. [Means for solving the problem]

[0011] One embodiment of the configuration of the invention disclosed in this specification is a gate electrode layer, a gate insulating layer, and a gate insulating layer formed on a substrate. a bottom-gate transistor including an oxide semiconductor layer; and an insulating layer on the transistor. and a conductive layer over the insulating layer, the insulating layer covering the oxide semiconductor layer and being in contact with the gate insulating layer. a gate insulating film formed on the gate electrode layer in a channel width direction of the oxide semiconductor layer; The conductive layer is formed between a channel formation region of the oxide semiconductor layer and a gate insulating layer. The semiconductor device is provided so as to cover the insulating layer and an end portion of the insulating layer and to be in contact with the gate electrode layer. do.

[0012] One embodiment of the configuration of the invention disclosed in this specification is a bottom gate structure for a driving circuit on the same substrate. A driving circuit portion including a transistor and a pixel portion including a pixel transistor, The transistor includes a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer. An insulating layer is provided on the semiconductor layer, and a conductive layer is provided on the insulating layer. The insulating layer covers the oxide semiconductor layer. and is provided in contact with the gate insulating layer, and The gate insulating layer and the insulating layer are aligned at their edges on the gate electrode layer, and the conductive layer is formed on the oxide semiconductor layer. The insulating layer covers the channel forming region, the gate insulating layer, and the end of the insulating layer, and is provided in contact with the gate electrode layer. It is a semiconductor device that can be used.

[0013] In the above structure, the source electrode layer and the drain electrode layer are formed between the oxide semiconductor layer and the insulating layer. The insulating layer may be provided between the gate insulating layer and the oxide semiconductor layer, or between the gate insulating layer and the oxide semiconductor layer.

[0014] In the above structure, the channel formation region of the oxide semiconductor layer is The gate insulating layer and insulating layer are stacked below, and the gate electrode layer and conductive layer surround the gate insulating layer and insulating layer. It has excellent impact resistance because it is made of a flexible substrate, and can be freely shaped. can.

[0015] When a transistor including an oxide semiconductor layer is provided over a flexible substrate, a flexible semiconductor device can be obtained. It is possible to create a device.

[0016] A transistor including an oxide semiconductor layer may be directly formed on a flexible substrate, or may be formed on another substrate. A transistor including an oxide semiconductor layer can be fabricated on a substrate and then separated and transferred to a flexible substrate. In order to separate and transfer the oxide semiconductor film from the formation substrate to the flexible substrate, A peeling layer may be provided between the transistor and the layer.

[0017] One embodiment of the invention disclosed in this specification is a gate electrode layer formed on a flexible substrate. A gate insulating layer is formed on the gate electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor layer is formed on the gate insulating layer. An insulating layer is formed covering the compound semiconductor layer, and an opening is formed in the gate insulating layer and the insulating layer. The gate insulating layer and the insulating layer are exposed at the top and bottom of the stack of the gate insulating layer and the insulating layer in the opening. A semiconductor device in which a conductive layer is formed covering an end portion of a stack of insulating layers and in contact with a gate electrode layer. This is the manufacturing method.

[0018] In one embodiment of the invention disclosed in this specification, a release layer is formed on a formation substrate, and a gate electrode is formed on the release layer. a gate electrode layer is formed on the gate electrode layer, a gate insulating layer is formed on the gate insulating layer, and an oxide film is formed on the gate insulating layer. A semiconductor layer is formed, an insulating layer is formed covering the oxide semiconductor layer, and a gate insulating layer and an insulating layer are formed on the insulating layer. An opening is formed to expose the gate electrode layer, and the upper part of the stack of the gate insulating layer and the insulating layer and the opening are a conductive layer covering an end of a stack of a gate insulating layer and an insulating layer and in contact with the gate electrode layer; The transistor is then separated from the manufacturing substrate by using a peeling layer. The transistors transferred to the support substrate are then transferred onto a flexible substrate. This is the manufacturing method.

[0019] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, in this specification, specific names are not used as matters for identifying the invention. This does not indicate [Effects of the Invention]

[0020] One embodiment of the present invention is a method for forming a channel formation region of an oxide semiconductor layer by stacking a plurality of oxide semiconductor layers in a channel width direction. The gate insulating layer and insulating layer are further surrounded by a gate electrode layer and a conductive layer. This makes it possible to add impact resistance.

[0021] One aspect of the present invention is to provide a flexible material that can be used in a wider variety of applications and is more convenient. A semiconductor device with improved reliability can be provided. [Brief explanation of the drawings]

[0022] [Figure 1] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 2] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 3] 1A to 1C illustrate one embodiment of a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate one embodiment of a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 9] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 10] 1A and 1B are diagrams illustrating electronic devices. [Figure 11] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0024] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor will be described as an example of a semiconductor device. The semiconductor layer in the semiconductor device disclosed in the specification is preferably an oxide semiconductor layer. can.

[0025] As shown in FIGS. 1A to 1C, the channel of the oxide semiconductor layer 403 of the transistor 410 The channel formation region has a channel length (L) direction and a channel width (W) direction.

[0026] 1A is a plan view of a transistor 410, and FIG. 1B is a schematic diagram of the transistor shown in FIG. 1A. 1(C) is a cross-sectional view of the transistor 410 taken along the line A1-A2 in the channel length (L) direction. FIG. 1 is a cross-sectional view taken along line B1-B2 in the panel width (W) direction.

[0027] As shown in FIGS. 1A to 1C, a transistor 410 is formed on a substrate 40 having an insulating surface. 0, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode The transistor 410 includes an insulating layer 407 and a drain electrode layer 405a and a drain electrode layer 405b. , and a conductive layer 411 are laminated in this order.

[0028] In addition, in the cross-sectional view in the channel width direction of FIG. 1C, the oxide semiconductor layer 403 is a gate insulating film. The gate insulating layer 402 and the insulating layer 407 surround the top, bottom, and edges of the gate insulating layer 402. The gate insulating layer 402 is connected to the gate electrode layer 401 at both ends. The oxide semiconductor layer 403, the gate insulating layer 402, and the insulating layer 407 are formed on the insulating layer 407. The gate insulating layer 402 and the insulating layer 407 are covered with the gate insulating layer 402 and both ends of the insulating layer 407. A conductive layer 411 is provided in contact with the pole layer 401 .

[0029] Therefore, in the channel width direction, the oxide semiconductor layer 403 is separated from the gate insulating layer 402 and the insulating layer 404. 07, and is surrounded by the gate electrode layer 401 and the conductive layer 411.

[0030] In this manner, the oxide semiconductor layer 403 is surrounded by the gate insulating layer, the gate electrode layer, the insulating layer, and the When the structure is such that the conductive layer is laminated to protect the conductive layer, the channel as shown by the arrow 445 in FIG. 1(C) is Even if a force (external force) is applied in the width (W) direction of the panel, the thick laminated film The structure is hard to bend, so the force applied to the oxide semiconductor layer 403 located in the center of the stack is reduced. Therefore, damage to the oxide semiconductor layer 403 due to an external impact can be prevented. It is possible.

[0031] In addition, an opening through which the gate electrode layer 401 is widely exposed is formed in the gate insulating layer 402 and the insulating layer 407. The gate electrode layer 401 and the conductive layer 411 are in contact with each other through the opening. If a conductive film with good adhesion is used as the gate electrode layer 401 and the conductive layer 411, the gate electrode layer 401 and the conductive layer 411 are formed as shown by the arrow 445. The gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, and the insulating layer 404 are Peeling at the interface between the layer 407 and the conductive layer 411 can be prevented.

[0032] In order to increase the adhesive strength between the gate electrode layer 401 and the conductive layer 411, a wide contact area is provided. As shown in FIG. 1A, the gate electrode layer 401 and the conductive layer 411 are preferably in contact with each other. The distance in the channel length direction of the oxide semiconductor layer 403 in the region where the oxide semiconductor layer 403 is formed is It is preferable that the distance is longer than the channel length.

[0033] The oxide semiconductor layer 403 is disposed in the center, and both ends of the oxide semiconductor layer 403 are connected to the gate insulating layer 402 and the insulating layer 403. 407 contacts and seals the gate electrode layer 401 and the conductive layer 411 contacts both ends of the gate electrode layer 401 and the conductive layer 411. Therefore, the structure can be symmetrical with respect to the line C1-C2. The force indicated by 45 is uniformly distributed, and a large force is locally applied to the oxide semiconductor layer 403. This can prevent the following.

[0034] Therefore, in the transistor 410, the curvature in the channel width direction of the oxide semiconductor layer 403 It can improve crack resistance and provide impact resistance.

[0035] In the drive circuit, the channel width of the transistor is made longer to allow more current to flow. However, in the case of a transistor with a long channel width, Therefore, the influence of external forces due to the channel width as shown in this embodiment is large. It is more effective to use transistors with bending resistance in the drive circuit, and they are shock-resistant. Therefore, a semiconductor device with excellent performance and high reliability can be obtained.

[0036] In order to have impact resistance, a flexible substrate is used for the substrate 400, and a flexible semiconductor device is obtained. It can be applied to a wide range of applications, and can be used for a wider variety of purposes, providing improved convenience and reliability. Therefore, a highly reliable semiconductor device can be provided.

[0037] Note that the transistor disclosed in this specification has a structure in which the oxide semiconductor layer It has excellent bending resistance, so it can be easily bent (frequently bent) when manufacturing semiconductor devices. It is preferable to fabricate a transistor with the channel width direction aligned with the direction of the height of the semiconductor layer.

[0038] 3A1, 3A2, 3B1, 3B2, 3C1, 3D1, 3D2, 3E1, 3E2 show an example of a method for manufacturing the transistor 410. 3(A1) to (E1) correspond to FIG. 1(B), and FIG. 3(A2) to ( E2) corresponds to Figure 1(C).

[0039] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 401 is formed by a process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0040] The substrate 400 having an insulating surface can be a flexible substrate, for example, polyethylene terephthalate. Polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), Polyacrylonitrile resin, polyimide resin, polymethyl methacrylate resin, polycarbonate Carbonate resin (PC), polyethersulfone resin (PES), polyamide resin, cyclohexyl Polyolefin resin, polystyrene resin, polyamide-imide resin, polyvinyl chloride resin, etc. As a flexible substrate, a structure in which a fibrous body is impregnated with an organic resin can be preferably used. (so-called prepreg) may be used. Films containing nitrogen and silicon, such as silicon nitride, and films containing nitrogen and aluminum, such as aluminum nitride Alternatively, a protective film with low water permeability such as a film containing cellulose acetate may be formed on the surface of the substrate.

[0041] When the material of the substrate 400 contains fibrous material, the fibrous material may be an organic compound or an inorganic compound. High strength fibers are specifically fibers with high tensile modulus or Young's modulus. Typical examples are polyvinyl alcohol fibers, polyester fibers, Polyamide fiber, polyethylene fiber, aramid fiber, polyparaphenylene benzoin Examples of the glass fiber include soxazole fiber, glass fiber, and carbon fiber. Examples of glass fibers include E glass, S glass, D glass, and Q glass. It is used in the form of woven or nonwoven fabric, and the fibrous body is impregnated with an organic resin and the organic resin is hardened. The structure may be used as the substrate 400. The substrate 400 may be made of a fibrous body and an organic resin. The use of a structure is preferable because it improves reliability against damage due to bending or local pressure. It is a simple configuration.

[0042] Also, a glass substrate (e.g., barium borosilicate glass or aluminum) that has been thinned to a degree that it is flexible can be used. A metal substrate made of lumino-borosilicate glass or a film-like metal substrate may also be used. There is no particular limitation on the material to be used, but aluminum, copper, nickel, aluminum alloys, etc. Alternatively, a metal alloy such as stainless steel can be suitably used.

[0043] In order to manufacture a flexible semiconductor device, a semiconductor device including an oxide semiconductor layer 403 is formed on a flexible substrate. The transistor 410 may be directly formed, or may be formed on another substrate including the oxide semiconductor layer 403. The transistor 410 may be fabricated and then peeled off and transferred to a flexible substrate. In order to separate and transfer the transistor including the oxide semiconductor layer from the substrate to the flexible substrate, It is advisable to provide a release layer between the stamper and the substrate.

[0044] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. , which has the function of preventing diffusion of impurity elements from the substrate 400, and The insulating layer is made of one or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film. The insulating film can be formed by a laminated structure.

[0045] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, or aluminum. Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloy materials containing these as the main components The insulating film can be formed as a single layer or a laminate using a material.

[0046] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 is , a silicon oxide layer, a silicon nitride layer, etc., are formed by using a plasma CVD method, a sputtering method, etc. , silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer , an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer may be formed as a single layer or can be formed by laminating.

[0047] The oxide semiconductor of this embodiment is obtained by removing impurities and by removing carriers other than the main components of the oxide semiconductor. By purifying the compound to the extent possible to minimize the content of impurities that act as donors, it is possible to produce a genuine (type I) or The oxide semiconductor is substantially intrinsic (i-type).

[0048] The highly purified oxide semiconductor layer contains very few carriers (close to zero). The concentration is 1 x 10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, even more preferred 1×10 11 / cm 3 is less than.

[0049] Since there are very few carriers in the oxide semiconductor layer, the off-state current of the transistor is low. The smaller the off-state current, the better.

[0050] Such highly purified oxide semiconductors are extremely sensitive to interface states and interface charges. Therefore, the interface between the oxide semiconductor layer and the gate insulating layer is important. The gate insulating layer in contact with the nitride semiconductor is required to have high quality.

[0051] For example, high-density plasma CVD using microwaves (e.g., frequency 2.45 GHz) produces dense This is preferable because it allows the formation of a high-quality insulating layer with high dielectric strength. The close contact between the gate insulating layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be considered as such.

[0052] Of course, if a good insulating layer can be formed as a gate insulating layer, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. Even if the insulating layer is one in which the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are modified by In any case, it is important that the film quality as a gate insulating layer is good, and that the oxidation Any material may be used as long as it can reduce the interface state density with the compound semiconductor and form a good interface.

[0053] In addition, the gate insulating layer 402 and the oxide semiconductor film 440 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent the oxide semiconductor film 440 from being broken, sputtering was performed as pretreatment before the formation of the oxide semiconductor film 440. The substrate 400 on which the gate electrode layer 401 is formed in the preheating chamber of the heating device, or the gate insulating layer 4 The substrate 400 on which the above-mentioned steps 02 are formed is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate 400. It is preferable to desorb and exhaust the impurities. A pump is preferable. This preheating process can be omitted. Before the insulating layer 407 is formed, the source electrode layer 405a and the drain electrode layer 405b are heated. The same process may be carried out on the formed substrate 400 .

[0054] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm or more, is formed on the gate insulating layer 402. An oxide semiconductor film 440 having a thickness of 30 nm or less is formed (see FIGS. 3A1 and 3A2).

[0055] Before the oxide semiconductor film 440 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 402 to generate plasma. It is preferable to remove the powdery material (also called particles or dust) that is sputtered. In this experiment, no voltage was applied to the target side, and a voltage was applied to the substrate side using an RF power supply in an argon atmosphere. This method involves applying a voltage to generate plasma near the substrate to modify the surface. Nitrogen, helium, oxygen, etc. may be used in place of the atmosphere.

[0056] The oxide semiconductor used for the oxide semiconductor film 440 is a quaternary metal oxide, In-S n-Ga-Zn-O oxide semiconductors and In-Ga-Zn-O ternary metal oxides Oxide semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors Conductor, Sn-Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, S n-Al-Zn-O oxide semiconductors and In-Zn-O oxides, which are binary metal oxides Semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg- O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. The oxide semiconductor may contain SiO2. In-Ga-Zn-O oxide semiconductors are made of indium (In), gallium (Ga), and zinc. It means an oxide film containing lead (Zn), and the stoichiometric ratio is not particularly important. Furthermore, elements other than In, Ga, and Zn may be contained.

[0057] The oxide semiconductor film 440 has the chemical formula InMO3(ZnO) m (m>0) A thin film can be used, where M is one selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or or Ga and Co.

[0058] In this embodiment, the oxide semiconductor film 440 is formed using an In—Ga—Zn—O-based oxide target. The oxide semiconductor film 440 is formed by a sputtering method using a rare gas ( Typically, under an argon atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas and oxygen. The film can be formed by sputtering.

[0059] Examples of targets for forming the oxide semiconductor film 440 by a sputtering method include The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] Using a target, an In-Ga-Zn-O film is formed. The composition is not limited to, for example, In2O3:Ga2O3:ZnO=1:1:2 [mol number An oxide target having a ratio of [0.01 to 0.01] may also be used.

[0060] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99% or less. By using a metal oxide target with a high filling rate, the oxide film formed is The compound semiconductor film can be a dense film.

[0061] The oxide semiconductor film 440 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0062] The substrate is held in a film-forming chamber maintained in a reduced pressure state, and the substrate temperature is preferably set to 100°C or more and 600°C or less. The temperature is preferably 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. Damage caused by coating is reduced. The removed sputtering gas is introduced, and an oxide semiconductor is deposited on the substrate 400 using the target. To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, e.g. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. As an exhaust means, a turbo pump (turbomolecular pump) with a cold trap is preferable. The deposition chamber evacuated using a cryopump may be, for example, a water Compounds containing hydrogen atoms, such as water (H2O), are more preferably compounds containing carbon atoms. Since the gases such as argon, etc. are exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0063] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed DC power supply is used, powdery substances (particles, etc.) generated during film formation are This is preferable because it can reduce the thickness (also called "slippage") and make the film thickness distribution uniform.

[0064] Next, the oxide semiconductor film 440 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disk is used, manufacturing costs can be reduced.

[0065] In addition, when a contact hole is formed in the gate insulating layer 402, the process is performed using an oxide semiconductor This can be done simultaneously with the processing of the film 440 .

[0066] The etching of the oxide semiconductor film 440 here can be performed by dry etching or wet etching. For example, the oxide semiconductor film 440 may be subjected to wet etching. The etching solution used for etching is a mixture of phosphoric acid, acetic acid, and nitric acid, or ammonia hydrogen peroxide. (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0067] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C. The temperature is set to 750°C or higher, or 400°C or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the facilities, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, the oxide semiconductor layer was cooled to room temperature and then cooled to room temperature without being exposed to the air. The recontamination of elements is prevented, and an oxide semiconductor layer 441 is obtained (see FIGS. 3B1 and 3B2).

[0068] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0069] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. You may also perform a GRTA.

[0070] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0071] After the oxide semiconductor layer is heated by the first heat treatment, high-purity oxygen gas, high-purity SiO 2 gas, and Introduce high-temperature N2O gas or ultra-dry air (dew point below -40°C, preferably below -60°C). It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable to set the concentration of the oxygen gas or N2O gas to 0.1 ppm or less. The oxidation process, which is simultaneously reduced by the removal of impurities through dehydration or dehydrogenation treatment, By supplying oxygen, which is the main component material of the oxide semiconductor, the oxide semiconductor layer can be enhanced. Purify and electrically make it type I (intrinsic).

[0072] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 440 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0073] In addition to the above, the first heat treatment may be performed after the oxide semiconductor layer is formed. After stacking the source electrode layer and the drain electrode layer on the insulating layer, or This may be done either after forming an insulating layer on the drain electrode layer or after forming an insulating layer on the drain electrode layer.

[0074] In addition, when a contact hole is formed in the gate insulating layer 402, the process is performed using an oxide semiconductor This may be done before or after the film 440 is subjected to the first heat treatment.

[0075] In addition, the oxide semiconductor layer is formed in two separate steps and heat-treated in two separate steps. Regardless of the material of the component, such as oxide, nitride, or metal, the film thickness is thick and the crystalline region (single crystal region) In other words, even if an oxide semiconductor layer having a crystal region with a c-axis aligned perpendicular to the film surface is formed, For example, a first oxide semiconductor film having a thickness of 3 nm to 15 nm is formed, and nitrogen, oxygen, In a rare gas or dry air atmosphere, the temperature is 450°C or higher and 850°C or lower, preferably 550°C or higher. The first heat treatment is performed at 750°C or less, and a crystalline region (including plate-like crystals) is formed in the region including the surface. Then, a second oxide semiconductor film having a thickness larger than that of the first oxide semiconductor film is formed. 2, and the oxide semiconductor film is formed at 450° C. or higher and 850° C. or lower, preferably 600° C. or higher and 70° C. or lower. Second heat treatment is performed at 0° C. or lower, and the first oxide semiconductor film is used as a seed for crystal growth. Crystal growth is performed to crystallize the entire second oxide semiconductor film, resulting in a thick crystalline region. Alternatively, an oxide semiconductor layer having a region may be formed.

[0076] Next, a source electrode layer and a drain electrode layer are formed over the gate insulating layer 402 and the oxide semiconductor layer 441. A conductive film is formed to become the source electrode layer (including wiring formed in the same layer). The conductive film used for the gate electrode layer and the drain electrode layer may be, for example, Al, Cr, Cu, Ta, or T. Metal film containing an element selected from I, Mo, and W, or a metal containing the above elements as components Nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) can be used. In addition, Ti, Mo, W can be applied to either or both of the upper and lower sides of the metal film such as Al or Cu. High-melting point metal films or their metal nitride films (titanium nitride film, molybdenum nitride film, nitride The source electrode layer and the drain electrode layer may be formed by laminating a tungsten oxide film. The conductive film used for the electrode layer may be formed of a conductive metal oxide. The oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), Indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide It is possible to use a material containing kon.

[0077] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by etching, Remove the mask.

[0078] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrodes adjacent to each other on the oxide semiconductor layer 441 may be formed by using a laser beam or an ArF laser beam. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the drain electrode layer determines the width of the gap between the bottom end of the drain electrode layer and the bottom end of the transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. et) is used to perform exposure during resist mask formation in the third photolithography process. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed of the circuit can be increased.

[0079] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0080] Note that when the conductive film is etched, the oxide semiconductor layer 441 is etched and divided. However, it is desirable to optimize the etching conditions so that the conductive film alone does not It is difficult to achieve a condition in which the oxide semiconductor layer 441 is etched while the oxide semiconductor layer 442 is not etched at all. When the conductive film is etched, only a part of the oxide semiconductor layer 441 is etched, and the groove In some cases, the oxide semiconductor layer may have a recess (concave portion).

[0081] In this embodiment, a Ti film is used as the conductive film, and an In—Ga— Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia hydrogen peroxide) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0082] Next, plasma treatment is performed using gases such as N2O, N2, or Ar to remove the exposed The plasma treatment may be performed to remove adsorbed water or the like attached to the surface of the oxide semiconductor layer. In this case, the insulating layer 407 is formed in contact with part of the oxide semiconductor layer without being exposed to air.

[0083] The insulating layer 407 has a thickness of at least 1 nm, and is formed by a method such as sputtering. The insulating layer 407 can be formed by appropriately using a method that does not mix impurities such as hydrogen. When hydrogen is contained in the oxide semiconductor layer, the hydrogen penetrates into the oxide semiconductor layer, or the oxide semiconductor layer is deformed by the hydrogen. Oxygen is extracted from the layer, and the back channel of the oxide semiconductor layer becomes low-resistance (N-type). Therefore, the insulating layer 407 should be as thin as possible. It is important that the deposition process does not use hydrogen, resulting in a hydrogen-free film.

[0084] The insulating layer 407 is typically made of a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An inorganic insulating film such as an aluminum film or an aluminum oxynitride film can be used.

[0085] In this embodiment, a silicon oxide film having a thickness of 200 nm is deposited as the insulating layer 407 by sputtering. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an atmosphere of argon, oxygen, or a mixture of rare gases and oxygen. In addition, a silicon oxide target or a silicon target may be used as the target. For example, a silicon target can be used in an atmosphere containing oxygen. A silicon oxide film can be formed by sputtering under atmospheric pressure. The insulating layer 407 formed by this method is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block the intrusion of these elements from the outside, typically a silicon oxide film. a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like. do.

[0086] As in the case of forming the oxide semiconductor film 440, residual moisture in the deposition chamber for the insulating layer 407 is removed. To achieve this, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 407 formed in a deposition chamber evacuated using an opto-pump was reduced. In addition, the exhaust means for removing the residual moisture in the film formation chamber of the insulating layer 407 may be: A turbo pump (turbomolecular pump) with a cold trap added may also be used.

[0087] The insulating layer 407 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use a high-purity gas from which impurities have been removed.

[0088] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. A part of the layer (channel forming region) is heated in a state where the layer is in contact with the insulating layer 407 .

[0089] Through the above steps, the oxide semiconductor film is subjected to the first heat treatment to remove hydrogen and Impurities such as moisture, a hydroxyl group, or hydrides (also called hydrogen compounds) are intentionally removed from the oxide semiconductor layer. The oxide semiconductor is formed by eliminating impurities and reducing the impurity concentration. Therefore, the oxide semiconductor layer can be supplied with oxygen, which is one of the main components of the oxide semiconductor layer. Purify and electrically make it type I (intrinsic).

[0090] Through the above steps, the transistor 410 is formed (see FIGS. 3C1 and 3C2).

[0091] Furthermore, when a silicon oxide layer containing many defects is used for the insulating layer 407, The heat treatment reduces hydrogen, moisture, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer. Impurities are diffused into the oxide silicon layer, and the impurities contained in the oxide semiconductor layer are further reduced. This has the effect of making people feel more comfortable.

[0092] A protective insulating layer may be further formed on the insulating layer 407. For example, a protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is the preferred method for forming a protective insulating layer. The protective insulating layer does not contain impurities such as moisture, and these impurities are prevented from penetrating from the outside. It uses an inorganic insulating film that blocks the There are.

[0093] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then reduced from the heating temperature to room temperature. The temperature drop at this temperature may be repeated several times.

[0094] Next, the gate insulating layer 402 and the insulating layer 407 are selectively removed to leave the gate electrode layer 401. Exposing openings 412a and 412b are formed (see FIGS. 3(D1) and 3(D2)). 2), the gate insulating layer 40 The gate insulating layer 402 and the insulating layer 407 are formed so as to surround and seal the oxide semiconductor layer 403 in the center. Openings 412a and 412b are formed in the layer 402 and the insulating layer 407. Since the gate insulating layer 402 and the insulating layer 407 were etched using the same mask, The edges of layer 402 and insulating layer 407 are roughly aligned.

[0095] Next, a conductive film is formed over the insulating layer 407, and the conductive film is etched using a photolithography process. The conductive layer 411 is formed by etching (see FIGS. 3(E1) and 3(E2)). The insulating film 404 is formed so as to cover at least the channel formation region of the oxide semiconductor layer 403.

[0096] As shown in FIG. 3E2, the oxide semiconductor layer 403 provided over the gate electrode layer 401 The upper part of the insulating layer 407 and the surrounding gate insulating layer 402 and the insulating layer A conductive layer 411 covers both ends of the gate electrode layer 407 and contacts the gate electrode layer 401 exposed in the opening. The conductive layer 411 is in contact with the gate electrode layer 401 and therefore has the same structure as the gate electrode layer 401. It becomes an electric potential.

[0097] By providing the conductive layer 411 having the same potential as the gate electrode layer 401, the transistor 4 10, the formation of a parasitic channel due to leakage current in the back channel can be prevented. can.

[0098] The conductive layer 411 also shields the external electric field, i.e., the external electric field is prevented from reaching the internal (transistor) It also has a function to prevent the device from affecting the circuitry (including the circuitry) (especially the electrostatic shielding function against static electricity). The shielding function of the conductive layer 411 prevents the transistor from being affected by external electric fields such as static electricity. This can prevent the electrical characteristics of 410 from fluctuating.

[0099] The transistor using the highly purified oxide semiconductor layer 403 manufactured in accordance with this embodiment is The current value in the off state (off current value) of the stator 410 is 10 per 1 μm of channel width. zA / μm at 85°C, and can be reduced to a level of less than 100 zA / μm at 85°C.

[0100] In addition, the transistor 410 including the oxide semiconductor layer 403 has relatively high field-effect mobility. Therefore, the above transistors are used in the pixel portions of liquid crystal display devices. By using a highly purified oxide, high-quality images can be obtained. By using transistors containing a compound semiconductor layer, a driving circuit section or a pixel section can be created separately on the same substrate. Since the semiconductor device can be manufactured using the same components, the number of components in the semiconductor device can be reduced.

[0101] As described above, the channel formation region of the oxide semiconductor layer is stacked in the channel width direction. By surrounding it with a gate insulating layer, an insulating layer, a gate electrode layer and a conductive layer, , and impact resistance can be added.

[0102] In addition, by adding flexibility, it can be used for a wider variety of applications, and it is more convenient and reliable. Therefore, a highly reliable semiconductor device can be provided.

[0103] (Embodiment 2) In this embodiment, another mode of a semiconductor device will be described with reference to FIG. A transistor is shown as an example of a semiconductor device. Portions and steps having similar functions can be performed in the same manner as in the above-described embodiment, and can be repeatedly performed. The explanation of the same parts will be omitted.

[0104] 2A and 2B show transistors 420a, 420b, and 420c connected in parallel. The multiple transistors 420a, 420b, and 420c are connected in parallel to realize This has the same effect as widening the channel width, allowing a larger amount of current to flow. By combining a configuration in which multiple transistors are arranged in parallel to divide the channel width, By using these transistors in combination, the degree of freedom in circuit design can be improved. , 420b, and 420c, which are capable of passing a large amount of current, are used for driving the driving circuit unit. It can be suitably used as a circuit transistor.

[0105] The oxide semiconductor layers 423a, 423b, and 423c of the transistors 420a, 420b, and 420c The channel forming region 3c has a channel length (L) direction and a channel width (W) direction. .

[0106] FIG. 2A is a plan view of transistors 420a, 420b, and 420c, and FIG. 2B is a plan view of transistors 420a, 420b, and 420c. In the channel width (W) direction of the transistors 420a, 420b, and 420c shown in FIG. 3 is a cross-sectional view taken along line B3-B4 in FIG.

[0107] As shown in FIGS. 2A and 2B, the transistors 420a, 420b, and 420c are electrically isolated. On a substrate 400 having a surface, a gate electrode layer 421, a gate insulating layer 422 (gate insulating layer 4 22a, 422b, and 422c), oxide semiconductor layers 423a, 423b, and 423c, and source The transistors 420a, 420b, and 420c include a drain electrode layer 425a and a drain electrode layer 425b. On the insulating layer 427 (insulating layers 427a, 427b, 427c), and the conductive layer 43 1 are stacked in order.

[0108] The transistors 420a, 420b, and 420c are connected in parallel, and the gate electrode layer 4 21, the source electrode layer 425a and the drain electrode layer 425b are provided in common.

[0109] In addition, in the cross-sectional view in the channel width direction of the oxide semiconductor layers 423a and 423b in FIG. , 423c are gate insulating layers 422a, 422b, 422c and insulating layers 427a, 427b, 427c, respectively. The upper, lower, and end portions are surrounded by gate insulating layers 422a, 422b, and 427c. , 422c and insulating layers 427a, 427b, 427c are in contact at both ends. A gate electrode layer 421 is provided under the layers 422a, 422b, and 422c, and an insulating layer 42 On the oxide semiconductor layers 423a, 423b, and 423c, the gate insulating film 427a, 427b, and 427c are formed. The insulating layers 422a, 422b, and 422c and the insulating layers 427a, 427b, and 427c are and gate insulating layers 422a, 422b, 422c, and insulating layers 427a, 427b, 4 A conductive layer 431 is provided to cover both ends of the gate electrode layer 421. .

[0110] Therefore, the oxide semiconductor layers 423a, 423b, and 423c are Gate insulating layers 422a, 422b, and 422c and insulating layers 427a, 427b, and 427c, respectively. , and is surrounded by a gate electrode layer 421 and a conductive layer 431 .

[0111] In this manner, the oxide semiconductor layers 423a, 423b, and 423c are surrounded by the gate electrode layer, the gate When the protection structure is formed by laminating a protective insulating layer, an insulating layer, and a conductive layer, Even if a force is applied, the thick laminated structure is hard to bend, so the Therefore, the force applied to the oxide semiconductor layers 423a, 423b, and 423c can be reduced. This prevents damage to the oxide semiconductor layers 423a, 423b, and 423c due to an external impact. It is possible.

[0112] In addition, the gate insulating layer 422 (gate insulating layers 422a, 422b, 422c) and the insulating layer 4 27 (insulating layers 427a, 427b, 427c) is provided with an opening in which the gate electrode layer 421 is widely exposed. The gate electrode layer 421 and the conductive layer 431 are in contact with each other through the openings. When a conductive film having good adhesion is used as the gate electrode layer 421 and the conductive layer 431, The gate electrode layer 421, the gate insulating layers 422a, 422b, and 422c, oxide semiconductor layers 423a, 423b, and 423c; insulating layers 427a, 427b, and 427c; Alternatively, peeling of the conductive layer 431 at the interface can be prevented.

[0113] In order to increase the adhesive strength between the gate electrode layer 421 and the conductive layer 431, a contact area is provided widely. As shown in FIG. 2A, the gate electrode layer 421 and the conductive layer 431 are preferably in contact with each other. The distance between the oxide semiconductor layers 423a, 423b, and 423c in the channel length direction is The distance can be made longer than the channel length of the oxide semiconductor layers 423a, 423b, and 423c. preferable.

[0114] In addition, in the transistors 420a, 420b, and 420c, the oxide semiconductor layer 4 23a, 423b, and 423c are arranged in the center, and both ends are connected to the gate insulating layers 422a and 42 2b, 422c contact with insulating layers 427a, 427b, 427c to seal them. The gate electrode layer 421 and the conductive layer 431 contact and seal the edges, so they are line-symmetrical structures. Therefore, the external force can be uniformly distributed, and the oxide semiconductor layer 423a , 423b, 423c, it is possible to prevent a large force from being applied locally.

[0115] Therefore, in the transistors 420a, 420b, and 420c, the oxide semiconductor layers 423a, 423b, 423c to increase bending resistance in the channel width direction and provide impact resistance. can be done.

[0116] In order to have impact resistance, a flexible substrate is used for the substrate 400, and a flexible semiconductor device is obtained. It can be applied to a wide range of applications, and can be used for a wider variety of purposes, providing improved convenience and reliability. Therefore, a highly reliable semiconductor device can be provided.

[0117] As described above, the channel formation region of the oxide semiconductor layer is stacked in the channel width direction. By surrounding it with a gate insulating layer, an insulating layer, a gate electrode layer and a conductive layer, , and impact resistance can be added.

[0118] In addition, by adding flexibility, it can be used for a wider variety of applications, and it is more convenient and reliable. Therefore, a highly reliable semiconductor device can be provided.

[0119] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0120] (Embodiment 3) In this embodiment, another mode of a semiconductor device will be described with reference to FIG. A transistor will be described as an example of a semiconductor device. This is an example in which the formation process and structure of the source electrode layer and the drain electrode layer are different. The same parts as those in the embodiment or parts having similar functions and steps are performed in the same manner as in the above embodiment. Therefore, repeated explanations will be omitted, and detailed explanations of the same parts will be omitted.

[0121] In Embodiments 1 and 2, the source electrode layer 405a and the drain electrode layer 405b is provided between the oxide semiconductor layer 403 and the insulating layer 407. The source electrode layer 405a and the drain electrode layer 405b are formed by the gate insulating layer 402 and the oxide semiconductor 4 shows an example in which the insulating layer 403 is provided between the insulating layer 403 and the insulating layer 404.

[0122] 5A is a plan view of the transistor 430, and FIG. 5B is a schematic diagram of the transistor shown in FIG. 5A. 5(C) is a cross-sectional view of the transistor 430 taken along the line A5-A6 in the channel length (L) direction. This is a cross-sectional view taken along line B5-B6 in the panel width (W) direction.

[0123] The transistor 430 shown in FIGS. 5A to 5C is a bottom-gate transistor. On a substrate 400, a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 406, a gate insulating layer 408, a gate insulating layer 409, a gate insulating layer 410, a gate insulating layer 411, a gate insulating layer 412, a gate insulating layer 413, a gate insulating layer 414, a gate insulating layer 415, a gate insulating layer 416, a The transistor 430 includes a drain electrode layer 405b and an oxide semiconductor layer 403. An insulating layer 407 is provided to cover and be in contact with the oxide semiconductor layer 403 .

[0124] In transistor 430, gate insulating layer 402 is formed between substrate 400 and gate electrode layer 400. 1, a source electrode layer 405a and a drain electrode layer 405b are provided on the gate insulating layer 402. The gate insulating layer 402 and the source electrode layer 405b are provided in contact with each other. 5a, an oxide semiconductor layer 403 is provided over a drain electrode layer 405b.

[0125] In addition, in the cross-sectional view in the channel width direction of FIG. 5C, the oxide semiconductor layer 403 is a gate insulating film. The gate insulating layer 402 and the insulating layer 407 surround the top, bottom, and edges of the gate insulating layer 402. The gate insulating layer 402 is connected to the gate electrode layer 401 at both ends. The oxide semiconductor layer 403, the gate insulating layer 402, and the insulating layer 407 are formed on the insulating layer 407. The gate insulating layer 402 and the insulating layer 407 are covered with the gate insulating layer 402 and both ends of the insulating layer 407. A conductive layer 411 is provided in contact with the pole layer 401 .

[0126] Therefore, in the channel width direction, the oxide semiconductor layer 403 is separated from the gate insulating layer 402 and the insulating layer 404. 07, and is surrounded by the gate electrode layer 401 and the conductive layer 411.

[0127] In this manner, the oxide semiconductor layer 403 is surrounded by the gate insulating layer, the gate electrode layer, the insulating layer, and the When the structure is protected by laminating conductive layers, the force in the channel width (W) direction (external force) Even if a force is applied (force applied from the center of the layer), the thick layer structure is difficult to bend. Therefore, the force applied to the oxide semiconductor layer 403 located at the outermost position can be reduced. Damage to the oxide semiconductor layer 403 due to impact can be prevented.

[0128] In addition, an opening through which the gate electrode layer 401 is widely exposed is formed in the gate insulating layer 402 and the insulating layer 407. The gate electrode layer 401 and the conductive layer 411 are in contact with each other through the opening. If a conductive film with good adhesion is used as the gate electrode layer 401 and the conductive layer 411, The gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, and the insulating layer 404 are formed by the force generated by the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, and the insulating layer 404. Peeling at the interface of the edge layer 407 or the conductive layer 411 can be prevented.

[0129] In order to increase the adhesive strength between the gate electrode layer 401 and the conductive layer 411, a wide contact area is provided. As shown in FIG. 5A, the gate electrode layer 401 and the conductive layer 411 are preferably in contact with each other. The distance in the channel length direction of the oxide semiconductor layer 403 in the region where the oxide semiconductor layer 403 is formed is It is preferable that the distance is longer than the channel length.

[0130] The oxide semiconductor layer 403 is disposed in the center, and both ends of the oxide semiconductor layer 403 are connected to the gate insulating layer 402 and the insulating layer 403. 407 contacts and seals the gate electrode layer 401 and the conductive layer 411 contacts both ends of the gate electrode layer 401 and the conductive layer 411. Therefore, the force applied from the outside is uniform. Therefore, it is possible to prevent a large force from being applied locally to the oxide semiconductor layer 403. can.

[0131] Therefore, in the transistor 430, the curvature of the oxide semiconductor layer 403 in the channel width direction It can improve crack resistance and provide impact resistance.

[0132] In order to have impact resistance, a flexible substrate is used for the substrate 400, and a flexible semiconductor device is obtained. It can be applied to a wide range of applications, and can be used for a wider variety of purposes, providing improved convenience and reliability. Therefore, a highly reliable semiconductor device can be provided.

[0133] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0134] (Fourth embodiment) In this embodiment mode, a transistor is formed on a flexible substrate by performing a peeling and transfer process from another manufacturing substrate. 4 shows an example of a method for manufacturing a semiconductor device having a capacitor. The present embodiment is the same as the first embodiment except for some differences in the steps. Therefore, the same parts are designated by the same reference numerals and detailed explanations of the same parts are omitted.

[0135] An example of a method for manufacturing a semiconductor device will be described in detail with reference to FIGS.

[0136] A separation layer 302 is formed on a first manufacturing substrate 300, and a first insulating layer 301 is formed on the separation layer 302. Preferably, the first insulating layer 302 is formed without exposing the formed release layer 302 to the atmosphere. By forming the layers successively, the peeling layer 302 and the first insulating layer 301 are formed. This prevents the intrusion of dust and impurities between the 301.

[0137] The first fabrication substrate 300 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or the like. A plate, a metal substrate, or the like can be used. As a glass substrate, a barium borosilicate glass The treatment temperature of this embodiment can be set to 1000 K. A plastic substrate having heat resistance that can withstand high temperatures may be used. In this case, the substrate to be fabricated can be appropriately selected in accordance with the process to be performed.

[0138] In this step, the peeling layer 302 is provided over the entire surface of the first manufacturing substrate 300. However, if necessary, a peeling layer 302 is provided on the entire surface of the first manufacturing substrate 300, and then the peeling layer 302 may be selectively removed to provide a release layer only in a desired area. The peeling layer 302 is formed in contact with the substrate 300 in the first manufacturing step. A silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer is formed between the substrate 300 and the release layer 302. Alternatively, an insulating layer such as a silicon nitride oxide layer may be formed.

[0139] The release layer 302 may be made of tungsten (W), molybdenum (Mo), titanium (Ti), or tantalum. (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr ), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os) , iridium (Ir), silicon (Si), or an element selected from these, or an element containing the element as the main component It is made of an alloy material or a compound material mainly composed of the above element, and is a single layer or a laminated layer. The crystal structure of the silicon-containing layer may be any of amorphous, microcrystalline, and polycrystalline.

[0140] The peeling layer 302 can be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet ejection method, and a dispense method.

[0141] When the release layer 302 has a single layer structure, it is preferably a tungsten layer, a molybdenum layer, or a titanium layer. A layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of titanium and molybdenum is formed. The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum. do.

[0142] When the peeling layer 302 has a laminated structure, it is preferable that the first layer is a tungsten layer, the second layer is a molybdenum layer, and the third layer is a tungsten layer. A layer containing a mixture of tungsten and molybdenum is formed, and a second layer containing tungsten and molybdenum is formed. Oxides, nitrides, and oxynitrides of tungsten, molybdenum, or mixtures of tungsten and molybdenum Or, a nitride oxide is formed.

[0143] The peeling layer 302 has a stacked structure of a layer containing tungsten and a layer containing tungsten oxide. In the case of forming a tungsten-containing layer, an insulating layer made of oxide is formed on the tungsten-containing layer. By forming a tungsten oxide layer at the interface between the tungsten-containing layer and the insulating layer, It may be possible to utilize the formation of a layer containing the same.

[0144] In addition, when a separation layer is formed and a transistor is formed over the formation substrate, the oxide semiconductor layer is dehydrated. The peeling layer is also heated by the heat treatment for hydrogenation and dehydrogenation, and in the subsequent process, the peeling layer is transferred from the production substrate to the support substrate. When peeling is performed, peeling at the interface of the peel layer becomes easy.

[0145] The surface of the layer containing tungsten may be treated by thermal oxidation, oxygen plasma treatment, or an acid treatment such as ozone water. A layer containing tungsten oxide may be formed by treating the surface with a solution having a strong chemical action. The plasma treatment and heat treatment are carried out using oxygen, nitrogen, nitrous oxide alone, or these gases and their combinations. It may be performed in a mixed gas atmosphere with other gases. This may be performed in a mixed gas atmosphere with tungsten nitride, oxynitride, etc. The same applies to the case where a layer containing a nitride and a nitride oxide is formed. Then, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed on top of it. good.

[0146] A layer to be peeled 304 is formed on the peeling layer 302 (see FIG. 4(A)). The layer to be peeled 304 is It includes a first insulating layer 301 and a transistor 410 .

[0147] First, a first insulating layer 301 is formed on a release layer 302. The first insulating layer 301 is made of a nitride. Silicon nitride, silicon oxynitride, silicon nitride oxide, etc., are insulating films containing nitrogen and silicon. It is preferably formed in a layer or multiple layers.

[0148] The first insulating layer 301 is formed by using a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. For example, the film can be formed by plasma CVD at a film formation temperature of 250°C to By forming the membrane at 400°C, it is possible to obtain a dense membrane with extremely low water permeability. The thickness of the first insulating layer 301 is 10 nm or more and 1000 nm or less, and further 100 nm or more. Preferably, it is 700 nm or less.

[0149] By providing the first insulating layer 301, peeling at the interface with the peeling layer 302 can be prevented in a later peeling step. Furthermore, cracks and damage to the semiconductor elements and wiring are prevented during the subsequent peeling process. In addition, the first insulating layer 301 functions as a protective layer for the semiconductor device. do.

[0150] A transistor 410 is formed over the first insulating layer 301, and a peeled layer 304 is formed. The separation layer 304 can be formed by applying the method described in the first embodiment, and therefore, a detailed description thereof will not be given here. Omit the details.

[0151] Note that this embodiment shows an example in which a protective insulating layer 409 is stacked over the insulating layer 407. In this embodiment, the protective insulating layer 409 is formed on the substrate 400 on which the insulating layer 407 is formed. The mixture is heated to a temperature of 100°C to 400°C, and a spa containing high-purity nitrogen from which hydrogen and moisture have been removed is used. A target gas is introduced and a silicon nitride film is formed using a silicon semiconductor target (Figure 4 (See (A)). In this case, as with the insulating layer 407, the remaining moisture in the processing chamber is removed. It is preferable to form the protective insulating layer 409 while removing the insulating film.

[0152] In addition, a planar insulating layer is formed on the transistor 410 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (lo In addition, multiple insulating films made of these materials can be stacked. A planarization insulating film may be formed by layering the same.

[0153] Next, a second fabrication substrate 306 is temporarily attached to the layer to be peeled 30 using a removable adhesive layer 305. By bonding the second substrate 306 to the peeled layer 304, The layer to be peeled 304 can be easily peeled from the peeling layer 302. This reduces the stress applied to the adhesive layer 304, protecting the transistor. 05, the second fabrication substrate 306 can be easily removed when it is no longer needed. .

[0154] The removable adhesive layer 305 can be, for example, a water-soluble resin. The water-soluble resin spread on the layer to be peeled 304 reduces the unevenness of the layer to be peeled 304, and the layer to be peeled 304 is adhered to the second substrate 306. In addition, the removable adhesive layer 305 may be an adhesive that can be peeled off by light or heat. The adhesive may be laminated on a water-soluble resin.

[0155] Next, the layer to be peeled 304 is peeled off from the first formation substrate 300 (see FIG. 4(B)). A variety of methods can be used.

[0156] For example, when a metal oxide film is formed as the peeling layer 302 on the side in contact with the first insulating layer 301, In this case, the metal oxide film is weakened by crystallization, and the peeled layer 304 is attached to the first fabrication substrate 30. After the metal oxide film is weakened by crystallization, it can be peeled off from the substrate. A part of the peeling layer 302 is then removed by a solution or a halogen fluoride gas such as NF3, BrF3, or ClF3. The metal oxide film may be peeled off by etching and then weakened.

[0157] The peeling layer 302 may be a film containing nitrogen, oxygen, hydrogen, or the like (for example, amorphous silicon containing hydrogen). The first substrate 300 is a transparent substrate. When a substrate having optical properties is used, laser light is applied from the first fabrication substrate 300 to the peeling layer 302. The nitrogen, oxygen, and hydrogen contained in the peeling layer are vaporized by irradiating the peeling layer with light, and the first fabrication substrate 300 is formed. and the release layer 302 can be used.

[0158] The peeling layer 302 is removed by etching, and the peeled layer 304 is then attached to the first substrate. It may be peeled off from 300.

[0159] Also, a method of mechanically polishing and removing the first fabrication substrate 300, or a method of removing the first fabrication substrate 300 Removed by etching with halogen fluoride gases such as NF3, BrF3, ClF3, or HF In this case, the peeling layer 302 does not need to be used.

[0160] In addition, laser irradiation, etching with gas or solution, or sharp knives or scalpels may cause A groove is formed by using the adhesive to expose the release layer 302, and the release layer 302 is then bonded to the adhesive using the groove as a starting point. The layer to be peeled 304 is attached to the first substrate 301 at the interface with the first insulating layer 301, which functions as a protective layer. It can also be peeled off from 300.

[0161] The peeling method may involve, for example, applying mechanical force (pulling off with a human hand or a gripping tool). The separation can be carried out by using a method such as a separation process using a rotating roller. The liquid is dropped onto the interface between the release layer 302 and the first insulating layer 301, so that the liquid penetrates the interface between the release layer 302 and the first insulating layer 301. The layer to be peeled 304 may be peeled off from the groove. A fluoride gas is introduced, and the peeling layer 302 is etched and removed with the fluoride gas to form a film having an insulating surface. A method of peeling the layer to be peeled 304 from the first fabrication substrate 300 may also be used. When peeling, a liquid such as water may be poured on the surface.

[0162] As another peeling method, when the peeling layer 302 is formed of tungsten, ammonia The peeling can be performed while etching the peeling layer with a mixed solution of water and hydrogen peroxide. .

[0163] Next, the substrate 400 is bonded to the peeled layer 304 using a resin layer 307 (see FIG. 4(C)). .).

[0164] The substrate 400 can be a flexible substrate as shown in Embodiment 1. Cut.

[0165] The resin layer 307 may be a photo-curable adhesive such as an ultraviolet curable adhesive, a reaction curable adhesive, Various curing adhesives such as thermosetting adhesives or anaerobic adhesives can be used. The adhesive materials used include epoxy resin, acrylic resin, silicone resin, and phenolic resin. Fat and the like can be used.

[0166] When a prepreg is used as the substrate 400, the peeled layer 30 is directly attached without using an adhesive. The organic resin of the structure is a polymer. Resin-curable, heat-curable, and UV-curable types that undergo further processing to harden It is better to use

[0167] After providing the substrate 400, the second fabrication substrate 306 and the removable adhesive layer 305 are removed, The transistor 410 is exposed (see FIG. 4(D)).

[0168] Through the above steps, a transistor 410 is formed on the substrate 400 using a transfer process. This can be done.

[0169] Note that although the present embodiment has illustrated a method of providing a transistor in the peeled layer, The invention disclosed in the specification is not limited to this, and other display elements may be formed (for example, light-emitting elements). etc.) Peeling and transposition may also be performed.

[0170] According to this embodiment, a transistor manufactured using a substrate with high heat resistance can be thin and It can be placed on a lightweight flexible substrate. Therefore, it is not limited by the heat resistance of the substrate and can be made flexible. Therefore, a semiconductor device can be formed.

[0171] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0172] (Embodiment 5) A semiconductor device having a display function using the transistors exemplified in any of Embodiments 1 to 4 ( The transistors, examples of which are shown in Embodiments 1 to 4, can be manufactured. It is more effective to use a transistor in the drive circuit. A part or the whole of the above is formed on the same substrate as the pixel section to form a system-on-panel. It is possible.

[0173] 6A and 6B, a pixel portion 4002 provided on a first substrate 4001 and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4006 is provided on the substrate 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001 and the sealing material 4004. The display element is sealed by the second substrate 4005 and the second substrate 4006. In B), the area surrounded by the sealant 4005 on the first substrate 4001 and are formed in different regions using a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. In FIG. 6(A) and (B), a signal line driver circuit 4003 is mounted. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a signal line driver circuit 4005 are connected to the pixel portion 4002. The various signals and potentials are supplied from the FPC4018.

[0174] 6A and 6B, the signal line driver circuit 4003 is formed separately, and the first substrate 4 001, but the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0175] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C FIG. 6B shows an example of mounting the signal line driver circuit 4003 by the OG method. This is an example in which the signal line driver circuit 4003 is implemented by the above.

[0176] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0177] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0178] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistors in the scan line driver circuit 4004 are the same as those shown in any of Embodiments 1 to 4. A transistor having such a structure can be applied.

[0179] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0180] One mode of the semiconductor device will be described with reference to FIGS. 7 to 9. This corresponds to the cross section at MN.

[0181] As shown in FIGS. 7 to 9, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminals of the FPC 4018. They are electrically connected via an anisotropic conductive film 4019 .

[0182] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. It is formed of a conductive film.

[0183] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 7 to 9, the transistors included in the pixel portion 4002 are 4004 and a transistor 4010 included in the scanning line driver circuit 4004. In FIG. 7, an insulating layer 4020 is provided over the transistors 4010 and 4011, and in FIG. 9, an insulating layer 4021 is further provided. Note that the insulating film 4023 is a base film. It is an insulating film that functions as a

[0184] In this embodiment, the transistor 4011 of the scan line driver circuit 4004 is The transistor 4011 is a transistor having an oxide semiconductor layer In the channel width direction, the channel forming region is formed by the upper and lower gate insulating layers, the gate electrode layer, and the insulating layer. The structure is surrounded by a layer and a conductive layer. Therefore, it is preferable to provide a long channel width of the transistor. A transistor with bending resistance in the channel width direction as shown in Fig. 1 has high impact resistance. A semiconductor device with excellent reliability can be obtained.

[0185] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. It can be used.

[0186] FIG. 7 shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013 includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer The liquid crystal layer 4008 is sandwiched between insulating films 4 The second electrode layer 4031 is provided on the second substrate 4006 side. The first electrode layer 4030 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween. It is structured as follows.

[0187] 4035 is a columnar spacer obtained by selectively etching the insulating film. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A pacer may be used.

[0188] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0189] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the phase and the chiral agent has a short response time of 1 msec or less, and Since the liquid crystal is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need for rubbing, the problem caused by rubbing is eliminated. To prevent electrostatic breakdown and reduce defects and damage to a liquid crystal display device during the manufacturing process. Therefore, it is possible to improve the productivity of the liquid crystal display device. The electrical characteristics of transistors that use Therefore, a transistor including an oxide semiconductor layer may be used. It is more effective to use a blue phase liquid crystal material in a liquid crystal display device.

[0190] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0191] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the high-purity oxide semiconductor layer can be set in consideration of the off-state current of the transistor and the like. By using a transistor having It is sufficient to provide a storage capacitor having a capacity preferably 1 / 5 or less of the capacity of the storage capacitor.

[0192] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0193] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode In addition, it can be applied to VA type liquid crystal display devices. A VA type liquid crystal display device is a device that controls the alignment of liquid crystal molecules in a liquid crystal display panel. VA type LCD displays have a characteristic that the panel surface is not electrically connected to the LCD panel when no voltage is applied. The liquid crystal molecules are aligned vertically. The multi-domain structure is designed to divide the device into sub-pixels (pixels) and tilt the molecules in different directions. A method known as multi-domain or multi-domain design can be used.

[0194] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0195] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may differ for each dot of the color element. The present invention is not limited to display devices with a monochromatic display, but can also be applied to display devices with a monochrome display. can.

[0196] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0197] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0198] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light emitting element is an organic EL element. do.

[0199] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite the substrate. Top emission, bottom emission where light is extracted from the surface on the substrate side, and surface on the substrate side and the opposite side of the substrate There are light emitting devices with a double-sided emission structure that extracts light from the It is possible.

[0200] FIG. 8 shows an example of a light-emitting device using a light-emitting element as a display element. The transistor 513 is electrically connected to the transistor 4010 provided in the pixel portion 4002 . The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second electrode layer 4032, and a second electroluminescent layer 4513. The electrode layer 4031 has a laminated structure, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed as appropriate according to the direction of emitted light.

[0201] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a certain slope.

[0202] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0203] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective film may be formed on the insulating film 4031 and the partition wall 4510. The protective film may be made of silicon nitride. A silicon nitride film, a silicon oxide film, a DLC film, etc. can be formed on the first substrate 400. The space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 is filled with a filler 45. 14 is provided and sealed. In this way, it is highly airtight and degassed so as not to be exposed to the outside air. Protective films with low wear (laminating films, UV-curing resin films, etc.) and covering materials It is preferable to package (enclose) the

[0204] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide Mido, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen may be used as a filler. stomach.

[0205] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0206] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0207] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that gather on one side is displayed. The first particles or the second particles contain a dye, and they move in the absence of an electric field. The color of the first particle and the color of the second particle are different (including colorless). )

[0208] In this way, the electrophoretic display device moves materials with high dielectric constants to areas with high electric fields, so-called This is a display that utilizes the dielectrophoretic effect.

[0209] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0210] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0211] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a display method that controls the orientation of spherical particles by creating a potential difference between the electrode layers. be.

[0212] FIG. 9 shows an active matrix electronic paper as one type of semiconductor device. The electronic paper is an example of a display device that uses the twisting ball display method.

[0213] A first electrode layer 4030 connected to the transistor 4010 and a second electrode layer 4031 provided on the second substrate 4006 The second electrode layer 4031 has a black area 4615a and a white area 4615b. 4613, which includes a liquid-filled cavity 4612 therearound. The spherical particles 4613 are filled with a filler 4614 such as a resin. The second electrode layer 4031 corresponds to a common electrode (opposite electrode). are electrically connected.

[0214] 7 to 9, the first substrate 4001 and the second substrate 4006 are made of flexible For example, a light-transmitting plastic substrate can be used. As for plastics, FRP (Fiberglass-Reinforced Plastic) rced Plastics) plate, PVF (Polyvinyl Fluoride) film, Polyethylene A steril film or an acrylic resin film can be used. It is also possible to use a sheet with a structure in which foil is sandwiched between PVF film or polyester film. Cut.

[0215] The insulating layer 4020 functions as a protective film for the transistor.

[0216] The protective film prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is made of silicon oxide by sputtering. silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film , a single layer of an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film; Alternatively, it may be formed by lamination.

[0217] The insulating layer 4021 functioning as a planarizing insulating film is formed of a material selected from the group consisting of acrylic, polyimide, and benzosilane. Heat-resistant organic materials such as clobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low-k materials, siloxane resins, and PS G (phosphorus glass), BPSG (boron phosphorus glass), etc. can be used. The insulating layer may be formed by stacking a plurality of insulating films made of these materials.

[0218] The method for forming the insulating layers 4020 and 4021 is not particularly limited. ttach method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (ink jet (printing, screen printing, offset printing, etc.), doctor knife, roll coater, A machine such as a stencil coater or a knife coater can be used.

[0219] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating film, and conductive film provided in the part are resistant to light in the visible light wavelength range. It shall be translucent.

[0220] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting diode (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0221] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide with silicon oxide added, etc. A conductive material that can be used can be used.

[0222] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0223] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or or a copolymer of two or more of aniline, pyrrole and thiophene or a derivative thereof Examples include the body.

[0224] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0225] As described above, by using the transistors described in any of Embodiments 1 to 4, various functions can be realized. It is possible to provide a display device having the above structure.

[0226] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0227] (Sixth embodiment) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples include:

[0228] 10A and 10B show a flexible semiconductor device formed by applying the above-described embodiment. This is an example of applying this to an electronic book. Figure 10(A) shows the electronic book in an open state. 10(B) shows the electronic book in a closed state. The flexible display panel 4312 and the third display panel 4313 are formed by applying the above embodiment. A semiconductor device having the above structure can be used.

[0229] The first housing 4305 has a first display panel 4311 having a first display portion 4301. The second housing 4306 includes a second display panel having an operation unit 4304 and a second display unit 4307. The third display panel 4313 is a double-sided display panel. The third display panel 4313 has a first display panel 4302 and a fourth display panel 4310. The first housing 4305 is inserted between the first display panel 4311 and the second display panel 4312. The first display panel 4311, the third display panel 4313, the second display panel 4312, and The first and second housings 4306 are connected by a fastening part 4308 in which a drive circuit is provided. The electronic book in FIG. 10 has a first display portion 4301, a second display portion 4307, and a third display portion 4308. The display unit 4302 has four display screens, a first display unit 4303 and a second display unit 4310.

[0230] A first housing 4305, a first display panel 4311, a third display panel 4313, a second display panel 4314, a The display panel 4312 and the second housing 4306 are flexible. In addition, plastic substrates are used for the first housing 4305 and the second housing 4306, and If a thin film is used for the display panel 4313, a thin e-book can be produced. .

[0231] The third display panel 4313 has both a third display portion 4302 and a fourth display portion 4310. The third display panel 4313 is a dual-emission type display panel. Alternatively, a single-side emission type display panel may be attached to the substrate.

[0232] FIG. 11 shows a semiconductor device formed by applying the above embodiment to an indoor lighting device 3001. The semiconductor device shown in the above embodiment mode can be enlarged in area; In addition, the semiconductor device shown in the above embodiment can be used as a large-area lighting device. The device can also be used as a desk lamp 3000. In addition to standard lighting fixtures and tabletop lighting fixtures, we also offer wall-mounted lighting fixtures, interior lighting for vehicles, emergency lights, etc. Also included.

[0233] As described above, the semiconductor device described in any of Embodiments 1 to 5 can be used in various electronic devices. Therefore, a highly reliable electronic device can be provided.

Claims

[Claim 1] a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a flexible substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer; the insulating layer covers the oxide semiconductor layer and is provided in contact with the gate insulating layer; an edge of the gate insulating layer coincides with an edge of the insulating layer on the gate electrode layer in a channel width direction of the oxide semiconductor layer; the conductive layer covers a channel formation region of the oxide semiconductor layer, the gate insulating layer, and the end portion of the insulating layer, and is provided in contact with the gate electrode layer.

Images