Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor element with improved reliability, and a data storage system including the same.SOLUTION: A semiconductor device according to the present invention includes a plate layer, gate electrodes separated from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer and extending by different lengths along a second direction that is perpendicular to the first direction, interlayer insulating layers stacked alternately with the gate electrodes, a channel structure penetrating at least a part of the gate electrodes and extending along the first direction, and a contact plug connected to each of the gate electrodes and extending along the first direction. Each of the gate electrodes includes a lower region and an upper region that is disposed on the lower region so as to be exposed from the interlayer insulating layer. The upper region includes a region where the level of the upper surface is lower in the second direction. An outer side surface of the upper region in the second direction exists on the lower region apart from the external side surface of the lower region in the second direction.SELECTED DRAWING: Figure 2a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing large amounts of data are required. To this end, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved reliability.

[0004] Another object of the present invention is to provide a data storage system including a semiconductor device with improved reliability. [Means for solving the problem]

[0005] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a first semiconductor structure including a substrate, a circuit element on the substrate, and a circuit wiring line on the circuit element; and a second semiconductor structure disposed on the first semiconductor structure and having first and second regions, wherein the second semiconductor structure includes: a plate layer; gate electrodes spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer and extending at different lengths along a second direction perpendicular to the first direction, the gate electrodes each including a lower region extending from the first region and an upper region disposed on the lower region in the second region; an interlayer insulating layer alternately stacked with the gate electrodes; a channel structure penetrating at least a portion of the gate electrode in the first region and extending along the first direction; contact plugs respectively connected to the gate electrodes in the second region and extending along the first direction; and a pad insulating layer interposed between the lower region and the upper region of each of the gate electrodes and spaced from the interlayer insulating layer.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor device includes a plate layer; gate electrodes on the plate layer, spaced apart from each other along a first direction perpendicular to an upper surface of the plate layer and extending at different lengths along a second direction perpendicular to the first direction; an interlayer insulating layer stacked alternately with the gate electrodes; channel structures penetrating at least a portion of the gate electrodes and extending along the first direction; and contact plugs connected to the gate electrodes and extending along the first direction, each of the gate electrodes including a lower region and an upper region disposed on the lower region so as to be exposed from the interlayer insulating layer, the upper region including a region whose top surface is lower in the second direction, and an outer surface of the upper region in the second direction may be located on the lower region and spaced apart from an outer surface of the lower region in the second direction.

[0007] In order to achieve the above object, according to one aspect of the present invention, a data storage system includes: a semiconductor storage device including a first semiconductor structure including a circuit element; a second semiconductor structure disposed on one surface of the first semiconductor structure and having first and second regions; and input / output pads electrically connected to the circuit element; and a controller electrically connected to the semiconductor storage device via the input / output pads and controlling the semiconductor storage device, wherein the second semiconductor structure includes: a plate layer; gate electrodes spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer, the gate electrodes including a lower region extending from the first region along a second direction perpendicular to the first direction and an upper region disposed on the lower region in the second region; a channel structure penetrating at least a portion of the gate electrode in the first region and extending along the first direction; contact plugs respectively connected to the gate electrodes in the second region and extending along the first direction; and a pad insulating layer interposed between the lower region and the upper region of each of the gate electrodes. [Effects of the Invention]

[0008] According to the present invention, a gate electrode includes a pad region connected to a contact plug, and by optimizing the manufacturing method and structure of this pad region, a semiconductor device with improved reliability and a data storage system including the same can be provided.

[0009] The various yet beneficial advantages and effects of the present invention are not limited to the above-mentioned contents, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 2a] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 2b] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 3a] 1 is a schematic enlarged partial view showing an enlarged region of a semiconductor device according to an exemplary embodiment; [Figure 3b] 1 is a schematic enlarged partial view showing an enlarged region of a semiconductor device according to an exemplary embodiment; [Figure 4a] 1 is a schematic enlarged partial view of a semiconductor device according to an exemplary embodiment; [Figure 4b] 1 is a schematic enlarged partial view of a semiconductor device according to an exemplary embodiment; [Figure 4c] 1 is a schematic enlarged partial view of a semiconductor device according to an exemplary embodiment; [Figure 5] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 8a] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8c] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8d] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8e] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8f] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8g] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8h] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8i] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8j] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8k] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8l] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 8m] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 9] 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10] 1 is a diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment; [Figure 11] 1 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment. [Figure 12] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0013] 2a and 2b are schematic cross-sectional views of a semiconductor device according to an exemplary embodiment, taken along the lines II' and II-II' in FIG.

[0014] 3a and 3b are schematic enlarged partial views showing enlarged regions of a semiconductor device according to an example embodiment, where Fig. 3a shows an enlarged view of region "A" in Fig. 2a, and Fig. 3b shows an enlarged view of region "B" in Fig. 2b.

[0015] 1 to 3b, the semiconductor device 100 includes a peripheral circuit region PERI, which is a first semiconductor structure including a substrate 201, and a memory cell region CELL, which is a second semiconductor structure including a plate layer 101. The memory cell region CELL is disposed above the peripheral circuit region PERI. In an exemplary embodiment, the memory cell region CELL may be disposed below the peripheral circuit region PERI, conversely.

[0016] The peripheral circuit region PERI includes a substrate 201 , an impurity region 205 and an isolation layer 210 in the substrate 201 , a circuit element 220 disposed on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit wiring line 280 .

[0017] The substrate 201 has an upper surface extending in the X and Y directions. An active region is defined in the substrate 201 by an isolation layer 210. An impurity region 205 containing impurities is disposed in a portion of the active region. The substrate 201 includes a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 is provided as a bulk wafer or an epitaxial layer.

[0018] The circuit elements 220 include planar transistors. Each circuit element 220 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, impurity regions 205 are disposed in the substrate 201 as source / drain regions.

[0019] The peripheral region insulating layer 290 is disposed on the substrate 201 and on the circuit element 220. The peripheral region insulating layer 290 includes multiple insulating layers formed in different process steps. The peripheral region insulating layer 290 is made of an insulating material.

[0020] The circuit contact plugs 270 and the circuit wiring lines 280 form circuit wiring structures electrically connected to the circuit elements 220 and the impurity regions 205. The circuit contact plugs 270 have a cylindrical shape, and the circuit wiring lines 280 have a line shape. Electrical signals are applied to the circuit elements 220 through the circuit contact plugs 270 and the circuit wiring lines 280. In an area not shown, the circuit contact plugs 270 are also connected to the circuit gate electrodes 225. The circuit wiring lines 280 are connected to the circuit contact plugs 270 and are arranged in multiple layers. The circuit contact plugs 270 and the circuit wiring lines 280 include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each may further include a diffusion barrier layer. In exemplary embodiments, the number of layers of the circuit contact plugs 270 and the circuit wiring lines 280 may vary.

[0021] The memory cell region CELL has first and second regions R1 and R2, and includes a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 120 stacked alternately with the gate electrode 130, a channel structure CH arranged to penetrate the stacked structure of the gate electrode 130 in the first region R1, first and second isolation regions MS1, MS2a, MS2b extending through the gate electrode 130, an upper isolation region US passing through a portion of the gate electrode 130 arranged at the top, a pad insulating layer 122 interposed within the gate electrode 130, and a contact plug 170 connected to the gate electrode 130 and extending vertically in the second region R2. The memory cell region CELL further includes a horizontal insulating layer 110 arranged under the gate electrode 130 in the second region R2, a substrate insulating layer 121 arranged to penetrate the plate layer 101, a support structure DCH arranged to penetrate the stacked structure of the gate electrode 130 in the second region R2, a contact insulating layer 160 around the contact plug 170, a stud 180 on the channel structure CH and the contact plug 170, a cell wiring line 185 on the stud 180, and a cell region insulating layer 190 covering the gate electrode 130.

[0022] In the memory cell region CELL, the first region R1 is a region where the gate electrodes 130 are vertically stacked and the channel structure CH is disposed, and is the region where the memory cells are disposed. The second region R2 is a region where the gate electrodes 130 extend with different lengths, and corresponds to a region for electrically connecting the memory cells to the peripheral circuit region PERI. The second region R2 is disposed at least at one end of the first region R1 in at least one direction, for example, the X direction.

[0023] The source structure SS includes a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104, which are stacked in sequence in the first region R1. However, in the exemplary embodiment, the number of conductive layers constituting the source structure SS may be variously changed.

[0024] The plate layer 101 has a plate shape and functions as at least a part of a common source line of the semiconductor device 100. The plate layer 101 has an upper surface extending in the X direction and the Y direction. The plate layer 101 includes a conductive material. For example, the plate layer 101 includes a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor includes silicon, germanium, or silicon-germanium. The plate layer 101 further includes an impurity. The plate layer 101 is provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0025] The first and second horizontal conductive layers 102 and 104 are sequentially stacked on the top surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 does not extend to the second region R2, while the second horizontal conductive layer 104 extends to the second region R2. The first horizontal conductive layer 102 functions as part of the common source line of the semiconductor device 100, for example, functions as the common source line together with the plate layer 101. As shown in FIG. 3b, the first horizontal conductive layer 102 is directly connected to the channel layer 140 around the channel layer 140. The second horizontal conductive layer 104 contacts the plate layer 101 in a portion of the second region R2 where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The first and second horizontal conductive layers 102 and 104 include a semiconductor material, for example, polycrystalline silicon.

[0026] The horizontal insulating layer 110 is disposed on the plate layer 101 at the same level as the first horizontal conductive layer 102 in at least a portion of the second region R2. The horizontal insulating layer 110 includes first and second horizontal insulating layers 111, 112 alternately stacked on the second region R2 of the plate layer 101. The horizontal insulating layer 110 is a layer that remains after a portion of it is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100.

[0027] The horizontal insulating layer 110 includes silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 include different insulating materials. For example, the first horizontal insulating layer 111 is made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of a different material from the interlayer insulating layer 120.

[0028] The substrate insulating layer 121 is disposed in part of the second region R2 so as to penetrate the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The substrate insulating layer 121 is further disposed in the first region R1, for example, in a region where a through via extending from the memory cell region CELL to the peripheral circuit region PERI is disposed. The upper surface of the substrate insulating layer 121 is coplanar with the upper surface of the second horizontal conductive layer 104, but is not limited to this. The substrate insulating layer 121 includes an insulating material, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0029] The gate electrode 130 is stacked vertically on the plate layer 101 and spaced apart from one another to form a stacked structure together with the interlayer insulating layer 120. The stacked structure includes vertically stacked lower and upper stacked structures. However, depending on the embodiment, the stacked structure may be a single stacked structure.

[0030] The gate electrodes 130 include a lower gate electrode 130L forming the gate of a ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and an upper gate electrode 130U forming the gate of a string selection transistor. The number (number of layers) of memory gate electrodes 130M forming memory cells is determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the upper and lower gate electrodes 130U and 130L may each have one to four or more layers and have the same or different structure as the memory gate electrode 130M. In an exemplary embodiment, the gate electrodes 130 further include a gate electrode 130 forming an erase transistor used for an erase operation utilizing the gate induced drain leakage (GIDL) phenomenon, disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L. In addition, some of the gate electrodes 130, for example, the memory gate electrode 130M adjacent to the upper or lower gate electrode 130U or 130L, may be dummy gate electrodes.

[0031] 1, the gate electrodes 130 are arranged so as to be separated from each other in the Y direction by a first isolation region MS1 ​​that extends continuously into the first region R1 and the second region R2. The gate electrodes 130 between a pair of first isolation regions MS1 form one memory block, but the scope of the memory block is not limited to this. Some of the gate electrodes 130, for example, memory gate electrodes 130M, each form one layer within one memory block.

[0032] The gate electrodes 130 are stacked vertically on the first region R1 and the second region R2, spaced apart from each other, and extend from the first region R1 to the second region R2 at different lengths, forming a stepped structure in part of the second region R2. The gate electrodes 130 may also be arranged to have a stepped structure in the Y direction. Due to this stepped structure, the lower gate electrodes 130 extend longer than the upper gate electrodes 130, and each gate electrode 130 has a region where its upper surface is exposed from the interlayer insulating layer 120 and the other gate electrodes 130. This region is called a pad region 130P. In each gate electrode 130, the pad region 130P is a region including an end of the gate electrode 130 along the X direction. The gate electrodes 130 are respectively connected to contact plugs 170 in the pad region 130P. The gate electrodes 130 include a region with increased thickness in the pad region 130P.

[0033] 3a, the gate electrode 130 includes a lower region 130_1 extending from the first region R1, and an upper region 130_2 arranged on the lower region 130_1 in the pad region 130P. The pad region 130P includes first to third pad regions 130P1, 130P2, and 130P3 arranged sequentially from the first region R1. The upper region 130_2 is arranged in the second pad region 130P2, and in the first pad region 130P1 and the third pad region 130P3, the top surface of the lower region 130_1 is exposed from the upper region 130_2.

[0034] The lower region 130_1 extends with a first thickness T1 throughout the entire first region R1 and a portion of the second region R2. The lower region 130_1 has the first thickness T1 at least in the region where the upper surface is covered with the interlayer insulating layer 120. In the first pad region 130P1, the lower region 130_1 has a second thickness T2 that is smaller than the first thickness T1. The first pad region 130P1 is a region between the side surface of the interlayer insulating layer 120 and the upper region 130_2. In the third pad region 130P3, the lower region 130_1 has a third thickness T3 that is smaller than the first thickness T1. The third thickness T3 is smaller than or equal to the second thickness T2.

[0035] The upper region 130_2 is disposed on the lower region 130_1 and the pad insulating layer 122 in the second pad region 130P2. The upper region 130_2 has a first side surface 130_2S1 and a second side surface 130_2S2 facing each other in the X direction. The first side surface 130_2S1 is referred to as an inner side surface, and the second side surface 130_2S2 is referred to as an outer side surface.

[0036] The upper region 130_2 includes first to third portions located sequentially from the first side surface 130_2S1. ​​The first portion is adjacent to the first pad region 130P1 and has an uppermost surface located at a first level. The first portion includes a region vertically overlapping the pad insulating layer 122. The second portion includes a bent region or a stepped region so that the overall thickness of the gate electrode 130 is reduced. The third portion has an upper surface located at a second level lower than the first level. The first portion is an end region including the first side surface 130_2S1, and the third portion is an end region including the second side surface 130_2S2. The second portion is a region where the upper surface drops from the first level to the second level. The degree of roundness and inclination of the bent region in the second portion may be varied in various embodiments. The first level is higher than the level of the lower surface of the gate electrode 130 directly above it. The first level is a level between the lower surface and the upper surface of the upper gate electrode 130. The first level may be, but is not limited to, higher than the level of the upper surface of the third pad region 130P3 of the upper gate electrode 130. However, in some embodiments, the first level may be the same as or lower than the level of the lower surface of the upper gate electrode 130.

[0037] The gate electrode 130 has a fourth thickness T4, which is the maximum thickness in the first portion. The fourth thickness T4 is a thickness including the pad insulating layer 122 inserted therein. The gate electrode 130 has a fifth thickness T5, which is smaller than the fourth thickness T4, in the third portion. The difference between the first level and the second level, i.e., the difference between the fourth thickness T4 and the fifth thickness T5, is in the range of about 3 nm to about 7 nm. The difference is greater than, but not limited to, the sum of the difference between the first thickness T1 and the second thickness T2 and the thickness of the pad insulating layer 122. When the third thickness T3 is smaller than the second thickness T2, the gate electrode 130 has a minimum thickness in the outer end region of the lower region 130_1 adjacent to the second side surface 130_2S2 of the upper region 130_2. When the second thickness T2 and the third thickness T3 are the same, the gate electrode 130 has a minimum thickness in each of the lower region 130_1 adjacent to the first side surface 130_2S1 and the second side surface 130_2S2.

[0038] The first side surface 130_2S1 is spaced apart from the upper interlayer insulating layer 120 by a first length L1. The first length L1 is the length of the first pad region 130P1. The first length L1 is, for example, in the range of about 10 nm to about 50 nm. The second side surface 130_2S2 is located on the lower region 130_1 and spaced apart from the outer side surface of the lower region 130_1 inward toward the first region R1. A portion of the upper surface of the lower region 130_1 is exposed outside the second side surface 130_2S2, and a step structure is formed between the second side surface 130_2S2 and a portion of the middle side surface of the lower region 130_1 extending therefrom and the upper surface of the lower region 130_1. Unless otherwise specified, in this specification, "inner side" means a side toward the first region R1, and "outer side" means a side away from the first region R1, and "inner side" and "outer side" are interpreted similarly.

[0039] The gate electrode 130 includes a metal material, such as tungsten (W). Depending on the embodiment, the gate electrode 130 includes a polycrystalline silicon or a metal silicide material. In an exemplary embodiment, the gate electrode 130 further includes a diffusion barrier, for example, the diffusion barrier includes tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0040] The pad insulating layer 122 is interposed within the gate electrode 130 in the pad region 130P. As shown in FIG. 3a, the pad insulating layer 122 is disposed between the lower region 130_1 and the upper region 130_2 in the second pad region 130P2. The pad insulating layer 122 is a remaining portion of the interlayer insulating layer 120 within the gate electrode 130 due to a manufacturing process for stably isolating adjacent pad regions 130P. This will be described in more detail below with reference to FIGS. 8b to 8l.

[0041] The pad insulating layer 122 is disposed in a first end region of the upper region 130_2, and at least one side surface is exposed through a first side surface 130_2S1. ​​The side surface of the pad insulating layer 122 along the X direction exposed through the first side surface 130_2S1 is coplanar with the first side surface 130_2S1. ​​The upper surface, lower surface, and at least one side surface of the pad insulating layer 122 are covered with the gate electrode 130.

[0042] The lower surface of the pad insulating layer 122 is located at substantially the same level as the lower surface of the adjacent interlayer insulating layer 120 in the X direction. The thickness of the pad insulating layer 122 is thinner than the thickness of the interlayer insulating layer 120. The second length L2 of the pad insulating layer 122 is shorter than the first length L1 of the first pad region 130P1, but is not limited to this. The pad insulating layer 122 includes an insulating material, and includes the same material as the interlayer insulating layer 120.

[0043] The interlayer insulating layer 120 is disposed between the gate electrodes 130 and forms a stacked structure with the gate electrodes 130. Like the gate electrodes 130, the interlayer insulating layers 120 are also disposed spaced apart from each other in a direction perpendicular to the top surface of the plate layer 101 and extending in the X direction. In the stacked structure, a relatively thick upper interlayer insulating layer 125 is disposed on the top of the lower and upper stacked structures. However, the thickness and shape of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may vary depending on the embodiment. The interlayer insulating layer 120 and the upper interlayer insulating layer 125 include an insulating material such as silicon oxide or silicon nitride.

[0044] The channel structures CH each form one memory cell string and are arranged spaced apart from each other in rows and columns on the plate layer 101 in the first region R1. The channel structures CH are arranged to form a checkerboard pattern in the XY plane or are arranged in a staggered pattern in one direction. The channel structures CH have a columnar shape and have inclined side surfaces that become narrower as they approach the plate layer 101 depending on the aspect ratio. Depending on the embodiment, at least a portion of the channel structures CH arranged at the end of the first region R1 may be a dummy channel.

[0045] The channel structure CH includes first and second channel structures CH1 and CH2 stacked vertically. The channel structure CH has a shape in which the lower first channel structure CH1 and the upper second channel structure CH2 are connected to each other, and has a bent portion due to the difference in width in the connection region. However, the number of channel structures stacked along the Z direction may vary depending on the embodiment.

[0046] Each of the channel structures CH includes a channel layer 140 disposed in a channel hole, a gate dielectric layer 145, a channel buried insulating layer 147, and a channel pad 149. As shown in the enlarged view of FIG. 3b, the channel layer 140 may be formed in an annular shape surrounding the internal channel buried insulating layer 147, or may have a columnar or rectangular columnar shape without the channel buried insulating layer 147, depending on the embodiment. The channel layer 140 is connected to the first horizontal conductive layer 102 at its bottom. The channel layer 140 includes a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0047] The gate dielectric layer 145 is disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 includes a tunneling layer, a charge storage layer, and a blocking layer stacked in sequence from the channel layer 140. The tunneling layer allows charges to tunnel into the charge storage layer and includes, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The charge storage layer is a charge trap layer or a floating gate conductive layer. The blocking layer includes silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In an exemplary embodiment, at least a portion of the gate dielectric layer 145 extends horizontally along the gate electrode 130.

[0048] The channel pad 149 is disposed only on the top end of the upper second channel structure CH2. The channel pad 149 includes, for example, doped polycrystalline silicon. Between the first channel structure CH1 and the second channel structure CH2, the channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 147 are connected to each other.

[0049] The support structures DCH are arranged spaced apart from one another in rows and columns on the plate layer 101 in the second region R2. As shown in FIG. 1, the support structures DCH are arranged to surround each contact plug 170 from four directions. However, in various embodiments, the arrangement of the support structures DCH may be varied. The support structures DCH have a columnar shape and have inclined side surfaces that become narrower as they approach the plate layer 101 according to the aspect ratio.

[0050] The support structure DCH has a circular, elliptical, or similar shape in the XY plane. The diameter or maximum width of the support structure DCH may be larger than that of the channel structure CH, but is not limited thereto. The support structure DCH may have the same or different internal structure as the channel structure CH. For example, the support structure DCH may not include a conductive layer and may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0051] The first and second isolation regions MS1, MS2a, and MS2b are arranged to extend along the X direction through the gate electrode 130. The first and second isolation regions MS1, MS2a, and MS2b are arranged parallel to each other. The first and second isolation regions MS1, MS2a, and MS2b penetrate the entire gate electrode 130 stacked on the plate layer 101, and further penetrate the underlying first and second horizontal conductive layers 102 and 104 and horizontal insulating layer 110 to be connected to the plate layer 101. The first isolation region MS1 ​​extends continuously and integrally along the X direction, while the second isolation regions MS2a and MS2b extend intermittently between a pair of first isolation regions MS1 or are arranged only in some regions. For example, the second central isolation region MS2a extends continuously in the first region R1 and intermittently in the X direction in the second region R2. The second auxiliary isolation region MS2b is arranged only in the second region R2 and extends intermittently along the X direction. However, in the embodiment, the arrangement order, number, etc. of the first and second isolation regions MS1, MS2a, MS2b are not limited to those shown in FIG.

[0052] The first and second isolation regions MS1, MS2a, and MS2b have a shape in which the width decreases toward the plate layer 101 due to a high aspect ratio, but are not limited thereto, and may have side surfaces perpendicular to the top surface of the plate layer 101. The first and second isolation regions MS1, MS2a, and MS2b include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0053] As shown in FIG. 1 , the upper isolation region US extends in the X direction in the first region R1 between the first isolation region MS1 ​​and the second central isolation region MS2a and between the second central isolation region MS2a. The upper isolation region US is disposed in part of the second region R2 and the first region R1 so as to penetrate some of the gate electrodes 130, including the uppermost upper gate electrode 130U. As shown in FIG. 2 b, the upper isolation region US separates, for example, three gate electrodes 130 from each other in the Y direction. However, the number of gate electrode layers 130 separated by the upper isolation region US may vary depending on the embodiment. The upper isolation region US includes an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0054] The contact plug 170 is coupled to the contact region 130P of the gate electrode 130 in the second region R2. The contact plug 170 penetrates at least a portion of the cell region insulating layer 190 and is coupled to each of the contact regions 130P of the gate electrode 130 exposed at the top. The contact plug 170 penetrates the gate electrode 130 below the contact region 130P, penetrates the second horizontal conductive layer 104, the horizontal insulating layer 110, and the plate layer 101, and is coupled to a circuit wiring line 280 in the peripheral circuit region PERI. The contact plug 170 is separated from the gate electrode 130 below the contact region 130P by the contact insulating layer 160. The contact plug 170 is separated from the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121. However, in some embodiments, the contact plug 170 may be coupled to the contact region 130P without penetrating the gate electrode 130.

[0055] As shown in FIG. 3A, each of the contact plugs 170 extends horizontally in the contact region 130P. The contact plug 170 includes a vertical extension 170V extending along the Z direction and a horizontal extension 170H extending horizontally from the vertical extension 170V to contact the gate electrode 130. The horizontal extension 170H is disposed around the vertical extension 170V and is surrounded on all sides by the gate electrode 130. The horizontal extension 170H is disposed within, but not limited to, the second pad region 130P2. The length from the side of the vertical extension 170V to the end of the horizontal extension 170H is shorter than the length from the side of the vertical extension 170V to the outer surface of the contact insulating layer 160. The contact plug 170 is separated from the gate electrode 130 below the contact region 130P, i.e., the gate electrode 130 that is not electrically connected, by the contact insulating layer 160.

[0056] The contact plug 170 includes a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some embodiments, the contact plug 170 includes a barrier layer extending along the side and bottom surfaces or has an air gap therein.

[0057] The contact insulating layers 160 are disposed below the contact region 130P so as to surround each side of the contact plug 170. The contact insulating layers 160 are disposed around each of the contact plugs 170 and spaced apart from each other along the Z direction. The contact insulating layers 160 are disposed at substantially the same level as the gate electrodes 130. The contact insulating layers 160 include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] The studs 180 and the cell wiring lines 185 constitute a cell wiring structure electrically connected to the memory cells in the memory cell region CELL. The studs 180 are connected to the channel structures CH and the contact plugs 170, and electrically connect the channel structures CH and the gate electrodes 130 to the cell wiring lines 185. The studs 180 have a plug shape, and the cell wiring lines 185 have a line shape. In an exemplary embodiment, the number of plugs and wiring lines constituting the cell wiring structure may be varied. The studs 180 and the cell wiring lines 185 include metals, such as tungsten (W), copper (Cu), or aluminum (Al).

[0059] The cell region insulating layer 190 is disposed to cover the stacked structure of the gate electrode 130 and the contact plug 170. The cell region insulating layer 190 is made of an insulating material and may be made of a plurality of insulating layers.

[0060] 4a to 4c are schematic enlarged partial views of a semiconductor device according to an exemplary embodiment, each showing an area corresponding to FIG.

[0061] 4a, the semiconductor device 100a does not include the pad insulating layer 122 (see FIG. 3a). As a result, in the gate electrode 130, the entire lower surface of the upper region 130_2 contacts the upper surface of the lower region 130_1. In this case, too, the upper region 130_2 has a shape in which the upper surface is bent and lowered in level.

[0062] Referring to FIG. 4b, the semiconductor device 100b does not include the pad insulating layer 122 (see FIG. 3a), and the upper region 130_2 of the gate electrode 130 does not include the first portion described above with reference to FIG. 3a. The upper region 130_2 does not have a flat upper surface extending from the upper end of the first side surface 130_2S1. ​​The upper region 130_2 has a shape in which a bent region begins at the upper end of the first side surface 130_2S1 and the level of the upper surface decreases. Such a shape of the upper region 130_2 is formed when the first length L1b of the first pad region 130P1 is relatively large.

[0063] Referring to FIG. 4c, in the semiconductor device 100c, the pad region 130P does not include the third pad region 130P3 (see FIG. 3a), and the second side surface 130_2S2 of the upper region 130_2 has a shape that is connected to the side surface of the lower region 130_1. The top surface of the lower region 130_1 is not exposed outside the upper region 130_2. The second side surface 130_2S2 has, but is not limited to, a rounded shape. In some embodiments, the second side surface 130_2S2 extends perpendicular to the Z direction.

[0064] 5 to 7 are schematic cross-sectional views of semiconductor devices according to exemplary embodiments, each of which shows a cross section corresponding to FIG.

[0065] 5, the semiconductor device 100d differs from the embodiment of FIG. 2a in the stacking configuration of the gate electrode 130 in the second region R2. The memory cell region CELL also includes first and second cell region insulating layers 192 and 194.

[0066] The gate electrode 130 has a stepped structure in a plurality of staircase regions GP. The gate electrode 130 has a shape in which a predetermined depth is removed from the lower portion of the gate electrode 130 and the upper portion of one of the upper stack structures GS1 and GS2 in the staircase regions GP. The staircase regions GP are arranged so as not to overlap each other in the Z direction. At least a portion of the gate electrode 130 constituting the upper stack structure GS2 extends horizontally on the staircase region GP of the lower stack structure GS1. The staircase regions GP are arranged in the order of the upper stack structure GS2, the lower stack structure GS1, and the upper stack structure GS2 from the first region R1 along the X direction. However, in embodiments, the arrangement form, arrangement order, depth, etc. of the staircase regions GP may be variously changed. In some embodiments, the gate electrode 130 of the upper stack structure GS2 is not arranged on the staircase region GP of the lower stack structure GS1.

[0067] The gate electrode 130 forms first and second step structures in each step region GP that are asymmetrical along the X direction. The first step structure is a step structure that is relatively adjacent to the first region R1 and has a lower level along the X direction, while the second step structure is a step structure or sloped structure that is relatively farther away from the first region R1 and has a higher level along the X direction. For example, in each step region GP, ​​the slope of the first step structure is smaller than the slope of the second step structure in the first region R1. However, in some embodiments, the first and second step structures may be symmetrical to each other. In the first step structure, the gate electrode 130 is connected to the contact plug 170, and in the second step structure, the gate electrode 130 forms a dummy region or structure that is not connected to the contact plug 170. In the embodiment, the specific shape of the step structure, the number of gate electrode 130 layers forming each step structure, etc. are not limited to those shown in FIG. 5. In some embodiments, the gate electrodes 130 are also arranged to have a stepped structure relative to one another in the Y direction.

[0068] The first and second cell region insulating layers 192 and 194 are disposed to cover the lower and upper stack structures GS1 and GS2, respectively, and include an insulating material.

[0069] 6, the memory cell region CELL of the semiconductor device 100e further includes a string channel structure SCH connected to the channel structure CH, a horizontal insulating layer 150, and an upper contact plug 171. The memory cell region CELL also includes first and second cell region insulating layers 192 and 194.

[0070] The gate electrode 130 includes first and second upper gate electrodes 130U1 and 130U2 as upper gate electrodes. The uppermost first upper gate electrode 130U1 is disposed to have a relatively large thickness compared to the other gate electrodes 130. The string channel structure SCH is disposed to penetrate the first upper gate electrode 130U1, and the channel structure CH is disposed to penetrate the gate electrodes 130 except for the first upper gate electrode 130U1.

[0071] The string channel structures SCH are connected to the channel structures CH. The string channel structures SCH are disposed on the channel structures CH, and may be, but are not limited to, shifted horizontally from the channel structures CH. Each of the string channel structures SCH includes a string channel layer disposed in a string channel hole and has the same or similar structure as the channel structure CH. The string channel layer is connected to a connection pad 151 at its lower end and electrically connected to the channel layer 140 of the channel structure CH through the connection pad 151. The connection pad 151 includes a conductive material, for example, polycrystalline silicon.

[0072] The horizontal insulating layer 150 is disposed between the channel structure CH and the string channel structure SCH and extends horizontally. The horizontal insulating layer 150 is disposed between the first upper gate electrode 130U1 and the second upper gate electrode 130U2. The horizontal insulating layer 150 is used as an etch stop layer when forming the string channel structure SCH and is also used when forming the connection pad 151. The horizontal insulating layer 150 includes an insulating material, and includes a material different from that of the interlayer insulating layer 120 and the first cell region insulating layer 192. In this embodiment, the contact plug 170 has a bent portion whose width decreases at or below the lower surface of the horizontal insulating layer 150.

[0073] The upper contact plug 171 is connected to the first upper gate electrode 130U1. The upper contact plug 171 does not penetrate the first upper gate electrode 130U1 but is connected to an upper surface or an upper region of the first upper gate electrode 130U1.

[0074] The first and second cell region insulating layers 192 and 194 are respectively disposed above and below the horizontal insulating layer 150. The first and second cell region insulating layers 192 and 194 include an insulating material.

[0075] Referring to FIG. 7, a semiconductor device 100f includes a first semiconductor structure S1 and a second semiconductor structure S2 bonded together by wafer bonding.

[0076] The description of the peripheral circuit region PERI described above with reference to FIGS. 1 to 2b applies to the first semiconductor structure S1. However, the first semiconductor structure S1 further includes bonding structures, namely, a first bonding via 295, a first bonding metal layer 298, and a first bonding insulating layer 299. The first bonding via 295 is disposed on top of the uppermost circuit wiring line 280 and is connected to the circuit wiring line 280. At least a portion of the first bonding metal layer 298 is connected to the first bonding via 295 above the first bonding via 295. The first bonding metal layer 298 is connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298, together with the second bonding metal layer 198, provides an electrical connection path by bonding the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding metal layer 298 is not connected to the underlying circuit wiring line 280 and is disposed solely for bonding. The first bonding via 295 and the first bonding metal layer 298 include a conductive material, such as copper (Cu). A first bonding insulating layer 299 is disposed around the first bonding metal layer 298. The first bonding insulating layer 299 also functions as a diffusion barrier for the first bonding metal layer 298 and includes at least one of, for example, SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0077] 1 to 3b, the description of the memory cell region CELL described above with reference to FIGS. 1 to 3b applies to the second semiconductor structure S2 unless otherwise specified. The second semiconductor structure S2 further includes bonding structures, that is, a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199. The second semiconductor structure S2 further includes a passivation layer 106 covering the top surface of the plate layer 101, and a cover insulating layer 105 disposed between the contact plug 170 and the plate layer 101.

[0078] The second bonding via 195 and the second bonding metal layer 198 are disposed below the lowermost cell wiring line 185. The second bonding via 195 connects the cell wiring line 185 and the second bonding metal layer 198, and the second bonding metal layer 198 is bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 is bonded to and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 include a conductive material, for example, copper (Cu). The second bonding insulating layer 199 includes at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0079] The first and second semiconductor structures S1, S2 are bonded by bonding the first bonding metal layer 298 to the second bonding metal layer 198 and bonding the first bonding insulating layer 299 to the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 is, for example, copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 is, for example, dielectric-dielectric bonding such as SiCN-SiCN bonding. The first and second semiconductor structures S1, S2 are bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0080] In this embodiment, the second semiconductor structure S2 does not include the first and second horizontal conductive layers 102 and 104 (see FIG. 2a). The channel structure CH is directly connected to the plate layer 101 with the channel layer 140 exposed through the upper end. However, the electrical connection between the channel structure CH and the common source line may be varied in various embodiments, and the channel structure CH and the source structure SS may have the same structure as in the embodiment of FIG. 2a.

[0081] The passivation layer 106 is disposed on the upper surface of the plate layer 101 to protect the semiconductor device 100f. The cover insulating layer 105 is disposed between the contact plugs 170 and the plate layer 101. The cover insulating layer 105 covers the upper ends of the contact plugs 170 and extends along the lower surface of the plate layer 101. However, in the exemplary embodiment, the cover insulating layer 105 can be disposed in various ways as long as it electrically isolates the contact plugs 170 from the plate layer 101. In some embodiments, the cover insulating layer 105 is disposed around the contact plugs 170 in a similar manner to the substrate insulating layer 121. The passivation layer 106 and the cover insulating layer 105 include an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon carbide, and may be composed of multiple insulating layers depending on the embodiment.

[0082] 8a to 8m are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment, each of which shows a cross section corresponding to FIG.

[0083] FIG. 9 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0084] Referring to FIG. 8a, a circuit element 220, a circuit wiring structure, and a peripheral region insulating layer 290 are formed on a substrate 201 to form a peripheral circuit region PERI.

[0085] First, an isolation layer 210 is formed in a substrate 201, and then a circuit gate dielectric layer 222 and a circuit gate electrode 225 are sequentially formed on the substrate 201. The isolation layer 210 is formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 are formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 is formed of silicon oxide, and the circuit gate electrode 225 is formed of at least one of, but not limited to, polysilicon or a metal silicide layer. Next, a spacer layer 224 and an impurity region 205 are formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on the embodiment, the spacer layer 224 may be composed of multiple layers. The impurity region 205 is formed by an ion implantation process.

[0086] Of the circuit wiring structures, the circuit contact plugs 270 are formed by forming a portion of the peripheral region insulating layer 290, etching away a portion of the insulating layer, and filling the portion with a conductive material. The circuit wiring lines 280 are formed, for example, by depositing a conductive material and then patterning it.

[0087] The peripheral region insulating layer 290 is made up of multiple insulating layers, which become part of each step of forming the circuit wiring structure, thereby forming the peripheral circuit region PERI.

[0088] Referring to Figures 8b and 9, a plate layer 101, a horizontal insulating layer 110, a second horizontal conductive layer 104, and a substrate insulating layer 121, in which a memory cell region CELL is provided, are formed on the peripheral circuit region PERI, and sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked to form a lower mold structure, and a staircase structure of the sacrificial insulating layers 118 and interlayer insulating layers 120 is formed (S110).

[0089] The plate layer 101 is formed on the peripheral region insulating layer 290. The plate layer 101 is made of, for example, polycrystalline silicon and is formed by a CVD process. The polycrystalline silicon that forms the plate layer 101 contains impurities.

[0090] The first and second horizontal insulating layers 111 and 112 constituting the horizontal insulating layer 110 are alternately stacked on the plate layer 101. The horizontal insulating layer 110 is a layer that will be partially replaced by the first horizontal conductive layer 102 of FIG. 2b in a subsequent process. The first horizontal insulating layer 111 includes a different material from the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 is made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of the same material as the subsequent sacrificial insulating layer 118. The horizontal insulating layer 110 is partially removed in some regions, for example, the second region R2, by a patterning process.

[0091] The second horizontal conductive layer 104 is formed on the horizontal insulating layer 110 and contacts the plate layer 101 in the areas where the horizontal insulating layer 110 has been removed.

[0092] The substrate insulating layer 121 is formed to penetrate the plate layer 101 in some areas, including areas where the contact plugs 170 (see FIG. 2a) are to be disposed. The substrate insulating layer 121 is formed by removing parts of the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104, and then filling these areas with an insulating material. After filling the insulating material, a planarization process is further performed using a chemical mechanical polishing (CMP) process. As a result, the top surface of the substrate insulating layer 121 is substantially coplanar with the top surface of the second horizontal conductive layer 104.

[0093] Next, a lower mold structure is formed on the second horizontal conductive layer 104 and the substrate insulating layer 121 at a height where the first channel structure CH1 (see FIG. 2a) of the channel structure CH (see FIG. 2a) will be disposed. The lower mold structure is formed by alternately stacking sacrificial insulating layers 118 and interlayer insulating layers 120.

[0094] The sacrificial insulating layer 118 is a layer at least a portion of which will be replaced by the gate electrode 130 (see FIG. 2a) in a subsequent process. The sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120 and is formed of a material that can be etched with etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 and the upper interlayer insulating layer 125 are made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120 and the upper interlayer insulating layer 125, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the interlayer insulating layers 120 do not all need to have the same thickness. The thicknesses of the interlayer insulating layer 120 and the sacrificial insulating layer 118 and the number of layers constituting the layers may be variously changed from those shown in the drawings.

[0095] Next, the staircase structure is formed by partially removing the sacrificial insulating layer 118 and the interlayer insulating layer 120 so that the sacrificial insulating layer 118 extends to different lengths in the second region R2. The staircase structure is formed by repeatedly performing a process of forming a mask layer using a photolithography process, performing an etching process, removing a portion of the mask layer using a trim process, and then performing the etching process.

[0096] The stair structure includes unit steps STa and STb, each of which includes one or more sacrificial insulating layers 118. In each unit step STa and STb, a portion of the interlayer insulating layer 120 remains on the uppermost sacrificial insulating layer 118. The side surfaces of the unit steps STa and STb are inclined relative to the top surface of the plate layer 101. Depending on the embodiment, some of the unit steps STa and STb have different inclinations.

[0097] Referring to FIGS. 8c and 9, the sacrificial insulating layer 118 is partially removed from the exposed side surfaces (S120).

[0098] The sacrificial insulating layer 118 is partially removed from the exposed side surfaces of the unit steps STa and STb to form a removal region PB. The sacrificial insulating layer 118 is removed by a wet etching process using an etchant containing phosphoric acid, for example. The lateral depth of the removal region PB is, for example, the same as or greater than the thickness of the sacrificial insulating layer 118. In this step, the side surfaces of the sacrificial insulating layer 118 remaining after partial removal are substantially perpendicular to the top surface of the plate layer 101.

[0099] 8d and 9, in the staircase structure, the interlayer insulating layer 120 is partially removed to expose the top surface of the sacrificial insulating layer 118 (S130).

[0100] The interlayer insulating layer 120 is partially removed from the upper surface exposed on the sacrificial insulating layer 118. This exposes the upper surface of the sacrificial insulating layer 118 in the staircase structure. The interlayer insulating layer 120 is selectively removed with respect to the sacrificial insulating layer 118 using, for example, a wet etching process.

[0101] In this step, the relatively thick interlayer insulating layer 120 exposed through the removal region PB is not entirely removed, but remains partially. The sacrificial insulating layer 118 is also partially removed from its exposed upper surface. The interlayer insulating layer 120 and the sacrificial insulating layer 118, whose upper surfaces are exposed upward, form respective preliminary pad regions 118P. In the preliminary pad region 118P, a step is formed between the upper surface of the interlayer insulating layer 120 and the upper surface of the sacrificial insulating layer 118.

[0102] 4a, the structure is formed by removing the interlayer insulating layer 120 from the preliminary pad region 118P at this stage. However, in this case, the sacrificial insulating layer 118 is removed to a relatively greater thickness in the preliminary pad region 118P.

[0103] Referring to FIGS. 8e and 9, a pad sacrificial layer 200 is formed to cover the staircase structure (S140).

[0104] The pad sacrificial layer 200 is formed to cover the entire staircase structure. The pad sacrificial layer 200 includes the same material as the sacrificial insulating layer 118, but has a different etching rate than the sacrificial insulating layer 118. For example, the pad sacrificial layer 200 and the sacrificial insulating layer 118 include silicon nitride, but have different physical properties, resulting in different etching degrees under specific etching conditions.

[0105] The pad sacrificial layer 200 is plasma-treated in situ after deposition, thereby forming a plasma-treated layer on a portion of the surface of the pad sacrificial layer 200. The plasma reaches the entire structure in a straight line, so that the plasma is formed on horizontal surfaces of the pad sacrificial layer 200, not on inclined or vertical surfaces. Because the side surfaces of the sacrificial insulating layer 118 are formed vertically by the process described above with reference to FIG. 8c, the plasma-treated layer at this stage is formed to be separated from each other between the preliminary pad regions 118P, without any connected regions even if there is a step.

[0106] Referring to FIGS. 8f and 9, the pad sacrificial layer 200 is partially removed to form raised pad regions 200P separated from each other (S150).

[0107] The pad sacrificial layer 200 is removed from the inclined surface regions of the pad sacrificial layer 200 where the plasma treatment layer is not formed, for example, by a wet etching process. This forms protruding pad regions 200P separated from each other along the X direction. In this step, after the pad sacrificial layer 200 is removed in the preliminary pad regions 118P, the exposed interlayer insulating layer 120 is partially removed, and the exposed sacrificial insulating layer 118 is also reduced to a predetermined thickness, lowering the level of the upper surface of the sacrificial insulating layer 118. The interlayer insulating layer 120 remaining below the protruding pad regions 200P forms the pad insulating layer 122. The protruding pad regions 200P are formed on the sacrificial insulating layer 118 and the pad insulating layer 122 in each preliminary pad region 118P.

[0108] As described above with reference to FIG. 8e, the plasma-treated layers are separated from one another, so that the protruding pad regions 200P formed in this step are also formed with stable separation between the adjacent preliminary pad regions 118P.

[0109] In the embodiment of Fig. 4b, if the distance between the protruding pad regions 200P is relatively large at this stage, the pad insulating layer 122 does not remain, and in the embodiment of Fig. 4c, the shape of the protruding pad regions 200P is changed depending on the etching process conditions at this stage, resulting in a structure formed by this.

[0110] Referring to FIG. 8g, a first channel sacrificial layer 119L is formed through the lower stack structure.

[0111] The first channel sacrificial layer 119L is formed in the first region R1 at a position corresponding to the first channel structure CH1. The first channel sacrificial layer 119L is formed by forming a lower channel hole penetrating the lower stack structure, depositing a material constituting the first channel sacrificial layer 119L in the lower channel hole, and then performing a planarization process. The first channel sacrificial layer 119L may include, for example, polycrystalline silicon. In some embodiments, when forming the first channel sacrificial layer 119L, a vertical sacrificial layer is also formed in a region corresponding to the lower region of the contact plug 170 in FIG. 2a.

[0112] Referring to FIG. 8h, the sacrificial insulating layers 118 and the interlayer insulating layers 120 constituting the upper stack structure are alternately stacked on the lower stack structure to form the protruding pad region 200P and the second channel sacrificial layer 119U.

[0113] In this step, an upper stacked structure is formed on the lower stacked structure at a height where the second channel structure CH2 (see FIG. 2a) of the channel structure CH (see FIG. 2a) will be disposed. The upper stacked structure is also formed by similarly performing the steps shown in FIGS. 8b to 8f to form the protruding pad region 200P. In some embodiments, the step of forming the protruding pad region 200P may be performed simultaneously on the lower stacked structure and the upper stacked structure.

[0114] The second channel sacrificial layers 119U are formed in the first region R1 at positions corresponding to the second channel structures CH2. The second channel sacrificial layers 119U are formed to be connected to the first channel sacrificial layers 119L. The second channel sacrificial layers 119U are formed by depositing the same material as the first channel sacrificial layers 119L, for example, polycrystalline silicon. In some embodiments, when the second channel sacrificial layers 119U are formed, a vertical sacrificial layer is also formed in a region corresponding to the upper region of the contact plug 170 in FIG. 2a.

[0115] Referring to FIG. 8i, a channel structure CH is formed through the lower laminate structure and the upper laminate structure.

[0116] First, a cell region insulating layer 190 is formed to cover the lower and upper stacked structures.

[0117] The channel structure CH is formed by removing the first and second channel sacrificial layers 119L and 119U in the first region R1 to form a hole-shaped channel hole, and then sequentially depositing at least a portion of the gate dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 in the channel hole.

[0118] The gate dielectric layer 145 is formed to have a uniform thickness using an ALD or CVD process. In this step, the gate dielectric layer 145 is formed in whole or in part, and a portion extending perpendicular to the plate layer 101 along the channel structure CH is formed in this step. The channel layer 140 is formed on the gate dielectric layer 145 in the channel hole. The channel-filled insulating layer 147 is formed to fill the channel hole and is made of an insulating material. The channel pad 149 is made of a conductive material, for example, polycrystalline silicon.

[0119] Referring to FIG. 8j, through-holes OH are formed through the lower and upper laminate structures.

[0120] The through holes OH are formed in the second region R2 in regions corresponding to the contact plugs 170 in Fig. 2a. The through holes OH are formed to penetrate the cell region insulating layer 190, the upper interlayer insulating layer 125, the protruding pad region 200P, the sacrificial insulating layer 118, and the interlayer insulating layer 120, and to penetrate the substrate insulating layer 121 at the bottom. The circuit wiring lines 280 are exposed through the bottom surfaces of the through holes OH.

[0121] In some embodiments, when forming the first and second channel sacrificial layers 119L, 119U, if a vertical sacrificial layer is also formed in the region corresponding to the contact plug 170, the vertical sacrificial layer is removed to form the through-hole OH.

[0122] Referring to FIG. 8k, a preliminary contact insulating layer 160P and a vertical sacrificial layer 191 are formed in the through-hole OH, a first horizontal conductive layer 102 is formed, and the protruding pad region 200P and the sacrificial insulating layer 118 are removed.

[0123] First, the protruding pad region 200P and the sacrificial insulating layer 118 exposed through the through-hole OH are partially removed. A predetermined length of the protruding pad region 200P and the sacrificial insulating layer 118 is removed around the through-hole OH to form a tunnel portion. The tunnel portion is formed to have a relatively short length in the preliminary pad region 118P and a relatively long length in the sacrificial insulating layer 118.

[0124] Specifically, initially, the tunnel portion is formed relatively long in the preliminary pad region 118P, contrary to the above. This is because the protruding pad region 200P includes a region having a relatively faster etching rate than the underlying sacrificial insulating layer 118. Next, a separate sacrificial layer is formed in the through hole OH and the tunnel portion. The sacrificial layer is made of a material having a slower etching rate than the sacrificial insulating layer 118. Next, the sacrificial layer and a portion of the sacrificial insulating layer 118 are removed. At this time, the sacrificial layer remains in the preliminary pad region 118P, and after the sacrificial layer is removed, a portion of the sacrificial insulating layer 118 is further removed from the lower portion. As a result, the tunnel portion is finally formed relatively short in the preliminary pad region 118P.

[0125] An insulating material is deposited in the through-holes OH and the tunnel portions to form preliminary contact insulating layers 160P. The preliminary contact insulating layers 160P are formed on the sidewalls of the through-holes OH and fill the tunnel portions. In the preliminary pad region 118P, the through-holes OH do not need to completely fill the tunnel portions.

[0126] The vertical sacrificial layer 191 fills the through holes OH and the tunnel portion of the preliminary pad region 118P. The vertical sacrificial layer 191 includes a material different from that of the preliminary contact insulating layer 160P, for example, polycrystalline silicon.

[0127] Next, openings are formed at the positions of the first and second isolation regions MS1, MS2a, and MS2b (see FIG. 1), penetrating the protruding pad region 200P, the sacrificial insulating layer 118, and the interlayer insulating layer 120 to the plate layer 101. Next, a separate sacrificial spacer layer is formed in the openings, and an etch-back process is performed to selectively remove the horizontal insulating layer 110 in the first region R1, along with a portion of the exposed gate dielectric layer 145. A conductive material is deposited in the region where the horizontal insulating layer 110 has been removed to form a first horizontal conductive layer 102, and the sacrificial spacer layer is then removed in the openings. Through this process, the first horizontal conductive layer 102 is formed in the first region R1.

[0128] The protruding pad region 200P and the sacrificial insulating layer 118 are then removed selectively to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the preliminary contact insulating layer 160P using, for example, a wet etch.

[0129] Referring to FIG. 8l, the gate electrode 130 is formed.

[0130] The gate electrode 130 is formed by depositing a conductive material in the area where the protruding pad region 200P and the sacrificial insulating layer 118 have been removed. The conductive material may include metal, polycrystalline silicon, or a metal silicide material. In some embodiments, a portion of the gate dielectric layer 145 is formed before forming the gate electrode 130. The gate electrode 130 has a shape corresponding to the protruding pad region 200P and the sacrificial insulating layer 118, and a pad insulating layer 122 is interposed therein. The lower region 130_1 and upper region 130_2 of the gate electrode 130 described above with reference to FIG. 3a, etc., are distinguished based on thickness for convenience of description. Therefore, the upper region 130_2 corresponds to a portion of the upper portion of the protruding pad region 200P. Therefore, the lower surface of the upper region 130_2 does not coincide with the lower surface of the protruding pad region 200P.

[0131] After forming the gate electrode 130, an insulating material is deposited in the openings formed in the regions of the first and second isolation regions MS1, MS2a, and MS2b (see FIG. 1) to form the first and second isolation regions MS1, MS2a, and MS2b.

[0132] Referring to FIG. 8m, the vertical sacrificial layer 191 in the through-hole OH is removed to form the contact plug 170.

[0133] The vertical sacrificial layer 191 is selectively removed with respect to the interlayer insulating layer 120 and the gate electrode 130. After the vertical sacrificial layer 191 is removed, the exposed preliminary contact insulating layer 160P is also partially removed. At this time, in the pad region 130P, the preliminary contact insulating layer 160P is completely removed, and the portion underneath remains to form the contact insulating layer 160. In the pad region 130P, if the gate dielectric layer 145 is exposed after the preliminary contact insulating layer 160P is removed, the gate dielectric layer 145 is also removed to expose the side surfaces of the gate electrode 130.

[0134] The contact plug 170 is formed by depositing a conductive material in the through hole OH. The contact plug 170 is formed to have a horizontal extension 170H (see FIG. 3a) that extends horizontally in the pad region 130P, thereby being physically and electrically connected to the gate electrode 130.

[0135] Next, referring to FIG. 2a, the semiconductor device 100 is manufactured by forming the contact plug 170, the stud 180 connected to the upper end of the channel structure CH, and the cell wiring line 185.

[0136] FIG. 10 is a diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment.

[0137] 10 , a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0138] The semiconductor device 1100 is a nonvolatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1 to 7. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0139] In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on the embodiment.

[0140] In an exemplary embodiment, the upper transistors UT1 and UT2 comprise string select transistors, and the lower transistors LT1 and LT2 comprise ground select transistors. The lower gate lines LL1 and LL2 are the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 are the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0141] In an exemplary embodiment, the lower transistors LT1 and LT2 include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used in an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0142] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 are electrically connected to the decoder circuit 1110 via a first connecting line 1115 extending from within the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via a second connecting line 1125 extending from within the first structure 1100F to the second structure 1100S.

[0143] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0144] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0145] The processor 1210 controls the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a controller interface 1221 that processes communication with the semiconductor device 1100. The controller interface 1221 transmits control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, and the like. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0146] FIG. 11 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment.

[0147] 11, a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001.

[0148] The main board 2001 includes a connector 2006 including a plurality of pins for coupling with an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In an exemplary embodiment, the data storage system 2000 communicates with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the data storage system 2000 operates using power supplied from the external host via the connector 2006. The data storage system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0149] The controller 2002 writes data to or reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0150] The DRAM 2004 is a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for the semiconductor package 2003. When the DRAM 2004 is included in the data storage system 2000, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003.

[0151] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b are each a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0152] The package substrate 2100 is a printed circuit board that includes package top pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. The input / output pads 2210 correspond to the input / output pads 1101 in FIG. 10. Each semiconductor chip 2200 includes a gate stack 3210 and a channel structure 3220. Each semiconductor chip 2200 includes the semiconductor device described above with reference to FIGS. 1 to 7.

[0153] In the exemplary embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. Depending on the embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 using a bonding wire method.

[0154] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0155] 12 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. FIG. 12 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 11, and conceptually illustrates a region obtained by cutting the semiconductor package 2003 of FIG. 11 along cutting line III-III′.

[0156] 12, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, package upper pads 2130 (see FIG. 11) disposed on the upper surface of the package substrate body 2120, lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The lower pads 2125 are connected to a wiring pattern 2005 of a main board 2001 of a data storage system 2000 via a conductive connector 2800, as shown in FIG.

[0157] Each of the semiconductor chips 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a contact plug 3235 electrically connected to a word line WL (see FIG. 10) of the gate stack structure 3210. As described above with reference to FIGS. 1 to 7, in each of the semiconductor chips 2200, the gate electrode 130 has a step structure in which the pad insulating layer 122 is interposed therein in the pad region 130P and the upper surface of the pad region 130P is lowered in level.

[0158] Each of the semiconductor chips 2200 includes a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 is disposed outside the gate stack structure 3210 and is further disposed to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 further includes an input / output pad 2210 (see FIG. 11 ) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0159] The present invention is not limited to the above-described embodiments and drawings. Therefore, various substitutions, modifications, and alterations and combinations of embodiments may be made by a person skilled in the art without departing from the technical spirit of the present invention, and these also fall within the scope of the present invention. [Explanation of symbols]

[0160] 100: Semiconductor device 101: Plate layer 102, 104: horizontal conductive layers 110: Horizontal insulating layer 118: Sacrificial insulating layer 120: Interlayer insulating layer 121: Substrate insulating layer 122: Pad insulation layer 125: Upper interlayer insulating layer 130: Gate electrode 140: Channel layer 145: Gate dielectric layer 147: Channel buried insulating layer 149: Channel Pad 160: Contact insulating layer 170: Contact plug 180:Stud 185: Cell wiring line 190: Cell area insulating layer 201: Substrate 205: Impurity region 210: Element isolation layer 220: Circuit element 222: Circuit gate dielectric layer 224: Spacer layer 225: Circuit gate electrode 270: Circuit contact plug 280: Circuit wiring line 290: Peripheral region insulating layer 1000: Data storage system 1100: Semiconductor device 1101: Input / Output Pad 1200: Controller

Claims

1. a first semiconductor structure including a substrate, a circuit element on the substrate, and a circuit wiring line on the circuit element; a second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure having first and second regions; The second semiconductor structure is a plate layer; gate electrodes on the plate layer, spaced apart from each other along a first direction perpendicular to an upper surface of the plate layer, and extending with different lengths along a second direction perpendicular to the first direction, the gate electrodes including a lower region extending from the first region and an upper region disposed on the lower region in the second region; an interlayer insulating layer alternately stacked with the gate electrode; a channel structure that penetrates at least a portion of the gate electrode in the first region and extends along the first direction; contact plugs connected to the gate electrodes in the second region and extending in the first direction; a pad insulating layer interposed between the lower region and the upper region of each of the gate electrodes and spaced apart from the interlayer insulating layer.

2. 2. The semiconductor device according to claim 1, wherein the upper surface of the upper region includes a bent region such that the overall thickness of each of the gate electrodes is reduced.

3. 2. The semiconductor device according to claim 1, wherein the upper region has an upper surface located at a first level in a first end region adjacent to the first region, and an upper surface located at a second level lower than the first level in a second end region opposite the first end region along the second direction.

4. 4. The semiconductor device according to claim 3, wherein the difference between the first level and the second level is in the range of 3 nm to 7 nm.

5. The semiconductor device of claim 1 , wherein the upper region is located above the lower region and spaced inward from a side surface of the lower region along the second direction toward the first region.

6. 2. The semiconductor device according to claim 1, wherein the lower region has a first thickness in a region covered by the interlayer insulating layer that contacts the lower region, and a second thickness smaller than the first thickness in a region between a side of the interlayer insulating layer and the upper region.

7. the gate electrode includes a first gate electrode and a second gate electrode disposed on the first gate electrode; 2. The semiconductor device according to claim 1, wherein a third level of the uppermost surface of the upper region of the first gate electrode is higher than a fourth level of the lower surface of the second gate electrode.

8. 8. The semiconductor device according to claim 7, wherein the third level is a level between an upper surface and the lower surface of the second gate electrode.

9. 2. The semiconductor device according to claim 1, wherein each of the gate electrodes has a maximum thickness at an inner end region adjacent to the first region in the upper region and a minimum thickness at an outer end region farthest from the first region in the lower region.

10. 2. The semiconductor device according to claim 1, wherein at least a side surface of the pad insulating layer along the second direction is exposed from each of the gate electrodes.

11. 11. The semiconductor device according to claim 10, wherein the side surface of the pad insulating layer is coplanar with the side surface of the upper region.

12. 2. The semiconductor device according to claim 1, wherein the thickness of the pad insulating layer is smaller than the thickness of each of the interlayer insulating layers.

13. 2. The semiconductor device of claim 1, wherein each of the contact plugs includes a vertical extension extending along the first direction and a horizontal extension extending horizontally from the vertical extension to contact the upper region and the lower region of one of the gate electrodes.

14. a plate layer; gate electrodes spaced apart from each other on the plate layer along a first direction perpendicular to an upper surface of the plate layer and extending with different lengths along a second direction perpendicular to the first direction; an interlayer insulating layer alternately stacked with the gate electrode; a channel structure extending along the first direction and penetrating at least a portion of the gate electrode; contact plugs connected to the gate electrodes and extending in the first direction, each of the gate electrodes includes a lower region and an upper region disposed on the lower region so as to be exposed from the interlayer insulating layer; the upper region includes a region where the level of an upper surface is lower in the second direction, a second surface of the upper region in the second direction, the second surface being spaced apart from the second surface of the lower region and positioned above the lower region;

15. the upper region includes first to third portions sequentially positioned along the second direction, 15. The semiconductor device of claim 14, wherein in the first portion, the upper surface of the upper region is located at a first level, in the second portion, the level of the upper surface is changed, and in the third portion, the upper surface is located at a second level lower than the first level.

16. 15. The semiconductor device of claim 14, wherein each of the gate electrodes has a minimum thickness in the lower region adjacent to at least one side of the upper region along the second direction.

17. 15. The semiconductor device according to claim 14, further comprising a pad insulating layer interposed between the lower region and the upper region of each of the gate electrodes.

18. 18. The semiconductor device according to claim 17, wherein each of the gate electrodes has a maximum thickness in a region where the gate electrodes overlap the pad insulating layer along the first direction.

19. a semiconductor storage device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure and having first and second regions, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor storage device via the input / output pads and configured to control the semiconductor storage device; The second semiconductor structure is a plate layer; gate electrodes each including a lower region on the plate layer, the lower region being spaced apart from the other along a first direction perpendicular to an upper surface of the plate layer, the lower region extending from the first region along a second direction perpendicular to the first direction, and an upper region disposed on the lower region in the second region; a channel structure that penetrates at least a portion of the gate electrode in the first region and extends along the first direction; contact plugs connected to the gate electrodes in the second region and extending in the first direction; a pad insulating layer interposed between the lower and upper regions of each of the gate electrodes.

20. 20. The data storage system of claim 19, wherein each of the gate electrodes covers an upper surface, a lower surface, and one side surface of the pad insulating layer.

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