Method for adjusting schottky barrier height in silicon carbide power diodes and power diode

Abstract

To provide a junction barrier Schottky (JBS) diode that has high efficiency in forward bias without the drawback of high losses in the reverse mode or reverse bias.SOLUTION: A silicon carbide power diode 100 includes a surface and a body 101 of semiconductor material having N-type conductivity, a switching region 102 of P-type conductivity originating at the surface and extending into the body, a surface portion 104 of P-type conductivity extending to the surface between the switching regions 102, an ohmic contact 129 in the switching region 102, and a first metal layer 110 above the surface and in direct electrical contact with the surface portion 104 and the ohmic contact.SELECTED DRAWING: Figure 2F

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to Italian Patent Application No. 102024000003835, filed February 22, 2024, entitled "METODO PER LA REGOLAZIONE DELL'ALTEZZA DELLA BARRIERA SCHOTTKY IN UN DIODO DI POTENZA IN CARBURO DI SILICIO, E DIODO DI POTENZA," which is incorporated herein by reference to the fullest extent permitted by law.

[0002] FIELD OF THE INVENTION The present disclosure relates to electronic devices and manufacturing processes for electronic devices, and more particularly to a method for adjusting the Schottky barrier height in a silicon carbide power diode and the power diode. [Background technology]

[0003] Electronic devices called JBS (Junction Barrier Schottky) or MPS (Merged PiN Schottky) diodes are known. Such devices are typically fabricated in a silicon carbide (SiC) substrate and include implanted zones with conductivity opposite to that of the substrate (e.g., P-type for an N-type substrate). In these devices, two types of separate contacts exist: an ohmic contact in the implanted zone and a Schottky contact in the area contained between the implanted zones.

[0004] These characteristics make JBS diodes particularly suitable for operation in high voltage power devices.

[0005] Nowadays, minimizing conduction losses in discrete power devices is a key requirement for reducing the overall energy consumption of modern power circuits and modules. For this reason, the possibility of controlling the Schottky barrier height (SBH) value is a very important aspect for adapting the voltage drop of a Schottky diode. Reducing the SBH significantly reduces the voltage drop. The negative effect of reducing the SBH is a significant increase in the leakage current in the reverse mode.

[0006] Therefore, a need is felt for a JBS diode that has high efficiency in forward bias without the drawbacks of high losses in reverse mode or reverse bias. Summary of the Invention

[0007] It is an object of the present disclosure to provide a device and manufacturing method that overcomes the shortcomings of the prior art and meets the needs noted above.

[0008] In accordance with the present disclosure, there is provided an electronic device and a process for manufacturing an electronic device, as claimed in the accompanying claims. [Brief explanation of the drawings]

[0009] In order that the present disclosure may be better understood, preferred embodiments will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Figure 1] 1 shows a cross-sectional view of the main physical structures of a semiconductor device including a JBS diode. [Figure 2A] 2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 2B] 2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 2C] 2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 2D]2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 2E] 2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 2F] 2A-2C illustrate cross-sectional views of a die of semiconductor material at subsequent manufacturing stages of the JBS diode of FIG. 1; [Figure 3A] 2C shows a variation of the manufacturing process steps shown in FIGS. 2A and 2B. [Figure 3B] 2C shows a variation of the manufacturing process steps shown in FIGS. 2A and 2B. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1 shows an embodiment of an electronic device 100 in a three-axis system of mutually orthogonal axes X, Y, and Z. The electronic device 100 forms a JBS (“Junction Barrier Schottky”) diode or an MPS (“Merged PiN Schottky”) diode and may generally be part of an integrated device with other electronic components not shown. The electronic device 100 is therefore generally formed in a manner known per se, for example in an active area externally bounded by an oxide field region or an edge termination region or an edge guard ring (e.g., a P-type implanted region).

[0011] The electronic device 100 comprises a substrate 101 of silicon carbide (SiC), particularly 4H—SiC, having N-type conductivity. The substrate 101 is formed of an N+ type substrate 101A having low resistivity and an N- type epitaxial layer 101B. For example, the substrate 101A has a thickness comprised between 40 and 500 μm, typically 180 μm, and a resistivity comprised between 10 and 30 mΩ·cm, typically 20 mΩ·cm. The epitaxial layer 101B has a thickness comprised between 3 and 15 μm, typically 10 mΩ·cm. 15 ~5×10 16 The doping is contained in 10 17The doping can be up to 100 . The substrate 101A and the epitaxial layer 101B may have thicknesses and conductivities different from those shown above, depending on the manufacturing and application needs. The body 101 has a first (front) surface 103 and a second (back) surface 109. The P-type implanted region 102 extends into the epitaxial layer 101B starting from the first surface 103. The implanted region 102 may extend longitudinally in a direction perpendicular to the plane of the drawing in the form of a strip, or may extend along the sides of a regular or irregular geometric figure.

[0012] According to the present disclosure, the upper part of the epitaxial layer 101B has a P-type surface layer 104. For example, the surface layer 104 may be 11 ~10 14 at / cm 3 The depth of the surface layer 104 is shallower than the depth of the implanted region 102. For example, the depth of the surface layer 104 is 0.1 μm, and the depth of the implanted region 102 is typically comprised between 0.4 and 0.8 μm, for example about 0.5 μm. According to embodiments in which the implantation is performed by utilizing the channeling effect, depths of the implanted region 102 up to 2 μm are also envisaged. The depth is considered here to be parallel to the Z axis, starting from the surface 103 towards the surface 109.

[0013] First metal layer 110 extends over first surface 103 of body 101. First metal layer 110 forms a Schottky contact or Schottky diode in the area of ​​epitaxial layer 101B between implanted regions 104 (i.e., in region 102). First metal layer 110 forms a JB diode in implanted region 102. The region of device 100 containing the JB element and the Schottky diode is the active area of ​​device 100.

[0014] The first metal layer 110 may have a thickness of, for example, 50 to 400 nm, particularly 200 to 400 nm. The first metal layer 110 is made of a material that allows a Schottky contact to be formed, for example, at a capacitance of 0.7 to 1.2 eV, for example, about 0.9 eV. For example, the first metal layer 110 is TiN. Other materials for the first metal layer 110 include, for example, Mo, MoN, WN, WC, Ta, and TaN.

[0015] A thicker second metal layer 112 extends over the first metal layer 110. The second metal layer 112 is, for example, an alloy containing aluminum (Al), for example AlSiCu, and has a thickness, for example, comprised between 2 and 10 μm (typically about 5 μm).

[0016] Additionally, a back contact metal layer 116 extends onto the second surface 109 of the body 101 .

[0017] The electronic device 100 of FIG. 1 can be implemented in the manner described below with reference to FIGS. 2A-2F.

[0018] First, in FIG. 2A, epitaxial layer 101B having upper surface 105 undergoes a step of adjusting the surface conductivity. For this purpose, a blanket ("unmasked") surface implantation is performed, represented by arrows 120 in FIG. 2A. According to the present disclosure, doping atoms, for example boron or aluminum atoms, are implanted at 10 12 ~10 15 at / cm 2 (boundary included) and with implantation energy comprised between 10 keV and 200 keV (boundary included). As a result, a surface layer 104 having P-type conductivity is formed.

[0019] 2B, a hard mask 121 having a window 122 is then formed on the upper surface 105 of the body 101. The window 122 can be used to 12 at / cm 2A P-type implant, represented generally by arrow 123, of aluminum or boron atoms is performed at a dose of 0.15 Mn and an implant energy in the range of 10-50 keV, thereby forming P-type region 125. Generally, the process parameters are optimized so that the depth of implanted region 102 is greater than the depth of surface layer 104, as shown.

[0020] 2C, the hard mask 121 is then removed and a thermal process of activation of the implanted ions is carried out, which is carried out at a temperature higher than 1500° C. (for example, 1600° C.) and allows activation of the implanted region 102 of FIG.

[0021] 2D, the top surface 105 is then covered by a masking layer 126, and a back metal layer is deposited on the second surface 109 of the body 101 to form the back contact metal layer 116. This step may include the formation of a rear ohmic contact (optional).

[0022] After removing the masking layer 126 from the upper surface 105 of the body 101 (FIG. 2E), further steps are performed to form an ohmic contact 129 on the front surface of the device, specifically forming a nickel region only in the implanted region 102 using a silicon oxide mask that covers the area of ​​the surface 105 different from the implanted region 102. Subsequent high-temperature thermal annealing (900°C-1000°C for a time period of 1-120 minutes) allows the formation of the nickel silicide Ni2Si ohmic contact 129 by chemical reaction between the deposited nickel and the silicon of the substrate 101 (more specifically, the epitaxial layer 101B). The nickel in contact with the mask oxide does not react. This is followed by a step to remove the unreacted metal and the mask. Other modes of forming the ohmic contact are possible instead of the one described. For example, the ohmic contact 129 may be formed by heating the implanted region 125 using a laser source, according to the teachings of EP 3896719 A1.

[0023] 2F, a front contact metal layer (first metal layer 110), for example TiN (or one of Mo, MoN, WN, WC, Ta, TaN), is deposited over surface 105 and ohmic contact 129. First metal layer 110 forms a continuous layer. As described above, first metal layer 110 is configured to form a Schottky contact with injection layer 104, for example with a barrier height equal to 0.9 eV.

[0024] In some embodiments, the second metal layer 111 is disposed on the first metal layer 110. The deposition of the first and second metal layers 110, 111 is performed, for example, by sputtering techniques.

[0025] In a manner not shown, a passivation layer is also formed on the second metal layer 111 to protect the second metal layer 111. The passivation layer includes openings or windows that expose selected portions of the second metal layer 111 for electrical contact.

[0026] 3A and 3B, the implantation step of P-type regions 125 is carried out before the implantation step of P-type surface layer 104. For this purpose, first, in FIG. 3A, a hard mask 121 having windows 122 is formed on top surface 105 of epitaxial layer 101B. Using windows 122, P-type regions 125 are implanted, as schematically represented by arrows 123.

[0027] After removing the hard mask 121 (FIG. 3B), a blanket ("unmasked") implantation step is performed to modify the conductivity of the surface zones of the epitaxial layer 101B lateral to the implanted region 125. For this purpose, P-type doping ions are implanted into the epitaxial layer 101B close to its upper surface 105 (as schematically represented by arrows 120), thus forming the surface layer 104. This is followed by a dopant activation step at temperatures above 1500°C. The device is completed according to the steps already described with reference to FIGS. 2C-2E.

[0028] The described electronic device 100 has many advantages.

[0029] In particular, the present disclosure allows for reduced losses in reverse bias with minimal increase in SBH.

[0030] Finally, it will be apparent that modifications and variations can be made to the devices and manufacturing processes described and illustrated herein without departing from the scope of the present disclosure as claimed in the appended claims.

[0031] Furthermore, the material of the substrate 101 may be one of 4H-SiC, 6H-SiC, 3C-SiC, 15R-SiC, or it may be silicon or another semiconductor material.

[0032] The electronic device 100 may alternatively be one of a Merged PiN Schottky (MPS) diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, or a DMOS.

Claims

1. 1. An electronic device comprising: a body of semiconductor material having a surface and N-type conductivity; a switching region having P-type conductivity originating at said surface and extending into said body; an ohmic contact region in the switching region; a surface portion of said body having P-type conductivity and extending to said surface at least between said switching regions; a metal layer on the surface of the body, the metal layer electrically contacting the body through the surface portion and electrically contacting the switching region through the ohmic contact region.

2. The electronic device of claim 1 , wherein the surface portion extends in electrical continuity along the entire surface.

3. The electronic device of claim 1 , wherein the surface portion is in direct electrical contact with the switching region.

4. The electronic device of claim 1 , wherein the contact metal layer is in direct electrical contact with the surface portion.

5. 2. The electronic device according to claim 1, wherein said metal layer is a metal for forming, together with said surface portion, a Schottky contact with a barrier height comprised between 0.7 and 1.2 eV, in particular equal to 0.9 eV.

6. 10. The electronic device of claim 1, wherein the contact metal layer is one of TiN, Mo, MoN, WN, WC, Ta, or TaN.

7. The electronic device of claim 1 , wherein the body is silicon carbide, SiC.

8. 2. The electronic device of claim 1, wherein the body comprises an epitaxial layer on a substrate, the surface belongs to the epitaxial layer, and the surface portion has a depth in the epitaxial layer starting from the surface that is smaller than a depth of the switching region.

9. The surface portion is 10 １１ ~10 １４ at / cm ３ 10. The electronic device of claim 1, having a P-type doping value comprised between:

10. 10. The electronic device of claim 1, forming a Junction Barrier Schottky (JBS) diode or a Merged PiN Schottky (MPS) diode.

11. 1. A method for manufacturing an electronic device, comprising: forming, in a surface and a solid body of semiconductor material having N-type conductivity, a switching region having P-type conductivity originating at the surface and extending into the body and separating regions of the surface of the solid body from each other; forming a surface layer having P-type conductivity extending over the surface at least between the switching regions; forming an ohmic contact region on the switching region; forming a metal layer over the surface in electrical contact with the ohmic contact region and a surface portion.

12. 12. The method for manufacturing an electronic device according to claim 11, wherein the surface layer extends electrically continuous along the surface.

13. 12. The method for manufacturing an electronic device of claim 11, wherein the surface layer and the switching region are formed in electrical contact with each other.

14. 12. The method for manufacturing an electronic device of claim 11, wherein the metal layer is formed in direct electrical contact with the surface portion.

15. 12. The method for manufacturing an electronic device according to claim 11, wherein the metal layer is a metal for forming, together with the surface layer, a Schottky contact with a barrier height comprised between 0.7 and 1.2 eV, in particular equal to 0.9 eV, the metal layer being a material in particular from among TiN, Mo, MoN, WN, WC, Ta, TaN.

16. The surface layer is 10 １２ ~10 １５ at / cm ２ 12. The method for manufacturing an electronic device of claim 11, wherein the semiconductor substrate is formed by implanting a P-type doping species at a dose comprised between:

Images