Photoelectric conversion device and driving method therefor

Abstract

To provide a photoelectric conversion device capable of acquiring a signal for display improved in image quality while acquiring a signal for sensing at high speed.SOLUTION: A photoelectric conversion device comprises: a plurality of pixels disposed to form a plurality of rows and a plurality of columns; output line groups disposed in the columns and each including first and second output lines; a pixel control section which controls readout of signals from the plurality of pixels on a row basis; and an amplitude restriction section for restricting a range of a signal amplitude a signal outputted to the output line group may take. The pixel control section executes first scan in which signals of pixels connected to the first output lines of the columns are successively read out and second scan in which signals of pixels connected to the second output lines of the columns are successively read out. In a case where a period in which a signal of a first pixel is read out by the first scan overlaps a period in which a signal of a second pixel connected to the second output line adjacent to the first output line to which the first pixel is connected is read out by the second scan, the amplitude restriction section restricts maximum signal amplitudes in the first output line and the second output line to different ranges.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a driving method thereof. [Background technology]

[0002] Patent Document 1 describes an imaging device that has two output lines arranged for each pixel column in a pixel area and is configured to simultaneously read out image signals with different frame rates, such as a display signal and a sensing signal, from these two output lines.The imaging device described in Patent Document 1 makes it possible to acquire a display signal in accordance with the frame rate of the image display device while acquiring a sensing signal at high speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-033072 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the imaging device described in Patent Document 1, no particular consideration was given to the parasitic capacitance between the output line that reads out the display signal and the output line that reads out the sensing signal. As a result, crosstalk occurs via the parasitic capacitance between the output line that reads out the display signal and the output line that reads out the sensing signal, which can cause degradation in the image quality of the display signal depending on the intensity of the sensing signal that is being read out at the same time.

[0005] An object of the present invention is to provide a photoelectric conversion device and a driving method thereof that can obtain a display signal with excellent image quality while obtaining a sensing signal at high speed. [Means for solving the problem]

[0006] According to one disclosure of the present specification, a pixel array includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric conversion unit; a plurality of output line groups arranged in each of the plurality of columns, each including at least a first output line and a second output line; a pixel control unit that controls, in units of rows, reading of signals from the plurality of pixels to the plurality of output line groups; and an amplitude limiting unit that limits a range of signal amplitude that can be taken by signals output to the plurality of output line groups, wherein the pixel control unit performs a first scanning that sequentially reads, in units of rows, signals of pixels connected to the first output line of each column; a first scan to read out a signal from a first pixel to the first output line and a second scan to output a signal from a second pixel to the second output line, the first scan overlapping a period in which a signal from a second pixel connected to the second output line adjacent to the first output line to which the first pixel is connected, the second scan being in a period in which a signal from the second pixel connected to the second output line adjacent to the first output line to which the first pixel is connected being read out, the amplitude limiting unit being configured to limit the ranges of the signal amplitudes on the first output line and the second output line when reading out from the first pixel and the second pixel such that a maximum signal amplitude on the first output line and a maximum signal amplitude on the second output line are different.

[0007] Furthermore, according to another disclosure of the present specification, there is provided a method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric conversion unit, and a plurality of groups of output lines arranged in each of the plurality of columns, each including at least a first output line and a second output line, wherein, when performing a first scan for sequentially reading out signals of pixels connected to the first output line of each column in units of rows and a second scan for sequentially reading out signals of pixels connected to the second output line of each column in units of rows, if a period for reading out signals of first pixels by the first scan overlaps with a period for reading out signals of second pixels connected to the second output line adjacent to the first output line to which the first pixel is connected by the second scan, the method limits the ranges of the signal amplitudes of the first output line and the second output line so that a maximum signal amplitude in the first output line is different from a maximum signal amplitude in the second output line. [Effects of the Invention]

[0008] According to the present invention, it is possible to acquire a sensing signal at high speed and also acquire a display signal with excellent image quality. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a first embodiment. [Figure 3] 3 is a block diagram showing an example of the configuration of a vertical drive circuit of the photoelectric conversion device according to the first embodiment. FIG. [Figure 4] 5A to 5C are diagrams showing a scanning method in the row direction in the method of driving the photoelectric conversion device according to the first embodiment. [Figure 5] FIG. 3 is a diagram conceptually illustrating crosstalk in the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 3 is a timing chart showing a method for driving the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration of a vertical drive circuit of a photoelectric conversion device according to a second embodiment. [Figure 9] FIG. 10 is a timing chart (part 1) showing a method for driving a photoelectric conversion device according to a second embodiment. [Figure 10] FIG. 10 is a timing chart (part 2) showing a method for driving a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 12] FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a third embodiment. [Figure 13] FIG. 10 is a circuit diagram showing a configuration example of an amplitude limiting circuit of a photoelectric conversion device according to a fourth embodiment. [Figure 14]FIG. 10 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment. [Figure 15] FIG. 11 is a timing chart (part 1) showing a method for driving a photoelectric conversion device according to a fifth embodiment. [Figure 16] FIG. 13 is a timing chart (part 2) showing a method for driving a photoelectric conversion device according to the fifth embodiment. [Figure 17] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a sixth embodiment. [Figure 18] FIG. 13 is a diagram showing a scanning method in the row direction in a driving method for a photoelectric conversion device according to a seventh embodiment. [Figure 19] FIG. 13 is a block diagram showing a schematic configuration of a photoelectric conversion system according to an eighth embodiment. [Figure 20] FIG. 13 is a diagram illustrating an example of the configuration of a photoelectric conversion system and a moving body according to a ninth embodiment. [Figure 21] FIG. 23 is a block diagram showing a schematic configuration of a device according to a tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0011] [First embodiment] The structure of a photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 3. Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. Fig. 2 is an equivalent circuit diagram showing an example configuration of a pixel of the photoelectric conversion device according to this embodiment. Fig. 3 is a block diagram showing an example configuration of a vertical drive circuit of the photoelectric conversion device according to this embodiment.

[0012] The photoelectric conversion device 100 according to this embodiment may be composed of a pixel region 10, a vertical driving circuit 20, a signal processing unit 30, a horizontal driving circuit 40, an output circuit 50, and a system control unit 60, for example, as shown in FIG.

[0013] The pixel region 10 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 has a photoelectric conversion unit that generates and accumulates signal charges in response to incident light, and outputs a pixel signal in response to the amount of received light. In FIG. 1, the first row R1 to the Mth row R2 are M M pixel rows including the first column C1 to the Nth column C N 1 illustrates a case in which the pixel region 10 is configured by an M×N pixel array consisting of N pixel columns including M and N. Here, M and N are any natural numbers. Typically, tens of millions of pixels 12 are arranged in the pixel region 10. Note that the number of rows and columns of the pixel array arranged in the pixel region 10 is not particularly limited. In addition to effective pixels that output pixel signals according to the amount of incident light, the pixel region 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like.

[0014] A control line group 14 is arranged in each row of the pixel region 10, extending in a first direction (the horizontal direction in FIG. 1). Each of the control line groups 14 includes a plurality of control lines corresponding to a plurality of types of control signals. Each of these plurality of control lines is connected to the pixels 12 arranged in the corresponding row and serves as a signal line common to these pixels 12. The first direction in which the control line group 14 extends is sometimes referred to as the row direction or horizontal direction. The control line group 14 is connected to a vertical drive circuit 20. In the following description, when the control line group 14 is to be distinguished by pixel row, the row number will be represented as m, such as control line group 14m.

[0015] In each column of the pixel region 10, an output line group 16 is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the output line group 16 includes a plurality of output lines. For the sake of simplicity in the following explanation, FIG. 1 illustrates an example in which the output line group 16 for each column is composed of two output lines 16A and 16B, but the number of output lines constituting the output line group 16 for each pixel column may be three or more. Each of these plurality of output lines is connected to the pixels 12 arranged in the corresponding column and forms a signal line common to these pixels 12. More specifically, each pixel 12 is connected to one of the plurality of output lines constituting the output line group 16 for the corresponding column. In the configuration example of FIG. 1, the odd-numbered rows (first row R1, third row R3, ..., (M-1)th row R M-1 ) are connected to the output line 16A, and the pixels 12 in the even-numbered rows (the second row R2, the fourth row R4, ..., the Mth row R M ) is connected to an output line 16B. The output line group 16 is connected to a signal processing unit 30. In the following description, when the output line group 16 and the output lines 16A and 16B are to be distinguished for each pixel column, the column number will be represented as n, and they will be represented as an output line group 16n and output lines 16nA and 16nB.

[0016] The vertical drive circuit 20 has a function of generating control signals for driving the pixels 12 in response to control signals supplied from the system control unit 60 and supplying the control signals to the pixels 12 via the control line group 14. The vertical drive circuit 20 sequentially outputs control signals to the control line group 14 for each row, thereby sequentially driving the pixels 12 in the pixel region 10 row by row. Signals read out from the pixels 12 row by row are input to the signal processing unit 30 via the output line group 16 arranged in each column of the pixel region 10. In other words, the vertical drive circuit 20 is a pixel control unit that controls the readout of signals from the multiple pixels 12 constituting the pixel region 10 to the multiple output lines 16A, 16B row by row. The vertical drive circuit 20 will be described in detail later.

[0017] The signal processing unit 30 has multiple column circuits (not shown) corresponding to the multiple output lines 16A and 16B constituting the output line group 16 of each column. Each of the multiple column circuits may include a current source, an amplitude limiting circuit, a processing circuit, and a signal holding circuit. The current source, together with an amplifying transistor M3 (described later), which is one of the components of the pixel 12, forms a source follower amplifier and functions to read pixel signals from the pixel 12 to the output line group 16. The amplitude limiting circuit functions to limit the range of signal amplitude that the output line group 16 can assume to a predetermined range. The processing circuit functions to perform predetermined signal processing on pixel signals output via the corresponding output line group 16. Examples of signal processing performed by the processing circuit include amplification, correction using correlated double sampling (CDS), and analog-to-digital conversion (AD conversion). The signal holding circuit includes a memory for holding pixel signals processed by the processing circuit.

[0018] The horizontal drive circuit 40 has a function of generating a control signal for reading out pixel signals from the signal processing unit 30 in response to a control signal supplied from the system control unit 60, and supplying the control signal to the signal processing unit 30. The horizontal drive circuit 40 sequentially scans the column circuits of each column of the signal processing unit 30, and outputs the pixel signals held in each of the column circuits to the output circuit 50.

[0019] The output circuit 50 has an external interface circuit and is a circuit for outputting the signal processed by the signal processing unit 30 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output circuit 50 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied to the external interface circuit. The SerDes transmission circuit is, for example, an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit.

[0020] The system control unit 60 is a control circuit that generates control signals for controlling the operations of the vertical drive circuit 20, the signal processing unit 30, and the horizontal drive circuit 40, and supplies the signals to each functional block. Note that at least some of the control signals supplied to each functional block may be supplied from outside the photoelectric conversion device 100.

[0021] Next, an example of the configuration of the pixel 12 in this embodiment will be described with reference to Fig. 2. Fig. 2 shows an equivalent circuit diagram of a pixel 12(m,n) arranged in the mth row and nth column among the multiple pixels 12 that make up the pixel region 10. Here, m is an integer from 1 to M, and n is an integer from 1 to N. The other pixels 12 that make up the pixel region 10 may have the same circuit configuration as pixel 12(m,n).

[0022] As shown in FIG. 2, the pixel 12(m,n) can be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, for example.

[0023] The photoelectric conversion element PD may be a photodiode formed by a semiconductor pn junction or an element having a photoelectric conversion film formed by at least one of an organic thin film and an inorganic thin film. The photoelectric conversion element PD has an anode connected to a ground voltage node and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion. The floating diffusion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include transistor gate capacitance, pn junction capacitance, wiring capacitance, etc. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line group 16n.

[0024] In the pixel configuration of FIG. 2, the control line group 14 for each row includes three control lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal TXm is supplied to the gate of the transfer transistor M1 from the vertical drive circuit 20. A control signal RESm is supplied to the gate of the reset transistor M2 from the vertical drive circuit 20. A control signal SELm is supplied to the gate of the selection transistor M4 from the vertical drive circuit 20. When each transistor is an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical drive circuit 20. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical drive circuit 20.

[0025] In this embodiment, the description will be made assuming that electrons, of the electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges (sometimes simply referred to as charges). When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be referred to by the opposite names.

[0026] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held by the capacitance component (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

[0027] The reset transistor M2 has a role of controlling a reset operation for resetting the node FD, which serves as a charge storage unit. That is, the reset transistor M2 is a reset unit that, when turned on, resets the node FD to a voltage corresponding to the voltage VDD. By turning on the transfer transistor M1 together with the reset transistor M2, it is also possible to reset the photoelectric conversion element PD to a voltage corresponding to the voltage VDD. However, resetting the photoelectric conversion element PD does not necessarily require that the reset transistor M2 and the transfer transistor M1 be turned on. For example, after the transfer transistor M1 is turned on to transfer the signal charge of the photoelectric conversion element PD to the node FD, the signal charge of the photoelectric conversion element PD can also be reset by turning on the reset transistor M2 to reset the node FD. The reset transistor M2 also serves as an amplitude limiter that limits the range of signal amplitude that the signal output to the output line group 16n can have.

[0028] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the output line group 16n. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (not shown) of the column circuit via the selection transistor M4, forming an amplifier unit (source follower circuit) with its gate as an input node. As a result, when the selection transistor M4 is in a conductive state (on state), the amplification transistor M3 outputs a signal corresponding to the potential of the node FD. As a result, the signal level of the output line group 16 becomes the signal level output by the amplification transistor M3. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal corresponding to the amount of charge held at the node FD.

[0029] Next, a configuration example of the vertical drive circuit 20 in this embodiment will be described with reference to Fig. 3. For example, as shown in Fig. 3, the vertical drive circuit 20 can be configured to include a vertical scanning section 24 and a buffer section 26. The buffer section 26 includes buffer sections 261 to 266 corresponding to the respective rows of the pixel region 10. MFor the sake of simplicity, FIG. 3 shows only the buffer units 261 to 26 M The buffer unit 26 corresponding to the m-th row m Only the buffer unit 26 is shown. m Other buffer sections 261 to 26 M The configuration of the buffer unit 26 m It can be similar to:

[0030] The vertical scanning unit 24 has a function of generating control signals for driving the pixels 12 in response to control signals supplied from the system control unit 60 and supplying the control signals to the pixels 12 via the control line group 14. The vertical scanning unit 24 may use logic circuits such as a shift register or an address decoder. The buffer unit 26 is a circuit that buffers the control signals generated by the vertical scanning unit 24 and has buffer circuits (buffer circuits B1, B3, and B4 in FIG. 3 ) connected to each of the multiple control lines that make up each of the control line group 14. The buffer circuits are mainly composed of inverter circuits or the like, but the circuit configuration is not particularly limited.

[0031] Buffer section 26 m 3, the control circuit 14m may include buffer circuits B1, B3, and B4 and switches S1, S2, and S3. The buffer circuit B1 is configured to buffer the control signal output from the vertical scanning unit 24 and output it as a control signal RESm to a corresponding control line in the control line group 14m. The buffer circuit B3 is configured to buffer the control signal output from the vertical scanning unit 24 and output it as a control signal TXm to a corresponding control line in the control line group 14m. The buffer circuit B4 is configured to buffer the control signal output from the vertical scanning unit 24 and output it as a control signal SELm to a corresponding control line in the control line group 14m.

[0032] A power supply voltage DVDDH is supplied to a high-level voltage node of the buffer circuit B1. A ground voltage SGND is supplied via switch S1, a voltage VRESL1 is supplied via switch S2, or a voltage VRESL2 is supplied via switch S3 to a low-level voltage node of the buffer circuit B1. With this configuration, the high level of the control signal RESm supplied to pixel 12(m,n) is the power supply voltage DVDDH. Furthermore, the low level of the control signal RESm can be selected from three voltages: the ground voltage SGND, the voltage VRESL1, and the voltage VRESL2, depending on the connections of switches S1 to S3. More specifically, the low level of the control signal RESm can be changed for each row by individually setting the connections of switches S1 to S3 for each row. The voltages VRESL1 and VRESL2 can be supplied from a reference voltage generating circuit (not shown) included in the photoelectric conversion device 100.

[0033] A voltage VTXH is supplied to a voltage node on the high level side of the buffer circuit B3. A voltage VTXL is supplied to a voltage node on the low level side of the buffer circuit B3. By adopting this configuration, the high level of the control signal TXm supplied to the pixel 12(m,n) becomes the voltage VTXH, and the low level of the control signal TXm becomes the voltage VTXL.

[0034] A power supply voltage DVDDH is supplied to a voltage node on the high level side of the buffer circuit B4. A voltage VSELL is supplied to a voltage node on the low level side of the buffer circuit B4. By adopting this configuration, the high level of the control signal SELm supplied to the pixel 12(m,n) becomes the power supply voltage DVDDH, and the low level of the control signal SELm becomes the voltage VSELL.

[0035] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Figs. 4 to 6. Fig. 4 is a diagram showing a scanning method in the row direction in the photoelectric conversion device according to this embodiment. Fig. 5 is a diagram conceptually showing crosstalk in the photoelectric conversion device according to this embodiment. Fig. 6 is a timing chart showing a method for driving the photoelectric conversion device according to this embodiment.

[0036] First, a row-direction scanning method in the photoelectric conversion device according to this embodiment will be described with reference to FIG. 4. In FIG. 4, the horizontal axis represents time, and the vertical axis represents pixel rows from which signals are read out. Solid lines represent row-direction scanning of display signals used for image formation, and dashed lines represent row-direction scanning of sensing signals. Note that sensing here refers to the operation of acquiring phase difference information for focusing on a display object and light intensity information for adjusting the light intensity of a displayed image. Scanning of display signals begins in synchronization with a display frame synchronization signal, and scanning of sensing signals begins in synchronization with a sensing frame synchronization signal.

[0037] The vertical drive circuit 20 is configured to perform scanning to sequentially read out signals from pixels 12 connected to output line 16A on a row-by-row basis, and scanning to sequentially read out signals from pixels 12 connected to output line 16B on a row-by-row basis. In the driving example shown in FIG. 4 , among the output lines constituting the output line group 16 for each column, the output line 16A connected to pixels 12 in odd-numbered rows is used as an output line for display signals, and the output line 16B connected to pixels 12 in even-numbered rows is used as an output line for sensing signals. By allocating display signals and sensing signals to the output lines 16A and 16B for each column and selecting pixels 12 so that both signals are not read out to the same output line, it is possible to simultaneously read out display signals and sensing signals from pixels 12 in different rows of the same column. In other words, two different scanning modes, a scanning mode for reading out display signals and a scanning mode for reading out sensing signals, are executed in parallel, and pixel signals in these two scanning modes can be simultaneously read out.

[0038] In the driving example of FIG. 4 , the pixel region 10 is scanned multiple times with the sensing signal while the pixel region 10 is scanned once with the display signal. That is, scannings 121, 122, and 123 of the sensing signal are sequentially performed in parallel with the period during which one scanning 111 of the display signal is performed. During the period of scanning 124 of the sensing signal, no scanning of the display signal is performed, and only the sensing signal is read out. The frame rate of the sensing frame synchronization signal is set to four times the frame rate of the display frame synchronization signal. In other words, four frames of the sensing signal can be acquired while one frame of the display signal is acquired. For example, if the frame rate of the display signal is 30 fps, the frame rate of the sensing signal can be set to 120 fps, which allows a relatively large number of sensing signals to be read out from the pixels 12 when viewed on the time axis relative to the display signal.

[0039] This type of operation is possible by thinning out the number of readout rows for the sensing signal to one-fourth the number of readout rows for the display signal.Thinning out the readout rows reduces the resolution of the image signal, but the readout speed in the row direction increases accordingly, making it possible to obtain a sensing signal with high time resolution.

[0040] On the other hand, one concern when applying the above-described driving method is the possibility of crosstalk occurring due to parasitic capacitance between the output line 16A used to read out the display signal and the output line 16B used to read out the sensing signal. Crosstalk here refers to a change in the voltage of one output line due to a change in the voltage of another adjacent signal line. For example, if the output lines 16A and 16B are arranged adjacent to each other, and the voltage of the output line 16B increases, the voltage of the output line 16A may also increase at a certain rate due to the parasitic capacitance between the output lines 16A and 16B.

[0041] The above-mentioned crosstalk will be conceptually explained using FIG. 5 . The driving method of this embodiment is characterized by its ability to simultaneously read out signals from pixels 12 arranged in different rows of the same pixel column, as shown, for example, at time t1 in FIGS. 4 and 5 . For example, if the sensing signal (row y in FIG. 5 ) being read out at time t1 is a high-luminance signal and the display signal (row x in FIG. 5 ) is a low-luminance signal, the output line 16A reading out the display signal may be affected by the output line 16B reading out the sensing signal. Similarly, the output line 16B reading out the sensing signal may be affected by the output line 16A reading out the display signal. This can result in high-luminance information affected by row y being mixed as a false signal into the display signal (row x), which should actually be low-luminance, resulting in a degradation of the quality of the displayed image. Alternatively, conversely, the luminance information of the display signal may be mixed as a false signal into the sensing signal.

[0042] Below, we will use Figure 6 to explain a method for driving a photoelectric conversion device that is suitable for suppressing the influence of crosstalk via parasitic capacitance between the output line 16A that reads out the display signal and the output line 16B that reads out the sensing signal, and thereby obtaining high-quality display signals.

[0043] FIG. 6 shows the transition of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, TXx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. Control signals RESy, TXy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in the odd rows. Voltage VLe is the voltage of the output line 16nB through which sensing signals are output from the pixels 12(y,n) in the even rows. Note that the control signals RESx, TXx, SELx, RESy, TXy, and SELy are active at a high level and inactive at a low level.

[0044] During the period up to time t10, pixel signal readout is not performed. During this period, the control signals RESx and RESy are maintained at a high level. As a result, the reset transistors M2 of the pixels 12(x,n) in the odd-numbered xth row and the even-numbered yth row are maintained in an on state, and the reset operation of the node FD continues. Also, during this period, the control signals TXx, TXy, SELx, and SELy are maintained at a low level. At this time, the levels of the voltages VLo and VLe are arbitrary.

[0045] The subsequent period from time t10 to time t18 corresponds to the readout period for pixel 12(x,n) and pixel 12(y,n), during which signal readout from the photoelectric conversion elements PD of pixel 12(x,n) and pixel 12(y,n) is performed.

[0046] First, at time t11, the control signals SELx and SELy are changed from low to high. This causes the selection transistor M4 of the pixel 12(x,n) to turn on, electrically connecting the pixel 12(x,n) to the output line 16nA. Also, the selection transistor M4 of the pixel 12(y,n) to turn on, electrically connecting the pixel 12(y,n) to the output line 16nB.

[0047] At the next time t12, the control signals RESx and RESy are changed from high to low. This causes the reset transistors M2 of the pixels 12(x,n) and 12(y,n) to turn off, and the reset state of the node FD is released. At this time, the buffer circuit 26 x By turning off the switches S1 and S3 and turning on the switch S2, the low level of the reset transistor M2 of the pixel 12(x, n) is set to the voltage VRESL1. y By turning off the switches S1 and S2 and turning on the switch S3, the low level of the reset transistor M2 of the pixel 12(y,n) is set to a voltage VRESL2 that is relatively higher than the voltage VRESL1.

[0048] When the control signals RESx and RESy transition from high to low, the potential of the node FD drops to a predetermined potential due to coupling between the gate of the reset transistor M2 and the node FD. The voltage of the node FD that stabilizes after the reset transistor M2 turns off becomes the reset voltage of the node FD of the pixel 12(x,n) and the pixel 12(y,n).

[0049] As a result, a signal corresponding to the reset voltage of the node FD of the pixel 12(x,n) is output to the output line 16nA via the amplification transistor M3 and the selection transistor M4. Also, a signal corresponding to the reset voltage of the node FD of the pixel 12(y,n) is output to the output line 16nB via the amplification transistor M3 and the selection transistor M4. These signals are processed in the signal processing unit 30 at the subsequent stage and read out as the N signals of the pixel 12(x,n) and the pixel 12(y,n), respectively.

[0050] At the next time t15, the control signals TXx and TXy are changed from low to high, which turns on the transfer transistors M1 of the pixels 12(x,n) and 12(y,n), and transfers the charges accumulated in the photoelectric conversion elements PD of the pixels 12(x,n) and 12(y,n) to the node FD.

[0051] As a result, a pixel signal corresponding to the amount of charge transferred from the photoelectric conversion element PD of pixel 12(x,n) to the node FD is output to the output line 16nA via the amplification transistor M3 and the selection transistor M4. The voltage VLo of the output line 16nA changes according to the amount of charge generated in the photoelectric conversion element PD. Also, a pixel signal corresponding to the amount of charge transferred from the photoelectric conversion element PD of pixel 12(y,n) to the node FD is output to the output line 16nB via the amplification transistor M3 and the selection transistor M4. The voltage VLe of the output line 16nB changes according to the amount of charge generated in the photoelectric conversion element PD.

[0052] Here, the range of signal amplitude that can be taken by the output lines 16A and 16B will be described in detail. Note that the range of signal amplitude that can be taken by the output lines 16A and 16B means the maximum signal amplitude that can be taken by the signals output to the output lines 16A and 16B.

[0053] As described above, the voltages of the output lines 16nA and 16nB change depending on the amount of charge transferred from the photoelectric conversion element PD to the node FD. Specifically, in the case of an electron-accumulation type photoelectric conversion element PD, the voltages of the output lines 16nA and 16nB (voltages VLo and VLe) change in a decreasing direction depending on the intensity of the pixel signal with respect to the reset voltage, as shown by the waveforms from time t15 onwards in FIG.

[0054] When the voltage at node FD drops in accordance with the amount of charge generated in photoelectric conversion element PD, the gate-source voltage of reset transistor M2 (hereafter referred to as voltage VGS) increases accordingly. When voltage VGS exceeds a certain value, reset transistor M2 turns on, and some of the charge transferred to node FD is discharged to the power supply node via reset transistor M2, which is in the on state. This operation continues until reset transistor M2 turns off, so the voltage at node FD can only drop to the level just before reset transistor M2 turns on due to the increase in voltage VGS. In other words, the signal amplitude that node FD can have is limited by reset transistor M2.

[0055] Here, the low level of the control signal RESy supplied to the pixel 12(y,n) is voltage VRESL2, which is higher than the low level voltage VRESL1 of the control signal RESx supplied to the pixel 12(x,n). In other words, the gate potential when controlling the reset transistor M2 of the pixel 12(x,n) to the non-reset state is deeper than the gate potential when controlling the reset transistor M2 of the pixel 12(y,n) to the non-reset state. In other words, the potential difference between the gate potential when controlling the reset transistor M2 to the non-reset state and the gate potential when controlling it to the reset state is larger for the pixel 12(x,n) than for the pixel 12(y,n).

[0056] Therefore, the voltage VGS that the reset transistor M2 of pixel 12(y,n) can assume for a certain potential of node FD is higher than the voltage VGS that the reset transistor M2 of pixel 12(x,n) can assume. As a result, the potential of node FD at which the reset transistor M2 of pixel 12(y,n) is turned on is higher than the potential of node FD at which the reset transistor M2 of pixel 12(x,n) is turned on. Therefore, the signal amplitude of node FD that pixel 12(y,n) can assume is smaller than the signal amplitude of node FD that pixel 12(x,n). In other words, the signal amplitude of node FD of pixel 12(y,n) is more limited than the signal amplitude of node FD of pixel 12(x,n).

[0057] For the above reasons, the signal amplitude (voltage Vb) that the output line 16nB can take is smaller than the signal amplitude (voltage Va) that the output line 16nA can take. As a result, even if the output of the output line 16nA from which the display signal is read out is affected by the output line 16nB from which the sensing signal is read out via parasitic capacitance, the signal amplitude of the output line 16nB becomes smaller, and therefore the influence of crosstalk on the output line 16nA is reduced.

[0058] The column circuit may also amplify the signals output to the output lines 16nA and 16nB by applying a gain. This gain may be a gain that increases or decreases the amplitude of an analog signal, or a gain for AD conversion that converts an analog signal into a digital signal. The greater the gain in the column circuit, the more susceptible the signal to crosstalk is to the effects of crosstalk, since the crosstalk component is also amplified by the gain. Therefore, when the column circuit gain is large, it is preferable to further limit the signal amplitude of the node FD that the pixel 12(y,n) can have, compared to when the gain is small. For example, the difference between the signal amplitude of the node FD that the pixel 12(x,n) can have at the first gain and the second gain and the signal amplitude of the node FD that the pixel 12(y,n) can have at the second gain is defined as the first difference and the second difference, respectively. In this case, if the second gain is larger than the first gain, it is preferable to make the second difference larger than the first difference. From a broader perspective, when the second gain is greater than the first gain, the second difference, which is the difference in maximum amplitude between the output lines 16nA and 16nB at the second gain, should be made larger than the first difference, which is the difference in maximum amplitude between the output lines 16nA and 16nB at the first gain.

[0059] For example, when the display signal for the xth row is a low-luminance signal and the sensing signal for the yth row is a high-luminance signal, the voltage drop of the output line 16nB from which the high-luminance signal for the yth row is read out is limited, thereby suppressing the influence of crosstalk via parasitic capacitance from the output line 16nB from which the high-luminance signal for the yth row is read out to the output line 16nA from which the low-luminance signal for the xth row is read out, thereby enabling to obtain a high-quality display image.

[0060] In this embodiment, the operation of suppressing the influence of crosstalk from the output line 16nB from which the sensing signal is read to the output line 16nA from which the display signal is read is described. However, by limiting the signal amplitude of the output line 16nA from which the display signal is read, the influence of crosstalk on the output line 16nB from which the sensing signal is read can be suppressed, and this can also be applied to the operation of acquiring a high-quality sensing image. That is, the operation of this embodiment aims to improve the quality of the display image by limiting the amplitude of some high-luminance signals for sensing, but it is also possible to select one of the two scanning modes to prioritize the image quality.

[0061] At the next time t16, the control signals TXx and TXy are changed from high to low. This turns off the transfer transistors M1 of the pixels 12(x,n) and 12(y,n), and ends the period of charge transfer from the photoelectric conversion elements PD to the nodes FD in the pixels 12(x,n) and 12(y,n). The signals output from the pixels 12(x,n) to the output lines 16nA and 16nB are processed by the signal processing unit 30 after the signal levels have settled, and are read out as the S signals of the pixels 12(x,n) and 12(y,n), respectively.

[0062] At the next time t17, the control signals RESx and RESy are changed from low to high, which turns on the reset transistors M2 of the pixels 12(x,n) and 12(y,n), starting the reset operation of the nodes FD of the pixels 12(x,n) and 12(y,n).

[0063] Also at time t17, the control signals SELx and SELy are changed from high to low. This causes the selection transistor M4 of pixel 12(x,n) to turn off, electrically disconnecting pixel 12(x,n) from output line 16nA. Also, the selection transistor M4 of pixel 12(y,n) to turn off, electrically disconnecting pixel 12(y,n) from output line 16nB.

[0064] In this way, signals are read out from pixel 12(x,n) and pixel 12(y,n) during one horizontal scanning period from time t10 to time t18. By repeatedly performing a similar signal read operation while scanning pixel rows, signals can be read out from the entire pixel region 10.

[0065] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0066] Although the present embodiment shows an example in which the influence of crosstalk caused by parasitic capacitance between adjacent output line groups in the same pixel column is suppressed, the configuration of the photoelectric conversion device and the driving method thereof according to the present embodiment can also be applied to other cases. For example, the configuration of the photoelectric conversion device and the driving method according to the present embodiment can also be applied to a case in which the influence of crosstalk caused by parasitic capacitance between output line groups spanning adjacent pixel columns is suppressed.

[0067] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Figs. 7 to 10. Components similar to those of the photoelectric conversion device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 7 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device according to this embodiment. Fig. 8 is a block diagram showing an example of the configuration of a vertical drive circuit of the photoelectric conversion device according to this embodiment. Figs. 9 and 10 are timing diagrams showing a method of driving the photoelectric conversion device according to this embodiment.

[0068] The photoelectric conversion device according to this embodiment is basically the same as the photoelectric conversion device according to the first embodiment, except for the configurations of the pixels 12 and the vertical drive circuit 20. In this embodiment, the photoelectric conversion device according to this embodiment will be described mainly with respect to the differences from the first embodiment, and the description of the similarities between the first embodiment and the photoelectric conversion device according to this embodiment will be omitted as appropriate.

[0069] 7, a pixel 12(m,n) of the photoelectric conversion device according to this embodiment includes photoelectric conversion elements PDA and PDB, transfer transistors M1A and M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The pixel 12(m,n) also includes an FD capacitance switching transistor M5. The photoelectric conversion element PDA and the photoelectric conversion element PDB of one pixel 12 can be configured to receive light that has passed through different pupil regions of one microlens.

[0070] The photoelectric conversion element PDA has an anode connected to the ground voltage node and a cathode connected to the source of the transfer transistor M1A. The photoelectric conversion element PDB has an anode connected to the ground voltage node and a cathode connected to the source of the transfer transistor M1B. The drains of the transfer transistors M1A and M1B are connected to the source of the FD capacitance switching transistor M5 and the gate of the amplification transistor M3. A node FD, to which the drains of the transfer transistors M1A and M1B, the source of the FD capacitance switching transistor M5, and the gate of the amplification transistor M3 are connected, is a floating diffusion region. The drain of the FD capacitance switching transistor M5 is connected to the source of the reset transistor M2. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line group 16n.

[0071] In the pixel configuration of FIG. 7, the control line group 14 for each row includes five control lines connected to the gates of the transfer transistors M1A and M1B, the gate of the reset transistor M2, the gate of the selection transistor M4, and the gate of the FD capacitance switching transistor M5. A control signal TXAm is supplied from the vertical drive circuit 20 to the gate of the transfer transistor M1A. A control signal TXBm is supplied from the vertical drive circuit 20 to the gate of the transfer transistor M1B. A control signal RESm is supplied from the vertical drive circuit 20 to the gate of the reset transistor M2. A control signal SELm is supplied from the vertical drive circuit 20 to the gate of the selection transistor M4. A control signal FDGm is supplied from the vertical drive circuit 20 to the gate of the FD capacitance switching transistor M5. When each transistor is an N-type MOS transistor, a high-level control signal supplied from the vertical drive circuit 20 turns the corresponding transistor on. A low-level control signal supplied from the vertical drive circuit 20 turns the corresponding transistor off.

[0072] The photoelectric conversion elements PDA and PDB convert incident light into an electric charge corresponding to the amount of light (photoelectric conversion) and store the generated electric charge. When the transfer transistor M1A is turned on, it transfers the electric charge held by the photoelectric conversion element PDA to the node FD. When the transfer transistor M1B is turned on, it transfers the electric charge held by the photoelectric conversion element PDB to the node FD. The electric charge transferred from the photoelectric conversion elements PDA and PDB is held by the capacitance component (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion elements PDA and PDB through charge-voltage conversion by the floating diffusion capacitance.

[0073] The FD capacitance switching transistor M5 serves to switch the capacitance value (floating diffusion capacitance) of the node FD. When the FD capacitance switching transistor M5 is turned on, its channel capacitance is added to the capacitance of the node FD. As a result, the capacitance value of the floating diffusion portion when the FD capacitance switching transistor M5 is on is larger than the capacitance value of the floating diffusion portion when the FD capacitance switching transistor M5 is off. In this way, the pixel 12 of this embodiment is configured to be able to switch the conversion efficiency of the output signal by making the capacitance value of the node FD variable using the FD capacitance switching transistor M5. The FD capacitance switching transistor M5 also serves as an amplitude limiting portion that limits the range of signal amplitude that the signal output to the output line group 16n can take. The connections and operations of the other components in the pixel 12 of this embodiment are similar to those of the pixel 12 of the first embodiment.

[0074] 7, the pixel 12(m,n) of the photoelectric conversion device according to this embodiment includes photoelectric conversion elements PDA and PDB, transfer transistors M1A and M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The pixel 12(m,n) also includes an FD capacitance switching transistor M5.

[0075] In the vertical drive circuit 20 of the photoelectric conversion device according to this embodiment, the buffer section 26 m The configuration of the buffer unit 26 in this embodiment is different from that in the first embodiment. m8, the control signal generator 14 may include buffer circuits B1, B2, B3A, B3B, and B4 and switches S1, S2, and S3. The buffer circuit B1 is configured to buffer the control signal supplied from the vertical scanning unit 24 and output it as a control signal RESm to a corresponding control line in the control line group 14m. The buffer circuit B2 is configured to buffer the control signal supplied from the vertical scanning unit 24 and output it as a control signal FDGm to a corresponding control line in the control line group 14m. The buffer circuit B3A is configured to buffer the control signal supplied from the vertical scanning unit 24 and output it as a control signal TXAm to a corresponding control line in the control line group 14m. The buffer circuit B3B is configured to buffer the control signal supplied from the vertical scanning unit 24 and output it as a control signal TXBm to a corresponding control line in the control line group 14m. The buffer circuit B4 is configured to buffer the control signal supplied from the vertical scanning unit 24 and output it as a control signal SELm to a corresponding control line in the control line group 14m.

[0076] A power supply voltage DVDDH is supplied to a voltage node on the high level side of the buffer circuit B2. A ground voltage SGND is supplied via switch S1, a voltage VRESL1 is supplied via switch S2, or a voltage VRESL2 is supplied via switch S3 to a voltage node on the low level side of the buffer circuit B2. With this configuration, the high level of the control signal FDGm supplied to pixel 12(m,n) is the power supply voltage DVDDH. Furthermore, the low level of the control signal FDGm can be selected from three voltages: the ground voltage SGND, the voltage VRESL1, and the voltage VRESL2, depending on the connections of switches S1 to S3. More specifically, by individually setting the connections of switches S1 to S3 for each row, the low level of the control signal FDGm can be changed for each row.

[0077] A voltage VTXH is supplied to the high-level voltage node of the buffer circuit B3A. A voltage VTXL is supplied to the low-level voltage node of the buffer circuit B3A. With this configuration, the high level of the control signal TXAm supplied to the pixel 12(m,n) becomes the voltage VTXH, and the low level of the control signal TXm becomes the voltage VTXL. Similarly, a voltage VTXH is supplied to the high-level voltage node of the buffer circuit B3B. A voltage VTXL is supplied to the low-level voltage node of the buffer circuit B3B. With this configuration, the high level of the control signal TXBm supplied to the pixel 12(m,n) becomes the voltage VTXH, and the low level of the control signal TXm becomes the voltage VTXL.

[0078] The connection relationship and operation of the buffer circuit B1 and the buffer circuit B4 are the same as those in the first embodiment.

[0079] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a timing diagram in an operation mode in which the FD capacitance switching transistor M5 is set to the off state, and Fig. 10 is a timing diagram in an operation mode in which the FD capacitance switching transistor M5 is set to the on state.

[0080] 9 and 10 show transitions of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, FDGx, TXAx, TXBx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. Control signals RESy, FDGy, TXAy, TXBy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in the odd rows. Voltage VLe is the voltage of the output line 16nB through which sensing signals are output from the pixels 12(y,n) in the even rows. Note that the control signals RESx, FDGx, TXAx, TXBx, SELx, RESy, FDGy, TXAy, TXBy, and SELy are active at a high level and inactive at a low level.

[0081] First, an operation mode in which the FD capacitance switching transistor M5 is turned off will be described with reference to FIG.

[0082] The period from time t20 to time t28 corresponds to the readout period for pixel 12(x,n) and pixel 12(y,n), during which signal readout from the photoelectric conversion elements PDA and PDB of pixel 12(x,n) and pixel 12(y,n) is performed. During this period, the control signals RESx and RESy are maintained at high level.

[0083] At time t20, the control signals RESx, RESy, FGDx, and FDGy are at high level, which turns on the reset transistor M2 and the FD capacitance switching transistor M5 of the pixel 12(x,n) and the pixel 12(y,n), and the node FD of these pixels 12 is in the reset state.

[0084] At the next time t21, the control signals SELx and SELy are changed from low to high. This causes the selection transistor M4 of the pixel 12(x,n) to turn on, electrically connecting the pixel 12(x,n) to the output line 16nA. Also, the selection transistor M4 of the pixel 12(y,n) to turn on, electrically connecting the pixel 12(y,n) to the output line 16nB.

[0085] At the next time t22, the control signals FDGx and FDGy are changed from high to low. This causes the FD capacitance switching transistors M5 of the pixels 12(x,n) and 12(y,n) to turn off, and the reset state of the node FD is released. At this time, the buffer circuit 26 x By turning off the switches S1 and S3 and turning on the switch S2, the low level of the FD capacitance switching transistor M5 of the pixel 12(x, n) is set to the voltage VRESL1. yBy turning off the switches S1 and S2 and turning on the switch S3, the low level of the FD capacitance switching transistor M5 of the pixel 12(y,n) is set to a voltage VRESL2 that is relatively higher than the voltage VRESL1.

[0086] During the subsequent period from time t23 to time t24, the control signals TXAx and TXAy are changed from low to high, which turns on the transfer transistors M1A of the pixels 12(x,n) and 12(y,n), and transfers the charges accumulated in the photoelectric conversion elements PDA of the pixels 12(x,n) and 12(y,n) to the node FD.

[0087] During the subsequent period from time t25 to time t26, the control signals TXAx, TXAy, TXBx, and TXBy are changed from low to high, which turns on the transfer transistors M1A and M1B of the pixels 12(x,n) and 12(y,n), and transfers the charges accumulated in the photoelectric conversion elements PDA and PDB of the pixels 12(x,n) and 12(y,n) to the node FD.

[0088] In this way, the pixel signal based on the two photoelectric conversion elements PDA and PDB included in pixel 12 is divided and acquired into a pixel signal based on the charge of one photoelectric conversion element PDA and a pixel signal based on the combined charge of the two photoelectric conversion elements PDA and PDB. This makes it possible to acquire a signal for focus detection simultaneously with acquiring an image signal. Specifically, the pixel signal based on the charge of the photoelectric conversion element PDA is used for focus detection, and the pixel signal based on the combined charge of the photoelectric conversion elements PDA and PDB is used to capture or display an image.

[0089] Here, the range of signal amplitude that can be taken by the output lines 16nA and 16nB after time t26 will be described.

[0090] When the voltage at node FD drops in accordance with the amount of charge generated in photoelectric conversion elements PDA and PDB, the gate-source voltage (voltage VGS) of FD capacitance switching transistor M5 increases accordingly. When voltage VGS exceeds a certain value, FD capacitance switching transistor M5 turns on, and some of the charge transferred to node FD is discharged to the power supply node via FD capacitance switching transistor M5 in the on state and reset transistor M2. This operation of FD capacitance switching transistor M5 is similar to that of reset transistor M2 in the first embodiment, which functions as a circuit that limits the signal amplitude at node FD.

[0091] Here, the low level of the control signal FDGy supplied to the pixel 12(y,n) is voltage VRESL2, which is higher than the low level voltage VRESL1 of the control signal FDGx supplied to the pixel 12(x,n). In other words, the gate potential when controlling the FD capacitance switching transistor M5 of the pixel 12(x,n) to the OFF state is deeper than the gate potential when controlling the FD capacitance switching transistor M5 of the pixel 12(y,n) to the OFF state. In other words, the potential difference between the gate potential when controlling the FD capacitance switching transistor M5 to the OFF state and the gate potential when controlling it to the ON state is larger for the pixel 12(x,n) than for the pixel 12(y,n).

[0092] Therefore, the signal amplitude of the node FD that the pixel 12(y,n) can have is smaller than the signal amplitude of the node FD that the pixel 12(x,n) can have, as described above. In other words, the signal amplitude of the node FD of the pixel 12(y,n) is more limited than the signal amplitude of the node FD of the pixel 12(x,n).

[0093] For the above reasons, the signal amplitude (voltage Vb) that the output line 16nB can assume is smaller than the signal amplitude (voltage Va) that the output line 16nA can assume. As a result, when, for example, the display signal for the xth row is a low-luminance signal and the sensing signal for the yth row is a high-luminance signal, the amount of voltage drop in the output line 16nB from which the high-luminance signal for the yth row is read out is limited. As a result, it is possible to suppress the influence of crosstalk via parasitic capacitance from the output line 16nB from which the high-luminance signal for the yth row is read out to the output line 16nA from which the low-luminance signal for the xth row is read out, thereby making it possible to obtain a high-quality display image.

[0094] Next, an operation mode in which the FD capacitance switching transistor M5 is turned on will be described with reference to FIG.

[0095] The period from time t30 to time t38 corresponds to the readout period for the pixels 12(x,n) and 12(y,n), during which signals are read out from the photoelectric conversion elements PDA and PDB of the pixels 12(x,n) and 12(y,n). During this period, the control signals FDGx and FDGy are maintained at a high level.

[0096] At time t30, the control signals RESx, RESy, FGDx, and FDGy are at high level, which turns on the reset transistor M2 and the FD capacitance switching transistor M5 of the pixel 12(x,n) and the pixel 12(y,n), and the node FD of these pixels 12 is in the reset state.

[0097] At the next time t31, the control signals SELx and SELy are changed from low to high. This causes the selection transistor M4 of the pixel 12(x,n) to turn on, electrically connecting the pixel 12(x,n) to the output line 16nA. Also, the selection transistor M4 of the pixel 12(y,n) to turn on, electrically connecting the pixel 12(y,n) to the output line 16nB.

[0098] At the next time t32, the control signals RESx and RESy are changed from high to low. This causes the reset transistors M2 of the pixels 12(x,n) and 12(y,n) to turn off, and the reset state of the node FD is released. At this time, the buffer circuit 26 x By turning off the switches S1 and S3 and turning on the switch S2, the low level of the reset transistor M2 of the pixel 12(x, n) is set to the voltage VRESL1. y By turning off the switches S1 and S2 and turning on the switch S3, the low level of the reset transistor M2 of the pixel 12(y,n) is set to a voltage VRESL2 that is relatively higher than the voltage VRESL1.

[0099] With this setting, when the FD capacitance switching transistor M5 is operated in the on state, the reset transistor M2 functions as a circuit that limits the signal amplitude of the node FD, as described in the first embodiment, thereby suppressing the influence of crosstalk via parasitic capacitance from the output line 16nB to the output line 16nA.

[0100] In this way, in the pixel 12 to which the FD capacitance switching transistor M5 is added, the influence of crosstalk via the parasitic capacitance from the output line 16nB to the output line 16nA can be suppressed regardless of whether the FD capacitance switching transistor M5 is operated in the on or off state, thereby making it possible to obtain a high-quality display image.

[0101] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0102] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Figs. 11 and 12. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and their description will be omitted or simplified. Fig. 11 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device according to this embodiment. Fig. 12 is a timing chart showing a driving method of the photoelectric conversion device according to this embodiment.

[0103] The photoelectric conversion device according to this embodiment is basically the same as the photoelectric conversion device according to the first or second embodiment, except for the configuration of the pixel 12. In this embodiment, the photoelectric conversion device according to this embodiment will be described mainly with respect to differences between the photoelectric conversion device according to the first or second embodiment and explanations of similarities with the first or second embodiment will be omitted as appropriate.

[0104] 11, the pixel 12(m,n) of the photoelectric conversion device according to this embodiment differs from the second embodiment in that the FD capacitance switching transistor M5 is added as a ground capacitance rather than between the reset transistor M2 and the node FD. Similar to the second embodiment, the pixel 12(m,n) has a plurality of photoelectric conversion elements PDA, PDB and a plurality of transfer transistors M1A, M1B.

[0105] The drain of the FD capacitance switching transistor M5 is connected to the node FD. The source of the FD capacitance switching transistor M5 is connected to the ground voltage node. In FIG. 11, the capacitance component added to the node FD when the FD capacitance switching transistor M5 is turned on is represented as capacitance C. As in the first embodiment, the source of the reset transistor M2 is connected to the node FD. As in the second embodiment, the FD capacitance switching transistor M5 also serves as an amplitude limiter that limits the range of signal amplitude that can be taken by a signal output to the output line group 16n. The other components of the pixel 12 and the vertical drive circuit 20 are the same as in the second embodiment.

[0106] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 12. Fig. 12 is a timing chart in an operation mode in which the FD capacitance switching transistor M5 is turned off.

[0107] FIG. 12 shows the transition of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, FDGx, TXAx, TXBx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. Control signals RESy, FDGy, TXAy, TXBy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in the odd rows. Voltage VLe is the voltage of the output line 16nB through which sensing signals are output from the pixels 12(y,n) in the even rows. Note that the control signals RESx, FDGx, TXAx, TXBx, SELx, RESy, FDGy, TXAy, TXBy, and SELy are active at a high level and inactive at a low level.

[0108] First, an operation mode in which the FD capacitance switching transistor M5 is turned off will be described with reference to FIG.

[0109] The period from time t40 to time t48 corresponds to the readout period for the pixels 12(x,n) and 12(y,n), during which signals are read out from the photoelectric conversion elements PDA and PDB of the pixels 12(x,n) and 12(y,n). During this period, the control signals FDGx and FDGy are maintained at a low level (ground voltage SGND).

[0110] Under these conditions, similarly to the first embodiment, the reset transistor M2 functions as a circuit that limits the signal amplitude of the node FD, and can suppress the influence of crosstalk via parasitic capacitance from the output line 16nB to the output line 16nA.

[0111] The operation mode in which the FD capacitance switching transistor M5 is turned on is the same as the operation of the second embodiment described with reference to FIG. 10, and therefore will not be described here.

[0112] In this way, in the pixel 12 to which the FD capacitance switching transistor M5 is added, the influence of crosstalk via the parasitic capacitance from the output line 16nB to the output line 16nA can be suppressed regardless of whether the FD capacitance switching transistor M5 is operated in the on or off state, thereby making it possible to obtain a high-quality display image.

[0113] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0114] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figs. 13 and 14. Components similar to those of the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 13 is a circuit diagram showing an example of the configuration of an amplitude limiting circuit of the photoelectric conversion device according to this embodiment. Fig. 14 is a timing chart showing a driving method of the photoelectric conversion device according to this embodiment.

[0115] In the photoelectric conversion devices according to the first to third embodiments, the reset transistor M2 and the FD capacitance switching transistor M5 included in the pixel 12 function as a circuit that limits the signal amplitude of the node FD, thereby limiting the signal amplitude of the output line group 16. In this embodiment, a photoelectric conversion device configured to limit the signal amplitude of the output line group 16 using an amplitude limiting circuit provided in the signal processing unit 30 will be described.

[0116] The signal processing unit 30 of the photoelectric conversion device according to this embodiment includes a plurality of amplitude limiting circuits 32 corresponding to the plurality of output lines 16A, 16B constituting the output line group 16 of each column. The amplitude limiting circuit 32n arranged in the nth column includes an amplitude limiting transistor M6 and switches S4, S5, and S6, as shown in FIG. 13 . The source of the amplitude limiting transistor M6 is connected to the output line group 16n. The drain of the amplitude limiting transistor M6 is connected to a node supplied with a fixed voltage, such as a power supply voltage (voltage VDD). The gate of the amplitude limiting transistor M6 is connected to a node supplied with a voltage VCLIPH via switch S4, a node supplied with a voltage VCLIPL1 via switch S5, and a node supplied with a voltage VCLIPL2 via switch S6. The amplitude limiting circuits 32 arranged in the other columns are similar. Other configurations of the photoelectric conversion device according to this embodiment are similar to those of the photoelectric conversion device according to the first embodiment.

[0117] By configuring the amplitude limiting circuit 32 in this manner, the gate voltage VG of the amplitude limiting transistor M6 can be selected from three voltages: VCLIPH, VCLIPL1, and VCLIPL2, depending on the connection states (conducting or non-conducting) of the switches S4, S5, and S6. More specifically, by individually setting the connection states of the switches S4, S5, and S6 for each row, the signal amplitude range of the output line group 16n can be changed for each row. In other words, the amplitude limiting circuit 32 serves as an amplitude limiting unit that limits the range of signal amplitude that signals output to the output line group 16n can have. Note that the circuit configuration shown in FIG. 13 is an example, and the circuit configuration of the amplitude limiting circuit 32 is not limited thereto. The voltages VCLIPH, VCLIPL1, and VCLIPL2 can be supplied from a reference voltage generating circuit (not shown) included in the photoelectric conversion device 100.

[0118] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIG. 14. FIG. 14 shows transitions of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, TXx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. VGo is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. Control signals RESy, TXy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. VGe is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nB through which sensing signals are output from the pixels 12(y,n) in even-numbered rows. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. The voltage VLe is the voltage of the output line 16nB to which the sensing signals are output from the pixels 12(y,n) in the even-numbered rows. Note that the control signals RESx, TXx, SELx, RESy, TXy, and SELy are active at a high level and inactive at a low level.

[0119] The period from time t50 to time t58 corresponds to the readout period of pixel 12(x,n) and pixel 12(y,n), and signal readout from the photoelectric conversion elements PD of pixel 12(x,n) and pixel 12(y,n) is performed.

[0120] During the period from time t50 to time t55, the switch S4 of the amplitude limiting circuit 32n is controlled to a conductive state (ON state), and the gate voltages VGo and VGe of the amplitude limiting transistor M6 are set to a voltage VCLIPH. The voltage VCLIPH is a voltage that limits the amplitude of the N signals on the output lines 16nA and 16nB, and is set to a voltage higher than voltages VCLIPL1 and VCLIPL2, which will be described later.

[0121] During the subsequent period from time t55 to time t56, the control signals TXx and TXy are changed from low to high, which turns on the transfer transistors M1 of the pixels 12(x,n) and 12(y,n), and transfers the charges accumulated in the photoelectric conversion elements PD of the pixels 12(x,n) and 12(y,n) to the node FD.

[0122] Also at time t55, the gate voltage VGo of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nA is set to the voltage VCLIPL1, and the gate voltage VGe of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nB is set to the voltage VCLIPL2, which is a voltage relatively higher than the voltage VCLIPL1.

[0123] The gate voltages VGo and VGe of the amplitude limiting transistor M6 can be changed for each readout row by changing the connection states of switches S4, S5, and S6. Specifically, in the xth row corresponding to pixel 12(x,n), switch S5 is set to a conductive state, and a voltage VCLIPL1 is supplied to the gate of the amplitude limiting transistor M6. In the yth row corresponding to pixel 12(y,n), switch S6 is set to a conductive state, and a voltage VCLIPL2 is supplied to the gate of the amplitude limiting transistor M6. The voltages VCLIPL1 and VCLIPL2 are voltages that limit the amplitude of the output lines 16nA and 16nB.

[0124] Here, the range of signal amplitude that can be taken by the output lines 16nA and 16nB will be described.

[0125] When the voltage of the output line group 16n drops in accordance with the amount of charge generated by the photoelectric conversion element PD, the gate-source voltage (voltage VGS) of the amplitude limiting transistor M6 increases accordingly. When the voltage VGS exceeds a certain value, the amplitude limiting transistor M6 turns on, and the voltage of the output line group 16n stops decreasing. This is the same operation as the reset transistor M2 and the FD capacitance switching transistor M5 described in the first to third embodiments, and the amplitude limiting transistor M6 limits the signal amplitude that can be taken by the output line group 16n.

[0126] Here, the gate voltage VGe of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the same output line 16nB as the pixel 12(y,n) is voltage VCLIPL2. This voltage VCLIPL2 is higher than voltage VCLIPL1, which is the gate voltage VGo of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the same output line 16nA as the pixel 12(x,n). In other words, the gate potential of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nA is deeper than the gate potential of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nB. In other words, the potential difference between the gate potential when controlling the amplitude limiting transistor M6 to the off state and the gate potential when controlling it to the on state is larger for the amplitude limiting transistor M6 corresponding to the output line 16nA than for the amplitude limiting transistor M6 corresponding to the output line 16nA.

[0127] Therefore, the signal amplitude of the output line 16nB is more limited than the signal amplitude of the output line 16nA, based on the same principle as that of the signal amplitude limit at the node FD by the reset transistor M2 and the FD capacitance switching transistor M5 in the first to third embodiments.

[0128] For the above reasons, the signal amplitude (voltage Vb') that the output line 16nB can take is smaller than the signal amplitude (voltage Va') that the output line 16nA can take. As a result, when, for example, the display signal for the xth row is a low-luminance signal and the sensing signal for the yth row is a high-luminance signal, the amount of voltage drop in the output line 16nB from which the high-luminance signal for the yth row is read out is limited. As a result, it is possible to suppress the influence of crosstalk via parasitic capacitance from the output line 16nB from which the high-luminance signal for the yth row is read out to the output line 16nA from which the low-luminance signal for the xth row is read out, making it possible to obtain a high-quality display image.

[0129] At time t57, the switch S4 of the amplitude limiting circuit 32n is turned on, and the gate voltages VGo and VGe of the amplitude limiting transistor M6 are set to the voltage VCLIPH, completing the signal readout operation for the pixel 12(x,n) and the pixel 12(y,n).

[0130] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0131] [Fifth embodiment] A photoelectric conversion device and a driving method thereof according to a fifth embodiment of the present invention will be described with reference to Fig. 15 and Fig. 16. Components similar to those of the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 15 and Fig. 16 are timing diagrams showing a driving method of the photoelectric conversion device according to this embodiment.

[0132] In this embodiment, an example will be described in which the driving method of the fourth embodiment, in which the signal amplitude of the output line group 16n is limited using the amplitude limiting circuit 32 of the signal processing unit 30, is applied to the photoelectric conversion device of the second embodiment. The photoelectric conversion device of this embodiment is similar to the photoelectric conversion device of the second embodiment, except that the signal processing unit 30 further includes the amplitude limiting circuit 32 described in the fourth embodiment.

[0133] FIG. 15 is a timing diagram in an operation mode in which the FD capacitance switching transistor M5 is operated in an off state, and FIG. 16 is a timing diagram in an operation mode in which the FD capacitance switching transistor M5 is operated in an on state.

[0134] 15 and 16 show transitions of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, FDGx, TXAx, TXBx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. VGo is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. Control signals RESy, FDGy, TXAy, TXBy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. VGe is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nB through which sensing signals are output from the pixels 12(y,n) in even-numbered rows. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. The voltage VLe is the voltage of the output line 16nB to which the sensing signals are output from the pixels 12(y,n) in the even-numbered rows. Note that the control signals RESx, FDGx, TXAx, TXBx, SELx, RESy, FDGy, TXAy, TXBy, and SELy are active at a high level and inactive at a low level.

[0135] First, an operation mode in which the FD capacitance switching transistor M5 is turned off will be described with reference to FIG.

[0136] The period from time t60 to time t68 corresponds to the readout period for pixel 12(x,n) and pixel 12(y,n), during which signals are read out from the photoelectric conversion elements PDA and PDB of pixel 12(x,n) and pixel 12(y,n). During this period, the control signals RESx and RESy are maintained at high level.

[0137] During the period from time t65 to time t67, the gate voltage VGe of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the same output line 16nB as the pixel 12(y,n) is set to a voltage VCLIPL2. Meanwhile, the gate voltage VGo of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the same output line 16nA as the pixel 12(x,n) is set to a voltage VCLIPL1 lower than the voltage VCLIPL2. As a result, the signal amplitude of the sensing signal output from the pixel 12(y,n) to the output line 16nB is more limited than the signal amplitude of the display signal output from the pixel 12(x,n) to the output line 16nA. Therefore, the influence of crosstalk via parasitic capacitance from the output line 16nB to the output line 16nA can be suppressed.

[0138] During the period from time t63 to time t65, the gate voltage VGo of the amplitude limiting transistor M6 of the amplitude limiting circuit 32, which is connected to the same output line 16nA as the pixel 12(x,n), is set to voltage VCLIPL2, which is relatively higher than voltage VCLIPL1, in order to limit the voltage of the signal based on the charge of one of the photoelectric conversion elements PDA.

[0139] Next, an operation mode in which the FD capacitance switching transistor M5 is turned on will be described with reference to FIG.

[0140] The period from time t70 to time t78 corresponds to the readout period for pixel 12(x,n) and pixel 12(y,n), during which signal readout from the photoelectric conversion elements PDA and PDB of pixel 12(x,n) and pixel 12(y,n) is performed. During this period, the control signals FDGx and FDGy are maintained at a high level.

[0141] The timing diagram of FIG. 16 differs from the timing diagram of FIG. 15 only in the control signals RESx, RESy, FDGx, and FDGy, and therefore a detailed description thereof will be omitted.

[0142] In this embodiment, regardless of whether the FD capacitance switching transistor M5 of the pixel 12 to which the FD capacitance switching transistor M5 is added is operated in the on state or the off state, the influence of crosstalk via the parasitic capacitance from the output line 16nB to the output line 16nA can be suppressed, thereby making it possible to obtain a high-quality display image.

[0143] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0144] [Sixth embodiment] A photoelectric conversion device and a driving method thereof according to a sixth embodiment of the present invention will be described with reference to Fig. 17. Components similar to those of the photoelectric conversion devices according to the first to fifth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 17 is a timing chart showing a driving method of the photoelectric conversion device according to this embodiment.

[0145] In this embodiment, an example will be described in which the driving method of the fourth embodiment, in which the signal amplitude of the output line group 16n is limited using the amplitude limiting circuit 32 of the signal processing unit 30, is applied to the photoelectric conversion device of the third embodiment. The photoelectric conversion device of this embodiment is similar to the photoelectric conversion device of the third embodiment, except that the signal processing unit 30 further includes the amplitude limiting circuit 32 described in the fourth embodiment.

[0146] A method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 17. Fig. 17 is a timing chart in an operation mode in which the FD capacitance switching transistor M5 is turned off.

[0147] FIG. 17 shows transitions of the waveforms of each signal during one horizontal period corresponding to time t1 in FIGS. 4 and 5. Control signals RESx, FDGx, TXAx, TXBx, and SELx are control signals supplied to the pixels 12 in the xth row that output display signals. VGo is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. Control signals RESy, FDGy, TXAy, TXBy, and SELy are control signals supplied to the pixels 12 in the yth row that output sensing signals. VGe is the gate voltage of the amplitude limiting transistor M6 of the amplitude limiting circuit 32 connected to the output line 16nB through which sensing signals are output from the pixels 12(y,n) in even-numbered rows. Voltage VLo is the voltage of the output line 16nA through which display signals are output from the pixels 12(x,n) in odd-numbered rows. The voltage VLe is the voltage of the output line 16nB to which the sensing signals are output from the pixels 12(y,n) in the even-numbered rows. Note that the control signals RESx, FDGx, TXAx, TXBx, SELx, RESy, FDGy, TXAy, TXBy, and SELy are active at a high level and inactive at a low level.

[0148] The period from time t80 to time t88 corresponds to the readout period for pixel 12(x,n) and pixel 12(y,n), during which signal readout from the photoelectric conversion elements PDA and PDB of pixel 12(x,n) and pixel 12(y,n) is performed. During this period, the control signals FDGx and FDGy are maintained at low level.

[0149] The timing diagram of Fig. 17 differs from the timing diagram of Fig. 15 only in the control signals RESx, RESy, FDGx, and FDGy, so a detailed description thereof will be omitted. Also, the timing diagram in the operation mode in which the FD capacitance switching transistor M5 is operated in the off state is the same as the timing diagram of Fig. 16, so a description thereof will be omitted here.

[0150] In this embodiment, regardless of whether the FD capacitance switching transistor M5 of the pixel 12 to which the FD capacitance switching transistor M5 is added is operated in the on state or the off state, the influence of crosstalk via the parasitic capacitance from the output line 16nB to the output line 16nA can be suppressed, thereby making it possible to obtain a high-quality display image.

[0151] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0152] [Seventh embodiment] A method for driving a photoelectric conversion device according to the seventh embodiment of the present invention will be described with reference to Fig. 18. Components similar to those in the photoelectric conversion devices according to the first to sixth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 18 is a diagram showing a scanning method in the row direction in the photoelectric conversion device according to this embodiment.

[0153] In this embodiment, another driving method for the photoelectric conversion device according to the first to sixth embodiments will be described. In the driving method of this embodiment, the row direction scanning method is different from the row direction scanning method described in the first embodiment with reference to FIG.

[0154] The row direction scanning method in this embodiment will be described with reference to Fig. 18. In Fig. 18, the horizontal axis represents time, and the vertical axis represents pixel rows from which signals are read out. Solid lines represent row direction scanning of display signals used for image formation, and dashed lines represent row direction scanning of sensing signals.

[0155] 18, as in the driving example of Fig. 4, it is assumed that the output lines 16A connected to the pixels 12 in odd rows are used as output lines for display signals, and the output lines 16B connected to the pixels 12 in even rows are used as output lines for sensing signals. Scanning 131 of the display signals is started in synchronization with the display frame synchronization signal, and scanning of the sensing signals 141 is started in synchronization with the sensing frame synchronization signal. The frame rates of the display frame synchronization signal and the sensing frame synchronization signal are the same, but the synchronization timings of the two synchronization signals are different, which is a feature of this driving example.

[0156] 18, if the output line used to read out the display signal and the output line used to read out the sensing signal are adjacent to each other, crosstalk via parasitic capacitance between the two output lines becomes a problem. For example, if the sensing signal (row y' in FIG. 18) being read out at time t2 is a high-luminance signal and the display signal (row x' in FIG. 18) is a low-luminance signal, the output line 16A that is reading out the display signal is affected by the output line 16B that is reading out the sensing signal.

[0157] The influence of crosstalk between adjacent output lines can be suppressed by applying the configuration and operation of the photoelectric conversion device described in the first to sixth embodiments. Specifically, crosstalk can be suppressed by making the reset transistor M2 and the FD capacitance switching transistor M5 of the pixel 12 function as circuits that limit the signal amplitude of the node FD. Alternatively, crosstalk can be suppressed by making the amplitude limiting circuit 32 of the signal processing unit 30 function as a circuit that limits the signal amplitude of the output lines 16A and 16B. This suppresses the influence of crosstalk and makes it possible to obtain a high-quality display image.

[0158] As described above, according to this embodiment, it is possible to acquire a display signal with excellent image quality while acquiring a sensing signal at high speed.

[0159] [Eighth embodiment] A photoelectric conversion system according to an eighth embodiment of the present invention will be described with reference to Fig. 19. Fig. 19 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0160] The photoelectric conversion device 100 described in the first to seventh embodiments can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Also included in the photoelectric conversion system is a camera module equipped with an optical system such as a lens and an imaging device. Fig. 19 illustrates a block diagram of a digital still camera as an example of such systems.

[0161] 19 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to seventh embodiments, and converts the optical image formed by the lens 202 into image data.

[0162] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0163] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or may be detachable.

[0164] Furthermore, the photoelectric conversion system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the image capture device 201 and the signal processing unit 208. Here, timing signals and the like may be input from outside, and the photoelectric conversion system 200 only needs to have at least the image capture device 201 and the signal processing unit 208 that processes the output signal output from the image capture device 201.

[0165] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0166] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device 100 according to the first to seventh embodiments is applied.

[0167] [Ninth embodiment] A photoelectric conversion system and a moving object according to a ninth embodiment of the present invention will be described with reference to Fig. 20. Fig. 20 is a diagram showing the configuration of the photoelectric conversion system and a moving object according to this embodiment.

[0168] FIG. 20(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 includes an image capture device 310. The image capture device 310 is the photoelectric conversion device 100 described in any one of the first to seventh embodiments. The photoelectric conversion system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the image capture device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the image capture device 310. The photoelectric conversion system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0169] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0170] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 20(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0171] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0172] [Tenth embodiment] A device according to a tenth embodiment of the present invention will be described with reference to Fig. 21. Fig. 21 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0173] FIG. 21 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any of the first to seventh embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0174] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0175] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0176] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0177] The device EQP shown in FIG. 21 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0178] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0179] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0180] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0181] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0182] Furthermore, in the above first to seventh embodiments, it is assumed that the number of output lines constituting the output line group 16 of each column is two, but the number of output lines constituting the output line group 16 of each column may be three or more.

[0183] Furthermore, the configuration of the pixel 12 described in the first to seventh embodiments is merely an example and can be modified as appropriate. For example, the number of photoelectric conversion elements PD included in one pixel 12 is not limited to one or two, and may be three or more. Furthermore, the number of FD capacitance switching transistors does not necessarily need to be one, and two or more FD capacitance switching transistors may be connected in parallel or series to the node FD. Furthermore, the pixel 12 may further include a transistor for discharging electric charge connected to the photoelectric conversion element PD.

[0184] Furthermore, the photoelectric conversion systems shown in the above eighth and ninth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 19 and 20(a).

[0185] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0186] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0187] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric conversion unit; a plurality of output line groups each including at least a first output line and a second output line, the plurality of output line groups being arranged in each of the plurality of columns; a pixel control unit that controls readout of signals from the plurality of pixels to the plurality of output line groups in units of the row; an amplitude limiting unit that limits a range of signal amplitudes that can be taken by signals output to the plurality of output line groups, the pixel control unit is configured to perform a first scan of sequentially reading out signals of pixels connected to the first output line of each column in units of the row, and a second scan of sequentially reading out signals of pixels connected to the second output line of each column in units of the row, a period in which a signal from a first pixel is read out to the first output line by the first scanning and a period in which a signal from a second pixel connected to the second output line adjacent to the first output line connected to the first pixel is read out to the second output line by the second scanning overlap each other; The amplitude limiting unit is configured to limit a range of a signal amplitude in the first output line and the second output line so that a maximum signal amplitude in the first output line and a maximum signal amplitude in the second output line are different when reading out from the first pixel and the second pixel. A photoelectric conversion device characterized by: (Configuration 2) each of the plurality of pixels includes a floating diffusion region to which charges of the photoelectric conversion region are transferred, an amplifying transistor that outputs a signal according to a potential of the floating diffusion region to a corresponding output line, and a reset transistor that resets a potential of the floating diffusion region; The pixel control unit sets a gate potential when controlling the reset transistor of the first pixel to a non-reset state and a gate potential when controlling the reset transistor of the second pixel to a non-reset state to different potentials, thereby causing the reset transistor to function as the amplitude limiting unit. 2. The photoelectric conversion device according to configuration 1, (Configuration 3) the gate potential when the reset transistor of the first pixel is controlled to the non-reset state is deeper than the gate potential when the reset transistor of the second pixel is controlled to the non-reset state, relative to the gate potential when the reset transistor of the first pixel is controlled to the reset state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line. 3. The photoelectric conversion device according to configuration 2. (Configuration 4) Each of the plurality of pixels further includes a capacitance switching transistor connected to the floating diffusion portion, The pixel control unit causes the reset transistor to function as the amplitude limiting unit when controlling the capacitance switching transistor to be in an on state. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 5) each of the plurality of pixels includes a floating diffusion region to which charges of the photoelectric conversion region are transferred, an amplifying transistor that outputs a signal corresponding to a potential of the floating diffusion region to a corresponding output line among the plurality of output line groups, and a capacitance switching transistor connected to the floating diffusion region; The pixel control unit sets a gate potential when controlling the capacitance switching transistor of the first pixel to an off state and a gate potential when controlling the capacitance switching transistor of the second pixel to an off state to different potentials, thereby causing the capacitance switching transistor to function as the amplitude limiting unit. 2. The photoelectric conversion device according to configuration 1, (Configuration 6) the gate potential when the capacitance switching transistor of the first pixel is controlled to be in the off state is deeper than the gate potential when the capacitance switching transistor of the second pixel is controlled to be in the off state, relative to the gate potential when the capacitance switching transistor of the first pixel is controlled to be in the on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) Each of the plurality of pixels further includes a reset transistor that resets the potential of the floating diffusion portion, The capacitance switching transistor is connected between the reset transistor and the floating diffusion region. 7. The photoelectric conversion device according to configuration 5 or 6. (Configuration 8) The capacitance switching transistor is connected between the floating diffusion portion and a ground voltage node. 7. The photoelectric conversion device according to configuration 5 or 6. (Configuration 9) the photoelectric conversion unit of each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit configured to receive light that has passed through different pupil regions of one microlens; the amplitude limiting unit limits a range of signal amplitudes in the first output line and the second output line so that the maximum signal amplitude in the first output line and the maximum signal amplitude in the second output line are the same when reading out signals based on charges of the first photoelectric conversion unit from the first pixel and the second pixel; The amplitude limiting unit limits ranges of signal amplitudes in the first output line and the second output line such that the maximum signal amplitude in the first output line and the maximum signal amplitude in the second output line are different when reading out signals based on charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel. 2. The photoelectric conversion device according to claim 1. (Configuration 10) the amplitude limiting unit includes a plurality of amplitude limiting circuits provided corresponding to the plurality of output lines, each having an amplitude limiting transistor connected between a node to which a fixed voltage is supplied and the corresponding output line; When reading out from the first pixel and the second pixel, the amplitude limiting unit sets a gate potential to be supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential to be supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line to different potentials. 2. The photoelectric conversion device according to configuration 1, (Configuration 11) the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line when reading out from the first pixel and the second pixel is deeper than the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line with respect to a predetermined gate potential that controls the amplitude limiting transistor to an on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line. 11. The photoelectric conversion device according to configuration 10. (Configuration 12) the photoelectric conversion unit of each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit configured to receive light that has passed through different pupil regions of one microlens; when reading out signals based on the charge of the first photoelectric conversion unit from the first pixel and the second pixel, a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line are set to the same potential; When reading out signals based on the charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel, a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line are set to different potentials. 11. The photoelectric conversion device according to configuration 10. (Configuration 13) the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line when reading out signals based on the charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel is deeper than the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line with respect to a predetermined gate potential that controls the amplitude limiting transistor to an on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line. 13. The photoelectric conversion device according to configuration 12. (Configuration 14) The signal output to the first output line is a display signal, and the signal output to the second output line is a sensing signal. 14. The photoelectric conversion device according to any one of configurations 1 to 13. (Configuration 15) The pixel control unit is configured to perform the second scanning on the plurality of pixels a plurality of times while performing the first scanning on the plurality of pixels once. 15. The photoelectric conversion device according to any one of configurations 1 to 14. (Configuration 16) further comprising a circuit for applying gain to the signals output to the group of output lines; When the gain is a first gain, a difference between a maximum signal amplitude of the first output line in the first scan and a maximum signal amplitude of the second output line in the second scan is a first difference; When the gain is a second gain greater than the first gain, a difference between a maximum signal amplitude of the first output line in the first scan and a maximum signal amplitude of the second output line in the second scan is a second difference that is larger than the first difference; 16. The photoelectric conversion device according to any one of configurations 1 to 15. (Configuration 17) The length of the period during which the first scanning is performed on the plurality of pixels is the same as the length of the period during which the second scanning is performed on the plurality of pixels. 15. The photoelectric conversion device according to any one of configurations 1 to 14. (Configuration 18) The first output line to which the first pixel is connected and the second output line to which the second pixel is connected are arranged in the same column. 18. The photoelectric conversion device according to any one of configurations 1 to 17. (Configuration 19) The first output line to which the first pixel is connected and the second output line to which the second pixel is connected are arranged in adjacent columns. 18. The photoelectric conversion device according to any one of configurations 1 to 17. (Configuration 20) The photoelectric conversion device according to any one of structures 1 to 19, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 21) A mobile object, The photoelectric conversion device according to any one of structures 1 to 19, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having: (Configuration 22) The photoelectric conversion device according to any one of structures 1 to 19, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising: (Method 1) A method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel including a photoelectric conversion unit, and a plurality of output line groups arranged in each of the plurality of columns, each output line group including at least a first output line and a second output line, the method comprising: When a first scan for sequentially reading out signals from pixels connected to the first output line of each column in units of rows and a second scan for sequentially reading out signals from pixels connected to the second output line of each column in units of rows are performed, if a period for reading out signals from first pixels by the first scan and a period for reading out signals from second pixels connected to the first output line connected to the first pixel and the second output line adjacent to the first output line connected to the first pixel by the second scan overlap, the ranges of the signal amplitudes on the first output line and the second output line are limited so that a maximum signal amplitude on the first output line and a maximum signal amplitude on the second output line are different. A method for driving a photoelectric conversion device. [Explanation of symbols]

[0188] PD, PDA, PDB...photoelectric conversion elements 10...Pixel area 12...pixels 14...Control line group 16...Output line group 20...Vertical scanning unit 26...Buffer section 30...Signal processing unit 32...Amplitude limiting circuit 100 Photoelectric conversion device

Claims

1. a plurality of pixels arranged in a plurality of rows and a plurality of columns, each including a photoelectric conversion unit; a plurality of output line groups each including at least a first output line and a second output line, the plurality of output line groups being arranged in each of the plurality of columns; a pixel control unit that controls readout of signals from the plurality of pixels to the plurality of output line groups in units of the row; an amplitude limiting unit that limits a range of signal amplitudes that can be taken by signals output to the plurality of output line groups, the pixel control unit is configured to execute a first scan that sequentially reads out signals of pixels connected to the first output line of each column in units of the row, and a second scan that sequentially reads out signals of pixels connected to the second output line of each column in units of the row, a period in which a signal from a first pixel is read out to the first output line by the first scanning and a period in which a signal from a second pixel connected to the second output line adjacent to the first output line connected to the first pixel is read out to the second output line by the second scanning overlap each other; The amplitude limiting unit is configured to limit a range of a signal amplitude in the first output line and the second output line so that a maximum signal amplitude in the first output line and a maximum signal amplitude in the second output line are different when reading out from the first pixel and the second pixel. A photoelectric conversion device characterized by:

2. each of the plurality of pixels includes a floating diffusion region to which charges of the photoelectric conversion region are transferred, an amplifying transistor that outputs a signal according to a potential of the floating diffusion region to a corresponding output line, and a reset transistor that resets a potential of the floating diffusion region; The pixel control unit sets a gate potential when controlling the reset transistor of the first pixel to a non-reset state and a gate potential when controlling the reset transistor of the second pixel to a non-reset state to different potentials, thereby causing the reset transistor to function as the amplitude limiting unit.

2. The photoelectric conversion device according to claim 1.

3. the gate potential when the reset transistor of the first pixel is controlled to the non-reset state is deeper than the gate potential when the reset transistor of the second pixel is controlled to the non-reset state, relative to the gate potential when the reset transistor of the first pixel is controlled to the reset state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line.

3. The photoelectric conversion device according to claim 2.

4. Each of the plurality of pixels further includes a capacitance switching transistor connected to the floating diffusion portion, The pixel control unit causes the reset transistor to function as the amplitude limiting unit when controlling the capacitance switching transistor to be in an on state.

3. The photoelectric conversion device according to claim 2.

5. each of the plurality of pixels includes a floating diffusion region to which charges of the photoelectric conversion region are transferred, an amplifying transistor that outputs a signal corresponding to a potential of the floating diffusion region to a corresponding output line among the plurality of output line groups, and a capacitance switching transistor connected to the floating diffusion region; The pixel control unit sets a gate potential when controlling the capacitance switching transistor of the first pixel to an off state and a gate potential when controlling the capacitance switching transistor of the second pixel to an off state to different potentials, thereby causing the capacitance switching transistor to function as the amplitude limiting unit.

2. The photoelectric conversion device according to claim 1.

6. the gate potential when the capacitance switching transistor of the first pixel is controlled to be in the off state is deeper than the gate potential when the capacitance switching transistor of the second pixel is controlled to be in the off state, relative to the gate potential when the capacitance switching transistor of the first pixel is controlled to be in the on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line.

6. The photoelectric conversion device according to claim 5.

7. Each of the plurality of pixels further includes a reset transistor that resets the potential of the floating diffusion portion, The capacitance switching transistor is connected between the reset transistor and the floating diffusion region.

6. The photoelectric conversion device according to claim 5.

8. The capacitance switching transistor is connected between the floating diffusion and a ground voltage node.

6. The photoelectric conversion device according to claim 5.

9. the photoelectric conversion unit of each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit configured to receive light that has passed through different pupil regions of one microlens; the amplitude limiting unit limits ranges of signal amplitudes in the first output line and the second output line such that the maximum signal amplitude in the first output line and the maximum signal amplitude in the second output line are equal when reading out signals based on charges of the first photoelectric conversion unit from the first pixel and the second pixel; The amplitude limiting unit limits a range of the signal amplitude in the first output line and the second output line so that the maximum signal amplitude in the first output line and the maximum signal amplitude in the second output line are different when reading out signals based on the charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel.

2. The photoelectric conversion device according to claim 1.

10. the amplitude limiting unit includes a plurality of amplitude limiting circuits provided corresponding to the plurality of output lines, each having an amplitude limiting transistor connected between a node to which a fixed voltage is supplied and the corresponding output line; When reading out from the first pixel and the second pixel, the amplitude limiting unit sets a gate potential to be supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential to be supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line to different potentials.

2. The photoelectric conversion device according to claim 1.

11. the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line when reading out from the first pixel and the second pixel is deeper than the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line with respect to a predetermined gate potential that controls the amplitude limiting transistor to an on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line.

11. The photoelectric conversion device according to claim 10.

12. the photoelectric conversion unit of each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit configured to receive light that has passed through different pupil regions of one microlens; when reading out signals based on the charge of the first photoelectric conversion unit from the first pixel and the second pixel, a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line are set to the same potential; When reading out signals based on the charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel, a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line and a gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line are set to different potentials.

11. The photoelectric conversion device according to claim 10.

13. the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the first output line when reading out signals based on the charges of the first photoelectric conversion unit and the second photoelectric conversion unit from the first pixel and the second pixel is deeper than the gate potential supplied to the amplitude limiting transistor of the amplitude limiting circuit connected to the second output line with respect to a predetermined gate potential that controls the amplitude limiting transistor to an on state; The maximum signal amplitude on the first output line is greater than the maximum signal amplitude on the second output line.

13. The photoelectric conversion device according to claim 12.

14. The signal output to the first output line is a display signal, and the signal output to the second output line is a sensing signal.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

15. The pixel control unit is configured to perform the second scanning on the plurality of pixels a plurality of times while performing the first scanning on the plurality of pixels once.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

16. further comprising a circuit for applying gain to the signals output to the group of output lines; When the gain is a first gain, a difference between a maximum signal amplitude of the first output line in the first scan and a maximum signal amplitude of the second output line in the second scan is a first difference; When the gain is a second gain greater than the first gain, a difference between a maximum signal amplitude of the first output line in the first scan and a maximum signal amplitude of the second output line in the second scan is a second difference that is greater than the first difference; 16. The photoelectric conversion device according to claim 15.

17. The length of a period during which the first scanning is performed on the plurality of pixels is the same as the length of a period during which the second scanning is performed on the plurality of pixels.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

18. The first output line to which the first pixel is connected and the second output line to which the second pixel is connected are arranged in the same column.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

19. The first output line to which the first pixel is connected and the second output line to which the second pixel is connected are arranged in adjacent columns.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

20. The photoelectric conversion device according to any one of claims 1 to 13, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

21. A mobile object, The photoelectric conversion device according to any one of claims 1 to 13, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

22. The photoelectric conversion device according to any one of claims 1 to 13, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

23. A method for driving a photoelectric conversion device having a plurality of pixels arranged in a plurality of rows and a plurality of columns, each pixel including a photoelectric conversion unit, and a plurality of output line groups arranged in each of the plurality of columns, each output line group including at least a first output line and a second output line, the method comprising: When a first scan for sequentially reading out signals from pixels connected to the first output line of each column in units of rows and a second scan for sequentially reading out signals from pixels connected to the second output line of each column in units of rows are performed, if a period for reading out signals from first pixels by the first scan overlaps with a period for reading out signals from second pixels connected to the first output line connected to the first pixel and the second output line adjacent to the first output line connected to the first pixel by the second scan, the ranges of the signal amplitudes on the first output line and the second output line are limited so that a maximum signal amplitude on the first output line and a maximum signal amplitude on the second output line are different. A method for driving a photoelectric conversion device.

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