Photoelectric conversion device and control method for the same

Abstract

To provide a photoelectric conversion device and a control method for the same, being able to suppress the image deterioration while suppressing crosstalk.SOLUTION: A photoelectric conversion device includes a plurality of pixels each including a photoelectric conversion unit, an input node, a transfer transistor, an amplification transistor, and a clip transistor. The clip transistor can switch a first operation in which a first voltage is supplied to a gate of the clip transistor in a first period of AD-converting a reset signal and a second period of AD-converting a pixel signal and a second voltage that is higher than the first voltage is supplied to the gate of the clip transistor in a transfer period in which the transfer transistor is on, and a second operation in which a third voltage that is higher than the first voltage is supplied to the gate of the clip transistor in the first period and the second period and a fourth voltage that is higher than the second voltage and the third voltage is supplied to the gate of the clip transistor in the transfer period.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a control method thereof. [Background technology]

[0002] Conventionally, imaging devices used in digital cameras, smartphones, etc. have sometimes been equipped with clipping transistors that clip pixel output in order to reduce the impact on peripheral areas when strong light is incident on a portion of the imaging surface. The imaging device disclosed in Patent Document 1 is capable of selecting whether to prioritize suppressing crosstalk or maintaining the dynamic range by switching the gate voltage of a reset transistor that functions as a clipping transistor. The imaging device disclosed in Patent Document 1 is configured to increase the gate voltage to increase the clip level only during the conduction period of a transfer gate that transfers electric charges. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-150115 Summary of the Invention [Problem to be solved by the invention]

[0004] However, although the imaging device of Patent Document 1 suppresses crosstalk by increasing the clip level when transferring electric charges, this can result in degradation of image quality.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a photoelectric conversion device and a control method thereof that can suppress crosstalk and image quality degradation. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a plurality of pixels each having a photoelectric conversion unit that accumulates charge according to incident light, an input node that holds the charge, a transfer transistor that transfers the charge from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charge of the input node, and a clip transistor that clips the voltage of the input node; and an AD conversion circuit that, in a first period, AD converts the pixel signal when the input node is reset, and, in a second period, AD converts the pixel signal based on the charge according to the incident light, A photoelectric conversion device is provided that is switchable between a first operation in which a first voltage is supplied to the gate of the clip transistor during the second period, and a second voltage higher than the first voltage is supplied to the gate of the clip transistor during a transfer period after the first period and before the second period in which the transfer transistor is on, and a second operation in which a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage and the third voltage is supplied to the gate of the clip transistor during the transfer period.

[0007] According to one disclosure of the present specification, there is provided a method for controlling a photoelectric conversion device including a photoelectric conversion unit that accumulates charges corresponding to incident light, an input node that holds the charges, a plurality of pixels each having a transfer transistor that transfers the charges from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charges of the input node, and a clip transistor that clips a voltage of the input node, and an AD conversion circuit that performs AD conversion on the pixel signal when the input node is reset during a first period, and performs AD conversion on the pixel signal based on the charges corresponding to the incident light during a second period, and a second operation in which a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage is supplied to the gate of the clip transistor during the transfer period. [Effects of the Invention]

[0008] According to the present invention, it is possible to realize a photoelectric conversion device and a control method thereof that can suppress image quality degradation while suppressing crosstalk. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a unit pixel according to a first embodiment. [Figure 3] 1 is a circuit diagram showing a configuration example of a buffer circuit according to a first embodiment. [Figure 4] 5 is a timing chart showing an example of operation in a high illuminance drive mode of the photoelectric conversion device according to the first embodiment. [Figure 5] 5 is a timing chart showing an example of operation in a low illuminance drive mode of the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 10 is a circuit diagram showing an example of the configuration of a unit pixel according to a second embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a configuration example of a buffer circuit according to a second embodiment. [Figure 8] 10 is a timing chart showing an example of operation in a low-gain, high-illuminance drive mode of the photoelectric conversion device according to the second embodiment. [Figure 9] 10 is a timing chart showing an example of operation in a low-gain, low-illuminance drive mode of the photoelectric conversion device according to the second embodiment. [Figure 10] 10 is a timing chart showing an example of operation of the photoelectric conversion device according to the second embodiment in a medium-gain, high-illuminance drive mode. [Figure 11] 10 is a timing chart showing an example of operation in a medium-gain low-illuminance drive mode of the photoelectric conversion device according to the second embodiment. [Figure 12] 10 is a timing chart showing an example of operation in a high-gain, high-illuminance drive mode of the photoelectric conversion device according to the second embodiment. [Figure 13] 10 is a timing chart showing an example of operation in a high-gain low-illuminance drive mode of the photoelectric conversion device according to the second embodiment. [Figure 14] FIG. 10 is a block diagram showing a schematic configuration of an imaging system according to a third embodiment. [Figure 15] FIG. 10 is a diagram illustrating an example of the configuration of an imaging system and a moving object according to a fourth embodiment. [Figure 16] FIG. 11 is a block diagram showing a schematic configuration of a device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment will be described with reference to Fig. 1 to Fig. 5. First, the schematic configuration of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0011] 1, the photoelectric conversion device according to this embodiment includes a pixel section 10, a vertical scanning circuit 20, a plurality of buffer circuits 30, and a plurality of column signal line clipping circuits 40. The photoelectric conversion device further includes a plurality of current sources 50, an AD (Analog-to-Digital) conversion section 60, a horizontal scanning circuit 70, a signal processing circuit 80, and a timing control section 90.

[0012] The pixel section 10 is provided with a plurality of unit pixels 11 arranged in an array of a plurality of rows and a plurality of columns. The number of unit pixels 11 constituting the pixel section 10 is not particularly limited. For example, the pixel section 10 may be constituted by a plurality of unit pixels 11 arranged in an array of several thousand rows and several thousand columns, as in a general digital camera. Alternatively, the pixel section 10 may be constituted by a plurality of unit pixels 11 arranged in one row or one column. Alternatively, the pixel section 10 may be constituted by a single unit pixel 11.

[0013] A control line 12 is arranged in each row of the pixel array of the pixel unit 10, extending in a first direction (the horizontal direction in FIG. 1). The control line 12 is connected to each of the unit pixels 11 arranged in the first direction, and serves as a signal line common to these unit pixels 11. The unit pixels 11 arranged in the same row are controlled by the same control line 12. Each of the control lines 12 may include multiple signal lines for supplying multiple types of control signals to the unit pixels 11. The control lines 12 in each row are connected to a vertical scanning circuit 20.

[0014] Column signal lines 13 are arranged in each column of the pixel array of the pixel unit 10, extending in a second direction (vertical direction in FIG. 1 ) intersecting the first direction. The column signal lines 13 are connected to the unit pixels 11 arranged in the second direction, respectively, and serve as signal lines common to these unit pixels 11. A plurality of column signal lines 13 (e.g., two) are arranged per column, and the unit pixels 11 in even rows and the unit pixels 11 in odd rows are connected to the same column signal line 13. Each column signal line 13 may include a plurality of signal lines for transferring signals output from the unit pixels 11. The column signal lines 13 of each column are connected to an AD conversion unit 60. Each unit pixel 11 converts incident light into an electrical signal and outputs the converted electrical signal to the AD conversion unit 60 via the column signal line 13. More specifically, each unit pixel 11 outputs a reset signal (pixel signal) before transferring charges generated by the photoelectric conversion unit and a pixel signal after transferring charges from the photoelectric conversion unit. The circuit configuration of the unit pixel 11 will be described later with reference to FIG.

[0015] The vertical scanning circuit 20 has a function of receiving a control signal output from the timing control unit 90, generating a control signal for driving the unit pixels 11, and supplying the control signal to the unit pixels 11 via the buffer circuit 30 and the control line 12. The vertical scanning circuit 20 may use logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 sequentially scans the unit pixels 11 in the pixel unit 10 two rows at a time, and outputs the pixel signal of each unit pixel 11 to the AD conversion unit 60 via the column signal line 13, thereby acquiring one frame of an image.

[0016] The plurality of buffer circuits 30 function as a circuit for amplifying the control signal output from the vertical scanning circuit 20, and also have a function for converting the signal between high and low levels. Each of the plurality of buffer circuits 30 is arranged for each control line 12. The buffer circuits 30 will be described later with reference to FIG. 3.

[0017] The column signal line clipping circuits 40 are known clipping circuits and have the function of limiting the amplitude of pixel signals transmitted to the column signal lines 13 to a predetermined voltage (VL clip level). Each of the column signal line clipping circuits 40 is provided for a corresponding column signal line 13. Each column signal line clipping circuit 40 includes a source follower amplifier, and when the voltage of the column signal line 13 due to the unit pixel 11 falls below the VL clip level based on the input voltage of the source follower amplifier, the source follower amplifier causes a current to flow through the column signal line 13. This prevents the voltage of the column signal line 13 from falling below the VL clip level. The VL clip level is controlled to be different when a reset signal is read out from when a pixel signal is read out. Control of the VL clip level will be described later with reference to FIGS. 4 and 5.

[0018] The current sources 50 have a function of supplying bias current. The current sources 50 are arranged for each column signal line 13, and supply the bias current to an amplification transistor M3 (source follower amplifier) ​​of the unit pixel 11, which will be described later, via the column signal line 13.

[0019] The AD conversion unit 60 includes a plurality of AD conversion circuits 61 and a plurality of memories 62. The plurality of AD conversion circuits 61 are arranged for respective column signal lines 13, and convert analog signals (reset signals, pixel signals) supplied from the unit pixels 11 via the column signal lines 13 into digital signals. The AD conversion circuits 61 output the converted digital signals to the memories 62.

[0020] The plurality of memories 62 have the function of storing digital signals. Each of the plurality of memories 62 is arranged for each AD conversion circuit 61. The memory 62 includes a plurality of unit memories, and stores the reset signals and pixel signals that have been AD converted by the AD conversion circuit 61.

[0021] The horizontal scanning circuit 70 has a function of receiving a control signal output from the timing control unit 90 and outputting the signals stored in the memories 62. Logic circuits such as a shift register and an address decoder may be used for the horizontal scanning circuit 70. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the reset signals and pixel signals held in each memory 62 to the signal processing circuit 80.

[0022] The signal processing circuit 80 has a function of processing digital signals. The signal processing circuit 80 subtracts the reset signal from the pixel signal, extracts only the signal corresponding to the amount of incident light, and outputs it to the outside of the photoelectric conversion device.

[0023] The timing control unit 90 has the function of controlling the operation and timing of the components. The timing control unit 90 generates control signals that control the operation and timing of the vertical scanning circuit 20, the AD conversion unit 60, the horizontal scanning circuit 70, and the signal processing circuit 80, and supplies the generated control signals to each component. The timing control unit 90 can be configured by various electronic components such as a CPU and memory.

[0024] Next, the configuration of the unit pixel 11 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the configuration of the unit pixel 11 according to this embodiment. The unit pixel 11 converts incident light into an electrical signal and outputs it. The unit pixel 11 has a photoelectric conversion element PD as a photoelectric conversion section, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

[0025] The photoelectric conversion element PD is, for example, a photodiode that accumulates charge in response to incident light. The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode of the photoelectric conversion element PD is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source (first main node) of the reset transistor M2 and the gate of the amplification transistor M3. An input node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion that stores charge. The floating diffusion capacitance includes PN junction capacitance, wiring capacitance, etc. The coefficient of charge-to-voltage conversion by the floating diffusion portion is determined by a capacitance Cfd composed of the floating diffusion capacitance, etc.

[0026] The drain (second main node) of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage node (power supply voltage line) to which a voltage VDD is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the column signal line 13.

[0027] 2, the control lines 12 in each row include a signal line connected to the gate of the transfer transistor M1, a signal line connected to the gate of the reset transistor M2, and a signal line connected to the gate of the selection transistor M4. Multiple unit pixels 11 in the same row are connected to a common signal line and are simultaneously controlled by a common control signal.

[0028] A control signal φTX_O is supplied to the gate of the transfer transistor M1 via a buffer circuit (not shown) from the vertical scanning circuit 20. When the control signal φTX_O is at a high level, the transfer transistor M1 is turned on, and when the control signal φTX_O is at a low level, the transfer transistor M1 is turned off.

[0029] A control signal φSEL_O is supplied to the gate of the selection transistor M4 via a buffer circuit (not shown) from the vertical scanning circuit 20. When the control signal φSEL_O is at a high level, the selection transistor M4 is turned on, and when it is at a low level, the selection transistor M4 is turned off.

[0030] A control signal φRES_O is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 20 via the buffer circuit 30. When the control signal φRES_O is at a high level, the reset transistor M2 is turned on, and when it is at a low level, the reset transistor M2 is turned off. Here, the control signal φRES_O can cause the reset transistor M2 to function as a clip transistor that clips the voltage of the input node FD. In other words, the control signal φRES_O can cause the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level (clip level) that corresponds to the gate voltage of the reset transistor M2.

[0031] In this embodiment, the description will be given assuming that electrons, among electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the unit pixel 11 may be configured as an N-type MOS transistor. When each transistor is configured as an N-type MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning circuit 20. Furthermore, the corresponding transistor is turned off when a low-level control signal is supplied from the vertical scanning circuit 20. However, the signal charges are not limited to electrons; holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor or the function of interest. Some or all of the names of the source and drain used in this embodiment may be reversed.

[0032] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the input node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the input node FD. As a result, the input node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0033] The selection transistor M4 selectively connects the unit pixels 11 of the row to be read out of the unit pixels 11 constituting the pixel section 10 to the column signal line 13 by switching it on and off. When the selection transistor M4 is turned on, it connects the amplification transistor M3 of the unit pixels 11 of the row to be read out to the column signal line 13. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source 50 via the selection transistor M4, forming an amplification circuit (source follower circuit) with its gate serving as an input node FD. As a result, the amplification transistor M3 outputs a signal based on the charge at the input node FD to the column signal line 13 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output section that outputs a pixel signal according to the amount of charge held at the input node FD.

[0034] The reset transistor M2 has the function of supplying a voltage (voltage VDD) to the input node FD to reset the input node FD, which serves as a charge storage unit. When the reset transistor M2 is turned on, it resets the input node FD to a voltage corresponding to the voltage VDD. Furthermore, when the voltage of the input node FD falls below the gate threshold voltage of the reset transistor M2 due to the charge transferred from the photoelectric conversion element PD, the reset transistor M2 turns on and the charge of the input node FD is discharged to the power supply (voltage VDD). This discharge of charge stops at a voltage that is lower than the gate voltage of the reset transistor M2 by the threshold voltage, so the reset transistor M2 functions as a clip transistor that limits the amplitude at the FD clip level corresponding to the gate voltage.

[0035] As described above, the unit pixel 11 can sequentially output a reset signal based on the state in which the potential of the input node FD is reset by the reset transistor M2, and a pixel signal whose signal level is based on the charge generated by the photoelectric conversion performed in the photoelectric conversion element PD.

[0036] The circuit configuration of the unit pixel 11 is not limited to the configuration shown in Figure 2. For example, the selection transistor M4 may be connected between the power supply voltage node to which the voltage VDD is supplied and the amplification transistor M3. The circuit configuration shown in Figure 2 is a so-called four-transistor type including the transfer transistor M1, the reset transistor M2, the amplification transistor M3, and the selection transistor M4, but is not limited to this. For example, a three-transistor circuit configuration may be used in which the selection transistor M4 is omitted and the amplification transistor M3 also functions as the selection transistor. A five-transistor or more circuit configuration having more transistors than that shown in Figure 2 may also be used.

[0037] Next, the configuration of the buffer circuit 30 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing an example configuration of the buffer circuit 30 according to this embodiment. The buffer circuit 30 not only functions as a circuit that amplifies the control signal output from the vertical scanning circuit 20, but also converts the signal between high and low levels. As shown in Fig. 3, the buffer circuit 30 has an inverter 31 and transistors M7, M8, and M9.

[0038] The inverter 31 includes a P-type MOS transistor M5 and an N-type MOS transistor M6.

[0039] The P-type MOS transistor M5 has a gate connected to the vertical scanning circuit 20, and a control signal φRESn is output from the vertical scanning circuit 20. The P-type MOS transistor M5 also has a source connected to a power supply (voltage VRESH) and a drain connected to the drain of the N-type MOS transistor M6 and the gate of the reset transistor M2.

[0040] The N-type MOS transistor M6 has a gate connected to the vertical scanning circuit 20, and a control signal φRESn is output from the vertical scanning circuit 20. The N-type MOS transistor M6 has a drain connected to the drain of the P-type MOS transistor M5 and the gate of the reset transistor M2, and a source connected to the sources of the transistors M7, M8, and M9.

[0041] The transistor M7 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL0 is output from the vertical scanning circuit 20. The transistor M7 has a drain connected to a power supply (voltage VRESL0), and a source connected to the source of the N-type MOS transistor M6 of the inverter 31. When a high-level control signal φRESL0 is output, the transistor M7 turns on and supplies a voltage VRESL0 (e.g., 0 V) ​​to the inverter 31. When a low-level control signal φRESL0 is output, the transistor M7 turns off and does not supply the voltage VRESL0 (e.g., 0 V) ​​to the inverter 31. The voltage VRESL0 is an example of a first voltage.

[0042] The transistor M8 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL1 is output from the vertical scanning circuit 20. The transistor M8 has a drain connected to a power supply (voltage VRESL1), and a source connected to the source of the N-type MOS transistor M6 of the inverter 31. When a high-level control signal φRESL1 is output, the transistor M8 turns on and supplies a voltage VRESL1 (e.g., 0.6 V) to the inverter 31. When a low-level control signal φRESL1 is output, the transistor M8 turns off and does not supply the voltage VRESL1 (e.g., 0.6 V) to the inverter 31. The voltage VRESL1 is an example of a second voltage or a third voltage.

[0043] The transistor M9 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL2 is output from the vertical scanning circuit 20. The transistor M9 has a drain connected to a power supply (voltage VRESL2) and a source connected to the source of the N-type MOS transistor M6 of the inverter 31. When a high-level control signal φRESL2 is output, the transistor M9 turns on and supplies a voltage VRESL2 (e.g., 1.2 V) to the inverter 31. When a low-level control signal φRESL2 is output, the transistor M9 turns off and does not supply the voltage VRESL2 (e.g., 1.2 V) to the inverter 31. The voltage VRESL2 is an example of a fourth voltage.

[0044] As described above, the buffer circuit 30 is configured to be able to switch the low level of the inverter 31 between three levels (0 V, 0.6 V, 1.2 V) by switching the control signals φRESL0, φRESL1, and φRESL2. In the buffer circuit 30, when the control signal φRESn output from the vertical scanning circuit 20 to the inverter 31 is low, the P-type MOS transistor M5 is turned on. A high level (voltage VRESH) is supplied as the control signal φRES_O to the reset transistor M2. On the other hand, when the control signal φRESn output from the vertical scanning circuit 20 to the inverter 31 is high, the N-type MOS transistor M6 is turned on. A low level (one of voltages VRESL0, VRESL1, and VRESL2) is supplied as the control signal φRES_O to the reset transistor M2. In this way, the buffer circuit 30 performs logic inversion and amplification of the control signal φRESn using the inverter 31, and supplies the control signal φRES_O to the reset transistor M2 of each unit pixel 11.

[0045] Next, an example of the operation of the photoelectric conversion device will be described. The photoelectric conversion device has two operations: a high-illuminance drive mode (first operation) that can be selected when the illuminance is high, and a low-illuminance drive mode (second operation) that can be selected when the illuminance is low. The two operations can be selected during image capture. Switching between the first and second operations may be performed by external control of the photoelectric conversion device, or by internal control of the photoelectric conversion device. For example, internal control of the photoelectric conversion device may involve operating in one of the first and second operations, and then switching to the other of the first and second operations if the obtained signal level is not within a desired range. Alternatively, the first and second operations may be periodically switched by internal control of the photoelectric conversion device. First, the high-illuminance drive mode will be described. FIG. 4 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the high-illuminance drive mode.

[0046] In the figure, φRESL2, φRESL1, φRESL0, and φRESn denote control signals to the buffer circuit 30, and φRES_O is generated by these control signals. In the figure, φSEL_O, φTX_O, and φRES_O denote control signals supplied to the unit pixel 11 to be read out of the pixel section 10. The figure shows an example of the voltage of the column signal line 13 when high-intensity light is incident on the unit pixel 11, causing charge to overflow from the photoelectric conversion element PD to the input node FD. In the figure, the FD clip level due to the gate voltage of the reset transistor M2 is indicated by a dashed line, and the VL clip level due to the column signal line clip circuit 40 is schematically indicated by a dotted line. In the figure, the timing of AD conversion of the reset signal is indicated by "N conversion," and the timing of AD conversion of the pixel signal is schematically indicated by "S conversion."

[0047] 4, the control signal φRESn is at a low level, and therefore the control signal φRES_O output from the buffer circuit 30 is at a high level (voltage VRESH). As a result, the voltage VRESH is supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0048] 4, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0049] At time t2, the vertical scanning circuit 20 changes the control signal φRESn from low to high. This turns on the N-type MOS transistor M6 of the buffer circuit 30, and the control signal φRES_O output from the buffer circuit 30 goes low. At this time, the control signals φRESL1 and φRESL2 are low and the control signal φRESL0 is high, so the transistors M8 and M9 of the buffer circuit 30 are off and the transistor M7 is on. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied to the gate of the reset transistor M2 via the transistor M7 as the control signal φRES_O. This turns off the reset transistor M2 of the unit pixel 11, and the input node FD goes into a floating state, disconnected from the power supply (voltage VDD).

[0050] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2 to time t6), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0051] From time t3 to time t4 (first period), the AD conversion circuit 61 AD converts the reset signal at the time of resetting the input node FD and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0052] At time t5, the vertical scanning circuit 20 changes the control signal φRESL0 from High to Low and changes the control signal φRESL1 from Low to High. This turns off the transistor M7 of the buffer circuit 30 and turns on the transistor M8. As a result, a voltage VRESL1 (e.g., 0.6 V) is supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M8. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also increases as the voltage of the control signal φRES_O increases from VRESL0 (e.g., 0 V) ​​to VRESL1 (e.g., 0.6 V).

[0053] At time t6, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6, the vertical scanning circuit 20 changes the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The drop in the voltage of the input node FD temporarily turns on the reset transistor M2, and the voltage of the input node FD is limited to the FD clip level based on VRESL1. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0054] At time t7, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0055] At time t8, the vertical scanning circuit 20 changes the control signal φRESL1 from high to low and the control signal φRESL0 from low to high. This turns off the transistor M8 in the buffer circuit 30 and turns on the transistor M7. As a result, a voltage VRESL0 (e.g., 0 V) ​​is supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M7. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also drops as the voltage of the control signal φRES_O drops from VRESL1 (e.g., 0.6 V) to VRESL0 (e.g., 0 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0056] At time t9, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL0. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES1 and VRESL0. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL1.

[0057] Between time t10 and time t11 (second period), the AD conversion circuit 61 performs AD conversion on pixel signals based on charges corresponding to incident light, and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62, and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals, extracts only the signals corresponding to the amount of incident light, and outputs them to the outside of the photoelectric conversion device.

[0058] At time t12, the vertical scanning circuit 20 changes the control signal φRESn from High to Low. This turns on the P-type MOS transistor M5 of the buffer circuit 30, and the control signal φRES_O output from the buffer circuit 30 becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0059] At time t13, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the readout of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the high illuminance drive mode, the FD clip level is controlled by switching the Low level of the control signal φRES_O between VRESL0 and VRESL1.

[0060] Next, the low illumination drive mode will be described. The low illumination drive mode differs from the high illumination drive mode shown in Fig. 4 in that the FD clip level is increased, but other processes are similar. Fig. 5 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the low illumination drive mode.

[0061] In the figure, φSEL_O, φTX_O, and φRES_O denote control signals supplied to the unit pixel 11 to be read out of the pixel section 10. Also in the figure, φRESL2, φRESL1, φRESL0, and φRESn denote control signals for the buffer circuit 30, which generate φRES_O. The figure shows an example of the voltage of the column signal line 13 when high-intensity light is incident on the unit pixel 11, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Also in the figure, the FD clip level due to the gate voltage of the reset transistor M2 is indicated by a dashed line, and the VL clip level due to the column signal line clip circuit 40 is schematically indicated by a dashed line. Also in the figure, the timing of AD conversion of the reset signal is indicated by "N conversion," and the timing of AD conversion of the pixel signal is schematically indicated by "S conversion."

[0062] 5, the control signal φRESn is at a low level, and therefore the control signal φRES_O output from the buffer circuit 30 is at a high level (voltage VRESH). As a result, the voltage VRESH is supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0063] 4, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0064] At time t2a, the vertical scanning circuit 20 changes the control signal φRESn from low to high. This turns on the N-type MOS transistor M6 of the buffer circuit 30, and the control signal φRES_O output from the buffer circuit 30 goes low. At this time, the control signals φRESL0 and φRESL2 are low and the control signal φRESL1 is high, so the transistors M7 and M9 of the buffer circuit 30 are off and the transistor M8 is on. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied to the gate of the reset transistor M2 via the transistor M8 as the control signal φRES_O. This turns off the reset transistor M2 of the unit pixel 11, and the input node FD goes into a floating state, disconnected from the power supply (voltage VDD).

[0065] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2a to time t6a), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0066] From time t3a to time t4a (first period), the AD conversion circuit 61 AD converts the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0067] At time t5a, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL2 from Low to High. This turns off the transistor M8 in the buffer circuit 30 and turns on the transistor M9. As a result, a voltage VRESL2 (e.g., 1.2 V) is supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M9. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 1.2 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also increases as the voltage of the control signal φRES_O increases from VRESL1 (e.g., 0.6 V) to VRESL2 (e.g., 1.2 V).

[0068] At time t6a, the column signal line clip circuit 40 lowers the VL clip level below the FD clip level. At the same time t6a, the vertical scanning circuit 20 controls the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The drop in the voltage of the input node FD temporarily turns on the reset transistor M2, and the voltage of the input node FD is limited to the FD clip level based on VRESL2. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0069] At time t7a, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0070] At time t8a, the vertical scanning circuit 20 changes the control signal φRESL2 from high to low and the control signal φRESL1 from low to high. This turns off the transistor M9 in the buffer circuit 30 and turns on the transistor M8. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M8. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also drops as the voltage of the control signal φRES_O drops from VRESL2 (e.g., 1.2 V) to VRESL1 (e.g., 0.6 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0071] At time t9a, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL1. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES2 and VRESL1. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL2.

[0072] From time t10a to time t11a (second period), the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0073] At time t12a, the vertical scanning circuit 20 changes the control signal φRESn from High to Low. This turns on the P-type MOS transistor M5 of the buffer circuit 30, and the control signal φRES_O output from the buffer circuit 30 becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0074] At time t13a, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the readout of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the low illuminance drive mode, the FD clip level is controlled by switching the Low level of the control signal φRES_O between VRESL1 and VRESL2.

[0075] As described above, according to the photoelectric conversion device and the control method thereof of this embodiment, the reset transistor M2 operating as a clipping transistor can switch between a low-illuminance drive mode and a high-illuminance drive mode. In the high-illuminance drive mode, a voltage VRESL0 is supplied to the gate of the reset transistor M2 during a period in which the reset signal and the pixel signal are AD converted. Furthermore, during a charge transfer period in which the transfer transistor M1 is on, which is after the period in which the reset signal is AD converted and before the period in which the pixel signal is AD converted, a voltage VRESL1 higher than the voltage VRESL0 is supplied to the gate of the reset transistor M2. In the low-illuminance drive mode, a voltage VRESL1 higher than the voltage VRESL0 is supplied to the gate of the reset transistor M2 during a period in which the reset signal and the pixel signal are AD converted. Furthermore, during a charge transfer period in which the transfer transistor M1 is on, a voltage VRESL2 higher than the voltage VRESL1 is supplied to the gate of the reset transistor M2.

[0076] As described above, in the high-illuminance drive mode, the low level of the control signal φRES_O is switched between voltages VRESL0 and VRESL1, and in the low-illuminance drive mode, the low level of the control signal φRES_O is switched between voltages VRESL1 and VRESL2. In the low-illuminance drive mode, voltage VRESL2 is supplied to the gate of the reset transistor M2 during the charge transfer period, so that the amplitude of the column signal line 13 is limited by the FD clip level based on voltage VRESL2 in the illuminance range where charge overflow does not occur after charge transfer. This makes it possible to suppress the impact on peripheral image quality caused by power supply fluctuations due to fluctuations in the column signal line 13 associated with charge transfer.

[0077] Even in shooting conditions where the low-illuminance drive mode is selected, some unit pixels 11 may be exposed to extremely bright light, such as sunlight. Therefore, even in the low-illuminance drive mode, it is necessary to suppress the impact on image quality at high illuminance levels, which can cause charge overflow after charge transfer. In the low-illuminance drive mode, the voltage drop on the column signal line 13 due to a decrease in the FD clip level at high illuminance levels, which can cause charge overflow after charge transfer, is determined by the voltage difference between voltages VRESL1 and VRESL2. The difference between voltages VRESL1 and VRESL2 in the low-illuminance drive mode corresponds to the difference between voltages VRESL0 and VRESL1 in the high-illuminance drive mode. Here, the difference between voltages VRESL1 and VRESL2 is the same as the difference between voltages VRESL0 and VRESL1. In this way, the low level of the control signal φRES_O is increased to voltage VRESL1 during periods other than the charge transfer period in the low-illuminance drive mode. Therefore, the voltage drop width of the column signal line 13 can be reduced compared to when the control signal φRES_O is raised to the low level only during the charge transfer period, which makes it possible to prevent the effects on peripheral image quality caused by power supply fluctuations due to fluctuations in the column signal line 13 caused by charge overflow after charge transfer and the effects of crosstalk caused by parasitic capacitance between multiple column signal lines 13 from worsening in the low-illuminance drive mode.

[0078] Furthermore, in the photoelectric conversion device according to this embodiment, the low level of the control signal φRES_O during the charge transfer period in the high illuminance drive mode and the low level of the control signal φRES_O during the AD conversion period in the low illuminance drive mode are the same voltage VRESL1, which reduces the number of transistors required to output the low level of the control signal φRES_O, thereby enabling the device to be made more compact.

[0079] Furthermore, in the photoelectric conversion device according to this embodiment, in the high-illuminance drive mode, the period during which voltage VRESL1 is supplied to the gate of the reset transistor M2, which operates as a clipping transistor, is longer than the period during which the transfer transistor M1 is on. Specifically, after voltage VRESL1 is supplied to the gate of the reset transistor M2, the transfer transistor M1 turns on, and after transfer transistor M1 turns off, voltage VRESL0 is supplied to the gate of the reset transistor M2. The period from when the transfer transistor M1 turns off to when voltage VRESL0 is supplied to the gate of the reset transistor M2 is longer than the period from when voltage VRESL1 is supplied to the gate of the reset transistor M2 to when the transfer transistor M1 turns on. This ensures sufficient time for the charge at input node FD to be discharged to the power supply (voltage VDD) during charge transfer.

[0080] Furthermore, in the photoelectric conversion device according to this embodiment, in the low-illuminance drive mode, the period during which the voltage VRESL2 is supplied to the gate of the reset transistor M2, which operates as a clipping transistor, is longer than the period during which the transfer transistor M1 is on. Specifically, after the voltage VRESL2 is supplied to the gate of the reset transistor M2, the transfer transistor M1 turns on, and after the transfer transistor M1 turns off, the voltage VRESL1 is supplied to the gate of the reset transistor M2. The period from when the transfer transistor M1 turns off to when the voltage VRESL1 is supplied to the gate of the reset transistor M2 is longer than the period from when the voltage VRESL2 is supplied to the gate of the reset transistor M2 to when the transfer transistor M1 turns on. This ensures sufficient time for the charge at the input node FD to be discharged to the power supply (voltage VDD) during charge transfer.

[0081] Furthermore, in the photoelectric conversion device according to this embodiment, the AD conversion circuit 61 simultaneously A / D converts pixel signals output from a plurality of unit pixels 11 in a plurality of rows, thereby improving the processing speed of the photoelectric conversion device.

[0082] Furthermore, in the photoelectric conversion device according to this embodiment, the FD clip level is lower than the VL clip level during the AD conversion period of the reset signal, and the FD clip level is higher than the VL clip level during the charge transfer period and the AD conversion period of the pixel signal. This allows the amplitude of the reset signal to be limited by the VL clip level, and the amplitude of the pixel signal to be limited by the FD clip level.

[0083] [Second embodiment] A photoelectric conversion device according to a second embodiment and a driving method thereof will be described with reference to FIGS. 6 to 13. First, a configuration example of a unit pixel of a photoelectric conversion device according to this embodiment will be described with reference to FIG. 6. FIG. 6 is a circuit diagram showing a configuration example of a unit pixel according to this embodiment. The photoelectric conversion device according to this embodiment differs from the first embodiment in that the capacitance of the input node FD is changeable. In this embodiment, components similar to those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0084] The unit pixel 11A converts incident light into an electrical signal and outputs the electrical signal. As shown in Fig. 6, the unit pixel 11A includes a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, a selection transistor M4, a first capacitance-addition transistor M2a, and a second capacitance-addition transistor M2b.

[0085] The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode of the photoelectric conversion element PD is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source (first main node) of the first capacitance adding transistor M2a and the gate of the amplifying transistor M3. An input node FD, to which the drain of the transfer transistor M1, the source of the first capacitance adding transistor M2a, and the gate of the amplifying transistor M3 are connected, is a so-called floating diffusion portion.

[0086] The drain (second main node) of the first capacitance-addition transistor M2a is connected to the source (first main node) of the second capacitance-addition transistor M2b, and the drain (second main node) of the second capacitance-addition transistor M2b is connected to the source of the reset transistor M2. That is, the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b are provided between the input node FD and the reset transistor M2. The first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b can add capacitance to the input node FD and function as switches that change the capacitance of the input node FD.

[0087] The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage node to which a voltage VDD is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the column signal line 13.

[0088] A control signal φCADD1_O is supplied to the gate of the first capacitance-adding transistor M2a from the vertical scanning circuit 20 via the buffer circuit 30A. When the control signal φCADD1_O is at a high level, the first capacitance-adding transistor M2a is turned on, and when the control signal φCADD1_O is at a low level, the first capacitance-adding transistor M2a is turned off. Here, the control signal φCADD1_O can cause the first capacitance-adding transistor M2a to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level (clip level) corresponding to the gate voltage of the first capacitance-adding transistor M2a.

[0089] A control signal φCADD2_O is supplied to the gate of the second capacitance adding transistor M2b from the vertical scanning circuit 20 via the buffer circuit 30A. When the control signal φCADD2_O is at a high level, the second capacitance adding transistor M2b is turned on, and when it is at a low level, the second capacitance adding transistor M2b is turned off. Here, the control signal φCADD2_O can cause the second capacitance adding transistor M2b to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level (clip level) corresponding to the gate voltage of the second capacitance adding transistor M2b.

[0090] By turning on all of the reset transistor M2, the first capacitance adding transistor M2a, and the second capacitance adding transistor M2b, the input node FD is reset to a voltage corresponding to the voltage VDD.

[0091] On the other hand, the coefficient of charge-voltage conversion by the floating diffusion section can be changed by controlling the on / off of the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b. Specifically, when the first capacitance-addition transistor M2a is turned off, the capacitance of the input node FD becomes Cfd. When the first capacitance-addition transistor M2a is turned on and the second capacitance-addition transistor M2b is turned off, the capacitance of the input node FD increases to Cfd+C1. When the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b are turned on and the reset transistor is turned off, the capacitance of the input node FD further increases to Cfd+C1+C2. In this way, by turning on the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b, the capacitance connected to the input node FD can be increased, thereby changing the coefficient of charge-voltage conversion by the floating diffusion section. That is, the unit pixel 11A is configured to change the coefficient of charge-voltage conversion by changing the capacitance of the input node FD in three stages: "large," "medium," and "small." When the capacitance of the input node FD is "large," the gain in the charge-voltage conversion is "low gain." When the capacitance of the input node FD is "medium," the gain in the charge-voltage conversion is "medium gain." When the capacitance of the input node FD is "small," the gain in the charge-voltage conversion is "high gain."

[0092] Next, the configuration of the buffer circuit 30A will be described with reference to Fig. 7. Fig. 7 is a circuit diagram showing an example configuration of the buffer circuit 30A according to this embodiment. The buffer circuit 30A not only functions as a circuit that amplifies the control signal output from the vertical scanning circuit 20, but also converts the signal between high and low levels. As shown in Fig. 7, the buffer circuit 30A has inverters 31, 31a, and 31b, and transistors M7, M8, and M9.

[0093] The inverter 31a includes a P-type MOS transistor M5a and an N-type MOS transistor M6a.

[0094] The P-type MOS transistor M5a has a gate connected to the vertical scanning circuit 20, and a control signal φCADD1n is output from the vertical scanning circuit 20. The P-type MOS transistor M5a has a source connected to a power supply (voltage VRESH) and a drain connected to the drain of the N-type MOS transistor M6a and the gate of the first capacitance adding transistor M2a.

[0095] The N-type MOS transistor M6a has a gate connected to the vertical scanning circuit 20, and a control signal φCADD1n is output from the vertical scanning circuit 20. The N-type MOS transistor M6a has a drain connected to the drain of the P-type MOS transistor M5a and the gate of the first capacitance adding transistor M2a, and a source connected to the sources of the transistors M7, M8, and M9.

[0096] The inverter 31b includes a P-type MOS transistor M5b and an N-type MOS transistor M6b.

[0097] The P-type MOS transistor M5b has a gate connected to the vertical scanning circuit 20, and a control signal φCADD2n is output from the vertical scanning circuit 20. The P-type MOS transistor M5b has a source connected to a power supply (voltage VRESH) and a drain connected to the drain of the N-type MOS transistor M6b and the gate of the second capacitance adding transistor M2b.

[0098] The N-type MOS transistor M6b has a gate connected to the vertical scanning circuit 20, and a control signal φCADD2n is output from the vertical scanning circuit 20. The N-type MOS transistor M6b has a drain connected to the drain of the P-type MOS transistor M5b and the gate of the second capacitance adding transistor M2b, and a source connected to the sources of the transistors M7, M8, and M9.

[0099] The transistor M7 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL0 is output from the vertical scanning circuit 20. The transistor M7 has a drain connected to a power supply (voltage VRESL0) and a source connected to the sources of the N-type MOS transistors M6, M6a, and M6b. When a high-level control signal φRESL0 is output, the transistor M7 turns on and supplies a voltage VRESL0 (e.g., 0 V) ​​to the inverters 31, 31a, and 31b. When a low-level control signal φRESL0 is output, the transistor M7 turns off and does not supply a voltage VRESL0 (e.g., 0 V) ​​to the inverters 31, 31a, and 31b.

[0100] The transistor M8 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL1 is output from the vertical scanning circuit 20. The transistor M8 has a drain connected to a power supply (voltage VRESL1) and a source connected to the sources of the N-type MOS transistors M6, M6a, and M6b. When a high-level control signal φRESL1 is output, the transistor M8 turns on and supplies a voltage VRESL1 (e.g., 0.6 V) to the inverters 31, 31a, and 31b. When a low-level control signal φRESL1 is output, the transistor M8 turns off and does not supply the voltage VRESL1 (e.g., 0.6 V) to the inverters 31, 31a, and 31b.

[0101] The transistor M9 has a gate connected to the vertical scanning circuit 20, and a control signal φRESL2 is output from the vertical scanning circuit 20. The transistor M9 has a drain connected to a power supply (voltage VRESL2) and a source connected to the sources of the N-type MOS transistors M6, M6a, and M6b. When a high-level control signal φRESL2 is output, the transistor M9 turns on and supplies a voltage VRESL2 (e.g., 1.2 V) to the inverters 31, 31a, and 31b. When a low-level control signal φRESL2 is output, the transistor M9 turns off and does not supply the voltage VRESL2 (e.g., 1.2 V) to the inverters 31, 31a, and 31b.

[0102] As described above, the buffer circuit 30A is configured to be able to switch the Low level of the inverters 31, 31a, and 31b between three levels (0 V, 0.6 V, and 1.2 V) by switching the control signals φRESL0, φRESL1, and φRESL2. In the inverter 31a, when the control signal φCADD1n output from the vertical scanning circuit 20 is at a Low level, the P-type MOS transistor M5a is turned on. Then, a High level (voltage VRESH) is supplied as the control signal φCADD1_O to the gate of the first capacitance-adding transistor M2a. On the other hand, when the control signal φCADD1n output from the vertical scanning circuit 20 is at a High level, the N-type MOS transistor M6a is turned on. Then, a Low level (one of voltages VRESL0, VRESL1, and VRESL2) is supplied as the control signal φCADD1_O to the gate of the first capacitance-adding transistor M2a. In this way, the buffer circuit 30A performs logical inversion and amplification of the control signal φCADD1n by the inverter 31a, and supplies the control signal φCADD1_O to the gate of the first capacitance adding transistor M2a of each unit pixel 11.

[0103] In the inverter 31b, when the control signal φCADD2n output from the vertical scanning circuit 20 is at a low level, the P-type MOS transistor M5b is turned on. Then, a high level (voltage VRESH) is supplied as the control signal φCADD2_O to the gate of the second capacitance adding transistor M2b. On the other hand, when the control signal φCADD2n output from the vertical scanning circuit 20 is at a high level, the N-type MOS transistor M6b is turned on. Then, a low level (one of voltages VRESL0, VRESL1, and VRESL2) is supplied as the control signal φCADD2_O to the gate of the second capacitance adding transistor M2b. In this way, the buffer circuit 30A logically inverts and amplifies the control signal φCADD2n using the inverter 31b, and supplies the control signal φCADD2_O to the gate of the second capacitance adding transistor M2b of each unit pixel 11.

[0104] In this way, the sources of the N-type MOS transistors M6, M6a, and M6b of the inverters 31, 31a, and 31b are connected to the same low-level power supply, which allows the low levels of the control signals φRES_O, φCADD1_O, and φCADD2_O to be switched between three levels: VRESL0, VRESL1, and VRESL2.

[0105] Next, the high-illuminance drive mode and the low-illuminance drive mode will be explained for each of the three gain stages. The photoelectric conversion device has six drive modes depending on the amount of incident light: low-gain high-illuminance drive mode, low-gain low-illuminance drive mode, medium-gain high-illuminance drive mode, medium-gain low-illuminance drive mode, high-gain high-illuminance drive mode, and high-gain low-illuminance drive mode. The six drive modes can be selected during shooting.

[0106] FIG. 8 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the low-gain, high-illuminance drive mode.

[0107] In the figure, φRESL2, φRESL1, φRESL0, and φRESn represent control signals of the buffer circuit 30A, which generate the φRES_O signal. In the figure, φSEL_O, φTX_O, and φRES_O represent control signals supplied to the unit pixel 11 to be read out of the pixel section 10. In the figure, control signals φCADD1n and φCADD2n represent control signals of the buffer circuit 30A, which generate the control signals φCADD1_O and φCADD2_O. In the figure, the control signals φCADD1_O and φCADD2_O represent control signals supplied to the unit pixel 11 to be read out of the pixel section 10, and to the gates of the first and second capacitance addition transistors M2a and M2b. The figure shows an example of the voltage of the column signal line 13 when high-intensity light is incident on the unit pixel 11, causing charge to overflow from the photoelectric conversion element PD to the input node FD. In the figure, the FD clip level due to the gate voltage of each transistor is indicated by a dashed line, and the VL clip level due to the column signal line clip circuit 40 is schematically indicated by a dashed line. In the figure, the timing of AD conversion of the reset signal is indicated by "N conversion," and the timing of AD conversion of the pixel signal is indicated by "S conversion."

[0108] In the low-gain, high-illuminance drive mode, the control signals φCADD1n and φCADD2n are low immediately before time t1b in FIG. 8. Therefore, the control signals φCADD1_O and φCADD2_O output from the buffer circuit 30A are high (voltage VRESH), and the voltage VRESH is supplied to the gates of the first and second capacitance-adding transistors M2a and M2b. This turns on the first and second capacitance-adding transistors M2a and M2b, and the capacitance of the input node FD becomes Cfd+C1+C2 (large capacitance). This results in a low gain in the charge-voltage conversion. Therefore, the amount of charge whose amplitude is limited by the FD clip level increases, enabling pixel signals to be AD-converted without being clipped even for subjects with higher illumination. Because the control signal φRESn is low immediately before time t1b, the control signal φRES_O output from the buffer circuit 30A is high (voltage VRESH). As a result, the voltage VRESH is supplied to the gate of the reset transistor M2, turning the reset transistor M2 on and resetting the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0109] 8, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0110] At time t2b, the vertical scanning circuit 20 changes the control signal φRESn from low to high. This turns on the N-type MOS transistor M6 of the buffer circuit 30A, and the control signal φRES_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL1 and φRESL2 are low and the control signal φRESL0 is high, so the transistors M8 and M9 of the buffer circuit 30A are off and the transistor M7 is on. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied to the gate of the reset transistor M2 via the transistor M7 as the control signal φRES_O. This turns off the reset transistor M2 of the unit pixel 11, and the input node FD goes into a floating state, disconnected from the power supply (voltage VDD).

[0111] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2b to time t6b), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0112] Between time t3b and time t4b, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0113] At time t5b, the vertical scanning circuit 20 changes the control signal φRESL0 from High to Low and changes the control signal φRESL1 from Low to High. This turns off the transistor M7 in the buffer circuit 30A and turns on the transistor M8. As a result, a voltage VRESL1 (e.g., 0.6 V) is supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M8. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also increases as the voltage of the control signal φRES_O increases from VRESL0 (e.g., 0 V) ​​to VRESL1 (e.g., 0.6 V).

[0114] At time t6b, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6b, the vertical scanning circuit 20 changes the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The drop in the voltage of the input node FD temporarily turns on the reset transistor M2, and the voltage of the input node FD is limited to the FD clip level based on VRESL1. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0115] At time t7b, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0116] At time t8b, the vertical scanning circuit 20 changes the control signal φRESL1 from high to low and the control signal φRESL0 from low to high. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M7. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M7. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also drops as the voltage of the control signal φRES_O drops from VRESL1 (e.g., 0.6 V) to VRESL0 (e.g., 0 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0117] At time t9b, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL0. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES1 and VRESL0. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL1.

[0118] Between time t10b and time t11b, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0119] At time t12b, the vertical scanning circuit 20 changes the control signal φRESn from High to Low. This turns on the P-type MOS transistor M5 of the buffer circuit 30A, and the control signal φRES_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD (Cfd+C1+C2) to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0120] At time t13b, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the readout of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of high illuminance driving, the FD clip level is controlled by switching the Low level of the control signal φRES_O between VRESL0 and VRESL1.

[0121] Next, the low-gain, low-illuminance drive mode of the photoelectric conversion device will be described with reference to Fig. 9. Fig. 9 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the low-gain, low-illuminance drive mode. The low-gain, low-illuminance drive mode differs from the low-gain, high-illuminance drive mode shown in Fig. 8 in that the FD clip level is increased, but otherwise similar processing is performed.

[0122] In the low-gain, low-illuminance drive mode, the control signals φCADD1n and φCADD2n are low immediately before time t1c shown in FIG. 9. Therefore, the control signals φCADD1_O and φCADD2_O output from the buffer circuit 30A are high (voltage VRESH), and the voltage VRESH is supplied to the gates of the first and second capacitance-adding transistors M2a and M2b. This turns on the first and second capacitance-adding transistors M2a and M2b, and the capacitance of the input node FD becomes Cfd+C1+C2 (large capacitance). This results in a low gain in the charge-voltage conversion. Therefore, the amount of charge whose amplitude is limited by the FD clip level increases, enabling AD conversion of pixel signals without clipping even for subjects with higher illumination. Because the control signal φRESn is low immediately before time t1c, the control signal φRES_O output from the buffer circuit 30A is high (voltage VRESH). As a result, the voltage VRESH is supplied to the gate of the reset transistor M2, turning the reset transistor M2 on and resetting the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0123] 9, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0124] At time t2c, the vertical scanning circuit 20 changes the control signal φRESn from low to high. This turns on the N-type MOS transistor M6 of the buffer circuit 30A, and the control signal φRES_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL0 and φRESL2 are low and the control signal φRESL1 is high, so the transistors M7 and M9 of the buffer circuit 30A are off and the transistor M8 is on. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied to the gate of the reset transistor M2 via the transistor M8 as the control signal φRES_O. This turns off the reset transistor M2 of the unit pixel 11, and the input node FD goes into a floating state, disconnected from the power supply (voltage VDD).

[0125] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2c to time t6c), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0126] Between time t3c and time t4c, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0127] At time t5c, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL2 from Low to High. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M9. As a result, a voltage VRESL2 (e.g., 1.2 V) is supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M9. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 1.2 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also increases as the voltage of the control signal φRES_O increases from VRESL1 (e.g., 0.6 V) to VRESL2 (e.g., 1.2 V).

[0128] At time t6c, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6c, the vertical scanning circuit 20 controls the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The drop in the voltage of the input node FD temporarily turns on the reset transistor M2, and the voltage of the input node FD is limited to the FD clip level based on VRESL2. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0129] At time t7c, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0130] At time t8c, the vertical scanning circuit 20 changes the control signal φRESL2 from high to low and changes the control signal φRESL1 from low to high. This turns off the transistor M9 in the buffer circuit 30A and turns on the transistor M8. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied as the control signal φRES_O to the gate of the reset transistor M2 of the unit pixel 11 via the transistor M8. This causes the reset transistor M2 to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the reset transistor M2, the FD clip level also drops as the voltage of the control signal φRES_O drops from VRESL2 (e.g., 1.2 V) to VRESL1 (e.g., 0.6 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0131] At time t9c, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL1. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES2 and VRESL1. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL2.

[0132] Between time t10c and time t11c, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0133] At time t12c, the vertical scanning circuit 20 changes the control signal φRESn from High to Low. This turns on the P-type MOS transistor M5 of the buffer circuit 30A, and the control signal φRES_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the reset transistor M2, turning on the reset transistor M2 and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0134] At time t13c, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the readout of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of low illuminance driving, the FD clip level is controlled by switching the Low level of the control signal φRES_O between VRESL1 and VRESL2.

[0135] As described above, even in a low-gain state in which two stages of capacitance are added to the input node FD, it is possible to prevent the adverse effects of fluctuations in pixel signals caused by charge overflowing from the photoelectric conversion element PD after charge transfer from worsening in the low-illumination drive mode.

[0136] Next, the medium-gain, high-illuminance drive mode of the photoelectric conversion device will be described with reference to Fig. 10. Fig. 10 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the medium-gain, high-illuminance drive mode.

[0137] In the medium-gain high-illuminance drive mode, immediately before time t1d shown in FIG. 10, the control signals φRESn, φCADD1n, and φCADD2n are at a low level. Therefore, the control signals φRES_O, φCADD1_O, and φCADD2_O output from the buffer circuit 30A are at a high level (voltage VRESH). The voltage VRESH is then supplied to the gates of the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b. This turns on the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b, and resets the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0138] 10, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0139] At time t2d, the vertical scanning circuit 20 changes the control signal φCADD2n from low to high. This turns on the N-type MOS transistor M6b of the buffer circuit 30A, and the control signal φCADD2_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL1 and φRESL2 are low and the control signal φRESL0 is high, so the transistors M8 and M9 of the buffer circuit 30A are off and the transistor M7 is on. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied to the gate of the second capacitance-addition transistor M2b via the transistor M7 as the control signal φCADD2_O. This turns off the second capacitance-addition transistor M2b of the unit pixel 11, and the input node FD is in a floating state, disconnected from the power supply (voltage VDD). At this time, the first capacitance-addition transistor M2a is on and the second capacitance-addition transistor M2b is off, so the input node FD has a capacitance Cfd+C1 (medium capacitance). This results in a "medium gain" in the charge-to-voltage conversion. Therefore, the amount of charge whose amplitude is limited at the FD clip level is smaller than in the "low gain" setting. However, because the amplitude of a signal with the same amount of charge is larger, the noise from the amplifier transistor M3 and the noise from the AD conversion are relatively smaller, improving the signal-to-noise ratio for low-light signals.

[0140] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2d to time t6d), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0141] From time t3d to time t4d, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0142] At time t5d, the vertical scanning circuit 20 changes the control signal φRESL0 from High to Low and changes the control signal φRESL1 from Low to High. This turns off the transistor M7 of the buffer circuit 30A and turns on the transistor M8. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied as the control signal φCADD2_O to the gate of the second capacitance-addition transistor M2b of the unit pixel 11 via the transistor M8. This causes the second capacitance-addition transistor M2b to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the second capacitance-addition transistor M2b, the FD clip level also increases as the voltage of the control signal φCADD2_O increases from VRESL0 (e.g., 0 V) ​​to VRESL1 (e.g., 0.6 V).

[0143] At time t6d, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6d, the vertical scanning circuit 20 changes the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage at the input node FD. The lowering of the voltage at the input node FD temporarily turns on the second capacitance addition transistor M2b, and the voltage at the input node FD is limited to the FD clip level based on VRESL1. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0144] At time t7d, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0145] At time t8d, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL0 from Low to High. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M7. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied as the control signal φCADD2_O to the gate of the second capacitance-addition transistor M2b in the unit pixel 11 via the transistor M7. This causes the second capacitance-addition transistor M2b to function as a clipping transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0 V). Because the FD clip level is determined by the gate voltage of the second capacitance-addition transistor M2b, the FD clip level also drops as the voltage of the control signal φCADD2_O drops from VRESL1 (e.g., 0.6 V) to VRESL0 (e.g., 0 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0146] At time t9d, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL0. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES1 and VRESL0. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL1.

[0147] Between time t10d and time t11d, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0148] At time t12d, the vertical scanning circuit 20 changes the control signal φCADD2n from High to Low. This turns on the P-type MOS transistor M5b of the buffer circuit 30A, and the control signal φCADD2_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the second capacitance-adding transistor M2b, turning on the second capacitance-adding transistor M2b and resetting the input node FD (Cfd+C1+C2) to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0149] At time t13d, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the reading of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of high illuminance driving, the Low level of the control signal φCADD2_O is switched between VRESL0 and VRESL1.

[0150] Next, the medium-gain low-illuminance drive mode of the photoelectric conversion device will be described with reference to Fig. 11. Fig. 11 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the medium-gain low-illuminance drive mode. The medium-gain low-illuminance drive mode differs from the medium-gain high-illuminance drive mode shown in Fig. 10 in that the FD clip level is increased, but otherwise similar processing is performed.

[0151] In the medium-gain low-illuminance drive mode, immediately before time t1e shown in FIG. 11, the control signals φRESn, φCADD1n, and φCADD2n are at a low level. Therefore, the control signals φRES_O, φCADD1_O, and φCADD2_O output from the buffer circuit 30A are at a high level (voltage VRESH). The voltage VRESH is then supplied to the gates of the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b. This turns on the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b, and resets the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0152] 11, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0153] At time t2e, the vertical scanning circuit 20 changes the control signal φCADD2n from low to high. This turns on the N-type MOS transistor M6b of the buffer circuit 30A, and the control signal φCADD2_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL0 and φRESL2 are low and the control signal φRESL1 is high, so the transistors M7 and M9 of the buffer circuit 30A are off and the transistor M8 is on. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied to the gate of the second capacitance-addition transistor M2b via the transistor M8 as the control signal φCADD2_O. This turns off the second capacitance-addition transistor M2b of the unit pixel 11, and the input node FD is in a floating state, disconnected from the power supply (voltage VDD). At this time, the first capacitance-addition transistor M2a is on and the second capacitance-addition transistor M2b is off, so the input node FD has a capacitance Cfd+C1 (medium capacitance). This results in a "medium gain" in the charge-to-voltage conversion. Therefore, the amount of charge whose amplitude is limited at the FD clip level is smaller than in the "low gain" setting. However, because the amplitude of a signal with the same amount of charge is larger, the noise from the amplifier transistor M3 and the noise from the AD conversion are relatively smaller, improving the signal-to-noise ratio for low-light signals.

[0154] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2e to time t6e), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0155] From time t3e to time t4e, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0156] At time t5e, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL2 from Low to High. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M9. This causes a voltage VRESL2 (e.g., 1.2 V) to be supplied as the control signal φCADD2_O to the gate of the second capacitance-addition transistor M2b in the unit pixel 11 via the transistor M9. This causes the second capacitance-addition transistor M2b to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 1.2 V). Because the FD clip level is determined by the gate voltage of the second capacitance-addition transistor M2b, the FD clip level also increases as the voltage of the control signal φCADD2_O increases from VRESL1 (e.g., 0.6 V) to VRESL2 (e.g., 1.2 V).

[0157] At time t6e, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6e, the vertical scanning circuit 20 controls the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The lowering of the voltage of the input node FD temporarily turns on the second capacitance adding transistor M2b, and the voltage of the input node FD is limited to the FD clip level based on VRESL2. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0158] At time t7e, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0159] At time t8e, the vertical scanning circuit 20 changes the control signal φRESL2 from High to Low and the control signal φRESL1 from Low to High. This turns off the transistor M9 of the buffer circuit 30A and turns on the transistor M8. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied as the control signal φCADD2_O to the gate of the second capacitance-addition transistor M2b of the unit pixel 11 via the transistor M8. This causes the second capacitance-addition transistor M2b to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the second capacitance-addition transistor M2b, the FD clip level also drops as the voltage of the control signal φCADD2_O drops from VRESL2 (e.g., 1.2 V) to VRESL1 (e.g., 0.6 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0160] At time t9e, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL1. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES2 and VRESL1. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL2.

[0161] Between time t10e and time t11e, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0162] At time t12e, the vertical scanning circuit 20 changes the control signal φCADD2n from High to Low. This turns on the P-type MOS transistor M5b of the buffer circuit 30A, and the control signal φCADD2_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the second capacitance-adding transistor M2b, turning on the second capacitance-adding transistor M2b and resetting the input node FD to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0163] At time t13e, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the reading of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of low-illuminance driving, the Low level of the control signal φCADD2_O is switched between VRESL1 and VRESL2.

[0164] As described above, even in a medium gain state in which the capacitance of the input node FD is added by one level, it is possible to prevent the adverse effects of fluctuations in pixel signals caused by charge overflowing from the photoelectric conversion element PD after charge transfer from worsening in the low-illumination drive mode.

[0165] Next, the high-gain, high-illuminance drive mode of the photoelectric conversion device will be described with reference to Fig. 12. Fig. 12 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the high-gain, high-illuminance drive mode.

[0166] In the high-gain, high-illuminance drive mode, the control signals φRESn, φCADD1n, and φCADD2n are at a low level immediately before time t1f shown in FIG. 12. Therefore, the control signals φRES_O, φCADD1_O, and φCADD2_O output from the buffer circuit 30A are at a high level (voltage VRESH). The voltage VRESH is then supplied to the gates of the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b. This turns on the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b, and resets the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0167] 12, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0168] At time t2f, the vertical scanning circuit 20 changes the control signal φCADD1n from low to high. This turns on the N-type MOS transistor M6a of the buffer circuit 30A, and the control signal φCADD1_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL1 and φRESL2 are low and the control signal φRESL0 is high, so the transistors M8 and M9 of the buffer circuit 30A are off and the transistor M7 is on. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied to the gate of the first capacitance-adding transistor M2a via the transistor M7 as the control signal φCADD1_O. This turns off the first capacitance-adding transistor M2a of the unit pixel 11, and the input node FD is in a floating state, disconnected from the power supply (voltage VDD). Since the first capacitance-adding transistor M2a is off, the input node FD has a capacitance Cfd (small capacitance). This results in a high gain in charge-voltage conversion. For this reason, the amount of charge whose amplitude is limited at the FD clip level is smaller than in the "medium gain" setting. However, because the amplitude of a signal with the same amount of charge is larger, the noise of the amplifier transistor M3 and the noise due to AD conversion are relatively smaller, improving the S / N ratio for low-light signals.

[0169] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2f to time t6f), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0170] Between time t3f and time t4f, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0171] At time t5f, the vertical scanning circuit 20 changes the control signal φRESL0 from High to Low and changes the control signal φRESL1 from Low to High. This turns off the transistor M7 of the buffer circuit 30A and turns on the transistor M8. As a result, a voltage VRESL1 (e.g., 0.6 V) is supplied as the control signal φCADD1_O to the gate of the second capacitance-addition transistor M2b of the unit pixel 11 via the transistor M8. This causes the first capacitance-addition transistor M2a to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the first capacitance-addition transistor M2a, the FD clip level also increases as the voltage of the control signal φCADD1_O increases from VRESL0 (e.g., 0 V) ​​to VRESL1 (e.g., 0.6 V).

[0172] At time t6f, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6f, the vertical scanning circuit 20 controls the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The lowering of the voltage of the input node FD temporarily turns on the first capacitance-addition transistor M2a, and the voltage of the input node FD is limited to the FD clip level based on VRESL1. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0173] At time t7f, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0174] At time t8f, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL0 from Low to High. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M7. This causes a voltage VRESL0 (e.g., 0 V) ​​to be supplied as the control signal φCADD1_O to the gate of the first capacitance-addition transistor M2a in the unit pixel 11 via the transistor M7. This causes the first capacitance-addition transistor M2a to function as a clipping transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0 V). Because the FD clip level is determined by the gate voltage of the first capacitance-addition transistor M2a, the FD clip level also drops as the voltage of the control signal φCADD1_O drops from VRESL1 (e.g., 0.6 V) to VRESL0 (e.g., 0 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0175] At time t9f, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL0. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES1 and VRESL0. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL1.

[0176] Between time t10f and time t11f, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs this to the outside of the photoelectric conversion device.

[0177] At time t12f, the vertical scanning circuit 20 changes the control signal φCADD1n from High to Low. This turns on the P-type MOS transistor M5a of the buffer circuit 30A, and the control signal φCADD1_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the first capacitance-adding transistor M2a, turning on the first capacitance-adding transistor M2a and resetting the input node FD (Cfd+C1+C2) to a voltage (reset voltage) at a reset level corresponding to the voltage VDD.

[0178] At time t13f, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the readout of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of high illuminance driving, the Low level of the control signal φCADD1_O is switched between VRESL0 and VRESL1.

[0179] Next, the high-gain low-illuminance drive mode of the photoelectric conversion device will be described with reference to Fig. 13. Fig. 13 is a timing chart showing an example of operation of the photoelectric conversion device according to this embodiment in the high-gain low-illuminance drive mode. The high-gain low-illuminance drive mode differs from the high-gain high-illuminance drive mode shown in Fig. 12 in that the FD clip level is increased, but otherwise similar processing is performed.

[0180] In the high-gain low-illuminance drive mode, immediately before time t1g shown in FIG. 13, the control signals φRESn, φCADD1n, and φCADD2n are at a low level. Therefore, the control signals φRES_O, φCADD1_O, and φCADD2_O output from the buffer circuit 30A are at a high level (voltage VRESH). The voltage VRESH is then supplied to the gates of the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b. This turns on the reset transistor M2, the first capacitance-addition transistor M2a, and the second capacitance-addition transistor M2b, and resets the input node FD (Cfd+C1+C2) to a reset level voltage (reset voltage) corresponding to the voltage VDD.

[0181] 13, the vertical scanning circuit 20 controls the control signal φSEL_O for the target unit pixel 11 (the unit pixels 11 in two rows) in the pixel section 10 to change from low level to high level. This turns on the selection transistor M4 of the target unit pixel 11, and the amplification transistor M3 of the target unit pixel 11 is connected to the column signal line 13 via the selection transistor M4. As a result, a bias current is supplied from the current source 50 to the amplification transistor M3 via the column signal line 13 and the selection transistor M4, and a reset signal corresponding to the reset voltage of the input node FD is output to the column signal line 13 via the selection transistor M4. This starts reading out the reset signals from the unit pixels 11 in two rows that are to be read out simultaneously.

[0182] At time t2g, the vertical scanning circuit 20 changes the control signal φCADD1n from low to high. This turns on the N-type MOS transistor M6a of the buffer circuit 30A, and the control signal φCADD1_O output from the buffer circuit 30A goes low. At this time, the control signals φRESL0 and φRESL2 are low and the control signal φRESL1 is high, so the transistors M7 and M9 of the buffer circuit 30A are off and the transistor M8 is on. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied to the gate of the first capacitance-adding transistor M2a via the transistor M8 as the control signal φCADD1_O. This turns off the first capacitance-adding transistor M2a of the unit pixel 11, and the input node FD is in a floating state, disconnected from the power supply (voltage VDD). Since the first capacitance-adding transistor M2a is off, the input node FD has a capacitance Cfd (small capacitance). This results in a high gain in charge-voltage conversion. For this reason, the amount of charge whose amplitude is limited at the FD clip level is smaller than in the "medium gain" setting. However, because the amplitude of a signal with the same amount of charge is larger, the noise of the amplifier transistor M3 and the noise due to AD conversion are relatively smaller, improving the S / N ratio for low-light signals.

[0183] Here, high-intensity light is incident on the unit pixel 11, and the charge that can be stored in the photoelectric conversion element PD is saturated, causing charge to overflow from the photoelectric conversion element PD to the input node FD. Because charge is overflowing at the input node FD in this way, the voltage of the column signal line 13 drops. During the reset signal readout period (time t2g to time t6g), the VL clip level is higher than the FD clip level, so the drop in the voltage of the column signal line 13 stops at the VL clip level.

[0184] Between time t3g and time t4g, the AD conversion circuit 61 performs AD conversion on the reset signal and outputs the AD-converted reset signal to the memory 62 ("N conversion" in the figure). The memory 62 stores the AD-converted reset signal output from the AD conversion circuit 61.

[0185] At time t5g, the vertical scanning circuit 20 changes the control signal φRESL1 from High to Low and the control signal φRESL2 from Low to High. This turns off the transistor M8 in the buffer circuit 30A and turns on the transistor M9. This causes a voltage VRESL2 (e.g., 1.2 V) to be supplied as the control signal φCADD1_O to the gate of the first capacitance-addition transistor M2a in the unit pixel 11 via the transistor M9. This causes the first capacitance-addition transistor M2a to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 1.2 V). Because the FD clip level is determined by the gate voltage of the first capacitance-addition transistor M2a, the FD clip level also increases as the voltage of the control signal φCADD1_O increases from VRESL1 (e.g., 0.6 V) to VRESL2 (e.g., 1.2 V).

[0186] At time t6g, the column signal line clipping circuit 40 lowers the VL clip level below the FD clip level. At the same time t6g, the vertical scanning circuit 20 controls the control signal φTX_O from low to high. This turns on the transfer transistor M1 of the unit pixel 11, and the charge accumulated in the photoelectric conversion element PD is transferred to the input node FD. The transferred charge is added to the charge already overflowing from the photoelectric conversion element PD at the input node FD, further lowering the voltage of the input node FD. The lowering of the voltage of the input node FD temporarily turns on the first capacitance-addition transistor M2a, and the voltage of the input node FD is limited to the FD clip level based on VRESL2. Furthermore, because the VL clip level is controlled to be lower than the FD clip level, the voltage of the column signal line 13 is also limited to the FD clip level.

[0187] At time t7g, the vertical scanning circuit 20 changes the control signal φTX_O from high to low, thereby turning off the transfer transistor M1 of the unit pixel 11 and stopping the transfer of charges from the photoelectric conversion element PD to the input node FD.

[0188] At time t8g, the vertical scanning circuit 20 changes the control signal φRESL2 from High to Low and the control signal φRESL1 from Low to High. This turns off the transistor M9 of the buffer circuit 30A and turns on the transistor M8. This causes a voltage VRESL1 (e.g., 0.6 V) to be supplied as the control signal φCADD1_O to the gate of the first capacitance-addition transistor M2a of the unit pixel 11 via the transistor M8. This causes the first capacitance-addition transistor M2a to function as a clip transistor that limits the amplitude of the pixel signal at an FD clip level corresponding to the gate voltage (e.g., 0.6 V). Because the FD clip level is determined by the gate voltage of the first capacitance-addition transistor M2a, the FD clip level also drops as the voltage of the control signal φCADD1_O drops from VRESL2 (e.g., 1.2 V) to VRESL1 (e.g., 0.6 V). At this time, the charge at the input node FD has already been discharged to the power supply (voltage VDD), so the voltage of the column signal line 13 does not change significantly.

[0189] At time t9g, the photoelectric conversion element PD reaches a saturated state, and charge again begins to overflow from the photoelectric conversion element PD to the input node FD. As a result, the voltages of the input node FD and the column signal line 13 begin to decrease, and the decrease in the voltages of the input node FD and the column signal line 13 stops at the FD clip level based on the voltage VRESL1. The amount of this voltage decrease in the column signal line 13 is determined by the voltage difference between the voltages VRES2 and VRESL1. Note that unless the illuminance is so high that charge again overflows to the input node FD immediately after the charge transfer, the amplitude of the column signal line 13 is limited at the FD clip level based on the voltage VRESL2.

[0190] Between time t10g and time t11g, the AD conversion circuit 61 performs AD conversion on the pixel signals and outputs the AD-converted pixel signals to the memory 62 ("S conversion" in the figure). The memory 62 stores the AD-converted pixel signals output from the AD conversion circuit 61. The horizontal scanning circuit 70 sequentially scans the memories 62 and outputs the AD-converted reset signals and pixel signals held in each memory 62 to the signal processing circuit 80. The signal processing circuit 80 subtracts the reset signals from the pixel signals and extracts only the signals corresponding to the amount of incident light, and outputs the extracted signals to the outside of the photoelectric conversion device.

[0191] At time t12g, the vertical scanning circuit 20 changes the control signal φCADD1n from High to Low. This turns on the P-type MOS transistor M5a of the buffer circuit 30A, and the control signal φCADD1_O output from the buffer circuit 30A becomes High (voltage VRESH). This causes the voltage VRESH to be supplied to the gate of the first capacitance-adding transistor M2a, turning on the first capacitance-adding transistor M2a and resetting the input node FD to a voltage (reset voltage) of a reset level corresponding to the voltage VDD.

[0192] At time t13g, the vertical scanning circuit 20 changes the control signal φSEL_O from High to Low. This turns off the selection transistor M4 of the unit pixel 11, disconnects the amplification transistor M3 of the unit pixel 11 from the column signal line 13, and ends the reading of signals from the unit pixels 11 in two rows that are read out simultaneously. As described above, in the case of low-illuminance driving, the Low level of the control signal φCADD1_O is switched between VRESL1 and VRESL2.

[0193] As described above, even in a high gain state in which no capacitance is added to the input node FD, it is possible to prevent the adverse effects of fluctuations in pixel signals caused by charge overflowing from the photoelectric conversion element PD after charge transfer from worsening in the low-illumination drive mode.

[0194] In the photoelectric conversion device according to the second embodiment, the reset transistor M2, the first capacitance-addition transistor M2a, or the second capacitance-addition transistor M2b selectively operates as a clipping transistor, and the photoelectric conversion device can suppress image quality degradation while suppressing crosstalk.

[0195] [Third embodiment] An imaging system according to a third embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0196] The photoelectric conversion devices described in the first and second embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in imaging systems. Fig. 14 illustrates a block diagram of a digital still camera as an example of such systems.

[0197] 14 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is a photoelectric conversion device described in any one of the first and second embodiments, and converts the optical image formed by the lens 202 into image data.

[0198] The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) on which a photoelectric conversion unit of the imaging device 201 is formed, or may be formed on a semiconductor substrate different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0199] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be removable.

[0200] The imaging system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0201] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0202] In this way, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device according to the first or second embodiment is applied.

[0203] [Fourth embodiment] An imaging system and a moving object according to a fourth embodiment of the present invention will be described with reference to Fig. 15. Fig. 15 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0204] FIG. 15(a) shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device described in any one of the first and second embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0205] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0206] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 15(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0207] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0208] [Fifth embodiment] A device according to a fifth embodiment of the present invention will be described with reference to Fig. 16. Fig. 16 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0209] FIG. 16 is a schematic diagram showing equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device of any of the first and second embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0210] The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-silicon vias (TSVs), inter-chip wiring formed by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0211] The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

[0212] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes signals output from the photoelectric conversion device APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The device EQP displays the signal output from the photoelectric conversion device APR on a display device DSPL and transmits the signal to the outside using a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

[0213] The device EQP shown in FIG. 16 can be an electronic device such as an information terminal with a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP can also be transportation equipment (mobile object) such as a vehicle, a ship, or an aircraft. The device EQP can also be medical equipment such as an endoscope or a CT scanner. The device EQP can also be medical equipment such as an endoscope or a CT scanner.

[0214] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0215] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser, and / or user. Therefore, if the photoelectric conversion device APR is installed in a device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, deciding to install the photoelectric conversion device APR according to this embodiment in the device EQP is advantageous in increasing the value of the device EQP.

[0216] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present invention.

[0217] For example, the photoelectric conversion device according to the second embodiment has been described as including the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b as transistors that add capacitance to the input node FD, but is not limited to this. For example, the photoelectric conversion device may include only the first capacitance-addition transistor M2a out of the first capacitance-addition transistor M2a and the second capacitance-addition transistor M2b, and may not include the second capacitance-addition transistor M2b. In this case, the reset transistor M2 or the first capacitance-addition transistor M2a selectively operates as a clip transistor.

[0218] Furthermore, although the three voltages VRESL0, VRESL1, and VRESL2 are used to switch the low level of the control signal φRES_O between the high-illuminance drive mode and the low-illuminance drive mode, the present invention is not limited to this. When the FD clip level during the charge transfer period in the low-illuminance drive mode is changed to a level higher than that in the high-illuminance drive mode, it is sufficient to obtain the desired effect by also raising the FD clip level outside the charge transfer period.

[0219] Furthermore, although the transfer transistor M1 is turned on after the FD clip level is increased, this is not limiting, and the FD clip level may be increased after the transfer transistor M1 is turned on. At least, it is sufficient to provide a time for discharging the charge at a high FD clip level between the time when the charge of the photoelectric conversion element PD is transferred to the input node FD and the time when AD conversion is performed, so as to obtain the effect of amplitude limitation.

[0220] Although the reset transistor M2 also functions as a clipping transistor in the above example, the present invention is not limited to this. For example, the reset transistor M2 may be configured to function as a separate transistor, without providing the clipping function in the reset transistor M2.

[0221] The disclosure of the above embodiment includes the following configurations and methods. (Configuration 1) a plurality of pixels each including a photoelectric conversion unit that accumulates charge corresponding to incident light, an input node that holds the charge, a transfer transistor that transfers the charge from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charge of the input node, and a clip transistor that clips a voltage of the input node; an AD conversion circuit that performs AD conversion on the pixel signal when the input node is reset during a first period, and performs AD conversion on the pixel signal based on the charge corresponding to the incident light during a second period; The clip transistor is a first operation in which a first voltage is supplied to a gate of the clipping transistor during the first period and the second period, and a second voltage higher than the first voltage is supplied to the gate of the clipping transistor during a transfer period after the first period and before the second period, during which the transfer transistor is on; a first operation in which a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage and the third voltage is supplied to the gate of the clip transistor during the transfer period. (Configuration 2) 2. The photoelectric conversion device according to configuration 1, wherein the difference between the first voltage and the second voltage corresponds to the difference between the third voltage and the fourth voltage. (Configuration 3) 3. The photoelectric conversion device according to configuration 1 or 2, wherein the second voltage and the third voltage are the same. (Configuration 4) 4. The photoelectric conversion device according to any one of configurations 1 to 3, wherein the period during which the second voltage or the fourth voltage is supplied to the gate of the clip transistor is longer than the period during which the transfer transistor is on. (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that after the second voltage or the fourth voltage is supplied to the gate of the clip transistor, the transfer transistor is turned on, and after the transfer transistor is turned off, the first voltage or the third voltage is supplied to the gate of the clip transistor. (Configuration 6) The photoelectric conversion device of any one of configurations 1 to 5, wherein the period from when the transfer transistor is turned off to when the first voltage or the third voltage is supplied to the gate of the clip transistor is longer than the period from when the second voltage or the fourth voltage is supplied to the gate of the clip transistor to when the transfer transistor is turned on. (Configuration 7) the pixel includes a reset transistor that resets a voltage of the input node; 7. The photoelectric conversion device according to any one of configurations 1 to 6, wherein the reset transistor operates as the clip transistor. (Configuration 8) a first main node of the reset transistor is connected to the input node; 8. The photoelectric conversion device according to configuration 7, wherein a second main node of the reset transistor is connected to a power supply voltage line. (Configuration 9) the pixel includes a reset transistor and a first capacitance adding transistor capable of adding capacitance to the input node; 9. The photoelectric conversion device according to any one of configurations 1 to 8, wherein the reset transistor or the first capacitance-addition transistor selectively operates as the clip transistor. (Configuration 10) a first main node of the first capacitance adding transistor is connected to the input node; a second main node of the first capacitance-addition transistor is connected to a first main node of the reset transistor; 10. The photoelectric conversion device according to configuration 9, wherein a second main node of the reset transistor is connected to a power supply voltage line. (Configuration 11) the pixel further includes a second capacitance adding transistor capable of adding capacitance to the input node; 11. The photoelectric conversion device according to configuration 9 or 10, wherein the reset transistor, the first capacitance-added transistor, or the second capacitance-added transistor selectively operates as the clip transistor. (Configuration 12) a first main node of the first capacitance adding transistor is connected to the input node; a second main node of the first capacitance-adding transistor is connected to a first main node of the second capacitance-adding transistor; a second main node of the second capacitance addition transistor is connected to a first main node of the reset transistor; 12. The photoelectric conversion device according to any one of configurations 9 to 11, wherein a second main node of the reset transistor is connected to a power supply voltage line. (Configuration 13) 13. The photoelectric conversion device according to any one of configurations 1 to 12, wherein the clip transistor operates in the first mode when the incident light has a high illuminance, and operates in the second mode when the incident light has a low illuminance. (Configuration 14) the plurality of pixels are arranged in a plurality of rows and a plurality of columns; A plurality of column signal lines are arranged for each of the columns of pixels. 14. The photoelectric conversion device according to any one of configurations 1 to 13, wherein the AD conversion circuit simultaneously AD converts the pixel signals output from the plurality of pixels in the plurality of rows. (Configuration 15) 15. The photoelectric conversion device according to any one of configurations 1 to 14, further comprising a column signal line clip circuit that limits the amplitude of the pixel signal transmitted to the column signal line. (Configuration 16) In the first period, a clip level of the clip transistor is lower than a clip level of the column signal line clip circuit; 16. The photoelectric conversion device according to configuration 15, wherein the clip level of the clip transistor is higher than the clip level of the column signal line clip circuit during the transfer period and the second period. (Configuration 17) The photoelectric conversion device according to any one of structures 1 to 16, and a signal processing device that processes a signal output from the photoelectric conversion device. (Configuration 18) A mobile object, The photoelectric conversion device according to any one of structures 1 to 16, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal output from the photoelectric conversion device; and a control means for controlling the moving body based on the distance information. (Configuration 19) The photoelectric conversion device according to any one of structures 1 to 16, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising: (Method 20) a plurality of pixels each including a photoelectric conversion unit that accumulates charges corresponding to incident light, an input node that holds the charges, a transfer transistor that transfers the charges from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charges of the input node, and a clip transistor that clips a voltage of the input node; a control method for a photoelectric conversion device including an AD conversion circuit that performs AD conversion on the pixel signal when the input node is reset during a first period, and AD conversion on the pixel signal based on the charge corresponding to the incident light during a second period, a first operation in which a first voltage is supplied to a gate of the clipping transistor during the first period and the second period, and a second voltage higher than the first voltage is supplied to the gate of the clipping transistor during a transfer period that is before the second period after the first period and in which the transfer transistor is on; a second operation in which a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage and the third voltage is supplied to the gate of the clip transistor during the transfer period. [Explanation of symbols]

[0222] 11...Unit pixel 40...Column signal line clip circuit 61...AD conversion circuit PD: Photoelectric conversion section FD...input node M1: Transfer transistor M2: Reset transistor M2a: First capacitance-added transistor M2b: Second capacitance-added transistor M3: Amplification transistor

Claims

1. a plurality of pixels each including a photoelectric conversion unit that accumulates charge corresponding to incident light, an input node that holds the charge, a transfer transistor that transfers the charge from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charge of the input node, and a clip transistor that clips a voltage of the input node; an AD conversion circuit that performs AD conversion on the pixel signal when the input node is reset during a first period, and performs AD conversion on the pixel signal based on the charge corresponding to the incident light during a second period; The clip transistor is a first operation in which a first voltage is supplied to a gate of the clipping transistor during the first period and the second period, and a second voltage higher than the first voltage is supplied to the gate of the clipping transistor during a transfer period after the first period and before the second period, during which the transfer transistor is on; a first operation in which a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage and the third voltage is supplied to the gate of the clip transistor during the transfer period.

2. 2. The photoelectric conversion device according to claim 1, wherein the difference between the first voltage and the second voltage corresponds to the difference between the third voltage and the fourth voltage.

3. 2. The photoelectric conversion device according to claim 1, wherein the second voltage and the third voltage are the same.

4. 2. The photoelectric conversion device according to claim 1, wherein a period during which the second voltage or the fourth voltage is supplied to the gate of the clipping transistor is longer than a period during which the transfer transistor is on.

5. The photoelectric conversion device of claim 1, characterized in that after the second voltage or the fourth voltage is supplied to the gate of the clip transistor, the transfer transistor is turned on, and after the transfer transistor is turned off, the first voltage or the third voltage is supplied to the gate of the clip transistor.

6. The photoelectric conversion device of claim 1, characterized in that the period from when the transfer transistor is turned off to when the first voltage or the third voltage is supplied to the gate of the clip transistor is longer than the period from when the second voltage or the fourth voltage is supplied to the gate of the clip transistor to when the transfer transistor is turned on.

7. the pixel includes a reset transistor that resets a voltage of the input node; 2. The photoelectric conversion device according to claim 1, wherein the reset transistor operates as the clipping transistor.

8. a first main node of the reset transistor is connected to the input node; 8. The photoelectric conversion device according to claim 7, wherein the second main node of the reset transistor is connected to a power supply voltage line.

9. the pixel includes a reset transistor and a first capacitance adding transistor capable of adding capacitance to the input node; 2. The photoelectric conversion device according to claim 1, wherein the reset transistor or the first capacitance-addition transistor selectively operates as the clipping transistor.

10. a first main node of the first capacitance adding transistor is connected to the input node; a second main node of the first capacitance-addition transistor is connected to a first main node of the reset transistor; 10. The photoelectric conversion device according to claim 9, wherein the second main node of the reset transistor is connected to a power supply voltage line.

11. the pixel further includes a second capacitance adding transistor capable of adding capacitance to the input node; 10. The photoelectric conversion device according to claim 9, wherein the reset transistor, the first capacitance-added transistor, or the second capacitance-added transistor selectively operates as the clip transistor.

12. a first main node of the first capacitance adding transistor is connected to the input node; a second main node of the first capacitance-adding transistor is connected to a first main node of the second capacitance-adding transistor; a second main node of the second capacitance adding transistor is connected to a first main node of the reset transistor; 12. The photoelectric conversion device according to claim 11, wherein a second main node of the reset transistor is connected to a power supply voltage line.

13. 2. The photoelectric conversion device according to claim 1, wherein the clip transistor operates in the first mode when the incident light has a high illuminance, and operates in the second mode when the incident light has a low illuminance.

14. the plurality of pixels are arranged in a plurality of rows and a plurality of columns; A plurality of column signal lines are arranged for each of the columns of pixels.

2. The photoelectric conversion device according to claim 1, wherein the AD conversion circuit simultaneously AD converts the pixel signals output from the plurality of pixels in the plurality of rows.

15. The photoelectric conversion device according to claim 14 , further comprising a column signal line clip circuit that limits the amplitude of the pixel signal transmitted to the column signal line.

16. In the first period, a clip level of the clip transistor is lower than a clip level of the column signal line clip circuit; 16. The photoelectric conversion device according to claim 15, wherein the clip level of the clip transistor is higher than the clip level of the column signal line clip circuit during the transfer period and the second period.

17. The photoelectric conversion device according to any one of claims 1 to 16, and a signal processing device that processes a signal output from the photoelectric conversion device.

18. A mobile object, The photoelectric conversion device according to any one of claims 1 to 16, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal output from the photoelectric conversion device; and a control means for controlling the moving body based on the distance information.

19. The photoelectric conversion device according to any one of claims 1 to 16, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on the information obtained by the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; and a storage device that stores information obtained by the photoelectric conversion device; An apparatus characterized by comprising:

20. a plurality of pixels each including a photoelectric conversion unit that accumulates charges corresponding to incident light, an input node that holds the charges, a transfer transistor that transfers the charges from the photoelectric conversion unit to the input node, an amplification transistor that outputs a pixel signal based on the charges of the input node, and a clip transistor that clips a voltage of the input node; a control method for a photoelectric conversion device including an AD conversion circuit that performs AD conversion on the pixel signal when the input node is reset during a first period, and AD conversion on the pixel signal based on the charge corresponding to the incident light during a second period, a first operation in which a first voltage is supplied to a gate of the clipping transistor during the first period and the second period, and a second voltage higher than the first voltage is supplied to the gate of the clipping transistor during a transfer period that is before the second period and after the first period and in which the transfer transistor is on; a third voltage higher than the first voltage is supplied to the gate of the clip transistor during the first period and the second period, and a fourth voltage higher than the second voltage and the third voltage is supplied to the gate of the clip transistor during the transfer period.

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