Method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device capable of suppressing diffusion in the ion-implanted layer after heating.SOLUTION: A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate 10 composed of an oxide semiconductor and having a surface area 10a; ion-implanting impurities of a first or second conductivity type from the surface area 10a of the semiconductor substrate 10; performing oxygen vacancy compensation in a region where an ion-implanted layer 31 is formed after heating the semiconductor substrate 10; and performing a heating treatment that activates impurities and forms the ion-implanted layer 31 after heating.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device having a semiconductor substrate made of an oxide semiconductor. [Background technology]

[0002] Conventionally, semiconductor devices having a semiconductor substrate made of an oxide semiconductor have been proposed. For example, Patent Document 1 proposes a Schottky barrier diode as a semiconductor device, which is constructed using a semiconductor substrate made of an oxide semiconductor. Specifically, this semiconductor device has n + On a type substrate, - The semiconductor device has a semiconductor substrate formed by stacking semiconductor layers of the same type. The semiconductor device has a first electrode that is connected to the semiconductor layer via a Schottky contact and a second electrode that is connected to the substrate via an ohmic contact. In addition, in this semiconductor device, a guard ring layer is formed as an electric field concentration relief structure on the outer edge of the portion of the semiconductor layer that is connected to the first electrode.

[0003] The guard ring layer in such a semiconductor device is formed by ion-implanting p-type impurities into the semiconductor layer and then performing a heat treatment to activate the p-type impurities. In other words, the guard ring layer is formed as a post-heat ion-implantation layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-39194 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the inventors have found that when a post-heat ion-implanted layer such as a guard ring layer is formed on a semiconductor substrate made of an oxide semiconductor, the desired characteristics cannot be obtained due to the diffusion of impurities. For example, when a guard ring layer is formed on the Schottky barrier diode described above, if the guard ring layer is formed wider than the desired range, the desired electric field relaxation function may not be obtained.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can suppress diffusion of an ion-implanted layer after heating. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes preparing a semiconductor substrate (10) made of an oxide semiconductor and having one surface (10a), ion-implanting impurities of a first conductivity type or a second conductivity type from the one surface of the semiconductor substrate, compensating for oxygen vacancies in a region of the semiconductor substrate where a post-heating ion-implanted layer (31, 34, 35, 36) will be formed, and performing a heat treatment to activate the impurities and form the post-heating ion-implanted layer.

[0008] According to this, oxygen vacancies in the region where the post-heating ion-implanted layer is formed are compensated for, which prevents impurities constituting the post-heating ion-implanted layer from diffusing through the oxygen vacancies, thereby suppressing fluctuations in the characteristics of the semiconductor device.

[0009] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2A] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. [Figure 2B]2B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 2B. [Figure 2D] 2D is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 2C. [Figure 3] FIG. 6 is a graph showing the Mg concentration and O concentration before heat treatment along the line AA in FIG. 5. [Figure 4] FIG. 6 is a graph showing the Mg concentration and O concentration after heat treatment, taken along line AA in FIG. 5. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor substrate used in the experiments of FIGS. 3 and 4. [Figure 6] FIG. 6 is a graph showing the Mg concentration and O concentration before heat treatment along the line AA in FIG. 5. [Figure 7] FIG. 6 is a graph showing the Mg concentration and O concentration after heat treatment, taken along line AA in FIG. 5. [Figure 8] FIG. 10 is a graph showing the relationship between the ratio of the O concentration to the Mg concentration and the Mg-termination depth. [Figure 9] FIG. 10 is a diagram for explaining the relationship between depth and Mg concentration and O concentration. [Figure 10] FIG. 10 is a diagram for explaining the relationship between depth and Mg concentration and O concentration. [Figure 11] FIG. 10 is a diagram for explaining the relationship between depth and Mg concentration and O concentration. [Figure 12] FIG. 10 is a diagram for explaining the relationship between depth and Mg concentration and O concentration. [Figure 13] FIG. 10 is a diagram showing the relationship between a pre-heating ion-implanted layer and an oxygen ion-implanted layer. [Figure 14] FIG. 4 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0012] (First embodiment) A first embodiment will be described with reference to the drawings. In the first embodiment, a semiconductor device in which a Schottky barrier diode including a post-heat ion-implanted layer is formed will be described as an example. First, the configuration of the semiconductor device of this embodiment will be described.

[0013] 1, the semiconductor device includes a semiconductor substrate 10 made of an oxide semiconductor. The semiconductor substrate 10 of this embodiment is made of n-type gallium oxide (GaO) doped with Sn (tin). + A substrate 11 of a type and a n-type Ga2O3-based - The semiconductor substrate 10 includes a semiconductor layer 12. The semiconductor layer 12 in this embodiment is an epitaxial layer grown on the substrate 11. Hereinafter, the semiconductor substrate 10 will be described with the surface of the semiconductor layer 12 opposite to the substrate 11 as one surface 10a of the semiconductor substrate 10, and the surface of the substrate 11 opposite to the semiconductor layer 12 as the other surface 10b of the semiconductor substrate 10.

[0014] A first electrode 21 is disposed on one surface 10a of the semiconductor substrate 10 and is connected to the semiconductor layer 12 via a Schottky contact. A second electrode 22 is disposed on the other surface 10b of the semiconductor substrate 10 and is connected to the substrate 11 via an ohmic contact.

[0015] A guard ring layer 31 formed by activating p-type impurities is formed on the outer edge of the semiconductor layer 12 at the portion connected to the first electrode 21. This guard ring layer 31 constitutes an electric field concentration mitigation structure that suppresses electric field concentration at the outer edge of the portion connected to the first electrode 21 and the semiconductor layer 12. As will be described later, this guard ring layer 31 is formed by ion-implanting p-type impurities and then activating the p-type impurities by a heat treatment. In this embodiment, the guard ring layer 31 corresponds to a post-heat ion-implantation layer.

[0016] The above is the configuration of the semiconductor device of this embodiment. In this embodiment, n-type can also be called the first conductivity type, and p-type can also be called the second conductivity type. Next, a method for manufacturing the above semiconductor device will be described with reference to Figures 2A to 2D.

[0017] First, as shown in FIG. 2A, a semiconductor substrate 10 is prepared in which a semiconductor layer 12 is stacked on a substrate 11.

[0018] Next, as shown in FIG. 2B , a mask (not shown) having an opening corresponding to the region where the guard ring layer 31 is to be formed is placed on the semiconductor layer 12, and p-type impurities are ion-implanted to form a pre-heating ion-implanted layer 32. Examples of p-type impurities include magnesium (Mg), beryllium (Be), calcium (Ca), zinc (Zn), nitrogen (N), nickel (Ni), and copper (Cu). The ion implantation is performed at a temperature of 500°C, for example. When the impurities are ion-implanted at a temperature of 500°C or lower, the impurities are in an inactive state. Therefore, in this step, a pre-heating ion-implanted layer 32 in which the impurities are in an inactive state is formed.

[0019] Here, the guard ring layer 31 shown in FIG. 1 is formed by ion-implanting p-type impurities and then activating the p-type impurities through heat treatment. However, there is a possibility that the p-type impurities may diffuse when activating the p-type impurities. If the guard ring layer 31 is formed with excessively diffused p-type impurities, the characteristics of the guard ring layer 31 may change, which may in turn change the characteristics of the semiconductor device. For this reason, the present inventors have conducted extensive research into the diffusion of p-type impurities when forming the guard ring layer 31. The present inventors have hypothesized that the diffusion of p-type impurities occurs via oxygen vacancies contained in the oxide semiconductor (i.e., Ga2O3), as will be described in detail later.

[0020] For this reason, in this embodiment, after ion implantation of p-type impurities, an oxygen vacancy compensation step is performed to compensate for oxygen vacancies in the region including the pre-heating ion-implanted layer 32, as shown in FIG. 2C. That is, an oxygen vacancy compensation step is performed to compensate for oxygen vacancies in the region where the guard ring layer 31 is to be formed. In this embodiment, the oxygen vacancy compensation step is performed by implanting oxygen ions as oxygen-containing ions into the region including the pre-heating ion-implanted layer 32. That is, in this embodiment, an oxygen vacancy compensation step is performed to implant oxygen ions to reduce oxygen vacancies in the pre-heating ion-implanted layer 32. Note that examples of oxygen-containing ions include O, CO, 18 Examples of suitable ions include O and MgO. Either the formation of the pre-heating ion implanted layer 32 or the implantation of oxygen ions may be performed first.

[0021] 2D, a heat treatment is performed at a temperature of 1000° C. or higher to sufficiently activate the p-type impurities and form guard ring layer 31. After that, although not specifically shown, first electrode 21 and second electrode 22 are formed to manufacture the semiconductor device. The heat treatment for forming guard ring layer 31 may be performed in common with a heat treatment performed in a separate subsequent step.

[0022] Next, the relationship between oxygen ions and the diffusion of p-type impurities will be described. The present inventors conducted extensive research into the relationship between oxygen ions and the diffusion of p-type impurities and obtained the results shown in FIGS. 3 and 4. As shown in FIG. 5, FIGS. 3 and 4 show the relationship between concentration and depth along line AA when a pre-heating ion-implanted layer 32 is formed and then a heat treatment is performed to form a guard ring layer 31. Note that FIG. 5 simply shows only one guard ring layer 31. The pre-heating ion-implanted layer 32 here is formed by ion-implanting Mg as a p-type impurity, and oxygen ions are implanted into the region including the pre-heating ion-implanted layer 32. Each ion implantation is performed at 500°C, and the heat treatment is performed at 1000°C or higher.

[0023] 3 and 4, the depth is the direction from one surface 10a of the semiconductor substrate 10 toward the other surface 10b, and the thickness of the semiconductor layer 12 is 8.5 μm. Therefore, a depth of 0 μm in FIGS. 3 and 4 refers to the one surface 10a of the semiconductor substrate 10. The Mg concentration before heat treatment in FIG. 4 is the same as the Mg concentration in FIG. 3. The Sn concentration in FIG. 4 indicates the concentration of Sn doped in the substrate 11.

[0024] 3 shows the results when the Mg concentration in the ion-implanted layer 32 before heating is 1×10 18 cm -3 3 shows the results of Mg ion implantation so that the depth of the pre-heating ion-implanted layer 32 is about 0.5 μm. FIG. 3 also shows the results of O concentration (i.e., oxygen concentration) when oxygen ions are implanted at varying concentrations to approximately the same depth as the pre-heating ion-implanted layer 32. Specifically, in FIG. 3, the O concentration is 1.25×10 18 cm -3 , 5×10 18 cm -3 , 1×10 19 cm -3 3 and 4, the O concentration is 1.25×10 as the ratio of the O concentration to the Mg concentration. 18 cm -3When the O concentration is 5×10, the ratio is 1:1.25. 18 cm -3 When the O concentration is 1×10 19 cm -3 4, as a comparative example, the ratio of Mg concentration to O concentration is shown as 1:0 when no oxygen ions are implanted. Note that when oxygen ions are implanted here, CO2 gas is mass-separated and the extracted oxygen ions are implanted.

[0025] 4, when guard ring layer 31 is formed and oxygen ions are not implanted (i.e., Mg:O=1:0), it is confirmed that Mg is diffused more widely in the depth direction than Mg before heat treatment. In this example, it is confirmed that Mg is diffused to a depth of 8.5 μm, and that it has diffused to the interface with substrate 11.

[0026] It was also confirmed that implanting oxygen ions resulted in a shallower Mg termination depth. In other words, it was confirmed that compensating for oxygen vacancies made it more difficult for Mg to diffuse. In this example, it was confirmed that the greater the amount of oxygen ions implanted, the shallower the Mg termination depth. In other words, it was confirmed that the greater the ratio of the O concentration to the Mg concentration, the shallower the Mg termination depth.

[0027] The inventors also conducted similar experiments by changing the Mg concentration, and obtained the results shown in Figures 6 and 7. Note that Figure 6 shows the results when the Mg concentration was 1 x 10 19 cm -3 6 shows the result of ion implantation of Mg so that the depth of the pre-heating ion-implanted layer 32 is about 0.5 μm. In addition, FIG. 6 shows the result of ion implantation of oxygen ions at varying concentrations to approximately the same depth as the pre-heating ion-implanted layer 32. Specifically, in FIG. 6, 18 O concentration is 1×10 18 cm -3 , 1.25×10 19 cm -3 , 1×10 20 cm -3Oxygen ions are implanted so that: 18 The O concentration is relative to the Mg concentration. 18 As a ratio of O concentrations, 18 O concentration is 1×10 18 cm -3 If the ratio is 1:0.1, 18 O concentration is 1.25 × 10 19 cm -3 If the ratio is 1:1.25, 18 O concentration is 1×10 20 cm -3 In this case, when oxygen ions are implanted, the ratio of oxygen-containing ions is 1:10. 18 O (i.e., oxygen isotope) is ion-implanted.

[0028] The Mg concentration before the heat treatment in FIG. 7 is the same as the Mg concentration in FIG. 6. 18 The O concentration is the concentration before heat treatment in Figure 6. 18 O concentration is 1×10 20 cm -3 (i.e., Mg: 18 The results are the same as in the case of (O=1:10). 18 The O concentration is the total concentration of the O contained in the semiconductor substrate 10. 18 O concentration.

[0029] As shown in FIG. 7, when the guard ring layer 31 is formed, the Mg concentration and 18 Even when the ratio of the O concentration to the Mg:O concentration is 1:0.1, when oxygen ions are not implanted (i.e., when Mg: 18 It is confirmed that the diffusion of Mg is suppressed compared to the case where the oxygen ion implantation is performed in the presence of oxygen ions (O=1:0). In other words, the diffusion of Mg can be suppressed by implanting oxygen ions. 18 It was confirmed that the diffusion of Mg can be sufficiently suppressed if the O concentration is 0.1 times or more the Mg concentration.

[0030] In this example, the Mg concentration and 18It was also confirmed that when the ratio of Mg to O concentration was 1:10, there was almost no diffusion of Mg and O. 18 The O concentration is the total concentration of the O contained in the semiconductor substrate 10. 18 The O concentration is higher in the range of depths of approximately 0.5 μm or less than that at locations deeper than 0.5 μm because the ion-implanted oxygen isotopes are included.

[0031] In addition, the results in Figure 7 show that the Mg concentration 18 The ratio of Mg concentration to O concentration is 1:0.1. 18 It was confirmed that Mg did not diffuse when the ratio of Mg to O concentration was 1:1.25. Although the exact reason for this is not clear, the inventors presume that the relationship between the amount of Mg implanted and the amount of oxygen isotopes (i.e., oxygen ions) implanted is due to the influence of the relationship between the oxygen vacancies that may be formed during Mg ion implantation and the amount of oxygen isotopes that compensate for the oxygen vacancies.

[0032] The relationships in Figures 4 and 7 can be summarized as shown in Figure 8. As shown in Figure 8, it can be confirmed that in the range where the ratio of O concentration to Mg concentration, O / Mg, is greater than 1.25, the larger the O / Mg ratio, the more difficult it becomes for Mg to diffuse. Note that the Mg depth before heat treatment in Figure 8 is the termination depth of Mg before heat treatment, which is approximately 0.5 μm in Figures 3 and 6.

[0033] Furthermore, to summarize the above results, when the oxygen vacancy compensation step is performed, it is preferable that the relationship between the Mg concentration and the O concentration be as follows before the heat treatment.

[0034] First, as shown in Figure 9, when Mg ions are implanted as a p-type impurity, it is preferable that the O concentration be 0.1 times or more the Mg concentration. This sufficiently suppresses the diffusion of Mg. Note that although the above describes an example of implanting Mg ions as a p-type impurity, similar effects can be obtained when other impurities, as described below, are implanted, as long as the O concentration is 0.1 times or more the concentration of the implanted impurity.

[0035] As described above, it is presumed that Mg diffuses through oxygen vacancies when activated by heat treatment. Therefore, as shown in FIGS. 10 to 12, oxygen ions are preferably implanted deeper than the impurities used to form the guard ring layer 31. That is, before heat treatment, the termination depth of the O concentration is preferably set deeper than the termination depth of the Mg concentration. This makes it easier to suppress Mg diffusion in the depth direction. In this case, as shown in FIG. 13, if the region into which oxygen ions are implanted is defined as the oxygen ion-implanted layer 33, the oxygen ion-implanted layer 33 is preferably formed so as to entirely surround the pre-heating ion-implanted layer 32. In other words, it is preferable that the pre-heating ion-implanted layer 32 is present only within the oxygen ion-implanted layer 33. This also suppresses Mg diffusion in the in-plane direction of the semiconductor substrate 10.

[0036] As shown in Fig. 10, the O concentration is preferably higher than the Mg concentration throughout the entire depth direction. However, as shown in Fig. 11, even if the O concentration is lower than the Mg concentration in some areas, the diffusion of Mg can be suppressed by compensating for oxygen vacancies. Furthermore, as shown in Fig. 12, it is preferable that the total amount of oxygen ions implanted is greater than the total amount of Mg ions implanted. This makes it easier to compensate for oxygen vacancies and suppress the diffusion of Mg.

[0037] 10 to 12, Mg is used as an example of a p-type impurity for forming guard ring layer 31, but the same applies to the case where other p-type impurities are ion-implanted. Also, while the example of forming guard ring layer 31 by ion-implanting p-type impurities has been described here, the same applies to the case where an n-type impurity is ion-implanted to form a post-heating ion-implanted layer. For example, when an impurity is ion-implanted into semiconductor substrate 10 made of an oxide semiconductor to form a post-heating ion-implanted layer, the impurity to be used may be at least one of Mg, Be, Ca, Zn, N, Ni, Cu, Si, Ge, Sn, C, and Cl.

[0038] According to the present embodiment described above, the oxygen vacancy compensation step is performed before the heat treatment to form the guard ring layer 31 (i.e., the post-heat ion-implanted layer). This prevents the impurities constituting the guard ring layer 31 from diffusing through the oxygen vacancies, thereby preventing fluctuations in the characteristics of the semiconductor device.

[0039] In addition, in this embodiment, the oxygen vacancy compensation process can suppress the diffusion of impurities, so that when the heat treatment is performed to activate the impurities, the heat treatment can be performed at a high temperature of 1000°C or higher, and the impurities can be sufficiently activated.

[0040] (1) In this embodiment, the oxygen vacancy compensation step is performed by implanting oxygen-containing ions, which allows oxygen vacancy compensation to be performed in a simple manner.

[0041] (2) In this embodiment, the post-heating ion-implanted layer can be formed by ion-implanting at least one of Mg, Be, Ca, Zn, N, Ni, Cu, Si, Ge, Sn, C, and Cl as the impurity to form the post-heating ion-implanted layer, thereby improving the freedom of impurity selection.

[0042] (3) In this embodiment, when the guard ring layer 31 is formed by ion implantation of Mg, by ion implanting oxygen-containing ions so that the O concentration before the heat treatment is 0.1 times or more the Mg concentration (i.e., the implanted impurity concentration), the diffusion of Mg can be sufficiently suppressed during the heat treatment.

[0043] (4) In this embodiment, by making the O concentration before the heat treatment higher overall than the impurity concentration, it is possible to easily suppress the diffusion of impurities when the heat treatment is performed.

[0044] (5) In this embodiment, the termination depth of the oxygen-containing ions before the heat treatment is set to be deeper than the termination depth of the impurities, which makes it easier to suppress the diffusion of the impurities when the heat treatment is performed.

[0045] (6) In this embodiment, the total amount of oxygen-containing ions implanted when forming the pre-heating ion-implanted layer 32 is set to be greater than the total amount of impurities implanted when forming the pre-heating ion-implanted layer 32, which makes it easier to suppress the diffusion of impurities during the heat treatment.

[0046] (Modification of the first embodiment) A modification of the first embodiment will be described. In the first embodiment, the semiconductor device may be configured such that a junction barrier Schottky diode in which a donor compensation layer 34 is formed is formed on the inner edge of a portion of the semiconductor layer 12 that is connected to the first electrode 21, as shown in Fig. 14. In this case, the donor compensation layer 34, like the guard ring layer 31, is configured of a post-heating ion-implanted layer that is activated after ion-implantation of p-type impurities. Therefore, by performing an oxygen vacancy compensation step also on the portion where the donor compensation layer 34 is formed, diffusion of the donor compensation layer 34 can be suppressed.

[0047] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the semiconductor element is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0048] The semiconductor device of this embodiment is configured by forming a MOSFET, as shown in Fig. 15. Specifically, this semiconductor device includes a semiconductor substrate 10 similar to that of the first embodiment. A channel layer 35 serving as a donor compensation layer is formed on one surface 10a of the semiconductor substrate 10. An n-type source layer 36 is formed in a surface portion of the channel layer 35.

[0049] The channel layer 35 is formed by ion-implanting p-type impurities and then activating the p-type impurities. The source layer 36 is formed by ion-implanting n-type impurities and then activating the p-type impurities. Therefore, in this embodiment, the channel layer 35 and the source layer 36 correspond to post-heating ion-implanted layers.

[0050] Moreover, on one surface 10a of the semiconductor substrate 10, a gate insulating film 37 made of an oxide film or the like is disposed on the channel layer 35. Then, on the gate insulating film 37, a gate electrode 38 made of doped polysilicon or the like is disposed.

[0051] A first electrode 21, which functions as a source electrode and is connected to the channel layer 35 and the source layer 36, is disposed on one surface 10a of the semiconductor substrate 10. A second electrode 22, which functions as a drain electrode and is connected to the substrate 11, is disposed on the other surface 10b of the semiconductor substrate 10.

[0052] Such a semiconductor device is manufactured by preparing a semiconductor substrate 10, and then forming a channel layer 35 and a source layer 36, as well as forming a gate insulating film 37, a gate electrode 38, a first electrode 21, a second electrode 22, etc.

[0053] The channel layer 35 is formed by ion-implanting p-type impurities and then activating the p-type impurities, while the source layer 36 is formed by ion-implanting n-type impurities and then activating the n-type impurities. Therefore, in this embodiment, the channel layer 35 is formed by ion-implanting p-type impurities and oxygen-containing ions, followed by a heat treatment. Similarly, the source layer 36 is formed by ion-implanting n-type impurities and oxygen-containing ions, followed by a heat treatment. In this case, the step of ion-implanting oxygen-containing ions to form the channel layer 35 and the step of ion-implanting oxygen-containing ions to form the source layer 36 may be performed in the same step.

[0054] As in the present embodiment described above, even in a semiconductor device including the channel layer 35 and the source layer 36 formed from the post-heating ion-implanted layer, the oxygen vacancy compensation step can be performed to suppress diffusion of impurities forming the channel layer 35 and the source layer 36.

[0055] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0056] In each of the above embodiments, examples have been described in which the heat treatment is performed at 1000°C or higher, but the heat treatment may be performed at a temperature lower than 1000°C as long as the impurities are activated, for example, at a temperature higher than 500°C but lower than 1000°C.

[0057] In each of the above embodiments, the oxygen vacancy compensation step may be performed by other methods than by ion implantation of oxygen-containing ions. For example, before ion implantation of impurities into the semiconductor substrate 10, a heat treatment may be performed in the atmosphere to incorporate oxygen from the atmosphere into the semiconductor substrate 10, thereby compensating for oxygen vacancies.

[0058] Furthermore, in each of the above embodiments, after the oxygen vacancy compensation step, the impurity ion implantation and the heat treatment to activate the impurity may be performed simultaneously. For example, after the oxygen vacancy compensation step, the impurity ion implantation may be performed at a temperature of 1000°C, thereby activating the impurity while implanting the impurity. This eliminates the need for a heat treatment solely for activating the impurity, thereby reducing the number of manufacturing steps.

[0059] Furthermore, in each of the above embodiments, an example has been described in which the semiconductor substrate 10 is of n-type, but the semiconductor substrate 10 may be of p-type, and n-type impurities may be ion-implanted to form an ion-implanted layer after heating.

[0060] In addition, in each of the above embodiments, an example has been described in which the semiconductor substrate 10 is made of GaO. However, the semiconductor substrate 10 may be made of any oxide semiconductor, such as a GaO-based material such as (AlInGa)O.

[0061] In the second embodiment, a semiconductor device in which a planar gate type MOSFET is formed has been described, but the semiconductor device may be configured with a trench gate type MOSFET formed therein. Also, the semiconductor device may be configured with an IGBT having a similar structure formed therein, in addition to a MOSFET. In the case of an IGBT, the n-type MOSFET in the first embodiment is + The substrate 11 is + The structure is the same as that of the second embodiment except for the change to a mold substrate (that is, collector layer).

[0062] [Disclosure of the Invention] The present disclosure described above can be understood from the following viewpoints, for example.

[0063] [First viewpoint] A method for manufacturing a semiconductor device, comprising: Preparing a semiconductor substrate (10) made of an oxide semiconductor and having one surface (10a); ion-implanting impurities of a first conductivity type or a second conductivity type from one surface of the semiconductor substrate; performing oxygen vacancy compensation in the region of the semiconductor substrate where the ion-implanted layer (31, 34, 35, 36) will be formed after heating; and performing a heat treatment to activate the impurities and form the post-heating ion-implanted layer.

[0064] [Second perspective] The method for manufacturing a semiconductor device according to the first aspect, wherein the oxygen vacancy compensation includes implanting oxygen-containing ions that contain oxygen.

[0065] [Third Perspective] The impurity is ion-implanted so as to form a pre-heating ion-implanted layer (32) in which the impurity is in an inactive state; The method for manufacturing a semiconductor device according to the second aspect, wherein the heat treatment is carried out after the impurity ion implantation and the oxygen vacancy compensation.

[0066] [Fourth viewpoint] The method for manufacturing a semiconductor device according to the second aspect, wherein after the oxygen vacancy compensation, the impurities are ion-implanted at a temperature at which the impurities are activated, thereby simultaneously implanting the impurities and performing the heat treatment.

[0067] [Fifth viewpoint] The method for manufacturing a semiconductor device according to any one of the second to fourth aspects, wherein the impurity ion implantation and the oxygen vacancy compensation are performed by implanting the oxygen-containing ions so that the oxygen concentration is 0.1 times or more the impurity concentration.

[0068] [Sixth viewpoint] The method for manufacturing a semiconductor device according to the fifth aspect, wherein the impurity ion implantation and the oxygen vacancy compensation are performed such that the oxygen concentration is higher than the impurity concentration in the entire region in the depth direction of the semiconductor substrate.

[0069] [Seventh viewpoint] The method for manufacturing a semiconductor device according to any one of the second to fourth aspects, wherein the impurity is ion-implanted and the oxygen-containing ions are ion-implanted at the same time such that, in the ion-implantation of the impurity and the oxygen vacancy compensation, a termination depth of the oxygen-containing ions is deeper than a termination depth of the impurity in a depth direction of the semiconductor substrate at an implantation concentration.

[0070] [Eighth viewpoint] The method for manufacturing a semiconductor device according to the seventh aspect, wherein the impurity is ion-implanted and the oxygen-containing ions are simultaneously implanted so that, in implantation concentrations, a total amount of oxygen when the oxygen-containing ions are ion-implanted is greater than a total amount of impurities ion-implanted when the impurity is ion-implanted.

[0071] [Ninth viewpoint] The method for manufacturing a semiconductor device according to any one of the second to eighth aspects, wherein the impurity ion implantation includes ion implantation of at least one of Mg, Be, Ca, Zn, N, Ni, Cu, Si, Ge, Sn, C, and Cl.

[0072] [10th viewpoint] The method for manufacturing a semiconductor device according to any one of the first to ninth aspects, wherein the step of preparing the semiconductor substrate comprises preparing the semiconductor substrate made of a Ga2O3-based material.

[0073] [11th viewpoint] The method for manufacturing a semiconductor device according to a tenth aspect, wherein the step of preparing the semiconductor substrate comprises preparing the semiconductor substrate made of (AlInGa)2O3 as a Ga2O3-based material. [Explanation of symbols]

[0074] 10. Semiconductor substrate 10a one side 31 Guard ring layer (ion-implanted layer after heating) 32 Pre-heating ion implanted layer

Claims

1. A method for manufacturing a semiconductor device, comprising: Preparing a semiconductor substrate (10) made of an oxide semiconductor and having one surface (10a); ion-implanting impurities of a first conductivity type or a second conductivity type from one surface of the semiconductor substrate; performing oxygen vacancy compensation in the region of the semiconductor substrate where the ion-implanted layer (31, 34, 35, 36) will be formed after heating; and performing a heat treatment to activate the impurities and form the post-heating ion-implanted layer.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxygen vacancy compensation comprises implanting oxygen-containing ions containing oxygen.

3. The impurity is ion-implanted so as to form a pre-heating ion-implanted layer (32) in which the impurity is in an inactive state; 3. The method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed after the impurity ion implantation and the oxygen vacancy compensation.

4. 3. The method for manufacturing a semiconductor device according to claim 2, wherein after the oxygen vacancy compensation, the impurity is ion-implanted at a temperature at which the impurity is activated, thereby simultaneously implanting the impurity and performing the heat treatment.

5. 5. The method for manufacturing a semiconductor device according to claim 2, wherein the oxygen-containing ions are implanted so that the oxygen concentration is 0.1 times or more the impurity concentration in the ion implantation and the oxygen vacancy compensation.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the impurity is ion-implanted and the oxygen-containing ions are ion-implanted so that the oxygen concentration is higher than the impurity concentration in the entire region in the depth direction of the semiconductor substrate in the ion-implantation of the impurity and the oxygen vacancy compensation.

7. 5. The method for manufacturing a semiconductor device according to claim 2, wherein the impurity is ion-implanted and the oxygen-containing ions are ion-implanted at the same time so that, in the implantation concentration, a termination depth of the oxygen-containing ions is deeper than a termination depth of the impurity in a depth direction of the semiconductor substrate.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the impurity is ion-implanted and the oxygen-containing ions are simultaneously implanted so that, in implantation concentrations, a total amount of oxygen when the oxygen-containing ions are ion-implanted is greater than a total amount of impurities ion-implanted when the impurities are ion-implanted.

9. 5. The method for manufacturing a semiconductor device according to claim 2, wherein the impurity ion implantation includes ion implantation of at least one of Mg, Be, Ca, Zn, N, Ni, Cu, Si, Ge, Sn, C, and Cl.

10. By preparing the semiconductor substrate, Ga ２ O ３ 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made of a material selected from the group consisting of fluorine and fluorine-containing compounds.

11. By preparing the semiconductor substrate, Ga ２ O ３ As a material of the system, (AlInGa) ２ O ３ The method for manufacturing a semiconductor device according to claim 10 , wherein the semiconductor substrate is prepared by:

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