Semiconductor device

Abstract

To provide a semiconductor device.SOLUTION: A semiconductor device comprises: a first type semiconductor structure that includes a first lattice constant, and includes a first side and a second side that is opposite to the first side; an active structure that is positioned on the first side, and emits a radial ray, of which a peak wavelength is 1000nm to 2000nm; and a first contact layer that is positioned to the second side, includes a second lattice constant, and contains a first dopant having a first doping concentration that is larger than 1*1018 / cm3. A difference between the second lattice constant and the first lattice constant is at least 0.5%.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a lattice constant difference. [Background technology]

[0002] With the rapid advancement of science and technology, semiconductor devices play a vital role in fields such as information transmission and energy conversion, and research and development of related materials is also being continuously conducted. For example, semiconductor materials can be applied to various photoelectric devices, such as light emitting diodes (LEDs), laser diodes (LDs), solar cells, power devices, and acoustic wave sensors, as well as in fields such as lighting, displays, communications, detection, and power supply systems.

[0003] The principle of light emission in light-emitting diodes is that when a current is applied, electrons in the N-type semiconductor layer combine with holes in the P-type semiconductor layer, converting electrical energy into light energy. Light-emitting diodes have the advantages of low power consumption and long service life, and are widely used in traffic lights, backlight modules, various types of lighting, medical equipment, etc., replacing traditional light sources. Infrared light-emitting diodes also have a large market and potential in detection systems, recognition systems, monitoring systems, and vehicle light sources. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor element having a lattice constant difference. [Means for solving the problem]

[0005] According to some embodiments of the present invention, a semiconductor device is provided, comprising: a first-type semiconductor structure having a first lattice constant and having a first side and a second side opposite the first side; an active structure located on a first side of the first-type semiconductor structure and emitting radiation, the peak wavelength of the radiation being between 1000 nm and 2000 nm; and a first contact layer located on a second side of the first-type semiconductor structure, the first contact layer having a second lattice constant and a lattice constant greater than 1×10 18 / cm 3

[0023] including a first dopant having a first doping concentration greater than wherein the difference between the second lattice constant and the first lattice constant is at least 0.5%. [Brief explanation of the drawings]

[0006] DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will now be described in detail with reference to the drawings, in which various features are not drawn to scale and are for illustrative purposes only. The dimensions of elements may be arbitrarily increased or decreased to more clearly illustrate the features of the present invention. [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to an embodiment. [Figure 3] FIG. 1 is a top view of a semiconductor device according to an embodiment. [Figure 4A] 3A to 3C are cross-sectional views of stages in manufacturing the semiconductor device in FIG. 2. [Figure 4B] 3A to 3C are cross-sectional views of stages in manufacturing the semiconductor device in FIG. 2. [Figure 5] FIG. 1 is a diagram showing the relationship between the concentration of an element and the depth in a partial area of ​​a semiconductor element according to an embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor element according to another embodiment. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor element according to another embodiment. [Figure 8] FIG. 2 is a diagram showing a package structure of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following describes several examples to help those skilled in the art understand the present invention more easily. Note that these examples are merely illustrative and do not limit the present invention. Those skilled in the art may adjust the examples described below according to their needs, for example, by changing the order of the processes and / or adding or removing some steps.

[0008] Furthermore, other elements or steps may be added based on the embodiments described below. For example, a phrase such as "forming a second layer / structure on a first layer / structure" may include an embodiment in which the first layer / structure is in direct contact with the second layer / structure, or an embodiment in which the first layer / structure is not in direct contact with the second layer / structure due to the inclusion of other elements between the first and second layers / structures. The relative spatial relationship between the first and second layers / structures may change depending on the operation or use of the device in different orientations. Furthermore, the present invention may duplicate numerals and / or letters as reference characters in different embodiments; such duplication is for brevity and clarity, and does not represent a relationship between different embodiments. Furthermore, as used herein, a phrase such as "a layer "consisting essentially of material X" means that the layer is primarily composed of material X, but does not exclude the inclusion of dopants or unavoidable impurities.

[0009] In the embodiments of the present invention, unless otherwise specified, chemical formulas may include "stoichiometric compounds" and "non-stoichiometric compounds," where a "stoichiometric compound" refers to a compound in which the total amount of Group 3 elements is the same as the total amount of Group 5 elements, and a "non-stoichiometric compound" refers to a compound in which the total amount of Group 3 elements is different from the total amount of Group 5 elements. For example, a chemical formula of AlGaAs means that the compound contains Group 3 elements Al and / or Ga and also contains Group 5 element As, where the total amount of Group 3 elements (Al and / or Ga) may be the same as or different from the total amount of Group 5 element (As).

[0010] Also, when each compound represented by a chemical formula is a stoichiometric compound, AlGaAs represents Al x1 Ga (1-x1) As, where 0 < x1 < 1, AlInP represents Al x2 In (1-x2) P, where 0 < x2 < 1, AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0 < x3 < 1 and 0 < y1 < 1, AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x4 In x4 As, where 0 < x4 < 1 and 0 < y2 < 1, AlGaN represents Al x5 Ga (1-x5) [[ID=?]]N, where 0 < x5 < 1, AlAsSb represents AlAs x6 Sb (1-x6) where 0 < x6 < 1, InGaP represents In x7 Ga 1-x7 P, where 0 < x7 < 1, InGaAsP represents In x8 Ga 1-x8 As 1-y3 P y3 where 0 < x8 < 1 and 0 < y3 < 1, InGaAsN represents In x9 Ga 1-x9 As 1-y4 N y4 where 0 < x9 < 1 and 0 < y4 < 1, AlGaAsP represents Al x10 Ga 1-x10 As 1-y5 P y5 where 0 < x10 < 1 and 0 < y5 < 1, InGaAs represents In x11 Ga 1-x11 As, where 0 < x11 < 1.

[0011] It seems there is an issue with the "?N" in the original text. Please check and correct it if possible for a more accurate translation.For ease of explanation, the present invention will be described below using a tetrad (i.e., four-element) light-emitting diode as an example, but the present invention is not limited thereto. The present invention can also be applied to other types of semiconductor devices, such as dyadic (i.e., two-element) or ternary (i.e., three-element) light-emitting diodes or other semiconductor devices, and the two electrodes of the semiconductor device may be located on either side of the semiconductor device or on the same side of the semiconductor device. Note that the terms "tetrad" (i.e., quaternary), "ternary" (i.e., ternary), and "dyadic" (i.e., binary) mean that the semiconductor stack layers of the light-emitting diode contain compounds consisting of four, three, and two elements, respectively.

[0012] The following describes semiconductor devices based on several embodiments of the present invention, which are particularly applicable to light-emitting devices emitting near-infrared (NIR) rays. In these embodiments, a semiconductor device is provided. When the semiconductor device is a light-emitting diode, a contact layer and / or window layer near the light-emitting surface uses a material that does not absorb light (hereinafter referred to as a non-light-absorbing material). Since the absorption wavelength of this non-light-absorbing material differs from the emission wavelength of the active structure, it does not absorb the light emitted by the active structure, thereby improving light-emitting efficiency. Furthermore, since there is no need to remove the contact layer in an additional step in a subsequent process, the manufacturing steps can be reduced. Furthermore, performing a roughening process on the contact layer and / or window layer can further improve the brightness of the semiconductor device. In some embodiments, the material of the active structure may include a quaternary compound semiconductor, such as AlInGaAs or InGaAsP, and the non-light-absorbing material may include a binary compound semiconductor, such as GaAs or InP. In another embodiment, the active structure is or consists essentially of AlInGaAs and the optically non-absorbing material consists essentially of GaAs or InP, and in still other embodiments, the active structure is or consists essentially of InGaAsP and the optically non-absorbing material consists essentially of GaAs or InP.

[0013] 1 is a cross-sectional view of one embodiment of a semiconductor device 100. The semiconductor device 100 includes a base 102 and a semiconductor stack layer S located on the base 102. The semiconductor stack layer S includes a first contact layer 104, a first window layer 106, a buffer layer 108, a first-type semiconductor structure 110, an active structure 112, a second-type semiconductor structure 114, a second window layer 116, and a second contact layer 118.

[0014] In some embodiments, the semiconductor stack layers S can be epitaxially grown or connected to the base 102; i.e., the base 102 can be a growth substrate or a non-growth substrate. The base 102 is used to support the semiconductor stack layers S and other layers or structures thereon, and the base 102 can be transparent, semi-transparent, or opaque to the light emitted by the active structure 112, and can be a conductor, a semiconductor, or an insulator. In this embodiment, since the semiconductor device 100 is vertically configured, the base 102 is a conductive material and includes a metal material, a metal alloy material, a metal oxide material, a semiconductor material, or a carbon-containing material. The metal material may include Cu, Al, Cr, Sn, Au, Ni, Ti, Pt, Pb, Zn, Cd, Sb, or Co. The metal alloy material is an alloy containing these metal materials. The semiconductor material may include, but is not limited to, a Group IV semiconductor or a Group III-V semiconductor, such as Si, Ge, SiC, GaN, GaP, GaAs, AsGaP, or InP. The metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, or IZO. The carbon-containing material may include, but is not limited to, diamond-like carbon (DLC) or graphene. In another embodiment, when the semiconductor device 100 has a non-vertical configuration, the base 102 may include an insulating material, such as sapphire, glass, an insulating nitride (e.g., SiN), or an insulating oxide (e.g., SiO). In this embodiment, the semiconductor device is a near-infrared light-emitting device, and the material of the base 102 includes InP or GaAs, for example, the material of the base 102 is InP or GaAs, or consists essentially of InP or GaAs.

[0015] In some embodiments, the formation of the second contact layer 118, the second window layer 116, the second-type semiconductor structure 114, the active structure 112, the first-type semiconductor structure 110, the buffer layer 108, the first window layer 106, and the first contact layer 104 may be grown, in order, on the base 102 or growth substrate (not shown) by an epitaxial method, including MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), similar methods, or a combination thereof.

[0016] In some embodiments, the materials of the first contact layer 104, the first window layer 106, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 may each independently comprise a III-V (also referred to as "III-V") compound semiconductor material, such as AlGaInAs, AlGaAs, AlInAs, GaInAs, AlAs, GaAs, InAs, AlGaInP, AlGaP, AlInP, GaInP, AlP, GaP, InP, AlInGaN, AlInN, AlGaN, InGaN, AlAsSb, AlSb, AsSb, InGaAsP, InAsP, GaAsP, InGaAsN, InAsN, GaAsN, InN, AlGaAsP, AlAsP, or similar III-V compound semiconductor materials.

[0017] As shown in FIG. 1, the active structure 112 is located between the first-type semiconductor structure 110 and the second-type semiconductor structure 114. When the semiconductor device 100 according to the present invention is a light-emitting device, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 may be, for example, cladding layers and / or confinement layers, which provide electrons and holes, respectively, and have a larger energy gap than the active layer, thereby improving the probability that the electrons and holes will combine and emit light in the active structure 112. The active structure 112 may emit radiation. For example, for a near-infrared light-emitting device, the radiation may have a peak wavelength between 1000 nm and 2000 nm, preferably between 1200 nm and 1800 nm, e.g., 1250 nm and 1650 nm.

[0018] The semiconductor device 100 may include a single heterostructure (SH), double heterostructure (DH), double-sided double heterostructure (DDH), or multiple quantum wells (MQW) structure. In some embodiments, the active structure 112 is an MQW structure, which includes multiple barrier layers and multiple well layers stacked alternately, with the barrier layers having a higher energy gap than the well layers. In some embodiments, the barrier layers and well layers may each independently include a quaternary material or a trinary material. In some embodiments, the active structure 112 may include Al, Ga, In, P, or As, preferably an N-free quaternary compound, such as AlGaInAs or InGaAsP.

[0019] 1, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 are located on either side of the active structure 112, respectively. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 may be single-layered or multi-layered, and have a larger energy gap than the active structure 112. They are used to confine carriers in the active structure 112, effectively prevent carrier overflow in the active structure 112, and / or provide electrons and holes to the active structure 112, respectively. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 may include Group III or V semiconductor materials, suitable examples of which have been described above and will not be described in detail here. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 are preferably ternary or binary compounds containing Al, Ga, As, P, In, or a combination thereof, and preferably excluding N, such as InAlAs or InP.

[0020] In some embodiments, the first-type semiconductor structure 110 has a first conductivity type, and the second-type semiconductor structure 114 has a second conductivity type, where the first conductivity type is different from the second conductivity type. For example, the first conductivity type and the second conductivity type may be P-type and N-type, respectively, or N-type and P-type, respectively. The first-type semiconductor structure 110 and the second-type semiconductor structure 114 have different conductivity types, for example, by adding different dopants. For example, the first-type semiconductor structure 110 has a first dopant, and the second-type semiconductor structure 114 has a second dopant that is different from the first dopant of the first-type semiconductor structure 110. Specifically, these dopants may include Mg, Zn, Si, Te, etc. In some embodiments, the first-type semiconductor structure 110 and the second-type semiconductor structure 114 can be doped by in-situ doping during epitaxial growth and / or by performing an implantation process with P-type or N-type dopants after epitaxial growth. For example, in this embodiment, the dopant of the first-type semiconductor structure 110 is Zn and the dopant of the second-type semiconductor structure 114 is Si.

[0021] In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 and the doping concentration of the dopant in the second-type semiconductor structure 114 are each independently 1×10 16 / cm 3 ~5×10 18 / cm 3 In one embodiment, the doping concentration of the dopant in the first-type semiconductor structure 110 may be greater than the doping concentration of the dopant in the second-type semiconductor structure 114. By way of example, the doping concentration of the dopant in the first-type semiconductor structure 110 may be in the range of 1×10 17 / cm 3 ~1×10 18 / cm 3 and preferably 3 x 10 17 / cm 3 ~8×10 17 / cm 3and the doping concentration of the dopant in the second-type semiconductor structure 114 is 3×10 16 / cm 3 ~1×10 18 / cm 3 and preferably 5 x 10 16 / cm 3 ~9×10 17 / cm 3 In some embodiments, the thickness of the first-type semiconductor structure 110 and the thickness of the second-type semiconductor structure 114 may each independently be in the range of 100 nm to 1200 nm, for example, both in the range of 200 nm to 1000 nm.

[0022] In the description of the embodiment of the present invention, the first contact layer 104 and the first window layer 106 are each composed of the same non-absorbing material, and the non-absorbing material is GaAs. The first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 may each independently comprise any suitable material. However, the present invention is not limited to this example. In another example, the first contact layer 104 and the first window layer 106 may each independently comprise different non-absorbing materials, such as GaAs and InP, respectively. Furthermore, the second contact layer 118 and the second window layer 116 may each independently comprise the same or different non-absorbing materials, and the first contact layer 104 and the first window layer 106 may each independently comprise any suitable material. Alternatively, in other embodiments, the first contact layer 104, the first window layer 106, the second contact layer 118, and the second window layer 116 comprise optically non-absorbing materials, which may be the same or different.

[0023] As shown in FIG. 1, the semiconductor device 100 includes a first contact layer 104 positioned above a first-type semiconductor structure 110, with the first-type semiconductor structure 110 positioned between the first contact layer 104 and the base 102. Specifically, the first-type semiconductor structure 110 includes a first side S1 and a second side S2 opposite the first side S1, with the second side S2 being farther from the base 102 than the first side S1. The active structure 112 is disposed on the first side S1, and the first contact layer 104 is disposed on the second side S2. The energy gap of the first contact layer 104 is larger than the energy gaps of the active structure 112 and the first-type semiconductor structure 110, thereby preventing a decrease in the efficiency of the semiconductor device 100 due to light absorption by the first contact layer 104. In one embodiment, the difference between the energy gap of the first contact layer 104 and the energy gap of the active structure 112 is 0.3 eV to 0.8 eV, preferably 0.4 eV to 0.7 eV.

[0024] The first-type semiconductor structure 110 has a first lattice constant, and the first contact layer 104 has a second lattice constant, where the first lattice constant is different from the second lattice constant, i.e., the first-type semiconductor structure 110 and the first contact layer 104 are lattice mismatched. When the first-type semiconductor structure 11 consists of a single layer, the lattice constant of the single layer is defined as the first lattice constant. When the first-type semiconductor structure 11 consists of multiple layers, the average (arithmetic mean) of the lattice constants of these multiple layers is defined as the first lattice constant. In some embodiments, the difference between the second lattice constant and the first lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, and more preferably 3% to 4.5%. The difference D1 between the second lattice constant and the first lattice constant is calculated using the following formula (1), where d1 represents the first lattice constant and d2 represents the second lattice constant.

[0025] Difference D1=((d2-d1) / d2)×100%...Equation (1) In this embodiment, the material of the first-type semiconductor structure 110 is In 0.53 Al 0.47As or essentially In 0.53 Al 0.47 The first lattice constant is 5.848, and the material of the first contact layer 104 is GaAs or essentially GaAs, the second lattice constant is 5.653, and the difference between the second lattice constant and the first lattice constant is 3.45%. The lattice constants may be obtained in any suitable manner. For example, the lattice constants of the first-type semiconductor structure 110 and the first contact layer 104 may be analyzed using a diffraction pattern by transmission electron microscopy (TEM), or the lattice constant information may be obtained by X-ray diffraction (XRD) at a temperature of 300 K. In the context of the present invention, the "lattice constant" is defined as the lattice constant a of a substantially unstrained layer.

[0026] In one embodiment, the thickness of the first contact layer 104 may be in the range of 5 nm to 100 nm, for example, 50 nm. In addition, the surface of the first contact layer 104 may have a selectively roughened structure, which can reduce the probability of the light emitted by the active structure 112 undergoing total reflection in the semiconductor stack layer S, improve the light extraction efficiency, and further improve the brightness of the semiconductor device 100.

[0027] 1, the first window layer 106 is disposed between the first contact layer 104 and the first-type semiconductor structure 110. The first window layer 106 is used to increase the light extraction efficiency of the semiconductor device 100 and / or distribute current uniformly in the semiconductor stack layers S. In one embodiment, the first window layer 106 and the first contact layer 104 are made of the same material, i.e., the first window layer 106 and the first contact layer 104 have the same lattice constant (both have a second lattice constant) and differ from the first lattice constant of the first-type semiconductor structure 110 by at least 0.5%; for example, the materials of the first contact layer 104 and the first window layer 106 are both GaAs or consist essentially of GaAs. In another embodiment, the first contact layer 104 and the first window layer 106 may be made of different materials, and the first window layer 106 may have a lattice constant that differs from the first lattice constant by less than 0.5%. In other embodiments, the material of the first window layer 106 may be the same as the material of the base 102, for example, the first contact layer 104 may be GaAs or consist essentially of GaAs, and the first window layer 106 and the base 102 may both be InP or consist essentially of InP.

[0028] The conductivity type of the first contact layer 104 and the first window layer 106 may also be the same as the conductivity type of the first-type semiconductor structure 110. For example, the conductivity types of the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 are all P-type, and the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 all contain the same dopant, for example, Zn. The doping of the first contact layer 104 and the first window layer 106 is performed by in-situ doping during epitaxial growth and / or by implanting with a dopant after epitaxial growth. The doping concentration of the dopant in the first contact layer 104 is greater than the doping concentration of the first-type semiconductor structure 110 and is less than 1×10 18 / cm 3, which allows a relatively low resistance between the first contact layer 104 and the electrode structure thereon, and preferably the doping concentration of the dopant in the first contact layer 104 is, for example, 2×10 18 / cm 3 ~5×10 19 / cm 3 The first window layer 106 has a greater thickness and / or a relatively lower doping concentration than the first-type semiconductor structure 110, which can increase light extraction or improve lateral current spreading capabilities.

[0029] The doping concentration of the dopant in the first contact layer 104 is different from the doping concentration of the dopant in the first window layer 106. In some embodiments, the doping concentration of the dopant in the first window layer 106 is less than the doping concentration of the dopant in the first contact layer 104. In one embodiment, the doping concentration of the dopant in the first window layer 106 is less than 2×10 16 / cm 3 ~1×10 19 / cm 3 may be in the range of, for example, 4 × 10 16 / cm 3 ~8×10 18 / cm 3 is.

[0030] In some embodiments, the thickness of the first window layer 106 may be greater than the thickness of the first contact layer 104. In one embodiment, the thickness of the first window layer 106 may be in the range of 300 nm to 10,000 nm, preferably in the range of 500 nm to 8,000 nm, and in this embodiment is, for example, 7,000 nm.

[0031] As shown in FIG. 1 , the buffer layer 108 is provided between the first window layer 106 and the first-type semiconductor structure 110 to reduce the energy level difference between the first-type semiconductor structure 110 and the first window layer 106. Specifically, there is a valence band energy gap (Ev) difference between the valence band energy level of the first window layer 106 and the valence band energy level of the first-type semiconductor structure 110, and there is a conduction band energy gap (Ec) difference between the conduction band energy level of the first window layer 106 and the conduction band energy level of the first-type semiconductor structure 110. When the valence band energy gap difference and / or the conduction band energy gap difference are too large, an additional voltage difference must be provided to transport carriers, which may cause a high forward voltage (Vf) in the semiconductor device, resulting in problems such as a decrease in saturation current or early failure of the semiconductor device. Therefore, providing the buffer layer 108 between the first window layer 106 and the first-type semiconductor structure 110 can avoid such problems. The buffer layer 108 has a valence band energy level between the valence band energy level of the first-type semiconductor structure 110 and the valence band energy level of the first window layer 106, and the buffer layer 108 has a conduction band energy level between the conduction band energy level of the first-type semiconductor structure 110 and the conduction band energy level of the first contact layer 104, thereby reducing the energy level difference between the first-type semiconductor structure 110 and the first window layer 106 and improving the reliability of the semiconductor device 100. In another embodiment, the first window layer 106 may be selectively provided, and when the semiconductor device 100 does not include the first window layer 106, the buffer layer 108 may be provided between the first contact layer 104 and the first-type semiconductor structure 110 and directly contact the first contact layer 104 and the first-type semiconductor structure 110. As described above, the buffer layer 108 can reduce the energy level difference between the first contact layer 104 and the first-type semiconductor structure 110.

[0032] In some embodiments, the material of the buffer layer 108 may include a four-component semiconductor compound, such as AlGaInAs or InGaAsP. When the first contact layer 104 is GaAs or substantially consists of GaAs, and the first-type semiconductor structure 110 is InAlAs or substantially consists of InAlAs, the material of the buffer layer 108 is (Al x Ga 1-x ) 0.47 In 0.53 As (0 < x < 1), or substantially consists of (Al x Ga 1-x ) 0.47 In 0.53 As (0 < x < 1). In another embodiment, when the first contact layer 104 is GaAs or substantially consists of GaAs, and the first-type semiconductor structure 110 is InP or substantially consists of InP, the material of the buffer layer 108 is InGaAsP or substantially consists of InGaAsP.

[0033] When the buffer layer 108 is located between the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), the buffer layer 108 has the same conductivity type as the first-type semiconductor structure 110 and the first window layer 106 (or the first contact layer 104), and the three may include the same dopant. In one embodiment, the doping concentration of the dopant in the buffer layer 108 may be in the range of 5×10 16 / cm 3 ~2×10 18 / cm 3 , for example, 5×10 17 / cm 3 ~1×10 18 / cm 3 [[ID=三十六]]. Also, the thickness of the buffer layer 108 may be in the range of 10 nm to 200 nm, for example, 100 nm.

[0034] [[ID=三十九]] The buffer layer 108 is optional, and in some embodiments, the buffer layer 108 may not be provided, i.e., the first window layer 106 directly contacts the first-type semiconductor structure 110. The location and quantity of the buffer layer 108 may be adjusted depending on the characteristics of the actual product. In other embodiments, two or more buffer layers may be provided, and these buffer layers may have the same or different materials and / or doping concentrations. For example, in some embodiments, an additional buffer layer (not shown) may be provided between the second-type semiconductor structure 114 and the second window layer 116.

[0035] As shown in FIG. 1 , the second window layer 116 is disposed between the second-type semiconductor structure 114 and the base 102, with the second window layer 116 being spaced from the second side S2 of the first-type semiconductor structure 110. In some embodiments, the material of the second window layer 116 may include a Group III or V semiconductor material. In some embodiments, the material of the second window layer 116 may include a transparent conductive material. By way of example, but not limitation, the material of the second window layer 116 may include a metal oxide material or a semiconductor material. The metal oxide may include, but is not limited to, ITO, indium oxide (InO), tin oxide (SnO), chromium titanium oxide (CTO), antimony tin oxide (ATO), aluminum-doped zinc oxide (AZO), zinc tin oxide (ZTO), gallium-doped zinc oxide (GZO), indium tungsten oxide (IWO), ZnO, magnesium oxide (MgO), or IZO. The semiconductor material may include, but is not limited to, InP, GaAs, AlGaAs, GaP, etc. The material of the first window layer 106 may refer to the material of the second window layer 116. In one embodiment, the material of the second window layer 116 is the same as the material of the first window layer 106, e.g., all of InP or consisting essentially of InP. In other embodiments, the material of the second window layer 116 is different from the material of the first window layer 106, e.g., InP and GaAs, respectively, or consisting essentially of InP and GaAs, respectively.

[0036] The second window layer 116 has a third lattice constant that is different from the second lattice constant of the first contact layer 104. In some embodiments, the difference between the third lattice constant and the second lattice constant is at least 0.5%, for example, in the range of 1% to 6%, preferably 2% to 5%, and more preferably 3% to 4.5%. As described above, the third lattice constant of the second window layer 116 can be analyzed in any suitable manner. In some embodiments, the difference between the third lattice constant and the first lattice constant is 0.5% or less, and in other embodiments, the difference between the third lattice constant and the first lattice constant is less than 0.2% and greater than 0. The difference D2 between the third lattice constant and the first lattice constant is calculated using the following equation (2), where d1 represents the first lattice constant and d3 represents the third lattice constant.

[0037] Difference D2=((d3-d1) / d3)×100%...Equation (2) In one embodiment, the doping concentration of the dopant in the second window layer 116 is 1×10 16 / cm 3 It can be larger than, for example, 2 × 10 16 / cm 3 ~1×10 18 / cm 3 In some embodiments, the thickness of the second window layer 116 may be less than the thickness of the first window layer 106. In another embodiment, the thickness of the second window layer 116 may be greater than the thickness of the second-type semiconductor structure 114, or the second window layer 116 may have a relatively lower doping concentration than the second-type semiconductor structure 114, which may increase light extraction or improve lateral current spreading capabilities. In some embodiments, the thickness of the second window layer 116 may be in the range of 100 nm to 1000 nm, for example, 500 nm.

[0038] As shown in FIG. 1 , a second contact layer 118 may be optionally disposed between the second window layer 116 and the base 102, and the second contact layer 118 is spaced from the second side S2 of the first-type semiconductor structure 110. The material of the second contact layer 118 may include Group III or V semiconductor materials, and suitable examples have been described above, so detailed descriptions thereof will be omitted here. The conductivity type of the second contact layer 118 and the second window layer 116 is the same as the conductivity type of the second-type semiconductor structure 114. For example, the conductivity types of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 are all N-type, and the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 all contain the same dopant, e.g., Si. The doping concentration of the dopant in the second contact layer 118 is different from the doping concentration of the dopant in the second window layer 116. In some embodiments, the doping concentration of the dopant in the second contact layer 118 is greater than the doping concentration of the dopant in the second window layer 116. In one embodiment, the doping concentration of the dopant in the second contact layer 118 is greater than 5×10 17 / cm 3 , so that there is a relatively low resistance between the second contact layer 118 and the base 102. For example, the doping concentration of the dopant in the second contact layer 118 may be greater than 1×10 18 / cm 3 ~1×10 20 / cm 3 is in the range.

[0039] The semiconductor device 100 includes a first electrode 122 and a second electrode 120, respectively, located on opposite sides of the semiconductor device 100. For example, in this embodiment, the first contact layer 104 is located between the first-type semiconductor structure 110 and the first electrode 122, and the base 102 is located between the second electrode 120 and the second-type semiconductor structure 114, thereby forming a vertical semiconductor device 100. However, the present invention is not limited thereto, and in some other embodiments, the first electrode 122 and the second electrode 120 may be located on the same side of the base 102, thereby forming a horizontal semiconductor device. In one embodiment, the first contact layer 104 is formed between the first-type semiconductor structure 110 and the first electrode 122, and corresponds only to the location of the first electrode 122.

[0040] The first electrode 122 and the second electrode 120 are all connected to an external power source to conduct electrical current to the semiconductor device 100. In some embodiments, the material of the first electrode 122 and the material of the second electrode 120 may each independently comprise a metal material, an alloy material, a metal oxide material, or a carbon-containing material. By way of example, the metal material may include, but is not limited to, Al, Cr, Cu, Sn, Au, Ni, Ti, Pt, Pb, Zn, Cd, Sb, or Co; the alloy material may include an alloy of any combination of these metals; and the metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, IWO, ZnO, or IZO. The carbon-containing material may include, but is not limited to, DLC or graphene.

[0041] FIG. 2 is a cross-sectional view of a semiconductor device 200 according to one embodiment, and FIG. 3 is a top view of the semiconductor device 200 according to one embodiment. FIG. 2 corresponds to a cross-sectional view taken along line AA′ in FIG. 3. In FIG. 2, the same elements as in FIG. 1 are designated by the same reference numerals. Furthermore, the materials and characteristics of these elements are similar to those described above, and therefore detailed descriptions thereof are omitted here. Compared to the semiconductor device 100 shown in FIG. 1, the semiconductor device 200 of this embodiment undergoes one chip bonding process. Therefore, the order of the semiconductor stack layers S is reversed from that shown in FIG. 1, and the first-type semiconductor structure 110 is located between the base 102 and the active structure 112. Furthermore, after the connection process, the second contact layer 118 and the second window layer 116 are located on the path of light emitted by the active structure 112, so the second contact layer 118 and the second window layer 116 can be made of a non-light-absorbing material to make the energy gap of the second contact layer 118 and the second window layer 116 larger than the energy gap of the active structure 112, for example, InP. The chip connection process will be described later.

[0042] 1, the semiconductor device 200 further includes a reflective structure 130, a conductive structure 140, and a connecting layer 124 located between the base 102 and the semiconductor stack layer S, in addition to the base 102, the semiconductor stack layer S, the first electrode 122, and the second electrode 120. In addition, in this embodiment, the first contact layer 104 may be selectively omitted, and the properties such as the lattice constant, energy gap difference, doping concentration, and thickness of the second contact layer 118, the second window layer 116, and the second-type semiconductor structure 114 may refer to the relationships between the first contact layer 104, the first window layer 106, and the first-type semiconductor structure 110 shown in FIG. In this embodiment, as shown in Figures 2 and 3, the second electrode 122 includes an electrode pad 1221 located at approximately the center of the upper surface of the semiconductor stack layer S, and a plurality of extension electrodes 1222 connected to the electrode pad 1221 and extending in a direction away from the electrode pad 1221, and the extension electrodes 1222 are used to uniformly spread current in the semiconductor stack layer S.

[0043] Specifically, the semiconductor device 200 includes a connecting layer 124 located between the reflective structure 130 and the base 102, thereby connecting the reflective structure 130 and the base 102. In some embodiments, the connecting layer 124 may include multiple sub-layers (not shown), and the material of the connecting layer 124 may include a conductive material, such as a metal oxide material, a semiconductor material, a metal material, a metal alloy material, or a carbon-containing material. For example, the metal oxide may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, ICO (indium cerium oxide), IWO, ITiO (indium titanium oxide), IZO, IGO (indium gallium oxide), or GAZO (gallium and aluminum codoped zinc oxide). The semiconductor material may include, but is not limited to, GaP. The metallic material may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, or W. The metallic alloy material is an alloy containing these metallic materials. The carbon-containing material may include, but is not limited to, graphene.

[0044] The reflective structure 130 is disposed between the base 102 and the semiconductor stack layer S and is used to reflect light emitted by the active structure 112 and increase the light extraction efficiency (LEE) of the semiconductor device 200. In some embodiments, the material of the reflective structure 130 may include, but is not limited to, a metal material or a metal alloy material. The metal material may include, but is not limited to, Cu, Al, Sn, Au, Ag, Pt, or W, and the metal alloy material is an alloy containing these metal materials.

[0045] In some embodiments, as shown in FIG. 2, the reflective structure 130 may include a third contact layer 132, a barrier layer 134 disposed on the third contact layer 132, a reflective connecting (glue) layer 136 disposed on the barrier layer 134, and a reflective layer 138 disposed on the reflective connecting layer 136. The third contact layer 132 can form a low-resistance contact with the underlying connecting layer 124. The barrier layer 134 can maintain the reflectivity of the reflective layer 138 by preventing the material of the connecting layer 124 from diffusing into the reflective layer 138 during processing, thereby destroying the structure of the reflective layer 138. The reflective connecting layer 136 is used to connect the reflective layer 138 and the barrier layer 134. The reflective layer 138 can reflect light emitted by the active structure 112. However, the present invention is not limited thereto. For example, the reflective structure 130 may include more structures, and the materials of the third contact layer 132, the barrier layer 134, the reflective connecting layer 136, and the reflective layer 138 may each independently include the same or different metal materials or metal alloy materials. The metal materials may include, but are not limited to, Cu, Al, Sn, Au, Ag, Pb, Ti, Ni, Pt, or W, and the metal alloy materials are alloys containing these metal materials.

[0046] The conductive structure 140 is located between the reflective structure 130 and the first contact layer 104. The conductive structure 140 is transparent to light emitted by the active structure 112 and is used to improve current conduction and diffusion between the first contact layer 104 and the reflective structure 130. In some embodiments, the conductive structure 140 cooperates with the reflective structure 130 to form an omnidirectional reflector (ODR), which can further increase the light extraction efficiency (LEE) of the semiconductor device 200. In some embodiments, the material of the conductive structure 140 may include a metal oxide material, a carbon-containing material, or a combination of these materials. The metal oxide material may include, but is not limited to, ITO, InO, SnO, CTO, ATO, AZO, ZTO, GZO, ZnO, ICO, IWO, ITiO, IZO, IGO, or GAZO. The carbon-containing material may include, but is not limited to, graphene.

[0047] 2, the conductive structure 140 includes a first conductive layer 142 positioned above the reflective structure 130 and a second conductive layer 144 positioned between the semiconductor stack layer S and the first conductive layer 142. In some embodiments, the material of the first conductive layer 142 may be different from the material of the second conductive layer 144. Specifically, the material of the first conductive layer 142 and the material of the second conductive layer 144 differ in at least one element, e.g., the material of the first conductive layer 142 is IZO and the material of the second conductive layer 144 is ITO.

[0048] In some embodiments, as shown in FIG. 2, an insulating layer 146 is disposed between the second conductive layer 144 and the first contact layer 104, and the insulating layer 146 directly contacts the second conductive layer 144. In some embodiments, the material of the insulating layer 146 may be selected to have a transmittance of greater than 90% for light emitted by the active structure 112, and the material of the insulating layer 146 may include an oxide insulating material or a non-oxide insulating material. For example, the oxide insulating material may include SiOx or a similar material, and the non-oxide insulating material may include SiNx, benzocyclobutene (BCB), cycloolefin copolymer (COC), or a fluorocarbon polymer. In other embodiments, the material of the insulating layer 146 may include a halide or a Group IIA and Group VII compound, such as calcium fluoride (CaF2) or magnesium fluoride (MgF2). In one embodiment, the material of the insulating layer 146 has a refractive index less than 1.6.

[0049] In some embodiments, the insulating layer 146 may include a plurality of holes 141 penetrating the insulating layer 146, allowing the conductive structure 140 to be in direct contact with and electrically connected to the semiconductor stack layer S via these holes 141.

[0050] In some embodiments, as shown in FIG. 2, the top surface of the second contact layer 118 and / or the second window layer 116 may be subjected to a roughening process to provide a roughened surface, which may scatter light emitted by the active structure 112 and improve the light extraction efficiency of the semiconductor device 200.

[0051] 4A-4B are cross-sectional views illustrating various stages in fabricating a semiconductor device according to one embodiment, illustrating the chip bonding process. In this embodiment, the base 102 is a non-growth substrate. As shown in FIG. 4A, the semiconductor stack layers S are epitaxially grown on the growth substrate 101. A sacrificial layer 103 may be optionally disposed between the semiconductor stack layers S and the growth substrate 101. In subsequent processing, as shown in FIG. 4B, the sacrificial layer 103 can be removed, allowing the first contact layer 104, first window layer 106, buffer layer 108, first-type semiconductor structure 110, active structure 112, second-type semiconductor structure 114, second window layer 116, and second contact layer 118 to separate from the growth substrate 101. In some embodiments, the sacrificial layer 103 may be formed on the growth substrate 101 before the second contact layer 118 is formed. In some embodiments, the semiconductor device does not include the sacrificial layer 103, and the second contact layer 118 may be formed directly on the growth substrate 101. In some other embodiments, a buffer structure (not shown) may be further provided between the second contact layer 118 and the growth substrate 101 to reduce lattice defects in the second contact layer 118 and the layers thereover, thereby improving the epitaxial quality of the semiconductor stack layer S. In other embodiments, the semiconductor device does not have the sacrificial layer 103, but includes an etch stop layer (not shown) located between the growth substrate 101 and the second contact layer 118, which subsequently functions to protect the semiconductor stack layer S when etching away the growth substrate 101, thereby preventing the semiconductor stack layer S from being damaged during the etching process; for example, the material of the etch stop layer is InGaAs or InGaP, or consists essentially of InGaAs or InGaP.

[0052] Additionally, in some embodiments, the sacrificial layer 103 comprises a material, such as aluminum arsenide (AlAs), that has a different etch selectivity than the material of the second contact layer 118. In some embodiments, the removal of the sacrificial layer 103 may use an etch etch process, a dry etch process, a laser lift-off (LLO) process, or a combination thereof.

[0053] 4B is a cross-sectional view of a semiconductor device at a manufacturing stage in one embodiment, in which a substrate transfer technique is used to bond the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 to a non-growth substrate (base 102) with an adhesive layer (not shown) between the first contact layer 104 and the non-growth substrate. The sacrificial layer 103 is then removed to detach the second contact layer 118 from the growth substrate 101, but the invention is not limited to this. By flipping the device upside down, the arrangement of the first contact layer 104, the first window layer 106, the buffer layer 108, the first-type semiconductor structure 110, the active structure 112, the second-type semiconductor structure 114, the second window layer 116, and the second contact layer 118 on the non-growth substrate is reversed from their arrangement on the growth substrate 101 in FIG. 4A. Specifically, before flipping, the active structure 112 is located between the first-type semiconductor structure 110 and the growth substrate 101, as shown in FIG. 4A, and after flipping, the first-type semiconductor structure 110 is located between the non-growth substrate and the active structure 112, as shown in FIG. 4B.

[0054] Growth substrate 101 may also include semiconductor materials such as, but not limited to, silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), zinc selenide (ZnSe), and indium phosphide (InP). In some embodiments, the material of growth substrate 101 may include, but is not limited to, sapphire. The material of the non-growth substrate and the material of growth substrate 101 may be the same or different, and in many embodiments, the non-growth substrate has different properties than growth substrate 101, such as higher thermal conductivity, electrical conductivity, transparency, or mechanical strength compared to growth substrate 101.

[0055] FIG. 5 is a graph showing the relationship between element concentration and depth in a partial region of a semiconductor device and between dopant doping concentration and depth in one embodiment. Specifically, FIG. 5 is a mass analysis diagram of a partial structure of the semiconductor device 100 of FIG. 1, obtained by secondary ion mass spectrometry (SIMS). Note that the present invention is not limited to this, and other techniques may be used to obtain the relationship diagram between element concentration and depth in a partial region of the semiconductor device 100. Here, the aforementioned depth refers to the depth in the direction from one side away from the base 102 to one side closer to the base 102; i.e., the closer to the base 102, the deeper the depth.

[0056] As shown in FIG. 5, according to the depth and order of each layer in the semiconductor device 100, the mass spectrometry diagram can be roughly divided into seven regions AG, where region A corresponds substantially to the position of the first contact layer 104, region B corresponds substantially to the position of the first window layer 106, region C corresponds substantially to the position of the buffer layer 108, region D corresponds substantially to the position of the first-type semiconductor structure 110, region E corresponds substantially to the position of the active structure 112, region F corresponds substantially to the position of the second-type semiconductor structure 114, and region G corresponds substantially to the position of the second window layer 116.

[0057] 5, the mass spectrum includes a first dopant 302, a second dopant 304, a first element 306, a second element 308, and a third element 310. The first contact layer 104, the first window layer 106, the buffer layer 108, and the first-type semiconductor structure 110 have a first dopant 302, which can make these layers P-type conductive, and the first dopant is Zn. The second-type semiconductor structure 114 and the second window layer 116 have a second dopant 304, which can make these layers N-type conductive, and the second dopant is Si. The first, second, and third elements are host elements of each layer and may be Group 3 or Group 5 elements. In Figure 5, the first element is indium, the second element is aluminum, and the third element is gallium, all of which are Group 3 elements. The atomic weight of the first element is greater than that of the third element, and the atomic weight of the second element is less than that of the third element. The concentrations of the first dopant 302 and the second dopant 304 are shown on the left vertical axis, and the contents of the first element 306, the second element 308, and the third element 310 are shown on the right vertical axis. The element contents shown on the right vertical axis indicate the relative relationship of the contents of single elements in each layer.

[0058] In region A, the first dopant 302 (Zn) has the highest concentration, which is 1×10 18 / cm 3and the concentration of the first dopant 302 decreases with increasing depth. Specifically, the Zn dopant in region A has a first doping concentration, the Zn dopant in region C has a second doping concentration, and the second doping concentration is less than the first doping concentration. The Zn dopant in region E has a third doping concentration, and the second doping concentration is between the first doping concentration and the third doping concentration. The Zn dopant in region B has a fourth doping concentration, and the fourth doping concentration is between the first doping concentration and the second doping concentration. In some embodiments, the ratio of the first doping concentration to the second doping concentration (first doping concentration / second doping concentration) is 10 to 100.

[0059] As shown in FIG. 5, the second dopant 304 (Si) in the G region has the highest doping concentration, which is about 1×10 18 / cm 3 Specifically, the Si dopant in the G region has a fifth doping concentration, and the Si dopant in the F region has a sixth doping concentration, the fifth doping concentration being greater than the sixth doping concentration. In some embodiments, the ratio of the fifth doping concentration to the sixth doping concentration is between about 2 and about 100.

[0060] As shown in Figure 5, the first element 306 (In) in region G has the largest content, and the content of the first element 306 gradually increases with increasing depth. Specifically, regions C, D, E, and F contain substantially the same content of In 306, and the ratios of the In content in regions C, D, E, and F to the In content in region A are all greater than 1000, so region A can be considered to contain no In. Here, "not containing" refers to "unintentional addition."

[0061] As shown in Figure 5, the content of the second element 308 (Al) in regions D and F is greater than the content of the second element 308 in region E. Regions D and F contain substantially the same content of Al 308, and the ratios of the Al content in regions D and F to the Al content in region A are all greater than 1000, so region A can be considered to contain no Al. Similarly, the ratios of the Al content in regions D and F to the Al content in region G are all greater than 1000, so region G can also be considered to contain no Al.

[0062] The third element 310 (Ga) has the highest content in regions A and B, and the Ga content in region E is smaller than the Ga content in regions A and B. Compared to the Ga content in regions A and B, the Ga contents in regions D, F, and G are extremely small. Specifically, the ratios of the Ga content in region A to the Ga content in regions D, F, and G are all greater than 1000, so regions D, F, and G can be considered to contain no Ga.

[0063] FIG. 6 is a cross-sectional view of a semiconductor device 300 according to another embodiment. For convenience, the same reference numerals are used to denote the same or similar structures. The methods and materials for forming these structures are the same as those described above, and therefore, detailed descriptions thereof are omitted here. In this embodiment, compared with the semiconductor device 100, the semiconductor device 300 does not include the second-type semiconductor structure 114, the second contact layer 118, and the buffer layer 108. The semiconductor device 300 is also a double heterostructure (DH), in which the material of the active structure 112 is a quaternary compound semiconductor, such as InGaAsP, and the material of the first contact layer 104 is a binary compound semiconductor, such as GaAs. In one embodiment, the material of the first window layer 106 is the same as the material of the second window layer 116 and may be different from the material of the first-type semiconductor structure 110. For example, the materials of the first window layer 106 and the second window layer 116 are both InP or consist essentially of InP. In another embodiment, the first contact layer 104 and the first window layer 106 include the same material, e.g., GaAs, and are different from the material of the second window layer 116, e.g., InP. Also, the doping concentration of the dopant in the second window layer 116 of the semiconductor device 300 is 8×10 17 / cm 3 It can be smaller than, for example, 1×10 16 / cm 3 ~5×10 17 / cm 3 is in the range.

[0064] FIG. 7 is a cross-sectional view of a semiconductor device 400 according to another embodiment. For convenience, the same reference numerals are used to denote the same or similar structures. The methods and materials for forming these structures are similar to those described above, and therefore will not be described in detail here. In this embodiment, the first electrode 122 and the second electrode 120 are located on the same side of the base 102, forming a horizontal semiconductor device 400. In another embodiment, a connecting layer 126 may be optionally provided between the semiconductor stack layer S and the base 102. The material of the connecting layer 126 may include an insulating material, such as, but not limited to, SiO2, Al2O3, AlN, and BCB. In these embodiments, the base 102 may be made of a material that is transparent to the light emitted by the active structure 112, allowing the semiconductor device to emit light from the base 102 side. Furthermore, the semiconductor device may be connected to a circuit board in a flip-chip manner, with the first electrode 122 and the second electrode 120 facing downward.

[0065] FIG. 8 is a diagram of a semiconductor device package structure according to one embodiment. As shown in FIG. 8, the package structure 500 includes a semiconductor device 100, a package plate 51, a mounting body 53, connecting lines 55, a contact structure 56, and a package material 58. The package plate 51 may include a ceramic or glass material. The package plate 51 includes a plurality of through holes 52. The through holes 52 can be filled with a conductive material, such as metal, to facilitate electrical conduction and / or heat dissipation. The mounting body 53 is located on one surface of the package plate 51b and includes a conductive material, such as metal. The contact structure 56 is located on the other surface of the package plate 51b. In this embodiment, the contact structure 56 includes contact pads 56a and 56b, which can be electrically connected to the mounting body 53 via the through holes 52. In one embodiment, the contact structure 56 may further include a thermal pad (not shown), for example, located between the contact pads 56a and 56b. The semiconductor element 100 is located on the mounting body 53 and may be a semiconductor element described in any embodiment of the present invention. In this embodiment, the mounting body 53 includes a first portion 53a and a second portion 53b, and the semiconductor element 100 is electrically connected to the second portion 53b of the mounting body 53 by a connecting wire 55. In another embodiment, the semiconductor element 100 is not located on the mounting body 53 but is located directly on the package plate 51, and an electrical connection can be formed with the contact structure 56.

[0066] The material of the connecting wires 55 may include a metal, such as gold, silver, copper, aluminum, or an alloy containing at least one of these elements. The packaging material 58 covers the semiconductor element 100 and protects it. Specifically, the packaging material 58 may include a resin material, such as epoxy resin or silicone resin. The packaging material 58 may further include a plurality of wavelength-converting particles (not shown) that convert a first light emitted by the semiconductor element 50 into a second light. The wavelength of the second light is greater than the wavelength of the first light. In other embodiments, the semiconductor element 100 in the packaging structure 500 may be the semiconductor element 200 or 300. Alternatively, in some embodiments, the packaging structure 500 may include a plurality of semiconductor elements 100, 200, and / or 300, which may be connected in series, parallel, or series-parallel.

[0067] In some embodiments of the present invention, a semiconductor device is provided, in which one or more contact layers and / or window layers in the semiconductor device are made of a material whose absorption wavelength is different from the emission wavelength of the active structure, thereby preventing light emitted by the active structure from being absorbed by the contact layers and / or window layers, improving luminous efficiency, and eliminating the need to remove the contact layers and / or window layers, which can affect brightness. Furthermore, the luminous efficiency can be further improved by performing a roughening process on the contact layers.

[0068] In addition, in some embodiments of the present invention, a buffer layer may be provided between the contact layer and the semiconductor structure in the semiconductor device to mitigate the difference in valence band energy level and / or conduction band energy level between the contact layer and the first-type semiconductor structure or the second-type semiconductor structure, thereby avoiding problems such as a decrease in saturation current or early failure of the semiconductor device and improving the reliability of the semiconductor device.

[0069] The semiconductor device according to the present invention can be applied to products in the fields of lighting, display, communication, detection, power supply systems, etc., such as lighting fixtures, monitors, mobile phones, tablet computers, automotive instrument panels, televisions, detectors, computers, wearable devices (e.g., watches, bracelets, necklaces, etc.), traffic lights, outdoor displays, etc.

[0070] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and any modification to the present invention falls within the technical scope of the present invention as long as it does not depart from the spirit of the present invention. [Explanation of symbols]

[0071] 100, 200, 300, 400: Semiconductor elements 101: Growth substrate 102: Bass 103: Sacrificial layer 104:First contact layer 106: First window layer 108:Buffer layer 110: First-type semiconductor structure 112: Active Structure 114: Second-type semiconductor structure 116: Second window layer 118:Second contact layer 122:First electrode 120:Second electrode 124: Connection layer 130: Reflective structure 132:Third contact layer 134: Barrier layer 136: Reflective connection layer 138: Reflective layer 140: Conductive structure 141: Hole 142:First conductive layer 144: Second conductive layer 146: Insulating layer 302: First Dopant 304: Second dopant 306: First element 308:Second element 310:Third element 500:Package structure 51: Package plate 52:Through hole 53: Mounting body 53a:First part 53b:Second part 55: Connection line 56: Contact structure 56a, 56b: contact pads 58: Packaging materials S: semiconductor stack layer S1: First side S2: Second side

Claims

1. A semiconductor device, A semiconductor stack of layers, a first-type semiconductor structure including a first side and a second side opposite the first side; an active structure located on the first side, the active structure including a quaternary compound semiconductor and emitting radiation, the peak wavelength of the radiation being between 1000 nm and 2000 nm; and a first contact layer located on the second side and comprising a Group 35 compound semiconductor material; a semiconductor stack layer comprising: a first window layer positioned between the first contact layer and the first-type semiconductor structure; a second window layer, wherein the active structure is located between the first-type semiconductor structure and the second window layer; a reflective structure located below the semiconductor stack layers; a conductive structure located between the reflective structure and the semiconductor stack layers; and an insulating layer positioned between the conductive structure and the semiconductor stack layers; Including, The second window layer is in direct contact with the active structure of the semiconductor device.

2. 10. The semiconductor device of claim 1, further comprising a buffer layer; The buffer layer is located between the first contact layer and the first-type semiconductor structure.

3. 10. The semiconductor device of claim 1, The semiconductor device, wherein the quaternary compound semiconductor is AlInGaAs or InGaAsP.

4. 10. The semiconductor device of claim 1, A semiconductor device, wherein the energy gap of the first contact layer is larger than the energy gaps of the active structure and the first-type semiconductor structure.

5. 10. The semiconductor device of claim 1, A semiconductor device, wherein the first-type semiconductor structure comprises a ternary or binary compound that does not contain nitrogen (N).

6. 10. The semiconductor device of claim 1, The semiconductor device, wherein the first contact layer and the first window layer comprise different materials.

7. 10. The semiconductor device of claim 1, A semiconductor device, wherein the first contact layer comprises GaAs, InGaAs, or InGaAsP.

8. 10. The semiconductor device of claim 1, a material of the second window layer and a material of the first window layer comprising InP;

9. 10. The semiconductor device of claim 1, further comprising a first electrode and a second electrode; The semiconductor device, wherein the first electrode and the second electrode are located on opposite sides of the semiconductor stack layer.

10. 10. The semiconductor device of claim 1, The reflective structure includes a barrier layer, a reflective adhesive layer overlying the barrier layer, and a reflective layer overlying the reflective adhesive layer.

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