Semiconductor storage device
JP2025134338APending Publication Date: 2025-09-17KIOXIA CORP
Patent Information
- Application Number
- JP2024032187
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-04
- Publication Date
- 2025-09-17
AI Technical Summary
Technical Problem
The yield of semiconductor memory devices, particularly NAND flash memory, is a challenge due to the complexity of manufacturing three-dimensional memory structures.
Method used
A novel configuration of memory pillars and conductors within the semiconductor memory device, including a first conductor positioned away from the wiring layer, with memory pillars extending in multiple directions and intersecting various regions, enhances the manufacturing process.
Benefits of technology
This configuration improves the yield of semiconductor memory devices by optimizing the manufacturing process and enhancing the integration and capacity of NAND flash memory.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure 2025134338000001_ABST
Abstract
To improve the yield of a semiconductor storage device.SOLUTION: A semiconductor storage device according to an embodiment comprises: a substrate 20 including first and second regions arranged in an X direction to each other on an XY plane, the second region including a third region and a fourth region STP arranged in a Y direction; a plurality of wiring layers 23 arranged in a Z direction crossing the XY plane and provided spaced apart from each other on the substrate and including a first wiring layer, each wiring layer including a bridge portion extending in the X direction in the third region BRG and a terrace portion arranged so as not to overlap an upper wiring layer in the fourth region STP; a contact CC extending in the Z direction; a first conductor LF including a first portion 23-1 in contact with the terrace portion of the first wiring layer in the fourth region, a second portion 23-2 in contact with a lower end of the contact in the third region, and a third portion 23-3 in contact with the first and second portions and provided spaced apart from the plurality of wiring layers excluding the first wiring layer; and a memory pillar extending in the Z direction in the first region, portions crossing each of the plurality of wiring layers functioning as a memory cell.SELECTED DRAWING: Figure 8
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Semiconductor device and method for manufacturing the same
US10090320B2