Semiconductor device

Abstract

To reduce an on-resistance in a trench MOSFET having a vertical channel fin structure while securing a short circuit resistance.SOLUTION: A trench MOSFET of a vertical channel fin structure having a plurality of trenches 2 arranged in a second direction and having a longitudinal direction in a first direction includes: a JFET region 8 of a first conductivity type sandwiched between body regions 9 of a second conductivity type; and a first current spreading region 23A of the first conductivity type sandwiched between first pocket regions 22A of the second conductivity type spaced apart from the body regions 9 via a first intermediate region 21A. A length (WJ) in the first direction of the JFET region 8<a length (Wp1) in the first direction of the first current spreading region 23A; an impurity concentration of a drift region 10<an impurity concentration of the first current spreading region 23A≤an impurity concentration of the first intermediate region 21A<an impurity concentration of the JFET region 8; and the dimensions of the body region 9 and the JFET region 8 in a depth direction from a lower portion of the trench 2 are both greater than 0.5 μm.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] As a type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] Fig. 7 is a perspective view showing a conventional trench MOSFET with a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] 7 has a plurality of trenches 2 arranged in a plane, with the longitudinal direction in a first direction and the lateral direction in a second direction. The trenches 2 shown by dotted lines in the cross section at the front of FIG. 7 are hypothetical positions corresponding to the trenches 2 in order to explain the positional relationship between the other components and the trenches 2.

[0005] The first conductivity type first source region 3 includes a region having a fin structure at least a portion of which is separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the first source region 3 and in contact with the first source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and second conductivity type body regions 9 are formed on both sides of the JFET region 8. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 7 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) in the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, a patent document related to such technology is, for example, Patent Document 1, and although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, Figure 3, and Figures 14 to 18 of Patent Document 1 describe a configuration similar to Figure 7 described above. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-207289 Summary of the Invention [Problem to be solved by the invention]

[0009] According to the structure of the conventional semiconductor device 1 shown in Fig. 7, the trench pitch can be reduced to increase the channel density, thereby increasing the number of channels, thereby reducing the on-resistance of the entire semiconductor chip. However, the conventional semiconductor device 1 shown in Fig. 7 has a problem in that, although the on-resistance is low due to the high channel density, the short-circuit resistance is correspondingly low.

[0010] Furthermore, in the conventional semiconductor device 1 shown in FIG. 7, the thickness (dimension in the depth direction) of the JFET region 8 is thin, which poses a problem of low short-circuit resistance.

[0011] Furthermore, in the conventional semiconductor device 1 shown in FIG. 7, when the impurity concentration of the JFET region 8 is the same as the impurity concentration of the drift region 10, the impurity concentration of the JFET region 8 is as low as the impurity concentration of the drift region 10, which increases the resistance of the JFET region 8 and makes it impossible to sufficiently reduce the on-resistance.

[0012] The problem to be solved by the present invention is to provide a semiconductor device that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems, the semiconductor device of the present invention includes a first source region of a first conductivity type including a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above and arranged in the second direction, at least a portion of which has a fin structure separated by the plurality of trenches, a channel region of a second conductivity type in contact with a lower surface of the first source region and having a fin structure separated by the plurality of trenches, a gate insulating film disposed inside the trench, a gate electrode including a region at least a portion of which is disposed inside the trench, a JFET region of the first conductivity type disposed below the channel region, body regions of a second conductivity type disposed on both sides of the JFET region, and a gate insulating film disposed between the body region and the JF a first intermediate region of a first conductivity type disposed in contact with a bottom surface of the ET region; first pocket regions of a second conductivity type disposed apart from the body region at a position overlapping the body region with the first intermediate region interposed therebetween; a first current spreading region of the first conductivity type disposed between adjacent first pocket regions; a drift region of the first conductivity type disposed below the first pocket region and the first current spreading region; and a drain region of the first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region, wherein ends of bottom surfaces of the plurality of trenches in the first direction are disposed within the body region, the channel region is connected to the body region, and a channel current flows in the channel region in a vertical direction; [Effects of the Invention]

[0014] According to the present invention, in a trench MOSFET with a vertical channel fin structure, it is possible to reduce the on-resistance while ensuring short-circuit resistance. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a top perspective view of a semiconductor device according to a first embodiment. [Figure 2] X1-X1' cross-sectional view of Figure 1. [Figure 3] X2-X2' cross-sectional view of Figure 1. [Figure 4] Cross-sectional view of Y1-Y1' in Figure 1. [Figure 5] FIG. 10 is a cross-sectional view of the semiconductor device of the second embodiment taken along the line X1-X1′. [Figure 6] FIG. 11 is a cross-sectional view of the semiconductor device according to the third embodiment taken along the line X1-X1′. [Figure 7] FIG. 1 is a perspective view showing a conventional trench MOSFET with a vertical channel fin structure. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted. [Example]

[0017] FIG. 1 is a top perspective view of a semiconductor device of Example 1. FIG. 2 is an X1-X1' cross-sectional view of FIG. 1. FIG. 3 is an X2-X2' cross-sectional view of FIG. 1. FIG. 4 is a Y1-Y1' cross-sectional view of FIG. 1. Note that FIG. 1 does not illustrate the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and barrier metal 17. Also, in FIG. 1, the position where a source contact plug 16 is to be disposed is indicated by a dotted line.

[0018] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a first source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of a first conductivity type, a body region 9 of a second conductivity type, a drift region 10 of a first conductivity type, a drain region 11 of a first conductivity type, a first intermediate region 21A of a first conductivity type, a first pocket region 22A of a second conductivity type, and a first current spreading region 23A of a first conductivity type.

[0019] In this embodiment, an example will be described in which the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type. In addition, although the impurity concentration is shown as an example in this embodiment, the present invention is not limited to this, and the impurity concentration may be changed within a range in which the intended operation of the embodiment can be realized. Note that the high concentration in this embodiment means a high concentration (for example, 8×10 18 cm -3 That's it, 1×10 21 cm -3 (See below).

[0020] The plurality of trenches 2 have their longitudinal direction in a first direction (the X1-X1' direction in FIG. 1) when viewed from above, and their lateral direction in a second direction (the Y1-Y1' direction in FIG. 1), and are arranged in multiple rows in the second direction. Furthermore, a trench group made up of multiple trenches 2 arranged in the second direction is also arranged in multiple rows in the first direction. Note that the trench 2 indicated by the dotted line in the cross-sectional view of FIG. 3 is a virtual representation of a position corresponding to the trench 2 in order to explain the positional relationship between other components and the trench 2.

[0021] The first source region 3 of the first conductivity type includes a region having a fin structure at least a part of which is separated by a plurality of trenches 2. The impurity concentration of the first source region 3 is, for example, a high concentration of n+.

[0022] A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the first source region 3 in contact with the first source region 3. The impurity concentration of the channel region 5 is, for example, a medium concentration of p.

[0023] A JFET region 8 of a first conductivity type is formed below the channel region 5, and body regions 9 of a second conductivity type are formed on both sides of the JFET region 8. The dimensions (tJ in FIG. 2) of the body region 9 and the JFET region 8 in the depth direction from the bottom of the trench 2 are both set to be greater than 0.5 μm. The impurity concentration of the JFET region 8 is set to be higher than the impurity concentration of the drift region 10. The impurity concentration of the JFET region 8 is, for example, a medium concentration of n. The impurity concentration of the body region 9 is, for example, a medium concentration of p.

[0024] The first intermediate region 21A of the first conductivity type is disposed in contact with the lower surfaces of the body region 9 and the JFET region 8. The impurity concentration of the first intermediate region 21A is, for example, a low concentration of n-.

[0025] The first pocket region 22A of the second conductivity type is disposed at a position overlapping the body region 9 with the first intermediate region 21A interposed therebetween, separated from the body region 9. The reason for separating the first pocket region 22A from the body region 9 is that if the impurity implantation for forming the first pocket region 22A and the impurity implantation for forming the body region 9 are performed in separate steps, and the first pocket region 22A and the body region 9 are in contact with each other, the impurity implantations may overlap at the boundary, making it more likely that implantation defects will occur at the boundary, and this implantation defect may make it more likely that an off-leak current (a leakage current that occurs when a reverse bias is applied during off-state) will occur. The impurity concentration of the first pocket region 22A is, for example, a medium concentration of p.

[0026] The first current spreading region 23A of the first conductivity type is disposed between adjacent first pocket regions 22A. The position where the first current spreading region 23A is disposed also overlaps with the JFET region 8 via the first intermediate region 21A. The first current spreading region 23A is a region where the current from the JFET region 8 spreads. The width (length in the first direction) is set so that the length in the first direction of the JFET region 8 (WJ in FIG. 2) is smaller than the length in the first direction of the first current spreading region 23A (Wp1 in FIG. 2). The impurity concentration of the first current spreading region 23A is, for example, a low concentration of n-.

[0027] The operations of the JFET region 8, body region 9, first intermediate region 21A, first pocket region 22A, and first current spreading region 23A in this embodiment will be described later.

[0028] As shown in FIG. 3, the channel region 5 is connected to the body region 9. Therefore, the width (length in the first direction) of the channel region 5 is the width obtained by subtracting the overlapping width between the trench 2 and the body region 9 from the width (length in the first direction) of the trench 2. Therefore, the width of the channel region 5 is substantially the same as the width (WJ in FIG. 2) of the JFET region 8.

[0029] Below the first pocket region 22A and the first current spreading region 23A, a drift region 10 of the first conductivity type is arranged. Also, below the drift region 10, a drain region 11 of the first conductivity type with a higher impurity concentration than the drift region 10 is arranged. The impurity concentration of the drift region 10 is, for example, a low concentration of n-. The impurity concentration of the drain region 11 is, for example, a high concentration of n+.

[0030] Note that the impurity concentrations are set such that the impurity concentration of the drift region 10 < the impurity concentration of the first current spreading region 23A ≤ the impurity concentration of the first intermediate region 21A < the impurity concentration of the JFET region 8.

[0031] As shown in FIGS. 2 and 4, a gate insulating film 6 is arranged inside the trench 2. Also, at least a part of the gate electrode 7 is arranged inside the trench 2. Note that the gate electrodes 7 arranged inside the trench 2 are connected to each other outside the trench 2. The gate electrode 7 can be formed of, for example, polysilicon.

[0032] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. In other words, the device is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch to increase the channel density, thereby reducing the on-resistance of the entire semiconductor chip.

[0033] Furthermore, in the semiconductor device 1 of this embodiment, as shown in FIG. 2 , the width (length in the first direction) (WTG) of the gate electrode 7 disposed inside the trench 2 is longer than the width (length in the first direction) (WJ) of the JFET region 8. The width (WTG) of the gate electrode 7 is calculated by subtracting the thickness of the gate insulating film (two portions, one in the first direction) from the width (length in the first direction) (WTR) of the trench 2. Since WTR > WTG > WJ, the ends of the bottom surfaces of the multiple trenches 2 in the first direction and the ends of the bottom surfaces of the gate electrodes 7 in the trench 2 in the first direction are located within the body region 9. This results in a structure in which the three-dimensional corners of the trench 2 and the gate electrode 7 are located within the body region 9. Therefore, even when a high voltage is applied, the electric field concentration is alleviated at the three-dimensional corners of the trench 2, where the electric field is likely to concentrate and the gate insulating film 6 is likely to be destroyed, and the destruction of the gate insulating film 6 can be suppressed. The higher the breakdown voltage and the higher the applied voltage, the more likely the electric field is to concentrate at the three-dimensional corners of the trench 2, making it more likely that the gate insulating film 6 will be destroyed. Therefore, the higher the breakdown voltage of the semiconductor device 1, the more desirable it is to have such a configuration.

[0034] Next, the operation of the JFET region 8, the body region 9, the first intermediate region 21A, the first pocket region 22A, and the first current spreading region 23A of this embodiment will be described.

[0035] In the semiconductor device 1 of this embodiment, the impurity concentration of the JFET region 8 is set higher than the impurity concentration of the drift region 10, and the thickness (dimension in the depth direction) (tJ) of the body region 9 and the JFET region 8 from the bottom of the trench 2 is set to be greater than 0.5 μm, as shown in Fig. 2. It is desirable to set the thickness (tJ) of the body region 9 and the JFET region 8 from the bottom of the trench 2 to be approximately the same thickness.

[0036] When a high voltage is applied between the drain and source, the depletion layer spreads in the JFET region 8, ensuring a breakdown voltage. Here, when the thickness (tJ) of the JFET region 8 is thin, as in the conventional structure shown in Figure 7, the depletion layer spreads mainly in the depth direction. The depletion layer spreads more easily when the impurity concentration is low. Therefore, the concentration in the JFET region 8 cannot be increased, and it is set to the same 1 × 10 as the concentration in the general drift region 10. 16 cm -3 is set to a certain extent.

[0037] In contrast, in this embodiment, by increasing the thickness (tJ) of the JFET region 8, when a high voltage is applied between the drain and source, the depletion layer begins to expand laterally from the body region 9 on both sides of the JFET region 8. When a higher voltage is applied, the depletion layer closes and pinches off. This allows the depletion layer to expand only half the width (WJ) of the JFET region 8, resulting in a depletion layer of the thickness (tJ) of the JFET region 8. As a result, the expansion of the depletion layer required for complete depletion is small, allowing the impurity concentration of the JFET region 8 to be increased while maintaining a sufficient breakdown voltage. Furthermore, since the impurity concentration of the JFET region 8 can be set high, the resistance of the JFET region 8 and the on-resistance can be reduced. The impurity concentration of the JFET region 8 can be increased as the thickness (tJ) of the JFET region 8 increases and the width (WJ) of the JFET region 8 decreases. Furthermore, although the temperature characteristic of the resistance of the JFET region 8 is positive, if the impurity concentration is high, the rate of increase in the resistance of the JFET region 8 is low even in a high-temperature environment, so the on-resistance of the entire semiconductor chip at high temperatures can be maintained at a low level.

[0038] Also, a depletion layer spreads to the first intermediate region 21A below the body region 9 and reaches the first pocket region 22A. Then, the depletion layer begins to spread horizontally from the first pocket region 22A, and the depletion layer also spreads horizontally to the first current spreading region 23A.

[0039] Therefore, the first current spreading region 23A in this embodiment also operates in the same manner as the JFET region 8. For the first current spreading region 23A, since the impurity concentration can be set higher than that of the drift region 10, the resistance of the first current spreading region 23A can be reduced, and the on-resistance can be reduced. As a result, the on-resistance can be further reduced compared to the case where there is no first current spreading region 23A.

[0040] However, since it is also required that the depletion layer spreads easily in the first intermediate region 21A and the first current spreading region 23A, the impurity concentration cannot be set as high as that of the JFET region 8. Therefore, the impurity concentration is set such that the impurity concentration of the drift region 10 < the impurity concentration of the first current spreading region 23A ≤ the impurity concentration of the first intermediate region 21A < the impurity concentration of the JFET region 8. Since the impurity concentrations of the first intermediate region 21A and the first current spreading region 23A cannot be set as high as that of the JFET region 8, the effect of reducing the on-resistance is smaller than that of the JFET region 8, but the breakdown voltage is easily ensured due to the low impurity concentration. Also, in order for the depletion layer to reach the first pocket region 22A, it is desirable that the thickness (tsp1) of the first intermediate region 21A is thin. Therefore, it is desirable that the thickness (tsp1) of the first intermediate region 21A is 0.1 μm or more and 0.5 μm or less, and more preferably 0.1 μm or more and 0.3 μm or less.

[0041] The thicknesses (tJ) of the body region 9 and the JFET region 8 from the lower part of the trench 2 are both preferably 0.8 μm or more and 1.3 μm or less. The larger the thickness (tJ) of the JFET region 8, the greater the above-described effect. The thickness (tp1) of the first current spreading region 23A (the dimension in the depth direction of the first current spreading region 23A from the lower part of the first intermediate region 21A) is preferably 0.5 μm or more and 1.0 μm or less.

[0042] The width (WTR) of the trench 2 is preferably 0.8 μm or more and 1.8 μm or less.

[0043] The width (WJ) of the JFET region 8 is preferably 0.3 μm or more and 1.4 μm or less. The narrower the width (WJ) of the JFET region 8, the greater the above-mentioned effects. The width (Wp1) of the first current spreading region 23A is preferably 1.0 μm or more and 3.5 μm or less.

[0044] The impurity concentration of the JFET region 8 is 8×10 16 cm -3 That's it, 1×10 18 cm -3 The impurity concentration of the first intermediate region 21A is preferably 1×10 16 cm -3 That's it, 1×10 17 cm -3 The impurity concentration of the first current spreading region 23A is preferably 1×10 16 cm -3 That's it, 1×10 17 cm -3 The impurity concentration of the drift region 10 is preferably 1×10 or less, which is the same as the impurity concentration of a general drift region 10. 15 cm -3 That's it, 1×10 16 cm -3 It is desirable that the following:

[0045] As described above, according to this embodiment, it is possible to realize a semiconductor device 1 that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.

[0046] In addition, the semiconductor device 1 of this embodiment also has a source electrode 12, a drain electrode 13, an interlayer insulating film 14, a second source region 4 of the second conductivity type, a source contact plug 16, a barrier metal 17, and a buffer region 15.

[0047] The source electrode 12 is disposed on the front surface side and is an electrode made of a metal such as aluminum.

[0048] The drain electrode 13 is disposed on the back surface side and is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold).

[0049] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the first source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0050] The second source region 4 of the second conductivity type is provided in contact with the upper surface of at least a portion of the body region 9. The impurity concentration of the second source region 4 is set higher than that of the body region 9. The impurity concentration of the second source region 4 is, for example, a high concentration of p+. By providing the second source region 4, the body region 9 of the second conductivity type and the source electrode 12 can be connected with lower resistance than connecting them via the first source region 3 of the first conductivity type or connecting them directly to the body region 9.

[0051] In this embodiment, the gate electrodes 7 are connected to each other above the trenches 2, and therefore a portion of the gate electrode 7 protrudes from the semiconductor layer surface (X1-X1' plane), forming a step. Therefore, in this embodiment, the gate electrodes 7, the first source region 3, and the second source region 4 are covered with an interlayer insulating film 14, and a source contact plug 16 is provided that penetrates the interlayer insulating film 14 and is connected to the first source region 3 and the second source region 4.

[0052] The source contact plug 16 is a contact plug that electrically connects the source electrode 12 and the first source region 3 or the second source region 4. The source contact plug 16 can be made of a conductive metal such as tungsten. The first source region 3 and the source contact plug 16, or the second source region 4 and the source contact plug 16, are preferably connected via a barrier metal 17. The barrier metal 17 can be, for example, a TiN / Ti stacked film. In addition to the barrier metal 17, a low-resistance material such as NiSi may also be used for the connection. The provision of the source contact plug 16 allows the source electrode 12 to be connected to the first source region 3 or the second source region 4 via the source contact plug 16, thereby stabilizing the connection between the source electrode 12 and the first source region 3 or the second source region 4. Furthermore, the surface of the source electrode 12 can be planarized, thereby stabilizing the connection of the source electrode 12 to an external device.

[0053] The first source region 3, the second source region 4, and the source contact plug 16 may be arranged such that the source contact plug 16 has its longitudinal direction in the second direction, and the first source region 3 and the second source region 4 are arranged alternately at least in the region overlapping with the source contact plug 16, as shown in Fig. 1 . The second source region 4 has its longitudinal direction in the first direction and its lateral direction in the second direction, and a plurality of second source regions 4 are arranged in the second direction. The arrangement of the first source region 3, the second source region 4, and the source contact plug 16 is not limited to this, and other arrangements may be used.

[0054] The drain region 11 has a high impurity concentration and contains crystal defects. For this reason, it is desirable to provide a buffer region 15 of the same conductivity type (first conductivity type) between the drift region 10 and the drain region 11 so that the depletion layer does not reach the drain region 11. Furthermore, in a pn structure using SiC, for example, degradation of breakdown voltage and characteristics may occur as a result of current flow or the like. To prevent this, it is necessary to eliminate carriers (promote recombination) within the buffer region 15, and therefore setting the impurity concentration of the buffer region 15 is important. The impurity concentration of the buffer region 15 is desirably higher than that of the drift region 10 and lower than that of the drain region 11; for example, a medium concentration of n is 1×10 17 cm -3 That's it, 1×10 19 cm -3 The following is desirable: The thickness of the buffer region 15 may be determined arbitrarily depending on the purpose, such as the breakdown voltage of the semiconductor device 1 and the degree of degradation suppression. Alternatively, the buffer region 15 may be configured with multiple buffer layers, and the impurity concentration of the multiple buffer layers may increase toward the drain region 11, and the thickness may decrease toward the drain region.

[0055] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may also be formed using a Si substrate, etc. Furthermore, for portions of the specification where no special description is given of the manufacturing method, the semiconductor device can be manufactured using a general semiconductor device manufacturing method, such as forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth, and so detailed description will be omitted. The same applies to the method of forming the source contact plug 16, etc.

[0056] One method for adjusting the impurity concentrations of the JFET region 8, the first intermediate region 21A, and the first current spreading region 23A is to use, for example, an n+ type SiC substrate as a base, an n+ type drain region 11, and then form the n- type drift region 10 using epitaxial growth. Then, epitaxial layers with different impurity concentrations are stacked to form the first current spreading region 23A, the first intermediate region 21A, and the JFET region 8. If there are regions with the same impurity concentration, they can be formed in the same epitaxial layer, thereby reducing the number of times epitaxial layers are formed. Since stacking epitaxial layers can be costly, an epitaxial layer with a low but uniform impurity concentration equivalent to the n- type drift region 10 may be formed, and then the JFET region 8, the first intermediate region 21A, and the first current spreading region 23A may be additionally formed in part of the formed epitaxial layer using impurity ion implantation or the like. The buffer region 15 may also be formed by stacking epitaxial layers with different impurity concentrations, or may be formed using impurity ion implantation technology or the like.

[0057] The impurity concentration and thickness of the channel region 5 are related to the threshold voltage of MOS operation and the channel resistance (and thus the on-resistance). The impurity concentration of the channel region 5 is 1×10 17 cm -3 That's it, 1×10 19 cm -3 Less than 1×10 is desirable 18 cm -3 It is more desirable that the impurity concentration profile of the channel region 5 is about 1×10. The impurity concentration profile of the channel region 5 may be a uniform profile or a non-uniform profile. As an example of a non-uniform profile, a gradient profile may be used in order to reduce the channel resistance by shallowing the channel depth. The gradient profile may be, for example, a profile in which the impurity concentration decreases as the position becomes deeper. Specifically, the impurity concentration on the source side may be set to a high peak value, and the impurity concentration may decrease as the position moves in the depth direction, i.e., toward the drain side. For example, in the case of a non-uniform profile such as a gradient profile, the peak value of the impurity concentration is 1×1017 cm -3 That's it, 1×10 19 cm -3 Less than 1×10 is desirable 18 cm -3 A degree is more desirable.

[0058] For example, when a high voltage is applied between the drain and source, the JFET region 8 is depleted and at the same time the depletion layer extends to the body region 9. Therefore, from the viewpoint of promoting depletion and maintaining a high breakdown voltage, it is important to set the impurity concentration in the body region 9 taking this into consideration.

[0059] The impurity concentration of the body region 9 is, for example, 1×10 17 cm -3 That's it, 1×10 19 cm -3 It is desirable to set the impurity concentration of the body region 9 to the following range: It is desirable that the impurity concentration of the body region 9 is higher than the impurity concentration of the channel region 5 within the above-mentioned range of impurity concentrations. The impurity concentration profile of the body region 9 may be either a uniform profile or a non-uniform profile.

[0060] The impurity concentration of the first pocket region 22A is 1×10 16 cm -3 That's it, 1×10 18 cm -3 It is desirable to set the impurity concentration of the first pocket region 22A to be lower than the impurity concentration of the body region 9. The thickness of the first pocket region 22A is the same as the thickness (tp1) of the first current spreading region, and is therefore desirable to be 0.5 μm or more and 1.0 μm or less. In addition, it is desirable for the thickness of the first pocket region 22A to be thicker than the thickness of the first intermediate region 21A.

[0061] Furthermore, in order to prevent the breakdown point in the drain-source breakdown voltage characteristics from affecting the bottom of trench 2, for example, in order to bring the breakdown point (avalanche point) inside body region 9, a point inside body region 9 may be provided that has a higher impurity concentration than other parts of body region 9. [Example]

[0062] FIG. 5 is a cross-sectional view of the semiconductor device of the second embodiment taken along the line X1-X1'.

[0063] The second embodiment is a modification of the first embodiment, in which the number of stages of the intermediate region, pocket region, and current spreading region is two.

[0064] The semiconductor device 1 of this embodiment has a second intermediate region 21B of a first conductivity type arranged above the drift region 10 in contact with the lower surfaces of the first pocket region 22A and the first current spreading region 23A, a second pocket region 22B of a second conductivity type arranged spaced apart from the first pocket region 22A in a position overlapping the first pocket region 22A via the second intermediate region 21B, and a second current spreading region 23B of the first conductivity type arranged between adjacent second pocket regions 22B.

[0065] It is desirable to set the length (Wp1) in the first direction of the first current spreading region 23A to be less than or equal to the length (Wp2) in the first direction of the second current spreading region 23B. Note that Fig. 5 illustrates the case where Wp1 = Wp2.

[0066] The impurity concentrations are preferably set so that: impurity concentration of drift region 10<impurity concentration of second current spreading region 23B≦impurity concentration of second intermediate region 21B≦impurity concentration of first current spreading region 23A.

[0067] Furthermore, it is desirable to set the thickness (tsp1) of the first intermediate region 21A≦the thickness (tsp2) of the second intermediate region 21B. Note that Fig. 5 illustrates the case where tsp1=tsp2.

[0068] The thickness (tp2) of the second pocket region 22B and the second current spreading region 23B is preferably greater than the thickness (tsp2) of the second intermediate region 21B.

[0069] The desirable numerical ranges (upper and lower numerical limits) related to the second intermediate region 21B, the second pocket region 22B, and the second current spreading region 23B are desirably set to the same numerical ranges as those for the first intermediate region 21A, the first pocket region 22A, and the first current spreading region 23A, based on the same concept as explained in Example 1.

[0070] According to this embodiment, the on-resistance can be further reduced compared to the first embodiment while ensuring short-circuit resistance. [Example]

[0071] FIG. 6 is a cross-sectional view of the semiconductor device of the third embodiment taken along the line X1-X1'.

[0072] The third embodiment is a modification of the second embodiment, in which the number of stages of the intermediate region, pocket region, and current spreading region is three.

[0073] The semiconductor device 1 of this embodiment has a third intermediate region 21C of the first conductivity type arranged above the drift region 10 in contact with the lower surfaces of the second pocket region 22B and the second current spreading region 23B, a third pocket region 22C of the second conductivity type arranged at a distance from the second pocket region 22B in a position overlapping the second pocket region 22B via the third intermediate region 21C, and a third current spreading region 23C of the first conductivity type arranged between adjacent third pocket regions 22C.

[0074] It is desirable to set the length (Wp2) in the first direction of the second current spreading region 23B to be equal to or less than the length (Wp3) in the first direction of the third current spreading region 23C. Note that Fig. 6 illustrates the case where Wp1 = Wp2 = Wp3.

[0075] The impurity concentrations are preferably set so that: impurity concentration of drift region 10<impurity concentration of third current spreading region 23C≦impurity concentration of third intermediate region 21C≦impurity concentration of second current spreading region 23B.

[0076] Furthermore, it is desirable to set the thickness (tsp2) of the second intermediate region 21B≦the thickness (tsp3) of the third intermediate region 21C. Note that Fig. 6 illustrates the case where tsp1=tsp2=tsp3.

[0077] The thickness (tp3) of the third pocket region 22C and the third current spreading region 23C is preferably greater than the thickness (tsp3) of the third intermediate region 21C.

[0078] The desirable numerical ranges (upper and lower numerical limits) related to the third intermediate region 21C, the third pocket region 22C, and the third current spreading region 23C are desirably set to the same numerical ranges as those for the first intermediate region 21A, the first pocket region 22A, and the first current spreading region 23A, based on the same concept as explained in Example 1.

[0079] According to this embodiment, the on-resistance can be further reduced compared to the second embodiment while ensuring short-circuit resistance.

[0080] In the same way as in the second and third embodiments, the number of stages of the intermediate region, pocket region, and current spreading region may be four or more.

[0081] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0082] 1: Semiconductor device 2: Trench 3: First source region 4: Second source region 5: Channel region 6: Gate insulating film 7: Gate electrode 8:JFET area 9: Body area 10: Drift region 11: Drain region 12: Source electrode 13: Drain electrode 14: Interlayer insulating film 15: Buffer area 16: Source contact plug 17: Barrier metal 21A: 1st intermediate area 21B: 2nd intermediate area 21C: Third intermediate area 22A: First pocket area 22B: Second pocket area 22C: Third pocket area 23A: First current spreading region 23B: Second current spreading region 23C: Third current spreading region

Claims

1. A plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above, the trenches being arranged in the second direction; a first source region of the first conductivity type including a region having a fin structure at least a portion of which is separated by the plurality of trenches; a second conductivity type channel region of a fin structure in contact with a lower surface of the first source region and separated by the plurality of trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed within the trench; a JFET region of a first conductivity type disposed below the channel region; a second conductivity type body region disposed on both sides of the JFET region; a first intermediate region of a first conductivity type arranged in contact with lower surfaces of the body region and the JFET region; a first pocket region of a second conductivity type arranged at a position overlapping the body region with the first intermediate region interposed therebetween and spaced apart from the body region; a first current spreading region of the first conductivity type disposed between adjacent first pocket regions; a drift region of a first conductivity type disposed below the first pocket region and the first current spreading region; a drain region of a first conductivity type that is disposed below the drift region and has a higher impurity concentration than the drift region; Ends of bottom surfaces of the plurality of trenches in the first direction are disposed within the body region; the channel region is connected to the body region, and a channel current flows in the channel region in a vertical direction; the length of the JFET region in the first direction is less than the length of the first current spreading region in the first direction, the impurity concentration of the drift region<the impurity concentration of the first current spreading region≦the impurity concentration of the first intermediate region<the impurity concentration of the JFET region, The semiconductor device is characterized in that the dimensions of the body region and the JFET region in the depth direction from the bottom of the trench are both greater than 0.5 μm.

2. In claim 1, The semiconductor device is characterized in that the thickness of the first intermediate region is 0.1 μm or more and 0.5 μm or less.

3. In claim 1, a dimension of the JFET region in a depth direction from a bottom of the trench is 0.8 μm or more and 1.3 μm or less; A semiconductor device, characterized in that the dimension of the first current spreading region in the depth direction from the bottom of the first intermediate region is 0.5 μm or more and 1.0 μm or less.

4. In claim 1, The semiconductor device is characterized in that the length of the trench in the first direction is 0.8 μm or more and 1.8 μm or less.

5. In claim 1, A semiconductor device, characterized in that the length of the JFET region in the first direction is 0.3 μm or more and 1.4 μm or less.

6. In claim 1, The impurity concentration of the JFET region is 8×10 １６ cm －３ That's it, 1 x 10 １８ cm －３ is as follows: The impurity concentration of the first intermediate region is 1×10 １６ cm －３ That's it, 1 x 10 １７ cm －３ is as follows: The impurity concentration of the first current spreading region is 1×10 １６ cm －３ That's it, 1 x 10 １７ cm －３ is as follows: The impurity concentration of the drift region is 1×10 １５ cm －３ That's it, 1 x 10 １６ cm －３ A semiconductor device characterized by:

7. In claim 1, a first conductivity type buffer region between the drift region and the drain region, the buffer region having an impurity concentration higher than that of the drift region and lower than that of the drain region;

8. In claim 7, The impurity concentration of the buffer region is 1×10 １７ cm －３ That's it, 1 x 10 １９ cm －３ A semiconductor device characterized by:

9. In claim 7, the buffer region is composed of a plurality of buffer layers, and the impurity concentrations of the plurality of buffer layers increase toward the drain region, and the thicknesses of the plurality of buffer layers decrease toward the drain region.

10. In claim 1, The impurity concentration of the channel region is 1×10 １７ cm －３ That's it, 1 x 10 １９ cm －３ A semiconductor device characterized by:

11. In claim 10, The semiconductor device is characterized in that the deeper the channel region is, the lower the impurity concentration becomes.

12. In claim 1, The impurity concentration of the body region is 1×10 １７ cm －３ That's it, 1 x 10 １９ cm －３ A semiconductor device characterized by:

13. In claim 1, The impurity concentration of the first pocket region is 1×10 １６ cm －３ That's it, 1 x 10 １８ cm －３ A semiconductor device characterized by:

14. In claim 1, A semiconductor device comprising: a body region having a point therein that has a higher impurity concentration than other portions of the body region.

15. In claim 1, a second source region of a second conductivity type in contact with an upper surface of at least a portion of the body region and having an impurity concentration higher than that of the body region;

16. In claim 1, a second intermediate region of the first conductivity type disposed above the drift region and in contact with lower surfaces of the first pocket region and the first current spreading region; a second pocket region of a second conductivity type arranged at a position overlapping the first pocket region with the second intermediate region interposed therebetween and spaced apart from the first pocket region; a second current spreading region of the first conductivity type disposed between adjacent second pocket regions; the length of the first current spreading region in the first direction is less than or equal to the length of the second current spreading region in the first direction, the impurity concentration of the drift region<the impurity concentration of the second current spreading region≦the impurity concentration of the second intermediate region≦the impurity concentration of the first current spreading region, A semiconductor device, characterized in that the thickness of the first intermediate region is less than or equal to the thickness of the second intermediate region.

17. In claim 16, a third intermediate region of the first conductivity type disposed above the drift region and in contact with lower surfaces of the second pocket region and the second current spreading region; a third pocket region of the second conductivity type arranged at a position overlapping the second pocket region with the third intermediate region interposed therebetween and spaced apart from the second pocket region; a third current spreading region of the first conductivity type disposed between adjacent third pocket regions; the length of the second current spreading region in the first direction is less than or equal to the length of the third current spreading region in the first direction, the impurity concentration of the drift region<the impurity concentration of the third current spreading region≦the impurity concentration of the third intermediate region≦the impurity concentration of the second current spreading region, A semiconductor device, characterized in that the thickness of the second intermediate region is less than or equal to the thickness of the third intermediate region.

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