LED device and method for manufacturing LED device

Abstract

To provide an LED device and a method for manufacturing the LED device that can reliably supply power to each LED while reducing the effort required to form a p-side electrode and an n-side electrode.SOLUTION: A monolithic LED 2 includes a p-type layer 303, a first n-type layer 301, a p-side electrode 31p, and an n-side electrode 31n, and a mounting surface 33p of the p-side electrode 31p and a mounting surface 33n of the n-side electrode 31n are at different heights. A multilayer wiring substrate 3 includes a first wiring layer 91, a second wiring layer 93, and an intermediate insulating layer 92, and the first wiring layer 91 is arranged on the side of the intermediate insulating layer 92 away from the monolithic LED 2 and is connected to the p-side electrode 31p through an opening 92A. The second wiring layer 93 is arranged on the side of the intermediate insulating layer 92 closer to the monolithic LED 2 and is connected to the n-side electrode 31n. The difference in height between the mounting surface 33p and the mounting surface 33n is equal to the difference in height between a mounting surface 97A of an anode-side bonding layer 95A of the first wiring layer 91 and a mounting surface 97K of a cathode-side bonding layer 95K of the second wiring layer 93.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an LED device and a method for manufacturing an LED device. [Background technology]

[0002] Patent Document 1 discloses a micro LED panel that is rectangular in plan view and in which a plurality of micro LED pixels are arranged in rows and columns. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-185515 Summary of the Invention [Problem to be solved by the invention]

[0004] In the micro LED panel of Patent Document 1, the thickness of the first conductivity type metal layer functioning as the n-side electrode is made thicker than the second conductivity type metal layer functioning as the p-side electrode, and the mounting surface of the first conductivity type metal layer and the mounting surface (the surface that comes into contact with the bonding material) of the second conductivity type metal layer are aligned in height. By aligning the height of the electrodes of each micro LED in this way, the panel is mounted in a way that ensures reliable power supply to each LED. However, forming a thick first conductivity type metal layer requires more material and time.

[0005] The present invention has been made in consideration of the above-mentioned conventional circumstances, and aims to provide an LED device and a method for manufacturing an LED device that can reliably supply power to each LED while reducing the effort required for forming a p-side electrode and an n-side electrode. [Means for solving the problem]

[0006] The LED device of the first invention is An LED device in which a plurality of LEDs are mounted on a multilayer wiring substrate, The LED is a p-type semiconductor and an n-type semiconductor stacked together; a p-side electrode for supplying power to the p-type semiconductor; an n-side electrode for supplying power to the n-type semiconductor; the mounting surfaces of the p-side electrode and the n-side electrode are at different heights, The multilayer wiring board comprises: a first wiring layer connected to one of the n-side electrode and the p-side electrode; a second wiring layer connected to the other of the n-side electrode and the p-side electrode; an intermediate insulating layer that insulates the first wiring layer from the second wiring layer; the first wiring layer is disposed on a side of the intermediate insulating layer away from the LED, and is electrically connected to one of the p-side electrode and the n-side electrode through an opening formed in the intermediate insulating layer; the second wiring layer is disposed on the LED side with respect to the intermediate insulating layer and is electrically connected to the other of the p-side electrode and the n-side electrode; The height difference between the mounting surface of the p-side electrode and the mounting surface of the n-side electrode is This is equal to the difference in height between the first wiring layer and the second wiring layer.

[0007] According to this configuration, the difference in height between the mounting surface of the p-side electrode and the mounting surface of the n-side electrode is equal to the difference in height between the first wiring layer and the second wiring layer, so it is possible to connect the first wiring layer and the second wiring layer to the p-side electrode and the n-side electrode so as to cancel out the difference in height between the mounting surface of the p-side electrode and the mounting surface of the n-side electrode.

[0008] The method for manufacturing an LED device according to the second aspect of the present invention includes: A method for manufacturing an LED device including an LED and a multilayer wiring substrate that supplies power to the LED, comprising: The multilayer wiring board comprises: a first step of laminating a first wiring layer connected to one of an n-side electrode and a p-side electrode of the LED on a support substrate; a second step of laminating an intermediate insulating layer on the first wiring layer; a third step of laminating a second wiring layer connected to the other of the n-side electrode and the p-side electrode on the intermediate insulating layer, In the second step, an opening is formed in the intermediate insulating layer to expose a part of the first wiring layer, In the third step, when the second wiring layer is laminated, a height adjusting portion is simultaneously laminated on the exposed first wiring layer in the opening.

[0009] According to this manufacturing method, a height adjustment section having the function of adjusting the height of the first wiring layer is laminated at the same time as the second wiring layer, so that the first wiring layer does not need to be laminated thickly, and the time required to laminate the first wiring layer can be easily shortened. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing an LED device according to a first embodiment. [Figure 2] 1 is a side view showing the structure of a monolithic LED according to a first embodiment. [Figure 3] 1 is a plan view showing a first wiring layer of a multilayer wiring board according to a first embodiment. [Figure 4] 2 is a plan view showing an intermediate insulating layer of the multilayer wiring board of Example 1. FIG. [Figure 5] FIG. 3 is a plan view showing a second wiring layer of the multilayer wiring board of the first embodiment. [Figure 6] 2 is a plan view showing a front insulating layer of the multilayer wiring board of Example 1. FIG. [Figure 7] 1A and 1B are enlarged views of a portion around an LED connection terminal of a multilayer wiring board according to Example 1, in which (A) is a plan view, (B) is a cross-sectional view taken along line AA in (A), (C) is a cross-sectional view taken along line BB in (A), and (D) is a cross-sectional view taken along line CC in (A). [Figure 8] 1 is a side view showing a state in which the monolithic LED of Example 1 is mounted on a multilayer wiring substrate. [Figure 9]1A to 1C are schematic diagrams illustrating steps for manufacturing the monolithic LED of Example 1. [Figure 10] 2A to 2C are schematic diagrams illustrating steps for manufacturing the multilayer wiring board of Example 1. [Figure 11] FIG. 10 is a side view showing the structure of the LED device of Example 2. [Figure 12] FIG. 10 is a side view showing the structure of the monolithic LED of Example 3. [Figure 13] FIG. 10 is a side view showing the structure of the LED device of Example 3. [Figure 14] FIG. 10 is a cross-sectional view showing a multilayer wiring board according to a fourth embodiment. [Figure 15] 10A to 10C are schematic diagrams illustrating steps for manufacturing a multilayer wiring board according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] A preferred embodiment of the present invention will now be described.

[0012] In the first aspect of the invention, the first wiring layer preferably includes a height adjusting portion having the same thickness as the second wiring layer within the opening on the LED side.

[0013] In the first aspect of the present invention, the multilayer wiring board preferably has a spacer layer made of an insulating material in an area where the first wiring layer is not formed.

[0014] In the first aspect of the invention, the LEDs preferably have light-emitting layers that emit light of different colors, and the heights of the p-side electrodes and the heights of the n-side electrodes provided on the LEDs are preferably the same.

[0015] In the first invention, height-adjusting electrodes are provided between the bonding layer formed on the first wiring layer and one of the n-side electrode and the p-side electrode, and between the bonding layer formed on the second wiring layer and the other of the n-side electrode and the p-side electrode, and it is preferable that the thickness of the height-adjusting electrodes is the same as the difference in height between the p-side electrode forming surface on which the p-side electrode is formed and the n-side electrode forming surface on which the n-side electrode is formed.

[0016] In the second invention, the LEDs are configured as pixels, The LED is preferably a monolithic LED in the form of a plurality of pixels formed on a substrate.

[0017] Next, a first embodiment of an LED device according to the present invention will be described with reference to FIGS.

[0018] Example 1 As shown in FIG. 1, the LED device 1 of the first embodiment includes a monolithic LED 2 and a multilayer wiring substrate 3.

[0019] [Monolithic LED configuration] As shown in FIG. 2, the monolithic LED 2 includes a sapphire substrate 10 serving as an LED substrate, a buffer layer 20, an epitaxial layer 30, a p-side electrode 31p, and an n-side electrode 31n.

[0020] [Sapphire substrate structure] The sapphire substrate 10 is a plate-shaped sapphire substrate having both surfaces polished to a flat surface. The thickness of the sapphire substrate 10 is, for example, 300 μm. In the monolithic LED 2, the upward-facing surface of each layer shown in FIG. 2 is defined as the upper surface.

[0021] [Buffer layer configuration] The buffer layer 20 is laminated on the upper surface of the sapphire substrate 10. The buffer layer 20 has a thickness of, for example, 2 μm. The buffer layer 20 is made of AlN, GaN, or the like grown at a low temperature.

[0022] [Epitaxial layer structure] The epitaxial layer 30 is stacked on the upper surface of the buffer layer 20. The epitaxial layer 30 has a first n-type layer 301 which is an n-type semiconductor, a light-emitting layer 302, a p-type layer 303 which is a p-type semiconductor, a tunnel junction layer 304, and a second n-type layer 305, which are stacked in this order.

[0023] The first n-type layer 301 is stacked on the upper surface of the buffer layer 20. The thickness of the first n-type layer 301 is, for example, 2 μm. The first n-type layer 301 is formed of, for example, GaN doped with n-type impurities such as Si.

[0024] The light emitting layer 302 is laminated on the upper surface of the first n-type layer 301. The light emitting layer 302 is formed, for example, as a multiple quantum well. The thickness of the light emitting layer 302 is, for example, 50 nm. The light emitting layer 302 is configured to be able to emit light of a predetermined emission wavelength.

[0025] P-type layer 303 is laminated on the upper surface of light emitting layer 302. The thickness of p-type layer 303 is, for example, 180 nm. P-type layer 303 is formed of, for example, GaN doped with p-type impurities such as Mg.

[0026] The tunnel junction layer 304 is stacked on the upper surface of the p-type layer 303. The thickness of the tunnel junction layer 304 is, for example, 25 nm. The tunnel junction layer 304 is formed by stacking an n++ GaN layer doped with a high concentration of Si and a p++ GaN layer doped with a high concentration of Mg. Here, n++ means a state in which n-type impurities are doped at a high concentration, and p++ means a state in which p-type impurities are doped at a high concentration. Note that by providing a tunnel junction layer between an n-type semiconductor and a p-type semiconductor, it becomes possible to pass a current from the n-type semiconductor (second n-type layer 305) to the p-type semiconductor (p-type layer 303).

[0027] The second n-type layer 305 is stacked on the upper surface of the tunnel junction layer 304. The second n-type layer 305 has a thickness of, for example, 400 nm. The second n-type layer 305 is formed of, for example, GaN doped with n-type impurities such as Si.

[0028] The monolithic LED 2 is configured to have a plurality of pixels 70 partitioned by partition grooves 80. That is, the monolithic LED 2 is an LED in the form of a plurality of pixels 70 formed on a sapphire substrate 10. The pixels 70 are arranged in a matrix on the upper surface of the sapphire substrate 10, aligned in one direction and in a direction perpendicular to the one direction (see FIG. 9(C)).

[0029] The partitioning grooves 80 are recessed from the upper surface of the second n-type layer 305 toward the sapphire substrate 10 (in the stacking direction L), and their bottom surfaces reach the upper surface of the sapphire substrate 10. The partitioning grooves 80 are formed perpendicular to the plate surface of the sapphire substrate 10. The outer periphery of each pixel 70 is formed in an island shape on the upper surface of the sapphire substrate 10 by the partitioning grooves 80.

[0030] Each pixel 70 has a light-emitting main body portion 72 and a non-light-emitting portion 73. In the light-emitting main body portion 72, the upper surface of the second n-type layer 305 (the uppermost surface of the epitaxial layer 30) is exposed. The non-light-emitting portion 73 is adjacent to the light-emitting main body portion 72 so as to be aligned in one direction. In the non-light-emitting portion 73, the light-emitting layer 302 to the second n-type layer 305 have been removed, and the first n-type layer 301 is exposed.

[0031] The p-side electrode 31p is laminated on the upper surface of the light-emitting main body 72 (the upper surface of the second n-type layer 305). The n-side electrode 31n is laminated on the upper surface of the non-light-emitting portion 73 (the surface where the first n-type layer 301 is exposed). The upper surface of the p-side electrode 31p is a mounting surface 33p that connects to a mounting surface 97A of a bonding layer 95 of a multilayer wiring substrate 3, which will be described later. The upper surface of the n-side electrode 31n is a mounting surface 33n that connects to a mounting surface 97K of a bonding layer 95 of a multilayer wiring substrate 3, which will be described later. In this manner, each pixel 70 is formed.

[0032] In each pixel 70 of the monolithic LED 2 configured as described above, the first n-type layer 301 (n-type semiconductor), the light-emitting layer 302, the p-type layer 303 (p-type semiconductor), the p-side electrode 31p, and the n-side electrode 31n are essential elements for the LED to emit light. In other words, the LED is configured as a pixel 70. The monolithic LED 2 has a configuration including a plurality of LEDs.

[0033] [Configuration of multilayer wiring board] As shown in FIG. 1, when the multilayer wiring board 3 is viewed from the front, the multilayer wiring board 3 has a plurality of LED connection terminals 81 formed in the center and a plurality of external terminals 82 formed in the outer edge.

[0034] The multilayer wiring board 3 has a support substrate 90, a first wiring layer 91, an intermediate insulating layer 92, a second wiring layer 93, a front insulating layer 94, a bonding layer 95, and a height adjusting portion 93D.

[0035] [Support substrate configuration] The support substrate 90 is made of, for example, Al2O3, Si, low thermal expansion glass, etc. The support substrate 90 is formed in the shape of a flat plate having an outer shape of 12 mm square.

[0036] [Configuration of the first wiring layer] The first wiring layer 91 is laminated on the upper surface of the support substrate 90. The first wiring layer 91 is formed by laminating, for example, Ti: 0.01 μm / Au: 0.28 μm / Ti: 0.01 μm in this order. As shown in FIG. 3 , the first wiring layer 91 has a plurality of wires 91A, a plurality of lead wires 91B, and a plurality of external terminal pads 91C. The first wiring layer 91 electrically connects an LED connection terminal 81 electrically connected to the p-side electrode 31p of the monolithic LED 2 to an anode-side external terminal 82 arranged around the periphery of the multilayer wiring substrate 3.

[0037] 7, the wiring 91A passes through the anode-side LED connection terminal 81 and extends in the direction of the LED connection terminal 81 corresponding to the p-side electrode 31p and the n-side electrode 31n of the pixel 70 of the monolithic LED 2. The interval between adjacent wirings 91A is set to be the same as the interval between adjacent pixels 70 in a direction perpendicular to the direction in which the p-side electrode 31p and the n-side electrode 31n of the pixel 70 of the monolithic LED 2 are aligned.

[0038] 3, a plurality of lead wires 91B are provided corresponding to each of the wirings 91A, connecting the wirings 91A to external terminal pads 91C on the anode side. The lead wires 91B are alternately connected to one end and the other end of each of the wirings 91A, and extend toward the external terminal pads 91C on the outer edge of the support substrate 90. The external terminal pads 91C are provided at positions corresponding to the external terminals 82.

[0039] [Structure of intermediate insulation layer] The intermediate insulating layer 92 is laminated on the upper surface of the support substrate 90 on which the first wiring layer 91 is formed. The intermediate insulating layer 92 is disposed between the first wiring layer 91 and the second wiring layer 93, thereby insulating the first wiring layer 91 from the second wiring layer 93. The intermediate insulating layer 92 is formed of, for example, SiO2 or Al2O3. The thickness of the intermediate insulating layer 92 is 0.7 μm. This thickness corresponds to the thickness obtained by removing the light-emitting layer 302 through the second n-type layer 305 to expose the first n-type layer 301.

[0040] 4, the intermediate insulating layer 92 is formed to entirely cover the support substrate 90 and the first wiring layer 91, except for a plurality of openings 92A and a plurality of openings 92B. The openings 92A correspond to the positions of the anode-side LED connection terminals 81 (see FIG. 1) and are provided so as to overlap with the respective wirings 91A (see FIG. 7). The openings 92B are provided so as to correspond to the positions of the external terminals 82.

[0041] [Configuration of the second wiring layer] The second wiring layer 93 is laminated on the upper surface of the support substrate 90 on which the first wiring layer 91 and the intermediate insulating layer 92 are formed. The second wiring layer 93 is formed, for example, by laminating Ti: 0.01 μm / Au: 0.28 μm / Ti: 0.01 μm in this order. As shown in FIG. 5 , the second wiring layer 93 includes multiple wires 93A, multiple lead wires 93B, multiple external terminal pads 93C, and multiple height adjustment portions 93D. The second wiring layer 93 electrically connects the LED connection terminal 81 electrically connected to the n-side electrode 31n of the monolithic LED 2 to the cathode-side external terminals 82 arranged around the periphery of the multilayer wiring substrate 3.

[0042] 7, the wiring 93A passes through the cathode-side LED connection terminal 81 and extends in a direction perpendicular to the wiring 91A of the first wiring layer 91. The interval between adjacent wirings 93A is set to be the same as the interval between adjacent pixels 70 in the direction in which the p-side electrode 31p and the n-side electrode 31n of the pixel 70 of the monolithic LED 2 are aligned.

[0043] The plurality of lead wires 93B are provided so as to correspond one to each of the wirings 93A and connect the wirings 93A to external terminal pads 93C on the cathode side. Each lead wire 93B is connected to one end of the corresponding wiring 93A and extends toward the external terminal pads 93C on the outer edge of the support substrate 90. The plurality of external terminal pads 93C are provided at positions corresponding to the external terminals 82.

[0044] As shown in FIG. 7, the plurality of height adjustment portions 93D are stacked on the upper surface of the wiring 91A of the first wiring layer 91 at the positions of the anode-side LED connection terminals 81 with the same thickness as the second wiring layer 93.

[0045] [Configuration of the front insulation layer] The front insulating layer 94 is laminated on the upper surface of the support substrate 90 on which the first wiring layer 91, the intermediate insulating layer 92, and the second wiring layer 93 are formed. The front insulating layer 94 is made of, for example, SiO2. The thickness of the front insulating layer 94 is, for example, 0.25 μm.

[0046] As shown in FIG. 6, the front-side insulating layer 94 is formed to entirely cover the support substrate 90, the first wiring layer 91, the intermediate insulating layer 92, and the second wiring layer 93, except for a plurality of openings 94A and a plurality of openings 94B. As shown in FIG. 7, the openings 94A are provided to correspond to the positions of the LED connection terminals 81 on both the anode and cathode sides. The anode-side openings 94A are provided to overlap the respective wirings 91A. The cathode-side openings 94A are provided to overlap the respective wirings 93A. The openings 94B are provided to correspond to the positions of the external terminals 82.

[0047] [Composition of bonding layer] The bonding layer 95 is laminated on the upper surface of the height adjustment portion 93D and the upper surface of the second wiring layer 93 at the positions of the plurality of openings 94A and the plurality of openings 94B of the front insulating layer 94. The bonding layer 95 corresponds to the LED connection terminal 81. The bonding layer 95 is formed, for example, from an alloy of Au and Sn. The thickness of the bonding layer 95 is, for example, 3 μm. The bonding layer 95 is thicker than the front insulating layer 94 and therefore protrudes above the front insulating layer 94. The bonding layer 95 formed in the opening 94A serves as a bonding bump for the LED.

[0048] 7(B), the bonding layer 95 laminated on the upper surface of the height adjusting portion 93D is an anode-side bonding layer 95A. The bonding layer 95 laminated on the upper surface of the wiring 93A of the second wiring layer 93 is a cathode-side bonding layer 95K. The height positions at which the anode-side bonding layer 95A and the cathode-side bonding layer 95K are disposed differ by the thickness of the intermediate insulating layer 92. This corresponds to the thickness removed from the light-emitting layer 302 to the second n-type layer 305 in order to expose the first n-type layer 301.

[0049] 7(B), the anode-side bonding layer 95A is laminated on the upper surface of the support substrate 90, on which the first wiring layer 91 and the height adjustment portion 93D of the second wiring layer 93 are laminated. In contrast, the cathode-side bonding layer 95K is laminated on the upper surface of the support substrate 90, on which the first wiring layer 91, the intermediate insulating layer 92, and the second wiring layer 93 are laminated. In other words, an extra intermediate insulating layer 92 is laminated on the cathode-side bonding layer 95K side compared to the anode-side bonding layer 95A side. Furthermore, the height adjustment portion 93D of the second wiring layer 93 has the same thickness as the second wiring layer 93. Therefore, the anode-side bonding layer 95A is formed at a height position lower than the cathode-side bonding layer 95K by the thickness of the intermediate insulating layer 92. In other words, the difference in height between the anode-side bonding layer 95A of the first wiring layer 91 and the cathode-side bonding layer 95K of the second wiring layer 93 is the same as the thickness of the intermediate insulating layer 92.

[0050] 8, when the monolithic LED 2 is mounted on the multilayer wiring substrate 3, the difference in height between the p-side electrode 31p and the n-side electrode 31n of the monolithic LED 2 is offset by the difference in height between the anode-side bonding layer 95A and the cathode-side bonding layer 95K of the multilayer wiring substrate 3. When the mounting surface 33p of the p-side electrode 31p becomes flush with the mounting surface 97A of the anode-side bonding layer 95A, the mounting surface 33n of the n-side electrode 31n becomes flush with the mounting surface 97A of the cathode-side bonding layer 95K.

[0051] In this way, the LED device 1 does not require thickening one of the electrodes of the monolithic LED 2, and the multilayer wiring structure allows the monolithic LED 2 to be stably mounted by adjusting the height of the anode side bonding layer 95A and the cathode side bonding layer 95K of the multilayer wiring substrate 3, thereby ensuring the supply of power to each LED.

[0052] [Monolithic LED manufacturing method] An example of a manufacturing method for the monolithic LED 2 will be described with reference to Fig. 9. The monolithic LED 2 is manufactured by performing a lamination process, a process for forming partition grooves 80, and a pixel formation process. First, in the lamination process, a buffer layer 20 and an epitaxial layer 30 are deposited by crystal growth on the upper surface of a sapphire substrate 10 using MOVPE (metal organic vapor phase epitaxy) as shown in Fig. 9(A).

[0053] Next, in the process of forming the partitioning grooves 80, as shown in FIG. 9(B), a plurality of island-shaped pixels 70 are formed on the sapphire substrate 10 by the partitioning grooves 80 whose peripheries reach the upper surface of the sapphire substrate 10.

[0054] Next, in the pixel formation process, the surface on which the pixels 70 are to be formed is exposed, as shown in Fig. 9(C). Specifically, a resist mask is laminated on the area where the light-emitting main body 72 is to be formed, and then dry etching using Cl2 is performed to remove the light-emitting layer 302 through the second n-type layer 305. Then, a p-side electrode 31p is formed on the upper surface of the light-emitting main body 72, and an n-side electrode 31n is formed on the upper surface of the non-light-emitting portion 73. In this way, the monolithic LED 2 is formed.

[0055] [Manufacturing method for multilayer wiring boards] An example of a method for manufacturing the multilayer wiring board 3 will be described with reference to FIGS. 4 to 6 and FIG. 10. FIG. 10 is a cross-sectional view of the periphery of the LED connection terminal 81, with the upper part corresponding to FIG. 7(D) and the lower part corresponding to FIG. 7(C). The multilayer wiring board 3 is manufactured by performing a first step, a second step, a third step, a fourth step, and a fifth step. First, in the first step, a first wiring layer 91 shown in FIG. 3 is laminated on the upper surface of the support substrate 90 by vapor deposition. At this time, wiring 91A is laminated as shown in FIG. 10(A).

[0056] Next, in the second step, the intermediate insulating layer 92 shown in FIG. 4 is laminated on the upper surface of the support substrate 90, the upper surface of the first wiring layer 91, the upper surface of the lead wire 91B, and the upper surface of the external terminal pad 91C using a sputtering method. Specifically, an SiO2 film is laminated as the intermediate insulating layer 92 over the entire upper surface of the support substrate 90. Then, a Ni mask is laminated on the upper surface of the SiO2 film except for areas where openings 92A and 92B will be formed. Then, the openings 92A and 92B are formed in the intermediate insulating layer 92 using an ICP (inductively coupled plasma) method. At this time, the intermediate insulating layer 92 and opening 92A are formed as shown in FIG. 10(B).

[0057] Next, in a third step, the second wiring layer 93 and the height adjustment portion 93D shown in Fig. 5 are laminated by vapor deposition. At this time, the wiring 93A and the height adjustment portion 93D are laminated as shown in Fig. 10(C). The height adjustment portion 93D is laminated on the upper surface of the wiring 91A exposed in the opening 92A.

[0058] Next, in the fourth step, the front insulating layer 94 shown in Fig. 6 is laminated. Then, the openings 94A and 94B are formed through the same steps as in the second step. At this time, the front insulating layer 94 and the opening 94A are formed as shown in Fig. 10(D).

[0059] Next, in a fifth step, a bonding layer 95 is laminated in the openings 94A and 94B by electrolytic plating. At this time, as shown in FIG. 10(E), the bonding layer 95 is laminated on the upper surface of the height adjustment portion 93D exposed by the opening 94A and on the upper surface of the wiring 93A. In this way, the multilayer wiring substrate 3 is formed.

[0060] [Mounting method for monolithic LEDs on multilayer wiring boards] Next, the monolithic LED 2 is mounted on the multilayer wiring substrate 3 (mounting process). The multilayer wiring substrate 3 shown by the solid lines in Fig. 8 is disposed so that the bonding layer 95 faces up. In contrast, the monolithic LED 2 shown by the dashed lines in Fig. 8 is disposed so that the p-side electrode 31p and the n-side electrode 31n face down. The relative positions of the monolithic LED 2 and the multilayer wiring substrate 3 are adjusted so that the mounting surface 33p of the p-side electrode 31p of each pixel 70 faces the mounting surface 97A of the anode-side bonding layer 95A, and the mounting surface 33n of the n-side electrode 31n faces the mounting surface 97K of the cathode-side bonding layer 95K. Then, by heating, the bonding layer 95 (an alloy of Au and Sn) is melted to bond the mounting surface 33p of the p-side electrode 31p of each pixel 70 to the mounting surface 97A of the anode-side bonding layer 95A, and the mounting surface 33n of the n-side electrode 31n to the mounting surface 97K of the cathode-side bonding layer 95K. In this way, the LED device 1 is completed.

[0061] In the LED device 1, when a voltage is applied to external terminals 82 on the anode and cathode sides of the multilayer wiring substrate 3, a voltage is applied from the LED connection terminal 81 to the p-side electrode 31p and the n-side electrode 31n of the monolithic LED 2. Then, positive charges and negative charges combine in the light-emitting layer 302 (see FIG. 2), causing light to be emitted from the light-emitting layer 302.

[0062] Next, the operation of the above embodiment will be described. In the LED device 1, a monolithic LED 2 is mounted on a multilayer wiring substrate 3. The monolithic LED 2 includes a stacked p-type layer 303 and a first n-type layer 301, a p-side electrode 31p that supplies power to the p-type layer 303, and an n-side electrode 31n that supplies power to the first n-type layer 301. The mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n are at different heights, and the multilayer wiring substrate 3 includes a first wiring layer 91 connected to the p-side electrode 31p via a height adjustment portion 93D and a bonding layer 95, a second wiring layer 93 connected to the n-side electrode 31n via the bonding layer 95, and an intermediate insulating layer 92 that insulates the first wiring layer 91 from the second wiring layer 93. The first wiring layer 91 is disposed on the side of the intermediate insulating layer 92 away from the monolithic LED 2 and is electrically connected to the p-side electrode 31p of the monolithic LED 2 via a height adjustment portion 93D provided in an opening 92A formed in the intermediate insulating layer 92. The second wiring layer 93 is disposed on the monolithic LED 2 side of the intermediate insulating layer 92 and is electrically connected to the n-side electrode 31n. The difference in height between the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n is equal to the difference in height between the mounting surface 97A of the bonding layer 95 (anode-side bonding layer 95A) of the first wiring layer 91 and the mounting surface 97K of the bonding layer 95 (cathode-side bonding layer 95K) of the second wiring layer 93.

[0063] According to this configuration, the difference in height between the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n is equal to the difference in height between the mounting surface 97A of the bonding layer 95 (anode-side bonding layer 95A) of the first wiring layer 91 and the mounting surface 97K of the bonding layer 95 (cathode-side bonding layer 95K) of the second wiring layer 93. Therefore, it is possible to connect the anode-side bonding layer 95A of the first wiring layer 91 and the cathode-side bonding layer 95K of the second wiring layer 93 to the p-side electrode 31p and the n-side electrode 31n so as to cancel out the difference in height between the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n.

[0064] The first wiring layer 91 includes a height adjustment portion 93D with the same thickness as the second wiring layer 93 within the opening 92A of the intermediate insulating layer 92 on the monolithic LED 2 side. This configuration allows the provision of the height adjustment portion 93D within the opening 92A to form a thick intermediate insulating layer 92. That is, the thickness of the intermediate insulating layer 92 can be set to the difference in height between the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n of the LED device 1. This further ensures insulation between the first wiring layer 91 and the second wiring layer 93. For example, even if some burrs are formed on the ends of the first wiring layer 91, the burrs can be filled by the thick intermediate insulating layer 92.

[0065] A method for manufacturing an LED device 1 includes a monolithic LED 2 and a multilayer wiring substrate 3 that supplies power to the monolithic LED 2. The multilayer wiring substrate 3 is formed by performing the following steps: a first step of laminating a first wiring layer 91 connected to a p-electrode 31p of the monolithic LED 2 on a support substrate 90; a second step of laminating an intermediate insulating layer 92 on the first wiring layer 91; and a third step of laminating a second wiring layer 93 connected to an n-electrode 31n on the intermediate insulating layer 92. In the second step, an opening 92A is formed in the intermediate insulating layer 92 to expose a portion of the first wiring layer 91. In the third step, when laminating the second wiring layer 93, a height adjustment portion 93D is simultaneously laminated on the exposed portion of the wiring 91A of the first wiring layer 91 in the opening 92A. This manufacturing method allows the height adjustment portion 93D to be formed in the same process as the wiring 93A, thereby reducing manufacturing effort compared to forming the height adjustment portion 93D in a separate process from the wiring 93A.

[0066] The monolithic LED 2 has a configuration in which a plurality of pixels 70 are formed on a sapphire substrate 10. With this configuration, it becomes possible to handle homogeneous monolithic LEDs 2 collectively.

[0067] <Example 2> The LED device 6 of Example 2 differs from Example 1 in that the second wiring layer 93 does not have a height adjustment portion, and the thickness of the intermediate insulating layer 192 is thinner by the thickness of the height adjustment portion. In Example 2, the same components as those in Example 1 are denoted by the same reference numerals, and detailed explanations thereof will be omitted.

[0068] As shown in FIG. 11 , the intermediate insulating layer 192 of the multilayer wiring substrate 5 is thinner than the intermediate insulating layer 92 of Example 1. Specifically, the intermediate insulating layer 192 is thinner than the intermediate insulating layer 92 of Example 1 by the thickness of the height adjustment portion 93D. The thickness of the intermediate insulating layer 92 of Example 1 is 0.7 μm, and the thickness of the height adjustment portion 93D is 0.3 μm, so the thickness of the intermediate insulating layer 192 of Example 2 is 0.4 μm. No height adjustment portion is disposed between adjacent wirings 93A as in Example 1. The thickness of the wirings 93A is 0.3 μm. The sum of the thickness of the multiple wirings 93A and the thickness of the intermediate insulating layer 192 is 0.7 μm. The bonding layer 95 is laminated on the upper surfaces of the wirings 93A of the second wiring layer 93 and the upper surfaces of the wirings 91A of the first wiring layer 91. The bonding layer 95 laminated on the upper surface of the wiring 91A of the first wiring layer 91 is disposed in the opening 192A and the opening 94A. The height difference between the mounting surface 97A of the anode-side bonding layer 95A and the mounting surface 97K of the cathode-side bonding layer 95K is 0.7 μm. This height difference is the same as the height difference between the mounting surface 97A of the anode-side bonding layer 95A and the mounting surface 97K of the cathode-side bonding layer 95K in Example 1. That is, by adjusting the thickness of the intermediate insulating layer 192, it is possible to fabricate a multilayer wiring substrate 5 that corresponds to the height difference between the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n of the monolithic LED 2 without providing a height adjustment section.

[0069] Example 3 The LED device 8 of Example 3 differs from Example 1 in the configuration of the monolithic LED 4. The monolithic LED 4 of Example 3 is configured by stacking three p-type layers, a light-emitting layer, and an n-type layer, and each of the three light-emitting layers emits light of a different emission wavelength. The monolithic LED 4 is configured such that layers for conducting electricity to each light-emitting layer are exposed and a circuit is formed. In Example 3, the same components as in Example 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0070] [Epitaxial layer structure] 12, the epitaxial layer 130 is stacked on the upper surface of the buffer layer 20. The epitaxial layer 130 has a first n-type layer 1301, a first light-emitting layer 130B (light-emitting layer), a first p-type layer 1302, a first tunnel junction layer 1303, a second n-type layer 1304, a second light-emitting layer 130G (light-emitting layer), a second p-type layer 1305, a second tunnel junction layer 1306, a third n-type layer 1307, a third light-emitting layer 130R (light-emitting layer), a third p-type layer 1308, a third tunnel junction layer 1309, and a fourth n-type layer 1310, which are stacked in this order.

[0071] The first light-emitting layer 130B is formed, for example, as a multiple quantum well. The thickness of the first light-emitting layer 130B is, for example, 50 nm. The first light-emitting layer 130B is configured to generate light having an emission wavelength corresponding to blue. The second light-emitting layer 130G is formed, for example, as a multiple quantum well. The thickness of the second light-emitting layer 130G is, for example, 50 nm. The second light-emitting layer 130G is configured to generate light having an emission wavelength corresponding to green. The third light-emitting layer 130R is formed, for example, as a multiple quantum well. The thickness of the third light-emitting layer 130R is, for example, 50 nm. The third light-emitting layer 130R is configured to generate light having an emission wavelength corresponding to red.

[0072] [Pixel configuration] 12, the monolithic LED 4 has pixels 170 defined by defining grooves 80. Each pixel 170 has a red LED 171R, a green LED 171G, and a blue LED 171B.

[0073] The partitioning grooves 80 are recessed from the upper surface of the fourth n-type layer 1310 toward the sapphire substrate 10 (in the stacking direction L), and their bottom surfaces reach the upper surface of the sapphire substrate 10. Each pixel 170 is formed in an island shape on the upper surface of the sapphire substrate 10 by the partitioning grooves 80.

[0074] The red LED 171R has a light-emitting body 172, a non-light-emitting portion 173, a p-side electrode 31p, and an n-side electrode 31n. The light-emitting body 172 exposes the upper surface of the fourth n-type layer 1310 (the uppermost surface of the epitaxial layer 130). The non-light-emitting portion 173 is adjacent to the light-emitting body 172 and aligned in one direction. The non-light-emitting portion 173 has the third light-emitting layer 130R through the fourth n-type layer 1310 removed, exposing the third n-type layer 1307. In the red LED 171R, a circuit that supplies electricity to the third light-emitting layer 130R is formed by the p-side electrode 31p provided on the p-side electrode formation surface 1310p of the fourth n-type layer 1310 and the n-side electrode 31n provided on the n-side electrode formation surface 1307n of the third n-type layer 1307.

[0075] The green LED 171G has a light-emitting body 174, a non-light-emitting portion 175, a p-side electrode 31p, and an n-side electrode 31n. The light-emitting body 174 has an exposed top surface of the third n-type layer 1307. The non-light-emitting portion 175 is adjacent to the light-emitting body 174 and aligned in one direction. The non-light-emitting portion 175 has the second light-emitting layer 130G through the fourth n-type layer 1310 removed, exposing the second n-type layer 1304. In the green LED 171G, the p-side electrode 31p is provided on a p-side electrode formation surface 1307p of the third n-type layer 1307. In the green LED 171G, the n-side electrode 31n is provided on an n-side electrode formation surface 1304n of the second n-type layer 1304.

[0076] 12, a height-adjusting electrode 32 is laminated on each of the p-electrode 31p and n-electrode 31n of the green LED 171G. The upper surface of the height-adjusting electrode 32 laminated on the p-electrode 31p of the green LED 171G is flush with the mounting surface 33p of the p-electrode 31p of the red LED 171R. The upper surface of the height-adjusting electrode 32 laminated on the n-electrode 31n of the green LED 171G is flush with the mounting surface 33n of the n-electrode 31n of the red LED 171R. In the green LED 171G, the p-electrode 31p, the n-electrode 31n, and the height-adjusting electrode 32 form a circuit that supplies electricity to the second light-emitting layer 130G.

[0077] The blue LED 171B has a light-emitting body 176, a non-light-emitting portion 177, a p-side electrode 31p, and an n-side electrode 31n. The light-emitting body 176 has an exposed top surface of the second n-type layer 1304. The non-light-emitting portion 177 is adjacent to the light-emitting body 176 and aligned in one direction. The non-light-emitting portion 177 has the first light-emitting layer 130B through the fourth n-type layer 1310 removed, exposing the first n-type layer 1301. In the blue LED 171B, the p-side electrode 31p is provided on a p-side electrode formation surface 1304p of the second n-type layer 1304. In the blue LED 171B, the n-side electrode 31n is provided on an n-side electrode formation surface 1301n of the first n-type layer 1301.

[0078] 12, two layers of height-adjusting electrodes 32 are laminated on each of the p-side electrode 31p and n-side electrode 31n of the blue LED 171B. The top surface of the height-adjusting electrode 32 laminated on the p-side electrode 31p of the blue LED 171B is flush with the mounting surface 33p of the p-side electrode 31p of the red LED 171R. The top surface of the height-adjusting electrode 32 laminated on the n-side electrode 31n of the blue LED 171B is flush with the mounting surface 33n of the n-side electrode 31n of the red LED 171R. In the blue LED 171B, the p-side electrode 31p, the n-side electrode 31n, and the height-adjusting electrode 32 form a circuit that supplies electricity to the first light-emitting layer 130B.

[0079] The first n-type layer 1301 (n-type semiconductor), the first light-emitting layer 130B, the first p-type layer 1302 (p-type semiconductor), the p-electrode 31p, and the n-electrode 31n are essential elements for the blue LED 171B (pixel 170) of the monolithic LED 4 configured as above to emit light as an LED. Also, the second n-type layer 1304 (n-type semiconductor), the second light-emitting layer 130G, the second p-type layer 1305 (p-type semiconductor), the p-electrode 31p, and the n-electrode 31n are essential elements for the green LED 171G (pixel 170) of the monolithic LED 4 to emit light as an LED. Furthermore, the third n-type layer 1307 (n-type semiconductor), the third light-emitting layer 130R, the third p-type layer 1308 (p-type semiconductor), the p-side electrode 31p, and the n-side electrode 31n in the red LED 171R (pixel 170) of the monolithic LED 4 are essential elements for the LED to emit light. In other words, the LED is configured as the pixel 170. The monolithic LED 4 has a configuration including multiple LEDs.

[0080] The thickness of the height-adjusting electrode 32 is the same as the etching depth for exposing the light-emitting body 174 of the green LED 171G from the light-emitting body 172 of the red LED 171R, and is the same as the etching depth for exposing the light-emitting body 176 of the blue LED 171B from the light-emitting body 174 of the green LED 171G. The height-adjusting electrode 32 increases the height of each of the p-side electrode 31p and n-side electrode 31n of the green LED 171G and the p-side electrode 31p and n-side electrode 31n of the blue LED 171B, thereby making the apparent heights of the p-side electrode 31p and n-side electrode 31n of the green LED 171G and the p-side electrode 31p and n-side electrode 31n of the blue LED 171B equal to the heights of the mounting surface 33p of the p-side electrode 31p and the mounting surface 33n of the n-side electrode 31n of the red LED 171R. That is, the monolithic LED 4 has a first light-emitting layer 130B, a second light-emitting layer 130G, and a third light-emitting layer 130R that emit light of different colors, and the apparent heights of the p-side electrodes 31p and the apparent heights of the n-side electrodes 31n provided on the blue LED 171B, the green LED 171G, and the red LED 171R are the same.

[0081] As shown in FIG. 13, the monolithic LED 4 and the multilayer wiring substrate 3 are configured such that the mounting surface 33p of the p-side electrode 31p of each pixel 170 is bonded to the mounting surface 97A of the anode-side bonding layer 95A, and the mounting surface 33n of the n-side electrode 31n is bonded to the mounting surface 97K of the cathode-side bonding layer 95K.

[0082] Example 4 In the LED device 1 of Example 1, the intermediate insulating layer 92 in the region where the first wiring layer 91 is not formed is laminated on the upper surface of the support substrate 90. In contrast, the multilayer wiring substrate 7 of the LED device 9 of Example 4 has a spacer layer 96 made of an insulating material in the region where the first wiring layer 91 is not formed. The intermediate insulating layer 92 in the region where the first wiring layer 91 is not formed is laminated on the upper surface of the support substrate 90 via the spacer layer 96. In Example 4, the same components as in Example 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0083] [Configuration of multilayer wiring board] The configuration of the multilayer wiring board 7 will be described with reference to Fig. 14. The upper part of Fig. 14 corresponds to Fig. 7(C), and the lower part of Fig. 14 corresponds to Fig. 7(D). The multilayer wiring board 7 has a support substrate 90, a spacer layer 96, a first wiring layer 91, an intermediate insulating layer 92, a second wiring layer 93, a height adjustment portion 93D, a front-side insulating layer 94, and a bonding layer 95.

[0084] The spacer layer 96 is laminated on the upper surface of the support substrate 90. The spacer layer 96 is formed of, for example, SiO2 or Al2O3. The spacer layer 96 is arranged on the upper surface of the support substrate 90 so as to cover the area not covered by the first wiring layer 91. The entire upper surface of the support substrate 90 is covered by the spacer layer 96 and the first wiring layer 91. The thickness of the spacer layer 96 is the same as the thickness of the first wiring layer 91.

[0085] The intermediate insulating layer 92 is laminated on the upper surface of the spacer layer 96 and the upper surface of the first wiring layer 91 .

[0086] [Manufacturing method for multilayer wiring boards] An example of a method for manufacturing the multilayer wiring board 3 will be described with reference to Fig. 15. The multilayer wiring board 3 is manufactured by performing a first step, a second step, a third step, a fourth step, and a fifth step. Example 4 differs from Example 1 in the first step.

[0087] First, in the first step, a spacer layer 96 is laminated over the entire upper surface of the support substrate 90 using a sputtering method (see FIG. 15(A)). Next, a resist mask is laminated over the upper surface of the spacer layer 96 except for the area where the opening 96A will be formed (not shown). Then, an ICP (inductively coupled plasma) method is used to form the opening 96A in the spacer layer 96, reaching the upper surface of the support substrate 90 (see FIG. 15(B)). Furthermore, using the resist mask laminated over the upper surface of the spacer layer 96, wiring 91A (first wiring layer 91) is laminated over the upper surface of the support substrate 90 exposed in the opening 96A by a vapor deposition method (see FIG. 15(C)). Then, the resist mask laminated over the upper surface of the spacer layer 96 is removed. This completes the first step.

[0088] Next, in a second step, an intermediate insulating layer 92 is deposited by sputtering on the upper surfaces of the spacer layer 96 and the first wiring layer 91. Then, a Ni mask (not shown) is deposited on the upper surface of the spacer layer 96 except for the area where the opening is to be formed. Then, an opening 92A is formed in the intermediate insulating layer 92 by ICP (inductively coupled plasma) (see FIG. 15(D)).

[0089] Next, in the third step, using a vapor deposition method, the wiring 93A of the second wiring layer 93 is laminated on the upper surface of the intermediate insulating layer 92, and the height adjustment portion 93D is laminated on the upper surface of the exposed wiring 91A in the opening 92A (see Figure 15(E)).

[0090] Next, in a fourth step, a front insulating layer 94 is laminated by sputtering on the upper surface of the intermediate insulating layer 92 and the upper surface of the wiring 93A of the second wiring layer 93. Then, through a process similar to the second step, openings 94A are formed so as to expose the upper surfaces of the height adjusting portions 93D and the upper surfaces of the wiring 93A (see FIG. 15(F)).

[0091] Next, in a fifth step, a bonding layer 95 is laminated on the upper surface of the height adjusting portion 93D exposed in the opening 94A and on the upper surface of the wiring 93A by electroplating (see FIG. 15(G)). In this way, the multilayer wiring substrate 7 is formed.

[0092] The multilayer wiring substrate 7 has a spacer layer 96 made of an insulating material in an area where the first wiring layer 91 is not formed. The intermediate insulating layer 92 in the area where the first wiring layer 91 is not formed is stacked on the upper surface of the support substrate 90 via the spacer layer 96. Therefore, the intermediate insulating layer 92 shown in FIG. 14 is less affected by the step caused by the first wiring layer 91, and in particular, when the upper surfaces of the first wiring layer 91 and the spacer layer 96 are at the same height, the intermediate insulating layer 92 is formed as a substantially flat layer.

[0093] In this way, the intermediate insulating layer 92, in which the influence of the step caused by the first wiring layer 91 is reduced, has more uniformity in the layer thickness around the end of the first wiring layer 91. This more reliably prevents the wiring 91A of the first wiring layer 91 from being exposed from the intermediate insulating layer 92. This also prevents short-circuiting between the wiring 91A of the first wiring layer 91 and the wiring 93A of the second wiring layer 93. Furthermore, the intermediate insulating layer 92, in which the influence of the step caused by the first wiring layer 91 is reduced, becomes closer to a flat layer. This means that the wiring 93A of the second wiring layer 93 formed on the intermediate insulating layer 92 has minimal unevenness in the vertical direction and a uniform thickness. This also makes it possible to keep the electrical resistance of the wiring 93A of the second wiring layer 93 low and stable.

[0094] 14 shows a case where the first wiring layer 91 and the spacer layer 96 have the same thickness, but it is sufficient if the effect of the step of the first wiring layer 91 can be reduced compared to when the spacer layer 96 is not present. In this case, the spacer layer 96 may be thicker than the first wiring layer 91. The depth of the opening 96A in the spacer layer 96 may not reach the support substrate 90. On the other hand, the spacer layer 96 may be thinner than the first wiring layer 91. The depth of the opening 96A may reach the support substrate 90, and a groove may also be formed in the support substrate 90. Furthermore, a groove may be formed in the support substrate 90, and the first wiring layer 91 may be formed in the groove, so that the spacer layer 96 surrounds the groove in the support substrate 90.

[0095] Although the description has been given of forming the opening 96A in the spacer layer 96 and then forming the first wiring layer 91 in the opening 96A, it is also possible to form the first wiring layer 91 and then form the spacer layer 96 around it.

[0096] Furthermore, a spacer layer may be provided around the second wiring layer 93 to flatten the front-side insulating layer 94. This increases the uniformity of the thickness of the front-side insulating layer 94, and more reliably prevents the wiring 93A of the second wiring layer 93 from being exposed to the surface of the front-side insulating layer 94. Furthermore, when the bonding portions are laminated by electrolytic plating, it is possible to prevent the bonding portion material from adhering to unnecessary portions.

[0097] When a spacer layer is provided around the second wiring layer 93, the intermediate insulating layer 92 is formed to be thick enough to accommodate the spacer layer, i.e., the thickness of the second wiring layer 93. Then, a groove is formed in the intermediate insulating layer 92 to the same thickness as the second wiring layer 93. Then, the second wiring layer 93 is formed in this groove.

[0098] When forming the grooves in the intermediate insulating layer 92, the external terminals 82 and the anode-side LED connection terminals 81 are not covered by the intermediate insulating layer 92, and the first wiring layer 91 is exposed. However, the etching rate of the first wiring layer 91 made of a metal such as Au, when using CF4 gas, for example, is significantly smaller than that of the intermediate insulating layer 92 made of SiO2 or the like. Therefore, the grooves in the intermediate insulating layer 92 can be formed without substantially damaging the first wiring layer 91. If the etching rate of the etching gas for the metal of the first wiring layer 91 is not sufficiently small, a metal layer with a sufficiently small etching rate may be added to the metal surface of the first wiring layer 91.

[0099] The present invention is not limited to the first to fourth embodiments described above with reference to the drawings, and the following embodiments are also included within the technical scope of the present invention. (1) In the LED devices of the above embodiments, after bonding the monolithic LED to the multilayer wiring substrate, the sapphire substrate serving as the LED substrate may be removed by a laser lift-off (LLO) method, a chemical lift-off method, or the like. In this case, instead of a monolithic LED, multiple LEDs are individually mounted on the multilayer wiring substrate. Multiple LEDs mounted on a multilayer wiring substrate can be easily achieved by batch mounting. (2) The LEDs may be configured without the tunnel junction layer and the second n-type layer, and a p-side electrode may be provided on the upper surface of the p-type layer. (3) In the multilayer wiring board, the wiring 91A of the first wiring layer 91 is the anode side and the wiring 93A of the second wiring layer 93 is the cathode side, but the reverse is also possible. Similarly, the p-side electrode and the n-side electrode of the multiple LEDs may also be reversed. (4) The openings in the intermediate insulating layer or the front insulating layer, or the grooves in the spacer layer may be formed by a lift-off method, in which the openings are formed when the resist mask is removed. Furthermore, the method is not limited to dry etching such as ICP, and wet etching may also be used. [Explanation of symbols]

[0100] 1,6,8,9:LED devices 2,4: Monolithic LED (multiple LEDs) 3,5,7: Multilayer wiring board 10: Sapphire substrate 30B: Light-emitting layer 33n: Mounting surface of n-side electrode 33p: Mounting surface of p-side electrode 31n:n side electrode 31p:p side electrode 32: Height adjustment electrode 70,170:pixels 90: Support substrate 91: First wiring layer 92,192: Intermediate insulating layer 92A, 192A: Opening 93: Second wiring layer 93D: Height adjustment part 95: Bonding layer 97K, 97A: Mounting surface of the bonding layer 96: Spacer layer 130B: First light-emitting layer (light-emitting layer) 130G: Second light-emitting layer (light-emitting layer) 130R: Third light-emitting layer (light-emitting layer) 301, 1301: First n-type layer (n-type semiconductor) 302: p-type layer (p-type semiconductor) 1301n, 1304n, 1307n: n-side electrode formation surface 1302: First p-type layer (p-type semiconductor) 1304: Second n-type layer (n-type semiconductor) 1304p, 1307p, 1310p: P side electrode formation surface 1305: Second p-type layer (p-type semiconductor) 1307: Third n-type layer (n-type semiconductor) 1308: Third p-type layer (p-type semiconductor)

Claims

1. An LED device in which a plurality of LEDs are mounted on a multilayer wiring substrate, The LED is a p-type semiconductor and an n-type semiconductor stacked together; a p-side electrode for supplying power to the p-type semiconductor; an n-side electrode for supplying power to the n-type semiconductor; the mounting surfaces of the p-side electrode and the n-side electrode are at different heights, The multilayer wiring board comprises: a first wiring layer connected to one of the n-side electrode and the p-side electrode; a second wiring layer connected to the other of the n-side electrode and the p-side electrode; an intermediate insulating layer that insulates the first wiring layer from the second wiring layer; the first wiring layer is disposed on a side of the intermediate insulating layer away from the LED, and is electrically connected to one of the p-side electrode and the n-side electrode through an opening formed in the intermediate insulating layer; the second wiring layer is disposed on the LED side with respect to the intermediate insulating layer and is electrically connected to the other of the p-side electrode and the n-side electrode; The height difference between the mounting surface of the p-side electrode and the mounting surface of the n-side electrode is an LED device having a height equal to the difference between the heights of the first wiring layer and the second wiring layer;

2. 2. The LED device according to claim 1, wherein the first wiring layer includes a height adjusting portion having the same thickness as the second wiring layer within the opening on the LED side.

3. 2. The LED device according to claim 1, wherein the multilayer wiring substrate has a spacer layer made of an insulating material in an area where the first wiring layer is not formed.

4. The plurality of LEDs have light-emitting layers that emit light of different colors, The LED device according to claim 1 , wherein the heights of the p-side electrodes and the heights of the n-side electrodes provided on the LEDs are the same.

5. A method for manufacturing an LED device including an LED and a multilayer wiring substrate that supplies power to the LED, comprising: The multilayer wiring board comprises: a first step of laminating a first wiring layer connected to one of an n-side electrode and a p-side electrode of the LED on a support substrate; a second step of laminating an intermediate insulating layer on the first wiring layer; a third step of laminating a second wiring layer connected to the other of the n-side electrode and the p-side electrode on the intermediate insulating layer, In the second step, an opening is formed in the intermediate insulating layer to expose a part of the first wiring layer, In the third step, when the second wiring layer is laminated, a height adjustment portion is simultaneously laminated on the exposed first wiring layer in the opening.

6. 6. The method for manufacturing an LED device according to claim 5, wherein the LED is a monolithic LED having a plurality of pixels formed on an LED substrate, and the LED substrate is then removed after bonding the LED to the multilayer wiring substrate.

Images