Hybrid pixel and hybrid sensor

Abstract

To provide a hybrid pixel and a hybrid sensor.SOLUTION: A hybrid pixel includes: a pixel circuit including at least one transfer transistor; a sensing circuit capable of sensing motion of an object; and at least one photodiode whose one end is connected to the pixel circuit and whose other end being connected to the sensing circuit. A semiconductor substrate of a first conductivity type in which a photoelectric conversion region corresponding to the photodiode is formed, includes a first region and a second region of a second conductivity type. The second region is physically separated from a second region of an adjacent hybrid pixel by a deep trench separation region, and the deep trench separation region is formed in the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a hybrid pixel and a hybrid sensor, and more particularly to a hybrid pixel and a hybrid sensor that can perform both the functions of an image sensor and a dynamic vision sensor. [Background technology]

[0002] An image sensor is a semiconductor device that converts externally incident optical signals into electrical signals and generates image information corresponding to the incident optical signals. Recently, with the development of the computer and communication industries, demand for image sensors has increased in various fields such as digital cameras, camcorders, mobile phones, security cameras, and medical micro cameras. Image sensors can generate images with high image quality, but they consume a lot of power.

[0003] When an event (e.g., a change in light intensity) occurs in a vision sensor, for example, a dynamic vision sensor, it generates information about the event, i.e., an event signal, and transmits the event signal to a processor. The vision sensor consumes little power because it outputs results only from pixels where a signal change occurs, but it only outputs information about the event.

[0004] Recently, there have been attempts to combine the image of an image sensor with the image of a dynamic vision sensor to achieve high image quality and a fast frame rate. However, when using part of the pixel area as a dynamic vision sensor, there is a problem that the signal-to-noise ratio (SNR) decreases due to a decrease in light intensity, making pixel design difficult. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems of the prior art, and an object of the present invention is to provide a hybrid sensor that can utilize both holes and electrons of a photodiode. [Means for solving the problem]

[0006] In order to achieve the above object, according to one aspect of the present invention, a hybrid pixel includes a pixel circuit including at least one transfer transistor, a sensing circuit capable of sensing the movement of an object, and at least one photodiode connected at one end to the pixel circuit and at the other end to the sensing circuit, wherein a semiconductor substrate of a first conductivity type in which a photoelectric conversion region corresponding to the photodiode is formed includes a first region of a second conductivity type and a second region surrounding the first region, and the second region is physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region, and the deep trench isolation region may be formed in the semiconductor substrate.

[0007] According to another aspect of the present invention, which has been made to achieve the above object, a hybrid pixel includes a pixel circuit including at least one transfer transistor, a sensing circuit capable of sensing the movement of an object, and at least one photodiode connected at one end to the pixel circuit and at the other end to the sensing circuit, wherein a semiconductor substrate of a first conductivity type in which a photoelectric conversion region corresponding to the photodiode is formed includes first and second regions of a second conductivity type, and the second region is physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region, and a first layer in which the pixel circuit and the at least one photodiode are formed and a second layer in which the sensing circuit is disposed may be different from each other.

[0008] According to one aspect of the present invention, there is provided a hybrid sensor including a pixel array including a plurality of hybrid pixels, each of which includes a photodiode, a pixel circuit connected to one end of the photodiode, and a sensing circuit connected to the other end of the photodiode, and further including a noise reduction circuit connected between the sensing circuit and the other end of the photodiode, and each of the plurality of hybrid pixels may be physically isolated from an adjacent hybrid pixel via a deep trench isolation region. [Effects of the Invention]

[0009] According to the present invention, the signal quality of the pixel signal can be improved, and a hybrid sensor can be realized without problems of light loss and pixel operation. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image processing device according to an exemplary embodiment of the present invention. [Figure 2] 1 is a block diagram illustrating a hybrid sensor according to an exemplary embodiment of the present invention. [Figure 3A] 1A and 1B are diagrams illustrating an example of a pixel array corresponding to a color filter array according to an exemplary embodiment of the present invention. [Figure 3B] 1A and 1B are diagrams illustrating an example of a pixel array corresponding to a color filter array according to an exemplary embodiment of the present invention. [Figure 3C] 1A and 1B are diagrams illustrating an example of a pixel array corresponding to a color filter array according to an exemplary embodiment of the present invention. [Figure 4A] FIG. 1 is a diagram illustrating a circuit diagram of a hybrid pixel according to an exemplary embodiment. [Figure 4B] FIG. 4B is a circuit diagram showing the hybrid pixel PXa of FIG. 4A. [Figure 5A] FIG. 4C is a cross-sectional view showing a layout region corresponding to region A in FIG. 4B. [Figure 5B] FIG. 5B is a diagram for explaining the flow of charges in the cross-sectional view of FIG. 5A. [Figure 6A] FIG. 1 is a circuit diagram illustrating a hybrid pixel according to an example embodiment. [Figure 6B] FIG. 6B is a layout plan view showing a partial configuration of the hybrid pixel shown in FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view taken along line AA' in FIG. 6B. [Figure 7] FIG. 1 is a circuit diagram illustrating a hybrid pixel according to an example embodiment. [Figure 8] FIG. 1 illustrates a stack structure of a hybrid sensor according to an exemplary embodiment. [Figure 9] FIG. 1 illustrates a stack structure of a hybrid sensor according to an exemplary embodiment. [Figure 10A] 1A and 1B illustrate stack structures of components of a hybrid pixel included in a hybrid sensor according to an exemplary embodiment of the present invention. [Figure 10B] 1A and 1B illustrate stack structures of components of a hybrid pixel included in a hybrid sensor according to an exemplary embodiment of the present invention. [Figure 11] 1 is a block diagram illustrating the structure of a hybrid pixel according to an exemplary embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating a hybrid pixel according to an example embodiment. [Figure 13] 13 is a timing chart for explaining turn-on timing of a transistor included in the noise removal circuit shown in FIG. 12. FIG. [Figure 14] 10 is a timing diagram for explaining turn-on timing of a transistor included in a noise removal circuit according to an exemplary embodiment. FIG. [Figure 15] 10 is a timing diagram for explaining turn-on timing of a transistor included in a noise removal circuit according to an exemplary embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Various embodiments of the present invention will now be described with reference to the drawings.

[0012] FIG. 1 is a block diagram illustrating an image processing device in accordance with an exemplary embodiment of the present invention.

[0013] Referring to FIG. 1 , the image processing device 10 includes a hybrid sensor 100 and a processor 300. The image processing device 10 according to the exemplary embodiment of the present invention may be installed in an electronic device having an image or optical sensing function. For example, the image processing device 10 may be installed in an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a navigation system, a drone, an Advanced Driver Assistance System (ADAS), etc. The image processing device 10 may also be installed as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring instruments, etc.

[0014] The hybrid sensor 100 is a sensor that can perform both a vision sensor function and an image sensor function. The vision sensor function is a function that detects changes in the intensity of incident light and outputs an event signal. The vision sensor function provided by the hybrid sensor 100 is a dynamic vision sensor function that outputs an event signal for a pixel where a change in light intensity is detected, i.e., a pixel where an event occurs. The change in light intensity is caused by the movement of an object photographed by the hybrid sensor 100 or by the movement of the hybrid sensor 100 or the image processing device 10 itself. The hybrid sensor 100 periodically or aperiodically transmits vision sensor data VDT including the event signal to the processor 300.

[0015] The image sensor function is to convert an optical signal from an object incident through an optical lens into an electrical signal and generate and output image data IDT based on the electrical signal. The hybrid sensor 100 includes a pixel array including a plurality of pixels arranged two-dimensionally and a readout circuit. The pixel array converts received optical signals into electrical signals. The pixel array may be implemented as a photoelectric conversion element such as a charge-coupled device (CCD) or a complementary metal oxide semiconductor (CMOS), but may also be implemented as various other types of photoelectric conversion elements. The readout circuit generates raw data based on the electrical signal provided from the pixel array and outputs the raw data or the raw data that has been preprocessed, such as by removing bad pixels, as image data IDT. The hybrid sensor 100 may be implemented as a semiconductor chip or package including the pixel array and the readout circuit.

[0016] According to the present invention, the hybrid sensor 100 performs both an image sensor function and a vision sensor function based on information (e.g., electrons and holes) obtained from at least one photodiode included in the hybrid pixel. The hybrid pixel included in the pixel array included in the hybrid sensor 100 includes at least one photodiode, a pixel circuit coupled to one end of the photodiode, and a sensing circuit coupled to the other end of the photodiode.

[0017] The processor 300 performs image processing on the image data IDT provided from the hybrid sensor 100. For example, the processor 300 performs image processing on the image data IDT to change the data format (e.g., converting Bayer pattern image data to YUV or RGB format) and image processing for improving image quality such as noise removal, brightness adjustment, and sharpness adjustment. The processor 300 processes the vision sensor data VDT received from the hybrid sensor 100 and detects object movement (or object movement on an image recognized by the image processing device 10) based on an event signal in the vision sensor data VDT.

[0018] In addition, the processor 300 matches the image frames included in the image data IDT provided from the hybrid sensor 100 with the vision sensor data VDT received from the hybrid sensor 100 using timestamp and synchronization signal information. The processor 300 may include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a dedicated microprocessor, a microprocessor, a general purpose processor, etc. In an embodiment, the processor 300 is an application processor or an image signal processor.

[0019] Meanwhile, the hybrid sensor 100 and the processor 300 may each be implemented as an integrated circuit (IC). For example, the hybrid sensor 100 and the processor 300 may be implemented on separate semiconductor chips. Alternatively, the hybrid sensor 100 and the processor 300 may be implemented as a single chip. For example, the hybrid sensor 100 and the processor 300 may be implemented as a system on chip (SoC).

[0020] The image processing device 10 controls an external device 400 to collect data. The image processing device 10 matches data collected from the device 400 using a timestamp. The device 400 may include an acceleration sensor, an inertial measurement unit (IMU), a gyro sensor, an infrared (IR) LED, a flashlight, and the like.

[0021] An accelerometer is a sensor that measures the acceleration and impact strength of a moving object, and processes the output signal to measure dynamic forces such as the object's acceleration, vibration, and impact. A gyro sensor is a sensor used to measure position and direction using the mechanical movement of a rotating object. An infrared (IR) LED is a device used in CCTV to capture images in dark places.

[0022] Inertial Measurement Units (IMUs) use a combination of accelerometers, gyroscopes, and sometimes magnetometers to act as orientation sensors in many consumer products, such as cell phones and cameras. Inertial Measurement Units operate by using one or more accelerometers to sense linear acceleration and one or more gyroscopes to sense rotational rate, and may also include a magnetometer. A typical configuration includes one accelerometer, one gyroscope, and one magnetometer per axis for the three axes of pitch, roll, and yaw.

[0023] FIG. 2 is a block diagram illustrating a hybrid sensor in accordance with an exemplary embodiment of the present invention.

[0024] The hybrid sensor 100 includes a pixel array 110, a row driver 120, a readout circuit 130, a ramp signal generator 140, a timing controller 150, an event detection circuit 160, and an interface circuit 170, and the readout circuit 130 includes an analog-to-digital conversion circuit 131 (hereinafter referred to as an ADC circuit) and a data bus 132.

[0025] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in a matrix. The plurality of pixels PX are hybrid pixels. According to one example, each of the plurality of pixels PX includes a pixel circuit for outputting an image signal and a sensing circuit for sensing whether an event has occurred. According to one example, the sensing circuit detects the movement of an object as an event and senses whether the movement has occurred. The pixel circuit and the sensing circuit included in each of the plurality of pixels PX share a photodiode included in each of the plurality of pixels PX. According to one example, the pixel circuit operates based on electrons in the photodiode, and the sensing circuit operates based on holes in the photodiode. Structures corresponding to the plurality of pixels PX will be described below with reference to FIG. 4A and subsequent figures.

[0026] Each pixel PX includes at least one photoelectric conversion element. The pixel PX senses light using the photoelectric conversion element and outputs an image signal, which is an electrical signal based on the sensed light. For example, the photoelectric conversion element is a light sensing element made of organic or inorganic material, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode (PIN photodiode). In one embodiment, each pixel PX may include multiple photoelectric conversion elements.

[0027] Meanwhile, a microlens (not shown) for collecting light is disposed above each pixel PX or above each pixel group consisting of adjacent pixels PX. Each of the plurality of pixels PX senses light in a specific spectral region from the light received through the microlens disposed thereover. For example, the pixel array 110 includes a red pixel (R) that converts light in the red spectral region into an electrical signal, a green pixel (G) that converts light in the green spectral region into an electrical signal, a blue pixel (B) that converts light in the blue spectral region into an electrical signal, and a white pixel (W) for noise reduction. A color filter array CF for transmitting light in a specific spectral region is disposed above each of the plurality of pixels PX. This will be described with reference to FIGS. 3A to 3C. However, the pixel array 110 is not limited thereto, and may include pixels that convert light in spectral regions other than red, green, and blue into electrical signals. According to one example, the pixels PX included in the pixel array 110 are RGBW pixels.

[0028] In each pixel PX, charges generated by a photoelectric conversion element such as a photodiode are accumulated in a floating diffusion node, and the charges accumulated in the floating diffusion node are converted into voltage. In this case, the ratio at which the charges accumulated in the floating diffusion node are converted into voltage is called the conversion gain. The conversion gain varies depending on the capacitance of the floating diffusion node.

[0029] The row driver 120 drives the pixel array 110 in units of row lines RL. The row driver 120 selects at least one row line RL from among the row lines RL constituting the pixel array 110. For example, the row driver 120 generates a selection signal to select one of the row lines RL. The pixel array 110 outputs a pixel signal from the row line RL selected by the selection signal. The pixel signal includes a reset signal and an image signal.

[0030] The row driver 120 generates control signals for controlling the pixel array 110. For example, the row driver 120 generates control signals for controlling the sensing circuits and transistors included in the pixel circuits included in the pixels PX. The row driver 120 independently provides the control signals for controlling the sensing circuits and transistors included in the pixel circuits included in the pixels PX. The row driver 120 provides the control signals to the plurality of pixels PX in response to timing control signals provided from the timing controller 150.

[0031] The timing controller 150 controls the timing of the row driver 120, the readout circuit 130, and the ramp signal generator 140. The timing controller 150 provides control signals for controlling the operation timing of each of the row driver 120, the readout circuit 130, and the ramp signal generator 140. The timing controller 150 adjusts the timing of a plurality of control line signals generated by the row driver 120 and determines the activation and deactivation timings of signals applied to the control lines. A specific timing control method of the timing controller 150 will be described later.

[0032] The ramp signal generator 140 generates a ramp signal RAMP that increases or decreases at a predetermined gradient, and provides the ramp signal RAMP to the ADC circuit 131 of the readout circuit 130 .

[0033] The readout circuit 130 reads out pixel signals from pixels PX on a row line RL selected by the row driver 120 among the plurality of pixels PX. The readout circuit 130 converts pixel signals received from the pixel array 110 via a plurality of column lines CL into digital data based on a ramp signal RAMP provided by a ramp signal generator 140, thereby generating and outputting pixel values ​​corresponding to the plurality of pixels PX on a row-by-row basis.

[0034] The ADC circuit 131 compares pixel signals received through each column line CL with a ramp signal RAMP and generates a pixel value, which is a digital signal, based on the comparison result. For example, it removes the reset signal from the image signal and generates a pixel value indicating the amount of light sensed by the pixel PX. The ADC circuit 131 samples and holds the pixel signal using a CDS (Correlated Double Sampling) method, double samples the level of a specific noise (e.g., a reset signal) and the level of the image signal, and generates a comparison signal based on the level corresponding to the difference. The ADC circuit 131 samples the provided pixel signal by first reading out the image signal and then reading out the reset signal using a DRS (Delta Reset Sampling) method.

[0035] The plurality of pixel values ​​generated by the ADC circuit 131 are output as image data IDT via a data bus 132. The image data IDT is provided to an image signal processor internal or external to the hybrid sensor 100.

[0036] The data bus 132 temporarily stores and then outputs the pixel values ​​output from the ADC circuit 131. The data bus 132 includes a plurality of column memories and a column decoder. The pixel values ​​stored in the plurality of column memories are output as image data IDT under the control of the column decoder.

[0037] According to an example, each of the plurality of pixels PX detects an event such as an increase or decrease in the intensity of received light. For example, each of the plurality of pixels PX is connected to the event detection circuit 160 via a column line extending in the column direction and a row line extending in the row direction. A signal indicating the occurrence of an event and polarity information of the event (i.e., whether it is an ON event where the intensity of light increases or an OFF event where the intensity of light decreases) are output from the pixel PX where the event occurred to the event detection circuit 160. In the present invention, the signal output from the pixel PX to the event detection circuit 160 is referred to as an event detection signal.

[0038] The event detection circuit 160 reads events, etc. from the pixel array 110 and processes the events, etc. The event detection circuit 160 generates event data EDT that includes polarity information of the event that occurred, the address of the pixel where the event occurred, and a timestamp. The event detection circuit 160 processes events, etc. that occurred in the pixel array 110 on a pixel-by-pixel basis, a pixel group including multiple pixels, a column-by-column basis, or a frame-by-frame basis.

[0039] The interface circuit 170 receives the event data EDT and the timestamp and transmits the vision sensor data VDT to the processor 300 according to a set protocol. The interface circuit 170 generates the vision sensor data VDT by packing the event data EDT and the timestamp in individual signal units, packets, or frames according to a set protocol, and transmits the vision sensor data VDT to the processor 300 (FIG. 1). For example, the interface circuit 170 includes one of an address event representation (AER) interface, a Mobile Industry Processor Interface (MIPI) interface, and a parallel interface.

[0040] According to the present invention, an image signal and an event detection signal are simultaneously output from the pixel PX included in the pixel array 110. That is, according to the present invention, the pixel PX included in the pixel array 110 is a hybrid pixel that can output both an image signal and an event detection signal. This allows desired image data to be synthesized, thereby increasing data utilization.

[0041] 3A to 3C are diagrams illustrating an example of a pixel array corresponding to a color filter array according to an exemplary embodiment of the present invention.

[0042] 3A, pixel array 110a includes a number of pixels arranged in a number of rows and columns. For example, a shared pixel, defined as a unit including pixels arranged in two rows and two columns, includes four sub-pixels. Pixel array 110a includes first through sixteenth shared pixels SP0 through SP15. Pixel array 110a further includes a color filter array CF so that shared pixels SP0 through SP15 sense various colors. For example, color filter array CF includes filters for sensing red (R), green (G), and blue (B), and each shared pixel SP0 through SP15 includes sub-pixels having the same color filter disposed thereon. For example, the first shared pixel SP0, the third shared pixel SP2, the ninth shared pixel SP8, and the eleventh shared pixel SP10 include subpixels with blue (B) color filters, the second shared pixel SP1, the fourth shared pixel SP3, the fifth shared pixel SP4, the seventh shared pixel SP6, the tenth shared pixel SP9, the twelfth shared pixel SP11, the thirteenth shared pixel SP12, and the fifteenth shared pixel SP14 include subpixels with green (G) color filters, and the sixth shared pixel SP5, the eighth shared pixel SP7, the fourteenth shared pixel SP13, and the sixteenth shared pixel SP15 include subpixels with red (R) color filters. In addition, the group including the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5, the group including the third shared pixel SP2, the fourth shared pixel SP3, the seventh shared pixel SP6, and the eighth shared pixel SP7, the group including the ninth shared pixel SP8, the tenth shared pixel SP9, the thirteenth shared pixel SP12, and the fourteenth shared pixel SP13, and the group including the eleventh shared pixel SP10, the twelfth shared pixel SP11, the fifteenth shared pixel SP14, and the sixteenth shared pixel SP15 are each arranged in the pixel array 110a to correspond to a Bayer pattern.According to one example, each of the group including the first shared pixel SP0, the second shared pixel SP1, the fifth shared pixel SP4, and the sixth shared pixel SP5, the group including the third shared pixel SP2, the fourth shared pixel SP3, the seventh shared pixel SP6, and the eighth shared pixel SP7, the group including the ninth shared pixel SP8, the tenth shared pixel SP9, the thirteenth shared pixel SP12, and the fourteenth shared pixel SP13, and the group including the eleventh shared pixel SP10, the twelfth shared pixel SP11, the fifteenth shared pixel SP14, and the sixteenth shared pixel SP15 corresponds to a block of the color filter array CF.

[0043] However, this is merely one embodiment, and the pixel array 110a according to the exemplary embodiment of the present invention may include various types of color filters. For example, the color filter array CF may include filters that sense not only red, green, and blue, but also yellow, cyan, magenta, and white. Furthermore, the pixel array 110a may include more shared pixels, and the arrangement of each of the shared pixels SP0 to SP15 may be embodied in various ways.

[0044] 3B , each of the shared pixels SP0, SP1, SP4, and SP5 includes nine subpixels. The first shared pixel SP0 includes nine subpixels with blue (B) color filters, and the second shared pixel SP1 and the fifth shared pixel SP4 each include nine subpixels with green (G) color filters. The sixth shared pixel SP5 includes nine subpixels with red (R) color filters. In some embodiments, the shared pixels SP0, SP1, SP4, and SP5 are referred to as nona cells.

[0045] 3C , each of the shared pixels SP0, SP1, SP4, and SP5 includes 16 subpixels. The first shared pixel SP0 includes 16 subpixels with blue (B) color filters, and the second shared pixel SP1 and the fifth shared pixel SP4 each include 16 subpixels with green (G) color filters. The sixth shared pixel SP5 includes 16 subpixels with red (R) color filters. In some embodiments, the shared pixels SP0, SP1, SP4, and SP5 are referred to as a hexadeca cell.

[0046] A shared pixel includes adjacent subpixels that have the same color filter. Although the shared pixels illustrated in Figures 3A to 3C are shown as examples including subpixels arranged in an N*N arrangement, the arrangement of the subpixels included in a shared pixel is not limited to N*N. N is a natural number greater than or equal to 2.

[0047] FIG. 4A is a circuit diagram illustrating a hybrid pixel according to an example embodiment.

[0048] 4A, the hybrid pixel PXa includes a photodiode 3000, a pixel circuit 1000 connected to one end of the photodiode, and a sensing circuit 2000 connected to the other end of the photodiode 3000. According to one example, the cathode of the photodiode 3000 is connected to the pixel circuit 1000, and the anode of the photodiode 3000 is connected to the sensing circuit 2000.

[0049] The pixel circuit 1000 generates a pixel signal having a voltage corresponding to the amount of charge generated by the photodiode 3000. The sensing circuit 2000 detects whether the change in the charge generated by the photodiode 3000 exceeds a predetermined threshold and generates an event detection signal. The pixel circuit 1000 included in the hybrid pixel PXa according to the present invention generates a pixel signal based on electrons generated by the photodiode 3000, and the sensing circuit 2000 generates an event detection signal based on holes generated by the photodiode 3000. Therefore, the pixel circuit 1000 uses a current based on electrons, and the sensing circuit 2000 uses a current based on holes. In this case, even if electrons accumulate in the photodiode 3000, a current based on holes continues to flow. Therefore, the pixel circuit 1000 maintains 4T operation, operates as a circuit separate from the sensing circuit 2000, and has various share structures. Furthermore, pixel signals generated from electrons have less noise than signals generated from holes, improving the signal quality of the pixel signal. Furthermore, since the sensing circuit 2000 uses hole current, a hybrid sensor can be realized without problems of light loss and pixel operation.

[0050] FIG. 4B is a circuit diagram illustrating an embodiment of the hybrid pixel PXa of FIG. 4A.

[0051] Referring to FIG. 4B, the hybrid pixel PXa includes a photodiode 3000a, a pixel circuit 1000a, and a sensing circuit 2000a. The pixel circuit 1000a includes a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX. A description of the operation of the pixel circuit 1000a will be omitted. Referring to FIG. 4B, one end of the transfer transistor TX included in the pixel circuit 1000a is connected to the cathode of the photodiode 3000a. The sensing circuit 2000a includes a transimpedance amplifier (TIA). According to one example, the transimpedance amplifier TIA amplifies a current value corresponding to holes output from the anode of the photodiode 3000a and outputs the amplified current value as a voltage. Although omitted for convenience of explanation, the sensing circuit 2000a may further include a comparator that compares the amplified hole current value with a reference value. According to an example, the sensing circuit 2000a is a circuit corresponding to a dynamic vision sensor for outputting an event detection signal, and the operation method of the sensing circuit 2000a will not be described here.

[0052] The circuit structures of the pixel circuit 1000a and the sensing circuit 2000a shown in FIG. 4B are merely examples, and the pixel circuit 1000a and the sensing circuit 2000a can be modified and applied in various ways as long as they perform the functions of a circuit structure that reads out a pixel signal and a circuit structure that compares the amount of charge change with a threshold and outputs it, respectively.

[0053] According to one example, the pixel circuit 1000a and the sensing circuit 2000a included in the hybrid pixel PXa share a photodiode 3000a, thereby performing both the image sensor function and the dynamic vision sensor function based on at least one photodiode included in one hybrid pixel PXa.

[0054] 5A is a cross-sectional view showing a layout region corresponding to region A in FIG. 4B. Referring to FIG. 5A, the hybrid pixel PXa includes a semiconductor substrate 2110, a photoelectric conversion region 2120, a vertical transmission gate VTG, a microlens 2130, a color filter 2140, deep trench isolation regions 2150 and 2160, and a contact region 2180.

[0055] The semiconductor substrate 2110 has a first surface SUF1 and a second surface SUF2 opposite to the first surface SUF1. The semiconductor substrate 2110 is doped with impurities of a first conductivity type (e.g., p-type) (e.g., boron (B)), and the floating diffusion region is doped with impurities of a second conductivity type (e.g., n-type) (e.g., phosphorus (P) or arsenic (As)). Although not shown, a p-type epitaxial layer is grown on the semiconductor substrate 2110, or a separate well region is formed, and a photoelectric conversion region 2120 and a vertical transmission gate VTG are formed on the p-type epitaxial layer and / or well region.

[0056] The photoelectric conversion region 2120 is formed in the semiconductor substrate 2110, and incident light reaches the photoelectric conversion region 2120 through the second surface SUF2 of the semiconductor substrate 2110. The photoelectric conversion region 2120 is a region corresponding to the photodiode 3000. The photoelectric conversion region 2120 generates charges (e.g., photocharges or holes) in a PN junction region through photoelectric conversion based on the incident light. The number of generated electrons increases as the brightness increases. The number of generated holes is the same as the number of electrons. According to one example, the photoelectric conversion region 2120 is a region formed by implanting a second conductivity type (e.g., n-type). The area and shape of the photoelectric conversion region 2120 are not limited to those illustrated in FIG. 5A.

[0057] 5A, the semiconductor substrate 2110 includes a first region 2120a and a second region 2120b. According to one example, the first region 2120a corresponds to the photoelectric conversion region 2120. According to one example, the second region 2120b is a region formed in the semiconductor substrate 2110 to surround the first region 2120a. According to one example, the second region 2120b is a remaining region of the semiconductor substrate 2110 excluding the region where the photoelectric conversion region 2120 is formed. According to one example, the second region 2120b is a region formed to allow hole movement between regions where holes are accumulated within the semiconductor substrate.

[0058] According to one example, the contact region 2180 is formed on the first surface SUF1 of the semiconductor substrate 2110. According to one example, the contact region 2180 is formed on the semiconductor substrate 2110 and forms a path for holes formed in the second region 2120b to travel along the contact region 2180 to the sensing circuit 2000b.

[0059] The vertical transmission gate VTG is formed on the first surface SUF1 of the substrate 2110. A portion of the vertical transmission gate VTG extends into the semiconductor substrate 2110 from the first surface SUF1 of the semiconductor substrate 2110 toward the photoelectric conversion region 2120. The vertical transmission gate VTG transfers electrons generated in the first region 2120a of the photoelectric conversion region 2120 to the floating diffusion region.

[0060] According to the present invention, electrons generated in the first region 2120a are transferred to the pixel circuit 1000a via the vertical transmission gate VTG, and holes generated in the second region 2120b are transferred to the sensing circuit 2000a through the contact region 2180.

[0061] The hybrid pixel PXa includes deep trench isolation (DTI) regions 2150, 2160. Depending on the embodiment, the deep trench isolation regions 2150, 2160 may extend from a first surface SUF1 of the semiconductor substrate 2110 to a depth spaced apart from the first surface SUF1, or may be formed completely through the semiconductor substrate 2110 from the first surface SUF1 to the second surface SUF2 of the semiconductor substrate 2110. The deep trench isolation regions 2150, 2160 contact the first surface SUF1 and / or the second surface SUF2 of the semiconductor substrate 2110. In one example, the contact surfaces of the deep trench isolation regions 2150, 2160 and the semiconductor substrate 2110 are not parallel. In one example, the deep trench isolation regions 2150, 2160 contact an STI region formed in the first surface SUF1 or the second surface SUF2 to form an isolation region. According to one example, the deep trench isolation regions 2150, 2160 are isolation regions formed by FDTI (Front Deep Trench Isolation). The deep trench isolation regions 2150, 2160 include an insulating layer and / or a conductive layer. For example, the deep trench isolation regions 2150, 2160 include a silicon oxide layer formed along the inner walls of the trench and a silicon layer filling the remainder of the trench. According to one example, the thickness of the deep trench isolation regions 2150, 2160 is not uniform.

[0062] According to the present invention, deep trench isolation regions 2150 and 2160 are formed to separate the first and second regions 2120a and 2120b of the hybrid pixel PXa from the first and second regions of the adjacent hybrid pixel PXa. According to the present invention, the first and second regions 2120a and 2120b are formed within the semiconductor substrate 2110, and a contact region 2180 is formed on the semiconductor substrate 2110. To ensure a complete hole transport path, the second region 2120b and its corresponding contact region 2180 must be completely isolated from the contact region of an adjacent pixel. To this end, the deep trench isolation regions 2150 and 2160 are formed on both sides of the first and second regions 2120a and 2120b to form individual pixels for the sensing circuit 2000a. According to the present invention, the sensing circuit 2000a is configured using hole currents separated for each hybrid pixel by the deep trench isolation regions 2150 and 2160.

[0063] The hybrid pixel PXa may further include a color filter CF and a microlens ML on the second surface SUF2 of the semiconductor substrate SUB. According to another example, instead of the color filter CF and / or the microlens ML, nanostructures are located on the second surface SUF2 of the semiconductor substrate SUB and serve to separate and / or guide light according to wavelength.

[0064] Fig. 5B is a diagram for explaining the flow of charges in the cross-sectional view of Fig. 5A, and Fig. 5B is a diagram for explaining the flow of charges from the first region 2120a and the second region 2120b included in the photoelectric conversion region 2120.

[0065] 5B, light L transmitted through microlens 2130 is transmitted to photoelectric conversion region 2120. Electrons (e-) generated in first region 2120a by light L flow toward vertical transmission gate VTG when a voltage is applied to vertical transmission gate VTG and are transmitted to the floating diffusion region of pixel circuit 1000a. Holes (h+) generated in second region 2120b by light L move through contact region 2180, and the hole current moved through contact region 2180 is transmitted to sensing circuit 2000a.

[0066] According to the exemplary embodiment of the present invention, electrons are used to generate pixel signals and holes are used to detect events, which results in a higher pixel signal level at the same brightness compared to the comparative embodiment where only electrons are used, improving the accuracy of event detection and improving image quality in low brightness environments.

[0067] FIG. 6A is a diagram illustrating a circuit diagram of a hybrid pixel according to an example embodiment.

[0068] 6A, the hybrid pixel PXb includes a pixel circuit 1000b, a sensing circuit 2000b, and a plurality of photodiodes 3000b. The pixel circuit 1000b, according to an example, includes first to fourth transfer transistors TX1, TX2, TX3, and TX4, a first floating diffusion node FD1, a source follower transistor SF1, a first selection transistor SX1, and first and second reset transistors RX1 and RX2. The operation of the pixel circuit 1000b is not a central focus of the present invention, and therefore will not be described here.

[0069] 6A, the plurality of photodiodes 3000b includes first to fourth photodiodes PD1, PD2, PD3, and PD4. Charges corresponding to light incident on the hybrid pixel PXb are accumulated through the first to fourth photodiodes PD1, PD2, PD3, and PD4. The amount of charge accumulated in the first to fourth photodiodes PD1, PD2, PD3, and PD4 is referred to as light amount data.

[0070] The pixel circuit 1000b is connected to the cathodes of the first to fourth photodiodes PD1, PD2, PD3, and PD4. The sensing circuit 2000b is connected to the anodes of the first to fourth photodiodes PD1, PD2, PD43, and PD4. According to one example, the pixel circuit 1000b and the sensing circuit 2000b share multiple photodiodes PD1, PD2, PD43, and PD4. While the embodiment of FIG. 6A illustrates an example in which the pixel circuit 1000b and the sensing circuit 2000b share four photodiodes, the present invention is not limited thereto, and the pixel circuit 1000b and the sensing circuit 2000b may share N photodiodes, where N is a natural number greater than or equal to 2. According to one example, the number of transfer transistors included in the pixel circuit 1000b is the same as the number of photodiodes 3000b connected to the pixel circuit 1000b. Referring to FIG. 6A, the number of transfer transistors included in the pixel circuit 1000b is four, and the number of photodiodes 3000b coupled to the pixel circuit 1000b is four.

[0071] Fig. 6B is a layout plan view showing a partial configuration of the hybrid pixel PXb of Fig. 6A, and Fig. 6C is a cross-sectional view taken along line AA' of Fig. 6B.

[0072] Referring to FIG. 6B, the four photodiodes PD1, PD2, PD3, and PD4 shown in FIG. 6A are provided as a 2x2 pixel structure symmetrical with respect to the center.

[0073] The hybrid pixel PXb in Figure 6B includes one semiconductor substrate 510, multiple photoelectric conversion regions 520, one floating diffusion region 530, four vertical transmission gates 540, a deep trench isolation region 560, a transistor 590, and a contact region 591. The hybrid pixel PXb in Figure 6B has a 4PD structure in which a central portion of the deep trench isolation region 560 is partially removed and the semiconductor substrate 510 is shared.

[0074] According to an example of FIG. 6B , the plurality of photoelectric conversion regions 520 include first regions 520a, 520b, 520c, and 520d. According to an example, the first regions 520a, 520b, 520c, and 520d are regions doped with a second conductivity type (e.g., n-type). Referring to FIG. 6B , the number of first regions 520a, 520b, 520c, and 520d corresponds to the number of photodiodes shared by the pixel circuit 1000b. Referring to FIG. 6B , the number of photodiodes shared by the pixel circuit 1000b is four, so the number of first regions 520a, 520b, 520c, and 520d is four. According to an example of FIG. 6B , the semiconductor substrate 510 includes a second region 520e surrounding the first regions 520a, 520b, 520c, and 520d. According to one example, a second region 520e is shown surrounding the first regions 520a, 520b, 520c, and 520d. A contact region 591 is also formed on the semiconductor substrate 510. According to one example, one contact region 591 corresponds to one second region 520e. That is, the number of second regions 520e and the number of contact regions 591 are the same. Referring to FIG. 6B, the first regions 520a, 520b, 520c, and 520d share the second region 520e and the contact region 591, so the number of contact regions and the number of second regions are the same as or less than the number of first regions. The contact region 591 may be formed at various positions on the top of the semiconductor substrate 510 within a range in contact with the second region 520e.

[0075] 6C , an embodiment is disclosed in which hybrid pixel PXb includes a semiconductor substrate 510, first regions 520c and 520d, a second region 520e, a contact region 591, a vertical transmission gate 540, a color filter 2140, a microlens 2130, and a deep trench isolation region 560. The descriptions of the semiconductor substrate 510, the vertical transmission gate 540, the color filter 2140, and the microlens 2130 correspond to the descriptions of the respective components described in FIG. 5A , and therefore, redundant descriptions will be omitted.

[0076] 6C, a second region 520e is formed surrounding the first regions 520c and 520d, and a contact region 591 is formed in the second region 520e, so that holes generated in the second region 520e are transferred to the sensing circuit. According to one example, the first regions 520c and 520d share the second region 520e.

[0077] According to the present invention, in the case of hybrid pixels sharing 4 PDs, one second region 520e is formed to surround the four first regions 520a, 520b, 520c, and 520d, and the four first regions 520a, 520b, 520c, and 520d share the second region 520e. It should be noted that, according to an example, in the case of hybrid pixels sharing 4 PDs, the four first regions 520a, 520b, 520c, and 520d are considered to be one pixel, and the deep trench isolation region 560 is formed to separate the hybrid pixels from adjacent hybrid pixels.

[0078] Compared to FIG. 5A, in FIG. 5A, when the first region 2120a and the second region 2120b included in the photoelectric conversion region 2120 correspond one-to-one, deep trench isolation regions 2150 and 2160 are formed to isolate the photoelectric conversion region 2120 from adjacent photoelectric conversion regions. In FIG. 6C, when the first regions 520a, 520b, 520c, and 520d and the second region 520e included in the photoelectric conversion region 520 do not correspond one-to-one, multiple first regions 520a, 520b, 520c, and 520d share one second region 520e. In this case, deep trench isolation region 560 is formed to isolate second region 520e from adjacent second regions. It should be noted that the deep trench isolation region is formed so that the second region of the photoelectric conversion region formed to have the same conductivity type as the substrate is completely isolated from the second region of the adjacent photoelectric conversion region.

[0079] FIG. 7 is a circuit diagram illustrating a hybrid pixel according to an example embodiment.

[0080] 7, the hybrid pixel PXc includes a photodiode 3000c, a pixel circuit 1000c connected to one end of the photodiode, and a sensing circuit 2000c connected to the other end of the photodiode 3000c. According to one example, the anode of the photodiode 3000c is connected to the pixel circuit 1000c, and the cathode of the photodiode 3000c is connected to the sensing circuit 2000c.

[0081] The pixel circuit 1000c generates a pixel signal having a voltage corresponding to the amount of charge generated by the photodiode 3000c. The sensing circuit 2000c detects whether the change in the amount of charge generated by the photodiode 3000c exceeds a predetermined threshold and generates an event detection signal. The pixel circuit 1000c included in the hybrid pixel PXc according to the present invention generates a pixel signal based on holes generated by the photodiode 3000c, and the sensing circuit 2000c generates an event detection signal based on electrons generated by the photodiode 3000c. Therefore, the pixel circuit 1000c uses a current based on holes, and the sensing circuit 2000c uses a current based on electrons. Even in such a case, the pixel circuit 1000c can operate as a circuit separate from the sensing circuit 2000c.

[0082] It should be noted that the embodiments of the present invention that are applicable to a pixel circuit using electrons and a sensing circuit using holes also apply to a pixel circuit using holes and a sensing circuit using electrons as shown in FIG.

[0083] FIG. 8 illustrates a stack structure of a hybrid sensor according to an exemplary embodiment.

[0084] 8, the hybrid sensor 1 includes an upper chip 40 and a lower chip 50. The upper chip 40 includes a sensing area SA in which some circuits of a plurality of pixels PX are provided, and a pad area PA1 around the sensing area SA. A plurality of upper pads PAD are arranged in the chip pad area PA1, and the plurality of upper pads PAD are connected to elements provided on the lower chip 50 through vias or the like.

[0085] The lower chip 50 includes a circuit region LC, in which peripheral circuits of the pixel array, such as a row driver 120, a readout circuit 130, a ramp signal generator 140, a timing controller 150, and an event detection circuit 160, are formed. According to an example, sensing circuits included in a plurality of pixels PX are formed in the circuit region LC. This will be described with reference to FIGS. 10A and 10B . In an embodiment, the lower chip 50 includes a memory region and a dummy region. The lower chip 50 includes a pad region PA2 around the circuit region LC. Memory devices, such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, are arranged in the memory region. However, the memory devices arranged in the memory region are not limited to DRAM devices or SRAM devices. The dummy region does not store data but serves to support the upper chip 40.

[0086] FIG. 9 is a diagram illustrating a stack structure of a hybrid sensor according to an exemplary embodiment.

[0087] 9, the hybrid sensor 2 includes multiple stacked chips. For example, a pixel array is formed on the top chip 40 and the middle chip 51, and peripheral circuits or memory for the pixel array are formed on the bottom chip 60. According to one example, multiple photodiodes and pixel circuits included in the hybrid pixel and corresponding wiring are formed on the top chip 40, and a sensing circuit and corresponding wiring are formed on the middle chip 51.

[0088] The lower chip 60 includes a circuit region LC, in which peripheral circuits of a pixel array are formed. In an embodiment, the lower chip 60 includes a memory region and a dummy region.

[0089] In an embodiment, the top chip 40 and the middle chip 51 are stacked together at wafer level, and the bottom chip 60 is attached to the bottom of the middle chip 51 at chip level.

[0090] FIG. 10A is a diagram illustrating a stack structure of components of a hybrid pixel included in a hybrid sensor according to an exemplary embodiment of the present invention.

[0091] For convenience of explanation, an embodiment is shown in which the photodiodes PD1, PD2, PD3, and PD4 included in one hybrid pixel 11 and the wiring structure of the pixel circuit and the sensing circuit are applied to a stack structure.

[0092] 10A, the hybrid pixel 11 includes an upper chip 41 and a lower chip 42. The upper chip 41 includes a first region 41a in which photodiodes PD1, PD2, PD3, and PD4 are formed, and a second region 41b in which pixel circuits and corresponding wiring are formed below the first region 41a. The lower chip 42 includes a sensing circuit and corresponding wiring. An objective lens 46 for applying light to the photodiodes PD1, PD2, PD3, and PD4 included in the upper chip 41 is disposed in an upper region of the upper chip 41.

[0093] According to one example, the top chip 41 of the hybrid pixel 11 corresponds to the top chip 40 in Figure 8, and the bottom chip 42 of the hybrid pixel 11 corresponds to the bottom chip 50 in Figure 8. According to one example, the top chip 41 of the hybrid pixel 11 corresponds to the top chip 40 in Figure 9, and the bottom chip 42 of the hybrid pixel 11 corresponds to the middle chip 51 in Figure 9.

[0094] According to one example, the pixel circuit uses electrons and includes an NMOS transistor, and the sensing circuit includes both an NMOS transistor and a PMOS transistor. Therefore, in the case of a sensing circuit including both an NMOS transistor and a PMOS transistor, an efficient stack structure can be formed by forming the sensing circuit in a layer separate from the pixel circuit and the photodiode.

[0095] According to one example, the photodiodes PD1, PD2, PD3, and PD4 are shared with one another, which corresponds to one hybrid pixel. According to one example, the hybrid pixel 11 including the photodiodes PD1, PD2, PD3, and PD4 is isolated from adjacent hybrid pixels by a deep trench isolation region 41c. According to one example, the deep trench isolation region 41c is formed to correspond to the depth of the first region 41a in which the photodiodes PD1, PD2, PD3, and PD4 are formed. Referring to FIG. 10A , the deep trench isolation region 41c is formed only in one region to the right of the first region 41a in which the photodiodes PD1, PD2, PD3, and PD4 are formed. However, this is for convenience of explanation, and it should be noted that the deep trench isolation region 41c is formed to surround all four sides of the first region 41a in which the photodiodes PD1, PD2, PD3, and PD4 are formed. According to the present invention, individual sensing pixels corresponding to each sensing circuit can be formed by using deep trench isolation regions 41c that physically separate adjacent hybrid pixels.

[0096] Although not shown in Fig. 10A, the photodiodes PD1, PD2, PD3, and PD4 each include a first region and a second region, and the photodiodes PD1, PD2, PD3, and PD4 share the second region. The description of this corresponds to the description of Figs. 6A to 6C, so further description will be omitted.

[0097] According to one example, the upper chip 41 and the lower chip 42 are electrically connected via a vertical region 45. The vertical region 45 extends in the Z-axis direction and is in contact with each of the upper chip 41 and the lower chip 42. According to one example, the vertical region 45 is a via for connecting charges generated in the photodiodes PD1, PD2, PD3, and PD4 to a sensing circuit. According to one example, the vertical region 45 is a TSV (Through Silicon Via) or C2C (Chip to Chip) for connecting charges of the photodiodes PD1, PD2, PD3, and PD4 to the sensing circuit.

[0098] FIG. 10B is a diagram illustrating a stack structure of components of a hybrid pixel included in a hybrid sensor according to an exemplary embodiment of the present invention.

[0099] For convenience of explanation, an embodiment is illustrated in which the photodiodes included in multiple hybrid pixels and the wiring structures of the pixel circuits and sensing circuits are applied to a stack structure. According to one example, the upper chip 61 of the hybrid pixel 21 corresponds to the upper chip 40 in FIG. 8, and the lower chip 62 of the hybrid pixel 21 corresponds to the lower chip 50 in FIG. 8. According to one example, the upper chip 61 of the hybrid pixel 21 corresponds to the upper chip 40 in FIG. 9, and the lower chip 62 of the hybrid pixel 21 corresponds to the middle chip 51 in FIG. 9.

[0100] 10B, the hybrid pixel 21 includes an upper chip 61 and a lower chip 62. The upper chip 61 includes a first region 61a in which photodiodes PD1, PD2, PD3, and PD4 are formed, and a second region 61b in which pixel circuits and corresponding wiring are formed below the first region 61a. The lower chip 62 includes a sensing circuit and corresponding wiring. An objective lens 66 for applying light to the photodiodes PD1, PD2, PD3, and PD4 included in the upper chip 61 is disposed in an upper region of the upper chip 61.

[0101] 10B illustrates a stack structure in which 16 hybrid pixels 11 are arranged, as shown in FIG. 10A. Region B in FIG. 10B corresponds to first and second regions 41a and 41b formed in the upper chip 41 in FIG. 10A, and therefore, a description thereof will be omitted.

[0102] 10B, the plurality of hybrid pixels are physically separated by deep trench isolation regions 61c. In the embodiments of FIGS. 10A and 10B, a hybrid pixel refers to a pixel corresponding to a single unit that shares a plurality of photodiodes PD1, PD2, PD3, and PD4. According to one example, the deep trench isolation region 61c is formed to correspond to the depth of the first region 61a in which the plurality of photodiodes PD1, PD2, PD3, and PD4 are formed. While FIG. 10B illustrates an embodiment in which the deep trench isolation region 61c is formed only between the four hybrid pixels in front of the first region 61a in which the photodiodes PD1, PD2, PD3, and PD4 are formed, this is for convenience of explanation. It should be noted that the deep trench isolation region 61c is formed to surround each hybrid pixel that shares the photodiodes PD1, PD2, PD3, and PD4 to prevent crosstalk with adjacent hybrid pixels.

[0103] Although not shown in Fig. 10B, the photodiodes PD1, PD2, PD3, and PD4 each include a first region and a second region, and the photodiodes PD1, PD2, PD3, and PD4 share the second region. The description of this corresponds to the description of Figs. 6A to 6C, so further description will be omitted.

[0104] 10B, the upper chip 61 and the lower chip 62 are electrically connected via a vertical region 65. The vertical region 65 extends in the Z-axis direction and contacts the upper chip 61 and the lower chip 62, respectively. In one example, the vertical region 65 is a via for connecting the charges of the photodiodes PD1, PD2, PD3, and PD4 to a sensing circuit. In one example, the vertical region 65 is a TSV or C2C for connecting the charges of the photodiodes PD1, PD2, PD3, and PD4 to the sensing circuit.

[0105] Referring to FIG. 10B, instead of forming only one vertical region 45 for connecting the pixel circuit and the sensing circuit included in one hybrid pixel as in FIG. 10A, a vertical region 65 for connecting holes of multiple hybrid pixels to one sensing circuit is included.

[0106] 10B, the hybrid pixel includes a plurality of first vertical regions 65b vertically connected to the outputs of the respective hybrid pixels to connect the outputs of the photodiodes included in the respective hybrid pixels, a plurality of first planar regions 65c connecting the plurality of first vertical regions 65b on the XY plane, and at least one second vertical region 65a connecting the plurality of first vertical regions 65b and the plurality of second planar regions 65c to a sensing circuit. According to one example, the plurality of first vertical regions 65b are vertical regions for connecting charges corresponding to the contact regions included in each hybrid pixel.

[0107] 10B, although only one second vertical region 65a is shown, it should be noted that this is merely an example and that multiple second vertical regions 65a may be included. Referring to FIG. 10B, contact regions separated by deep trench isolation regions in the upper chip 61 are combined into one wiring via wiring such as metal or polysilicon included in the vertical region 65 and connected to one sensing circuit.

[0108] Referring to the embodiment of Figure 10B, by combining the outputs of 16 hybrid pixels and performing event detection in the sensing circuit, it is possible to connect 16 times the signals, thereby facilitating operation in low light. According to another embodiment, to ensure the area and sensitivity of the sensing circuit, the hole signal outputs of multiple hybrid pixels are connected as shown in Figure 10B. According to another embodiment, if color information is not required in the sensing circuit, wiring can be formed by connecting the hole signals of photodiodes corresponding to RGB.

[0109] FIG. 11 is a block diagram illustrating the structure of a hybrid pixel according to an exemplary embodiment of the present invention.

[0110] Referring to FIG. 11, hybrid pixel PXd includes a photodiode 3000d, a pixel circuit 1000d, a sensing circuit 2000d, and a noise reduction circuit 4000d. In the description of FIG. 11, parts that overlap with the description of FIG. 4A will be omitted. According to one example, in the case of a sensing circuit 2000d using holes, noise due to TIA occurs, and if the noise fluctuates the ground level, it affects the SNR of the pixel signal. Referring to FIG. 11, noise reduction circuit 4000d is connected between the photodiode 3000d and the sensing circuit 2000d. The noise reduction circuit 4000d is connected between the anode of the photodiode 3000d and the sensing circuit 2000d. The noise reduction circuit 4000d includes a plurality of transistors and reduces noise due to the sensing circuit 2000d by controlling the on / off of the plurality of transistors.

[0111] FIG. 12 is a diagram illustrating a circuit diagram of a hybrid pixel according to an example embodiment.

[0112] 12, the hybrid pixel PXe includes a pixel circuit 1000e, a sensing circuit 2000e, a photodiode 3000e, and a noise reduction circuit 4000e. The pixel circuit 1000e includes a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX. The structure of the sensing circuit 2000e corresponds to the structure of the sensing circuit 2000 shown in FIG. 4A. According to one example, the descriptions of the pixel circuit 1000e, the sensing circuit 2000e, and the photodiode 3000e correspond to the descriptions of the pixel circuit, the sensing circuit, and the photodiode described with reference to FIGS. 4A to 10B, and therefore, redundant description will be omitted.

[0113] The noise elimination circuit 4000e includes a first transistor NRB and a second transistor NR. According to one example, the first transistor NRB is connected between the anode of the photodiode 3000e and the sensing circuit 2000e. The second transistor NR is connected between the anode of the photodiode 3000e and ground. According to one example, the first transistor NRB and the second transistor NR are connected in parallel. The noise elimination circuit 4000e forms a circuit that connects or disconnects the sensing circuit 2000e using the first transistor NRB and the second transistor NR. According to one example, the first transistor NRB of the noise elimination circuit 4000e controls the connection between the contact region of the photodiode 3000e and the sensing circuit 2000e, and the second transistor NR controls the connection between the contact region of the photodiode 3000e and ground or a specific other voltage.

[0114] When the first transistor NRB is turned on and the second transistor NR is turned off, the photodiode 3000e and the sensing circuit 2000e are connected. In this case, holes generated in the photodiode 3000e are transferred to the sensing circuit 2000e. When the first transistor NRB is turned off and the second transistor NR is turned on, the photodiode 3000e is connected to ground, and holes generated in the photodiode 3000e flow to ground, thereby discharging hole current. In this way, the connection between the sensing circuit 2000e and the photodiode 3000e is adjusted by controlling the turn-on and turn-off of the first transistor NRB and the second transistor NR.

[0115] FIG. 13 is a timing chart for explaining the turn-on timing of the transistors included in the noise removal circuit shown in FIG.

[0116] FIG. 13 shows a timing diagram of a selection control signal SEL applied to the selection transistor SX, a reset control signal RG applied to the reset transistor RX, a transmission control signal TG applied to the transmission transistor TX, a first control signal NRBS applied to the first transistor NRB, and a second control signal NRS applied to the second transistor NR.

[0117] 13, each section corresponding to one frame is illustrated. During one frame FRM, a reset time RST, an exposure time IT, a readout time RO, and a non-integration time (NIT) are assigned to each of multiple rows. The reset time RST corresponding to the section from t1 to t3, the exposure time IT corresponding to the section from t3 to t4, the readout time RO corresponding to the section from t4 to t6, and the non-integration time NIT corresponding to the section from t6 to t7 are illustrated.

[0118] The pixel is reset at a reset time RST corresponding to the period from t1 to t3. At time t2, the transfer transistor TX included in the pixel is turned on and transfers the charge generated in the photodiode to the floating diffusion node during the non-integration time NIT, thereby removing the charge. During the reset time RST, the reset control signal RG applied to the reset transistor RX is maintained at the second level, and the transfer transistor of the pixel is turned on with a reset voltage applied to the floating diffusion node, so both the floating diffusion node and the pixel are reset.

[0119] During exposure time IT, which corresponds to the period from t3 to t4, charges are generated and accumulated in the photodiode of the pixel due to an optical signal. The pixel is read out during readout time RO, which corresponds to the period from t4 to t6. At time t5, the transfer transistor TX included in the pixel is turned on, and during exposure time IT, the charges accumulated in the photodiode are transferred to the floating diffusion node, and a pixel voltage corresponding to the transferred charges is output via the column line (CL in FIG. 1). During readout time RO before time t5, signal sampling corresponding to the reset voltage (Reset Sampling) is performed, and during readout time RO after time t5, signal sampling corresponding to the image voltage (Signal Sampling) is performed. At t4, which is the start of readout time RO, the selection control signal SEL applied to the selection transistor SX transitions from a first level to a second level, and the reset control signal RG applied to the reset transistor RX transitions from a second level to a first level. At time t6, which is the end point of the read time R0, the selection control signal SEL applied to the selection transistor SX transitions from the second level to the first level, and the reset control signal RG applied to the reset transistor RX transitions from the first level to the second level. In the present invention, the first level is a low level, and the second level is a high level.

[0120] According to one example, during the reset time RST, the exposure time IT, and the non-integration time NIT, the second control signal NRS applied to the second transistor NR is maintained at a first level, and during the readout time RO, the second control signal NRS is maintained at a second level. According to one example, during the reset time RST, the exposure time IT, and the non-integration time NIT, the first control signal NRBS applied to the first transistor NRB is maintained at a second level, and during the readout time RO, the first control signal NRBS is maintained at a first level. According to one example, at time t4, which is the start of the readout time RO, the second control signal NRS transitions from the first level to the second level, and the first control signal NRBS transitions from the second level to the first level. According to one example, at time t6, which is the end of the readout time RO, the second control signal NRS transitions from the second level to the first level, and the first control signal NRBS transitions from the first level to the second level. According to one example, the first transistor NRB and the second transistor NR are complementary: when the first transistor NRB is turned on, the second transistor NR is turned off, and when the first transistor NRB is turned off, the second transistor NR is turned on.

[0121] According to one example, the first control signal NRBS applied to the first transistor NRB transitions from the second level to the first level before the CDS sampling time ST and transitions from the first level to the second level after the CDS sampling time ST. According to one example, the second control signal NRS applied to the second transistor NR transitions from the first level to the second level before the CDS sampling time ST and transitions from the second level to the first level after the CDS sampling time ST. The CDS sampling time ST is a section included in the read time R0.

[0122] That is, during the read time R0, the first transistor NRB is turned off and the second transistor NR is turned on, blocking the path connected to the sensing circuit 2000e during the read time R0 and blocking noise generated by the sensing circuit 2000e during the read time R0. According to one example, since the read time R0 is the period most vulnerable to noise, the signal applied to the transistor included in the noise removal circuit 4000e according to the present invention is controlled to remove noise.

[0123] 14 and 15 are timing diagrams illustrating the turn-on timing of transistors included in the noise removal circuit according to an exemplary embodiment. In the descriptions of FIGS. 14 and 15, descriptions that overlap with the description of FIG. 13 will be omitted.

[0124] 14, during a reset time RST corresponding to a period from t1 to t3, the second control signal NRS applied to the second transistor NR is maintained at a second level, and the first control signal NRBS applied to the first transistor NRB is maintained at a first level. According to one example, at time t1, which is the start of the reset time RST, the second control signal NRS transitions from the first level to the second level, and the first control signal NRBS transitions from the second level to the first level. According to one example, at time t3, which is the end of the reset time RST, the second control signal NRS transitions from the second level to the first level, and the first control signal NRBS transitions from the first level to the second level.

[0125] Referring to the embodiment of Figure 14, during the reset time RST corresponding to the period from t1 to t3, the second transistor NR is turned on and the first transistor NRB is turned off, thereby preventing the influence of noise generated by the sensing circuit 2000e even during the reset operation period.

[0126] 13 and 14 illustrate an embodiment in which the second transistor NR is turned on and the first transistor NRB is turned off during the entire duration of the reset time RST and / or the read time R0, but the present invention is not limited thereto, and the second transistor NR may be turned on and the first transistor NRB may be turned off during a time period corresponding to 90% or more of the entire duration of the reset time RST and / or the read time R0. According to one example, the second transistor NR is turned off and the first transistor NRB is turned on during a portion of the reset time RST and / or the read time R0. According to one example, during the reset time RST, before the transition point (time t2) of the transmission control signal TG applied to the transmission transistor TX from the first level to the second level, the second control signal NRS may transition from the first level to the second level so that the first control signal NRBS transitions from the second level to the first level, and after the transition point (time t2) of the transmission control signal TG applied to the transmission transistor TX from the second level to the first level, the second control signal NRS may transition from the second level to the first level so that the first control signal NRBS transitions from the first level to the second level.

[0127] 15, the first control signal NRBS maintains a first level during a portion of the exposure time IT and the non-integration time NIT, and the second control signal NRS maintains a second level during a portion of the exposure time IT and the non-integration time NIT. According to one example, the second transistor NR is turned on and the first transistor NRB is turned off during a portion of the exposure time IT and the non-integration time NIT, which correspond to the portions before and after the readout time of the photodiode. This intermittently removes noise that occurs during periods other than the reset time RST and the readout time R0.

[0128] In the timing diagrams of Figures 13 to 15, the multiple control signals SEL, RG, TG, NRS, and NRBS described in the timing diagrams are generated by the row driver 120 of Figure 2, and the timing control of the multiple control signals SEL, RG, TG, NRS, and NRBS described in the timing diagrams is controlled by the timing controller 150 of Figure 2.

[0129] The drawings and the specification have disclosed exemplary embodiments. Although specific terms have been used to describe the embodiments in this specification, these terms are used merely to describe the technical idea of ​​the present invention and are not used to limit the meaning or technical scope of the present invention. Therefore, a person skilled in the art will understand that various modifications and equivalent embodiments are possible. [Explanation of symbols]

[0130] 10 Image Processing Device 100 Hybrid Sensor 110 pixel array 120 Row Driver 130 Readout circuit 140 Ramp Signal Generator 150 Timing Controller 160 Event detection circuit 170 Interface Circuit 300 processors 400 devices 510, 2110 Semiconductor substrate 520, 2120 Photoelectric conversion area 530 Floating Diffusion Area 540 Vertical Transmission Gate 560, 2150, 2160 Deep trench isolation region 590 transistors 591, 2180 Contact area 2130 Microlens 2140 Color Filter IDT Image Data VDT vision sensor data

Claims

1. a semiconductor substrate; a pixel circuit including at least one transfer transistor; a sensing circuit capable of sensing the movement of an object; at least one photodiode, one end of which is connected to the pixel circuit and the other end of which is connected to the sensing circuit; the semiconductor substrate has a first conductivity type, the semiconductor substrate includes a photoelectric conversion region corresponding to the at least one photodiode, and the semiconductor substrate includes a first region of a second conductivity type and a second region surrounding the first region; the second region is physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region; The semiconductor substrate includes the deep trench isolation region.

2. The hybrid pixel of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

3. The hybrid pixel of claim 1 , wherein the deep trench isolation region is a front deep trench isolation (FDTI).

4. The hybrid pixel of claim 1 , wherein the number of the photodiodes is equal to the number of the transfer transistors.

5. the number of the first regions corresponds to the number of the photodiodes; The hybrid pixel of claim 4 , wherein the number of the second regions is equal to or less than the number of the first regions.

6. the pixel circuit is coupled to the cathode of the at least one photodiode; The hybrid pixel of claim 1 , wherein the sensing circuit is coupled to an anode of the at least one photodiode.

7. the pixel circuit is coupled to the anode of the at least one photodiode; The hybrid pixel of claim 1 , wherein the sensing circuit is coupled to the cathode of the at least one photodiode.

8. a semiconductor substrate; a pixel circuit including at least one transfer transistor; a sensing circuit capable of sensing the movement of an object; at least one photodiode, one end of which is connected to the pixel circuit and the other end of which is connected to the sensing circuit; the semiconductor substrate has a first conductivity type, the semiconductor substrate includes a photoelectric conversion region corresponding to the at least one photodiode, and the semiconductor substrate includes a first region of a second conductivity type and a second region surrounding the first region; the second region is physically separated from the second region of an adjacent hybrid pixel by a deep trench isolation region; A hybrid pixel, wherein a first layer including the pixel circuit and the at least one photodiode and a second layer including the sensing circuit are different from each other.

9. the first layer is a layer on top of the second layer; The hybrid pixel of claim 8 , further comprising a vertical region for electrically connecting the first layer and the second layer.

10. The vertical region is 10. The hybrid pixel according to claim 9, wherein the hybrid pixel is a TSV (Through Silicon Via) or a C2C (Chip to Chip).

11. The vertical region is a plurality of first vertical regions electrically connecting regions corresponding to the plurality of second regions of the first layer, respectively; a planar region for connecting the plurality of first vertical regions on a plane; The hybrid pixel of claim 9 , further comprising: a second vertical region for connecting the plurality of first vertical regions and the planar region to the sensing circuit.

12. The hybrid pixel of claim 9 , wherein the deep trench isolation region is a front deep trench isolation (FDTI).

13. a pixel array including a plurality of hybrid pixels; The plurality of hybrid pixels are A photodiode; a pixel circuit connected to one end of the photodiode; a sensing circuit connected to the other end of the photodiode; a noise reduction circuit connected between the sensing circuit and the other end of the photodiode; A hybrid sensor, wherein each of the plurality of hybrid pixels is physically isolated from adjacent hybrid pixels via a deep trench isolation region.

14. The noise removal circuit includes: a first transistor connected between the other end of the photodiode and the sensing circuit; The hybrid sensor of claim 13 , further comprising: a second transistor coupled between the other end of the photodiode and ground.

15. The hybrid sensor comprises: a row driver that generates signals to be applied to the pixel array; a timing controller for controlling the timing of signals generated by the row driver; The hybrid sensor of claim 14 , wherein the timing controller is configured to control timings of a first control signal and a second control signal applied to the first transistor and the second transistor.

16. The timing controller 16. The hybrid sensor of claim 15, further comprising: a timing control circuit for controlling the first control signal and the second control signal to turn off the first transistor and turn on the second transistor at a start point of a readout time of the photodiode.

17. The timing controller 16. The hybrid sensor of claim 15, further comprising: a timing control circuit for controlling the first control signal and the second control signal to turn on the first transistor and turn off the second transistor at the end of a readout time of the photodiode.

18. The timing controller 16. The hybrid sensor of claim 15, wherein the timing of the first control signal and the second control signal is controlled to turn on the first transistor and turn off the second transistor before and after a readout time of the photodiode.

19. The timing controller 20. The hybrid sensor of claim 18, wherein the timing of the first control signal and the second control signal is controlled to include a period in which the first transistor is turned off before and after a readout time of the photodiode, and the timing of the first control signal and the second control signal is controlled to include a period in which the second transistor is turned on before and after a readout time of the photodiode.

20. The timing controller 16. The hybrid sensor of claim 15, wherein the timing of the first control signal and the second control signal is controlled so as to turn off the first transistor and turn on the second transistor during a reset time of the photodiode.

Images