Semiconductor device

Abstract

To provide a semiconductor device that uses an oxide semiconductor and is highly reliable.SOLUTION: A semiconductor device includes a laminated structure including an oxide semiconductor layer and an insulation layer in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first layer where a channel is formed, and a second layer that is provided between the first layer and the insulation layer and has energy at a bottom end of a conduction band closer to a vacuum level than that at a bottom end of the conduction band of the first layer. In the above, the second layer functions as an insulation layer in contact with the oxide semiconductor layer, and a barrier layer that suppresses formation of defect level between the second layer and the channel. Further, the first layer and the second layer each include an ultra-fine crystal portion to such an extent that an atomic arrangement has no periodicity macroscopically or to such an extent that the atomic arrangement has no long-range order macroscopically. The first layer and the second layer include the crystal portion that the atomic arrangement is confirmed to have periodicity in a range of 1 nm or more and 10 nm or less, for example.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all electro-optical devices, semiconductor circuits, display devices, light-emitting devices and electronic equipment, all of which are semiconductors. It is a body device. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). It is widely applied to electronic devices such as transistors. Silicon-based semiconductor materials are widely known as conductive films, but other materials, such as semiconductors, are also widely used. Metal oxides (oxide semiconductors) that exhibit high conductivity are attracting attention.

[0004] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165529 Summary of the Invention [Problem to be solved by the invention]

[0006] Although transistors using oxide semiconductors can be obtained with relative ease, However, the physical properties tend to become unstable, making it difficult to ensure reliability.

[0007] In view of the above, one embodiment of the present invention is to provide a highly reliable semiconductor device including an oxide semiconductor. This is one of the challenges.

[0008] The above description of the problem does not preclude the existence of other problems. Problems other than those mentioned above include: It will be clear from the description of the specification, etc. that there are no other problems than those mentioned above. It is possible to extract [Means for solving the problem]

[0009] One embodiment of the disclosed invention is a stacked layer including an oxide semiconductor layer and an insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a first layer in which a channel is formed, and a first layer and an insulating layer. and the energy of the conduction band minimum of the first layer is closer to the vacuum level than the energy of the conduction band minimum of the first layer. and a second layer having energy. In the above, the second layer is in contact with the oxide semiconductor layer. The insulating layer functions as a barrier layer to prevent the formation of defect levels between the channel and the insulating layer. Moreover, the first and second layers each show periodic atomic arrangements macroscopically. For example, the atomic arrangement is in the range of 1 nm to 10 nm. The first layer and the second layer containing the crystalline portion are made of amorphous oxide. an oxide semiconductor layer having a reduced defect state density compared to a semiconductor layer, By applying this method, it is possible to suppress the fluctuation of the electrical characteristics of the transistor caused by the defect level density. This can be done.

[0010] More specifically, for example, the following configuration can be adopted.

[0011] One embodiment of the present invention is a gate electrode layer including: an oxide semiconductor layer; a gate electrode layer overlapping with the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode layer; The source electrode layer and the drain electrode layer overlap with the gate insulating layer via the oxide semiconductor layer. and an insulating layer formed of a first layer in which a channel is formed, and and a second layer between the insulating layer, and the first layer and the second layer each having a thickness of 10 The first and second layers each comprise an In-M-Zn oxide. oxides represented by (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) The atomic ratio of M to indium in the second layer is 1 / 100 of that of the first layer. The atomic ratio of M to S is higher than that of S.

[0012] Another embodiment of the present invention is a semiconductor device including an oxide semiconductor layer and a gate electrode overlapping with the oxide semiconductor layer. a gate insulating layer between the oxide semiconductor layer and the gate electrode layer; The source electrode layer and the drain electrode layer are connected to the gate insulating layer via the oxide semiconductor layer. The oxide semiconductor layer has a first layer in which a channel is formed and an insulating layer overlapping the first layer. a second layer between the first layer and the insulating layer, and a third layer between the first layer and the gate insulating layer. The first to third layers each contain crystals with a size of 10 nm or less, and the first layer, The second and third layers are made of In-M-Zn oxide (M is Al, Ga, Ge, Y). , Zr, Sn, La, Ce or Hf), and the second The atomic ratio of M to indium in the first layer and the atomic ratio of M to indium in the third layer are each of which has a higher atomic ratio of M to indium than that of the first layer. It is a body device.

[0013] In the semiconductor device, the third layer has a probe diameter of the electron beam of 1 nm or more and 10 nm or less. In the diffraction pattern of nanobeam electron diffraction focused at Multiple spots are observed.

[0014] In the semiconductor device, the first layer and the second layer are configured to have a probe diameter of the electron beam of 1n In the diffraction pattern obtained by nanobeam electron diffraction focused at a wavelength of 10 nm or more, A number of spots arranged circumferentially are observed.

[0015] In the semiconductor device, the energy of the bottom of the conduction band of the second layer is lower than that of the first layer. It is known that the energy level is close to the vacuum level in the range of 0.05 eV to 2 eV below the lower edge of the conductive band. preferable.

[0016] In the semiconductor device, the insulating layer is provided on and in contact with the oxide semiconductor layer. The oxide semiconductor layer and the source electrode are electrically connected to each other through a contact hole (also referred to as an opening) formed in the oxide semiconductor layer. In this case, the source electrode layer and the drain electrode layer may be electrically connected to each other. The drain electrode layer is connected to the first insulating layer through a contact hole provided in the second layer. It is preferable to electrically connect the layer.

[0017] In the semiconductor device, the source electrode layer and the drain electrode layer are formed on the side surfaces of the first layer. and the third layer is provided so as to be in contact with a part of the top surface of the source electrode layer and the drain electrode layer. a first insulating film provided on the source electrode layer and the drain electrode layer so as to be in contact with a part of the first layer exposed from the first insulating film; It may also be used. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. [Brief explanation of the drawings]

[0019] [Figure 1] 1A and 1B are schematic diagrams illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention and a band diagram thereof; [Figure 2] 1A and 1B are schematic diagrams illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention and a band diagram thereof; [Figure 3] 1A and 1B are schematic diagrams illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention and a band diagram thereof; [Figure 4] 1A and 1B are diagrams showing a cross-sectional TEM image and a nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 5] Schematic diagram showing a method for preparing a sample of a reference example. [Figure 6] FIG. 2 shows a nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 7] FIG. 2 shows a cross-sectional TEM image of a nanocrystalline oxide semiconductor layer. [Figure 8] FIG. 2 shows a nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 9] FIG. 1 shows a nanobeam electron diffraction pattern of a quartz glass substrate. [Figure 10] FIG. 2 shows a nanobeam electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 11] FIG. 10 shows the results of measuring the XRD spectrum of a nanocrystalline oxide semiconductor layer. [Figure 12] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 14] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Figure 15]1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 16] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 17] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram of a semiconductor device of one embodiment of the present invention. [Figure 19] 1A and 1B are a circuit diagram and a conceptual diagram of a semiconductor device of one embodiment of the present invention. [Figure 20] 1A to 1C illustrate a structure of a display panel according to an embodiment. [Figure 21] 1A to 1C are block diagrams illustrating electronic devices according to embodiments of the present invention. [Figure 22] 1A to 1C are diagrams illustrating external views of electronic devices according to embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is readily apparent to those skilled in the art that various modifications can be made to the modes and details. Therefore, the present invention should be construed as being limited to the description of the following embodiments. It's not something like that.

[0021] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a part having a specific function, the hatch pattern shall be the same and no specific symbol shall be attached. There is a match.

[0022] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0023] In this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" may be changed to "second" " or "third" etc. as appropriate. The ordinal numbers used to identify an aspect of the present invention may not match. There is a match.

[0024] (Embodiment 1) In this embodiment, an oxide semiconductor layer included in a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 1 to 11.

[0025] FIG. 1A is a schematic diagram illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention includes a gate electrode layer 102 and a gate insulating film over the gate electrode layer 102. a gate insulating layer 104, an oxide semiconductor layer 106 on the gate insulating layer 104, and an oxide semiconductor layer 106 and an insulating layer 108 on the insulating layer 106.

[0026] The oxide semiconductor layer 106 is formed between the first layer 106a and the insulating layer 108. The second layer 106b has a laminated structure.

[0027] The first layer 106a and the second layer 106b are so periodic that no periodicity is observed macroscopically in the atomic arrangement. Specifically, the first layer 106a and the second layer 106b are oxide semiconductor layers each including an extremely fine crystal part. The second layer 106b has a size of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. The crystalline portion of the nanocrystal (hereinafter referred to as nanocrystal (nc) in this specification) Also written as ).

[0028] The crystal portions included in the first layer 106a and the second layer 106b have a size close to that of the crystal portions. Or, a probe diameter smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less) In the electron diffraction pattern obtained by irradiating a sagittal beam, bright spots appear in a circular pattern (ring shape). It has areas of high intensity, and multiple spots (bright points) are observed within the areas of high brightness. A number of spots are arranged in a circular pattern, forming a ring-shaped area of ​​high brightness. This can also be rephrased as follows.

[0029] In addition, the measurement range by electron beam diffraction was determined by dividing the included crystal part in both the planar direction and the depth direction. By reducing the size to a range close to the size of the crystal part or to a range smaller than the size of the crystal part, In the sagittal diffraction pattern, regular spots that indicate a crystalline state may be observed. To reduce the measurement range in the planar direction, the probe diameter of the electron beam is reduced (for example, to 1 nm). In addition, to reduce the measurement range in the depth direction, for example, It is sufficient to measure an area that has been thinned to 10 nm or less by ion milling or the like.

[0030] In addition, both the first layer 106a and the second layer 106b have a high electric conductivity in both the cross-sectional direction and the planar direction. In the sagittal diffraction pattern, a plurality of spots arranged in the ring-shaped region of high brightness are It is possible to confirm that the crystal part does not have any orientation in the cross-sectional or planar direction. The random inclusion of the metal in the film results in spots that can be seen in the cross-sectional electron diffraction pattern. The spots observed in the electron diffraction pattern in the planar direction and the spots observed in the electron diffraction pattern in the planar direction show similar trends.

[0031] Note that the crystal part contained in the oxide semiconductor layer is 10 nm or less and is smaller than the diameter of the probe used. If the crystal has a larger crystal part than the cross section, the electron diffraction pattern will be different between the cross section direction and the planar direction. For example, there may be a tendency for the atomic arrangement to be larger than the probe diameter in the cross-sectional direction. The periodicity of the atomic arrangement in the planar direction is equal to or smaller than the probe diameter. When measuring a crystalline part having , the spots may be broader than those observed in the in-plane electron diffraction pattern. In addition, the first layer 106a and the second layer 106b are electrically connected in the cross-sectional direction and the planar direction, respectively. In the case where there are regions where the sagittal diffraction patterns have similar trends and regions where different trends are observed, For example, in the first layer 106a, near the interface with the second layer 106b, The electron diffraction patterns in the cross-sectional and planar directions show different trends. Near the interface with 04, the electron diffraction patterns in the cross-sectional and planar directions show similar trends. may be indicated.

[0032] As described above, the first layer 106a and the second layer 106b have a periodic atomic arrangement. The region having different properties is a very small range, for example, 1 nm to 10 nm. There is no order in the crystal orientation between the crystal parts. The oxide semiconductor layer 106b does not have any orientation in the entire film. Depending on the analysis method, the crystalline portions contained in the first layer 106a and the second layer 106b may be analyzed. In some cases, it may be impossible to distinguish the amorphous oxide semiconductor layer from the amorphous oxide semiconductor layer.

[0033] For example, the first layer 106a or the second layer 106b including the crystalline portion is Transmission electron microscope (TEM) from the planar direction Even when observed under a microscope, it is difficult to clearly confirm the crystal structure. is.

[0034] In addition, the oxide semiconductor layer 106 is formed by adding the oxide semiconductor X-ray diffraction (XRD) is a method of measuring the size of a sample by using X-rays with a diameter larger than that of the crystal. When structural analysis is performed using the out-of-plane method, , no peaks indicating crystal planes are detected.

[0035] Furthermore, a probe larger than the crystal portion is provided to the first layer 106a or the second layer 106b. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam with a diameter (for example, 100 nm or more) ) diffraction patterns resembling halo patterns may be observed.

[0036] In addition, as the probe diameter of the electron beam increases, the ring-shaped high brightness region described above increases. It can be seen that the ring width becomes wider. If the diameter is 50 nm or more, it becomes difficult to observe the spot within the ring-shaped area with high brightness. become.

[0037] The oxide semiconductor layer including nanocrystals described in this embodiment (hereinafter also referred to as a nanocrystal oxide semiconductor layer) The oxide semiconductor layer is a dense film having a high film density compared to an amorphous oxide semiconductor layer. The fewer defects in a compound semiconductor layer, or the lower the concentration of impurities such as hydrogen, the higher the film density. In an oxide semiconductor layer, oxygen defects and / or impurities such as hydrogen are factors that generate defect states. Therefore, the first layer 106a and the second layer 106b containing nanocrystals are amorphous oxide semiconductors. It can be said that this is a region where the defect level density is reduced compared to the conductor layer. The amorphous oxide semiconductor layer is, for example, a layer in which the atomic arrangement is disordered and does not contain crystalline components. This refers to an oxide semiconductor layer.

[0038] The first layer 106a and the second layer 106b are made of at least indium and zinc. It is preferable to use a metal oxide having the metal oxide as a constituent element. Alternatively, the layers 106a and 106b may be made of the same elements, but may have different compositions.

[0039] In this embodiment, both the first layer 106a and the second layer 106b are at least It is also a nanocrystalline oxide semiconductor layer containing indium and zinc, and depending on the material and film formation conditions, Therefore, in FIG. 1, the first layer 10 The interface between the first layer 106a and the second layer 106b is shown by a dotted line. The same is true for

[0040] The first layer 106a is an In-M-Zn oxide (wherein M is Al, Ga, Ge, Y, Zr, Sn, In the case where the second layer 106b is an oxide semiconductor layer represented by La, Ce, or Hf, The first layer 106a is made of In-M-Zn oxide (M is Al, Ga, Ge, Y, Z). r, Sn, La, Ce or Hf) and has a higher affinity for indium than the first layer 106a. It is preferable to use an oxide semiconductor layer in which the atomic ratio of M is high.

[0041] More specifically, the second layer 106b contains 1.5% of the above elements compared to the first layer 106a. oxide semiconductor containing 1,2,4-trimethyl-1,3,5-trimethyl-2,5 ... The aforementioned element M binds more strongly to oxygen than indium, so Oxide semiconductors with a high atomic ratio of M to M are less likely to have oxygen vacancies in the film. That is, the second layer 106b is an oxide semiconductor layer in which oxygen vacancies are less likely to occur than in the first layer 106a. Note that the higher the atomic ratio of M to indium, the lower the energy density of the oxide semiconductor layer. The gap (band gap) becomes larger, so the atomic ratio of M to indium becomes higher. If the second layer 106b is too thin, it functions as an insulating layer. It is preferable to adjust the atomic ratio of M to indium so that the layer can function.

[0042] The first layer 106a and the second layer 106b each contain at least indium, zinc, and Contains M (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) When the first layer 106a is an In-M-Zn oxide, the composition of the first layer 106a is In:M:Zn=x1:y1:z 1 [atomic ratio], and the second layer 106b is In:M:Zn=x2:y2:z2 [atomic ratio]. Therefore, it is preferable to make y2 / x2 larger than y1 / x1. x1 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. In this case, when y1 is equal to or greater than x1 in the first layer 106a, the electrical characteristics of the transistor are stabilized. However, if y1 is three times or more than x1, the field effect of the transistor Therefore, y1 is preferably less than three times x1.

[0043] When the first layer 106a is an In-M-Zn oxide, the I ions other than Zn and O are The atomic ratio of n to M is preferably 25 atomic % or more for In and 75 atomic % or more for M. %, more preferably In is 34 atomic % or more and M is less than 66 atomic %. When the second layer 106b is an In-M-Zn oxide, excluding Zn and O, The atomic ratio of In to M in the above is preferably less than 50 atomic % for In and less than 50 atomic % for M. % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more c% or more.

[0044] The second layer 106b has a conduction band minimum energy that is 0.0 times lower than that of the first layer 106a. 5 eV, 0.07 eV, 0.1 eV, 0.15 eV or more, and eV, 0.5 eV, or 0.4 eV, and is formed by oxide semiconductors close to the vacuum level. It is preferable to form

[0045] In such a structure, when an electric field is applied to the gate electrode layer 102, the oxide semiconductor layer 10 6, the first layer 106a, which has the smallest energy at the bottom of the conduction band, is the layer This becomes the main migration path (channel). Here, the channel formation region (first layer 106a) and the insulating layer By including the second layer 106b between the oxide semiconductor layer 106 and the insulating layer 108, The trap levels that can be formed by impurities and defects at the interface with 108 and the channel shape As a result, electrons flowing through the first layer 106a are trapped in the trap zone. This makes it possible to increase the on-state current of the transistor and In addition, when an electron is captured in the trap level, the electron becomes a negative fixed charge, which causes fluctuations in the threshold voltage of the transistor. However, since there is a gap between the first layer 106a and the trap level, the This can reduce the trapping of electrons, thereby reducing the fluctuation of the threshold voltage. .

[0046] The first layer 106a and the second layer 106b are not simply laminated but are connected in a continuous manner. In this case, a structure in which the energy of the bottom of the conduction band changes continuously between layers is formed. In other words, defects such as trap centers and recombination centers are formed at the interface of each layer. The stacked structure is such that no impurities that form levels exist. If impurities are present between the first layer 106a and the second layer 106b, the energy band Continuity is lost, and carriers are trapped at the interface or recombine and disappear. .

[0047] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (sputtering equipment) to continuously stack each film without exposing it to the air. Each chamber in the sputtering device is indispensable for the oxide semiconductor layer. An adsorption type vacuum pump such as a cryopump is used to remove as much water as possible. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent the backflow of gases, especially gases containing carbon or hydrogen, into the chamber.

[0048] Figure 1(B) shows a schematic diagram of a part of the band structure at D1-D2 of the stacked structure of Figure 1(A). Here, the gate insulating layer 104, which is an insulating layer in contact with the oxide semiconductor layer 106, is shown. A case where a silicon oxide layer is provided as the insulating layer 108 will be described. ), Evac indicates the energy of the vacuum level, and Ec indicates the energy of the bottom of the conduction band. show.

[0049] As shown in FIG. 1B, in the first layer 106a and the second layer 106b, The energy of changes smoothly without any barriers. In other words, it changes continuously. This is because the first layer 106a and the second layer 106b contain a common element, and both This is because a mixed layer is formed between the two regions due to the mutual movement of oxygen. Cut.

[0050] As shown in FIG. 1B, the first layer 106a in the oxide semiconductor layer 106 serves as a well. It can be seen that a channel region is formed in the first layer 106a. Since the energy of the conduction band minimum changes continuously, the first layer 106a and the second layer It can be said that the first layer 106b and the second layer 106b are continuously joined.

[0051] In the vicinity of the interface between the second layer 106b and the insulating layer 108, the constituent elements of the insulating layer 108 (for example, silicon dioxide) are present. Although trap levels can be formed due to impurities such as silicon or carbon, or defects, By providing a second layer 106b between the first layer 106a where the channel is formed, This allows the first layer 106a to be spaced apart from the trap level. When the energy difference between the first layer 106a and the second layer 106b is small, the electrons in the first layer 106a The electron can reach the trap level beyond the energy difference. This generates a negative fixed charge at the insulating film interface, and the threshold voltage of the transistor becomes positive. Therefore, the conduction band of the first layer 106a and the second layer 106b is shifted in the direction of the When the energy difference between the edges is 0.05 eV or more, preferably 0.15 eV or more, the This is preferable because it reduces fluctuations in the threshold voltage of the transistor and provides stable electrical characteristics.

[0052] In a semiconductor device using an oxide semiconductor layer, in order to improve reliability, a layer that functions as a channel must be formed. It is necessary to reduce the defect state density in the oxide semiconductor layer and its interface. The negative shift in threshold voltage of a transistor using a compound semiconductor layer is due to the channel and The cause is said to be the oxide semiconductor layer that functions as a It is possible.

[0053] Therefore, as shown in this embodiment, a semiconductor layer having a lower density of defect states than an amorphous oxide semiconductor layer is used. The oxide semiconductor layer including the reduced first layer 106a and the second layer 106b is used as a transistor. By using this material, the change in the electrical characteristics of the transistor caused by irradiation with visible light or ultraviolet light is reduced. Therefore, the reliability of the transistor can be improved.

[0054] FIG. 2A is a schematic diagram illustrating another example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. The stacked structure shown in FIG. 2A is the same as the stacked structure shown in FIG. 1A, in which the gate electrode layer 1 02, a gate insulating layer 104 on the gate electrode layer 102, and an oxide on the gate insulating layer 104. a semiconductor layer 116 and an insulating layer 108 on the oxide semiconductor layer 116; 116 includes a first layer 116a in which a channel is formed, and a layer between the first layer 116a and an insulating layer 108. a second layer 116b between the first layer 116a and the gate insulating layer 104; 116c, and

[0055] The oxide semiconductor layer 116 included in FIG. 2A is a first layer 116 functioning as a channel. 1A in that the third layer 116c is included between the gate insulating layer 104 and the gate insulating layer 104. The other configurations can be the same as those in FIG. 1(A) except for the oxide semiconductor layer 106. For example, the first layer 116a of the oxide semiconductor layer 116 may be the same as the oxide semiconductor layer 106 The description of the first layer 106a can be referred to. The layer 116b is the same as the second layer 106b of the oxide semiconductor layer 106 described above. This can be taken into consideration.

[0056] The first layer 116a, the second layer 116b, and the third layer 116c included in the oxide semiconductor layer 116 The third layer 116c is an oxide semiconductor layer containing nanocrystals. Similar to the first layer 116a and the second layer 116b, the layer 116a is made of at least indium and zinc. It is preferable to use a metal oxide having the same element as the first layer 116a to the third layer 116b. The layers 116c may be made of the same constituent elements but have different compositions.

[0057] The first layer 116a is an In-M-Zn oxide (wherein M is Al, Ga, Ge, Y, Zr, Sn, When the third layer 116c is an oxide semiconductor layer represented by La, Ce, or Hf, The first layer 116a is made of In-M-Zn oxide (M is Al, Ga, Ge, Y, Z). r, Sn, La, Ce or Hf) and has a higher affinity for indium than the first layer 116a. It is preferable that the third layer 116 be an oxide semiconductor layer having a high atomic ratio of M. The oxide semiconductor layer c is an oxide semiconductor layer in which oxygen vacancies are less likely to occur than in the first layer 116a. In particular, the third layer 116c preferably contains 1.5 times or more of the above elements compared to the first layer 116a. Preferably, an oxide semiconductor layer containing at least two times, more preferably at least three times, higher atomic ratio is used. do.

[0058] In addition, the third layer 116c, the first layer 116a, and the second layer 116b are at least Sium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or H When the third layer 116c is an In-M-Zn oxide containing a metal such as In:M:Z, n=x3:y3:z3 [atomic ratio], and the first layer 116a was In:M:Zn=x1:y1: z1 [atomic ratio], and the second layer 116b is In:M:Zn=x2:y2:z2 [atomic ratio] Then, it is preferable that y3 / x3 and y2 / x2 be greater than y1 / x1. y3 / x3 and y2 / x2 are 1.5 times or more, preferably 2 times or more, than y1 / x1. In this case, in the first layer 116a, y1 is greater than or equal to x1, and more preferably, 3 times or greater. If y1 is three times larger than x1, the electrical characteristics of the transistor can be stabilized. If the value is more than this, the field effect mobility of the transistor will decrease, so y1 should be three times x1. It is preferable that it is less than 10 ...

[0059] When the third layer 116c is an In-M-Zn oxide, the I ions except for Zn and O are The atomic ratio of n to M is preferably less than 50 atomic % for In and less than 50 atomic % for M. % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more When the first layer 116a is an In-M-Zn oxide, excluding Zn and O, The atomic ratio of In to M in the above is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. When the second layer 116b is an In-M-Zn oxide, the content of Zn and The atomic ratio of In and M excluding O is preferably less than 50 atomic % for In and less than 50 atomic % for M. 50 atomic % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more tomic% or more.

[0060] The third layer 116c and the second layer 116b may be layers containing different constituent elements. Alternatively, the layers may contain the same constituent elements in the same atomic ratio or in different atomic ratios.

[0061] The third layer 116c and the second layer 116b have conduction band minimum energies that are lower than those of the first layer 116a. 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 16a and the vacuum level is within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable to form the insulating film from an oxide semiconductor having a similar conductivity type.

[0062] FIG. 2B shows a schematic diagram of the band structure at D3-D4 of the layered structure of FIG. 2A.

[0063] As shown in FIG. 2B, the first layer 116a in the oxide semiconductor layer 116 is a well. The oxide semiconductor layer 11 is formed in the first layer 116a, and a channel region is formed in the first layer 116a. 6, the energy of the conduction band minimum changes continuously, so that the third layer 116c and the first layer It can also be said that the layer 116a and the second layer 116b are continuously joined together.

[0064] A third layer 116c provided above or below the first layer 116a, which functions as a channel. Alternatively, the second layer 116b may function as a barrier layer and may be a barrier layer between the insulating layer ( The gate insulating layer 104 and the insulating layer 108 are formed at the interface between the oxide semiconductor layer 116. The influence of trap levels on the first charge transport path, which is the main carrier path of the transistor, This can prevent the metal from reaching the layer 106a.

[0065] For example, oxygen vacancies in an oxide semiconductor layer are formed within the energy gap of the oxide semiconductor. This appears as a localized level at a deep energy position. The reliability of the transistor is reduced when the ions are trapped in the oxide semiconductor layer. In the laminated structure shown in Figure 2, the first layer The third layer 116c and the oxide semiconductor layer 116b are oxide semiconductor layers in which oxygen vacancies are less likely to occur than those in the oxide semiconductor layer 116a. The second layer 116b is provided above and below the first layer 116a, so that the second layer 116b functions as a channel. This can reduce oxygen vacancies in the first layer 116a.

[0066] In addition, the oxide semiconductor layer 116 may be formed by an insulating layer having a different constituent element (for example, a silicon oxide film). When the semiconductor contacts a silicon substrate (including an insulating underlayer), an interface state is formed at the interface between the two layers, and the interface state In such a case, a second transistor with a different threshold voltage may appear. This may cause the apparent threshold voltage of the transistor to fluctuate. In the transistor having the stacked structure shown in FIG. 2, the first layer 116a to the third layer 116c Each of the electrodes contains at least indium and zinc, and therefore functions as a channel. Therefore, the interface state is less likely to be formed at the interface of the first layer 116a, which functions as a transistor. The variation in electrical characteristics such as threshold voltage can be reduced.

[0067] In addition, when a channel is formed at the interface between the gate insulating layer 104 and the oxide semiconductor layer 116, However, interface scattering occurs at the interface, resulting in a decrease in the field-effect mobility of the transistor. In the transistor having the stacked structure of this embodiment, the first layer in which a channel is formed Between the layer 116a and the gate insulating layer 104, a third layer 116c comprising an oxide semiconductor is formed. The third layer 116c and the first layer 116a are provided with a thin film, and the scattering of carriers occurs at the interface between the third layer 116c and the first layer 116a. Therefore, the field-effect mobility of the transistor can be increased.

[0068] The third layer 116c and the second layer 116b are the gate insulating layer 104 and the insulating layer 106, respectively. The constituent elements of the layer 108 are mixed into the first layer 116a where the channel is formed, and the impurities It also functions as a barrier layer to prevent the formation of a level where the electrons are oxidized.

[0069] In FIG. 2B, the energy of the bottom of the conduction band of the third layer 116c is The case where the energy level is closer to the vacuum level than the conduction band minimum energy of b is shown as an example. The third layer 116c and the second layer 116b are, but are not limited to, is at least closer to the vacuum level than the energy of the bottom of the conduction band of the first layer 116a. The third layer 116c has the energy of the conduction band minimum of the second layer 116b. The energy of the conduction band minimum may be farther from the vacuum level than the energy of , both may have the same energy.

[0070] In the above description, the oxide semiconductor layer including at least the first layer and the second layer The bottom gate structure provided on the gate electrode layer via the gate insulating layer has been described. One aspect of the present invention is not limited to this.

[0071] FIG. 3A is a schematic diagram illustrating another example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. The stacked structure shown in FIG. 3A includes an insulating layer 108 and an oxide semiconductor layer over the insulating layer 108. a gate insulating layer 104 on the oxide semiconductor layer 116; The oxide semiconductor layer 116 is a first gate electrode layer 102 in which a channel is formed. layer 116a, a second layer 116b between the first layer 116a and the insulating layer 108, and a second layer 116b between the first layer 116a and the insulating layer 108. and a third layer 116c between the gate insulating layer 104 and the gate insulating layer 106a.

[0072] In addition, a part of the band structure at D5-D6 of the stacked structure in Figure 3(A) is shown in Figure 3(B). Illustrated in detail.

[0073] The stacked structure shown in Figure 3 is a top-gate structure in which the stacking order of the stacked structure shown in Figure 2 is reversed. The structure of each layer can be the same as that described above. For details of the top gate structure, please refer to the explanation in Figure 2. It is possible to play it.

[0074] In FIG. 3, the second layer 116b and the third layer 116c overlap the first layer 116a. 116c are provided, one embodiment of the present invention is a top gate type structure. For example, an oxide semiconductor layer may be provided to overlap the first layer 116a, forming a two-layer structure. The structure is applied to a top gate type having a gate electrode layer above the two oxide semiconductor layers. Good too.

[0075] As described above, the transistor including the stacked structure of this embodiment has a structure in which the oxide semiconductor layer By having a second layer between the first layer in which the channel is formed and the insulating layer, the oxide The semiconductor layer interface and the channel can be separated, which reduces the influence of the interface state on the channel. It is possible to suppress this.

[0076] In addition, the first to third layers 116a to 116c have a defect density lower than that of an amorphous oxide semiconductor. The first one is composed of nanocrystalline oxide semiconductor with reduced defect state density. By using the oxide semiconductor layer including the first to third layers in a transistor, This reduces fluctuations in the electrical characteristics of the capacitor, improving its reliability.

[0077] (Reference example) In this reference example, the nanocrystals contained in the oxide semiconductor layer of this embodiment were analyzed by nanobeam spectroscopy. This will be explained using electron diffraction patterns.

[0078] <Nanobeam electron diffraction pattern in the cross-sectional direction of the oxide semiconductor layer> Sample 1 used in this reference example In Sample 1, an oxide semiconductor layer corresponding to the first layer was formed using a An In-Ga-Zn oxide film was formed on a quartz glass substrate to a thickness of 50 nm. The conditions were as follows: using an oxide target with an In:Ga:Zn=1:1:1 (atomic ratio), Under oxygen atmosphere (flow rate 45sccm), pressure 0.4Pa, direct current (DC) power supply 0.5kW, After the oxide semiconductor layer was formed, the substrate was heated at 450° C. in a nitrogen atmosphere for 1 hour. and a second heat treatment at 450°C for 1 hour under a nitrogen and oxygen atmosphere. The theory was carried out.

[0079] The oxide semiconductor layer after the second heat treatment was subjected to ion milling using Ar ions. The thickness of the exfoliated film was approximately 40 nm (40 nm ± 10 nm). After bonding the quartz glass substrate on which the compound semiconductor layer is formed to the dummy substrate, cutting and polishing are performed. Therefore, the oxide semiconductor layer 2 was thinned to a thickness of about 50 μm. The quartz glass substrate 200 and the dummy substrate 202 are provided with the quartz glass substrate 200 and the dummy substrate 202, respectively. Argon ions are irradiated from a 3° angle, and ion milling is performed to remove the ions. A thinned region 210a was formed to a thickness of ±10 nm, and its cross section was observed.

[0080] The oxide semiconductor layer after the first and second heat treatments is thinned to a thickness of about 50 nm (40 nm±10 nm). A cross-sectional TEM image of the thinned sample 1 is shown in FIG. 4(A). The cross section shown in FIG. 4(A) is The electron diffraction patterns measured by nanobeam electron diffraction are shown in Figures 4(B) to 4(E). Figure 4(B) shows the electron beam diffraction pattern obtained by irradiating an electron beam focused to a probe diameter of 1 nm. Figure 4(C) shows the electron beam irradiated with an electron beam focused to a probe diameter of 10 nm. Figure 4(D) shows the diffraction pattern obtained by irradiating an electron beam focused to a probe diameter of 20 nm. Figure 4(E) shows the electron diffraction pattern obtained by converging the probe diameter to 30 nm. 1 shows the electron diffraction pattern obtained by irradiating the sample with an electron beam.

[0081] As shown in FIG. 4(B), the electron diffraction pattern of the sample 1 in the cross-sectional direction shows a ring-shaped It has a high brightness area, and multiple spots (bright points) are observed within the high brightness area. In addition, as shown in Figures 4(C) to 4(E), the electron beam probe diameter is increased to widen the measurement range. As the intensity of the light increases, the spots gradually become broader, and the width of the ring-shaped bright area also increases. It has been confirmed that this trend will continue.

[0082] When the size of the crystal part contained in Sample 1 of this Reference Example is 10 nm or less, or 5 nm or less In the case of Sample 1, in which the oxide semiconductor layer is sliced ​​to a thickness of about 50 nm, the measurement range in the depth direction is Since the measurement range is larger than the size of the crystal part, multiple crystal parts may be included within the measurement range. Therefore, an oxide semiconductor layer formed by the same method as in Sample 1 was formed to a thickness of 10 nm or less, preferably 5 nm or less. The area thinned to less than 100 nm, more preferably less than 300 nm, is used as sample 2, and its cross section is nano-sized. The crystals were observed by electron diffraction.

[0083] Ion milling was performed using Ar ions, and the resulting surface was polished to a depth of 10 nm or less, e.g., 5 nm, as shown in FIG. A region 210b thinned to about 10 nm was formed, and its cross section was observed.

[0084] 6(A) to 6(D) show the results of the probe analysis of four arbitrary points on a sample 2 thinned to 10 nm or less. The nanobeam electron diffraction pattern measured using an electron beam focused to a diameter of 1 nm is shown.

[0085] In Fig. 6(A) and Fig. 6(B), regular spots showing a crystalline state oriented in a specific plane are shown. From this, it can be seen that the oxide semiconductor layer according to this embodiment certainly has a crystalline portion. On the other hand, in Fig. 6(C) and Fig. 6(D), a ring-shaped high-luminance A plurality of spots arranged within the region are observed.

[0086] As described above, the size of the crystal part contained in the nanocrystalline oxide semiconductor layer is, for example, 10n Therefore, for example, the sample can be sliced ​​to a thickness of 10 nm or less. The electron beam is focused to 1 nm, and the measurement range is reduced in both the horizontal and vertical directions ( For example, if the area is reduced to a size smaller than the size of one crystal, the area to be measured will be This allows observation of regular spots that indicate a crystalline state oriented in a specific plane. In addition, if the area to be measured contains multiple crystalline parts, the electron beam that passes through the crystalline parts may The crystal spot can be observed in the depth direction by spreading out larger than the size of the crystal. In this case, multiple spots are expected to be observed in the nanobeam electron diffraction pattern. can be done.

[0087] Next, an oxide semiconductor layer having a composition different from that of Sample 1 and Sample 2 was prepared as Sample 3. The electron beam diffraction pattern was confirmed by irradiating the sample with an electron beam. This is an example of an oxide semiconductor layer that corresponds to the second layer or the third layer in the oxide semiconductor layer.

[0088] The method for fabricating Sample 3 is as follows. Sample 3 was fabricated by depositing an In-Ga-Zn oxide film on a quartz glass substrate. The film was formed on the substrate with a thickness of 100 nm. The film formation conditions were In:Ga:Zn=1:3:2( The oxide target with the atomic ratio of 1000 to 10000 was used under an oxygen and argon atmosphere (Ar flow rate 30 sccm, oxygen flow rate 15 sccm), pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, base The plate temperature was room temperature.

[0089] The oxide semiconductor layer thus formed was sliced ​​to a thickness of about 50 nm (40 nm ± 10 nm). A cross-sectional TEM image is shown in Figure 7. The cross section shown in Figure 7 was also measured by nanobeam electron diffraction. The electron diffraction patterns measured are shown in Figure 8(A), Figure 8(B), Figure 8(C), Figure 8(D), Figure 8( The results are shown in Figure 8(E) and Figure 8(F). Figure 8(A) shows the electron beam focused to a probe diameter of 1 nm. Figure 8(B) shows the electron diffraction pattern of the sample focused at a probe diameter of 10 nm. The electron diffraction pattern is shown in Figure 8(C) when the probe diameter is set to 20 nm. The electron diffraction pattern of the sample was obtained by irradiating the sample with an electron beam with a probe diameter of 30 nm. The electron diffraction pattern is shown in Fig. 8(E) when the electron beam is focused at a probe diameter of m. The electron diffraction pattern was obtained by irradiating the sample with an electron beam focused to 50 nm. ) is the electron diffraction pattern obtained by irradiating an electron beam focused at a probe diameter of 100 nm. .

[0090] As shown in Figure 8, Sample 3, which has a different composition from Sample 1, also has a cross-sectional electron diffraction pattern. The image has a ring-shaped area of ​​high brightness, and a plurality of spots are formed within the area of ​​high brightness. Bright spots are observed. 8(E) and 8(F), when the electron beam probe diameter is increased to widen the measurement range, The multiple spots gradually become broader, and the width of the ring-shaped bright area also increases. It is confirmed that

[0091] <Nanobeam electron diffraction pattern on a quartz glass substrate> Figure 9 shows the pattern of nanobeam electron diffraction on a quartz glass substrate. The nanobeam electron diffraction pattern in Fig. 9 is shown. The measurement conditions in Fig. 9 are the same as those in Fig. 4(B) and Fig. 8(A). ) and the electron beam probe diameter was converged to 1 nm.

[0092] As can be seen from Figure 9, the quartz glass substrate with an amorphous structure does not diffract to a specific spot but is instead focused on the main A halo pattern with continuously changing brightness is observed from the spot. In the film having the structure, even if electron beam diffraction is performed on a very small area, The multiple spots arranged in a circular pattern, which are observed in the oxide semiconductor layer of Therefore, the multiple spots arranged in a circular pattern observed in Samples 1 to 3 of this reference example It is confirmed that this is specific to the oxide semiconductor layer of this reference example.

[0093] <<Nanobeam electron diffraction patterns in the cross-sectional and planar directions of the oxide semiconductor layer>> Next, The oxide semiconductor layer was irradiated with electron beams from both the cross-sectional and planar directions. The sagittal diffraction patterns were compared. The method for preparing Sample 4 used for comparison is as follows.

[0094] In sample 4, an In-Ga-Zn oxide film was formed on a quartz glass substrate to a thickness of 50 nm. The deposition conditions were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, the experiment was carried out in an oxygen atmosphere (flow rate 45sccm), with a pressure of 0.4Pa and a direct current (DC) power supply of 0. The power was 5 kW and the substrate temperature was room temperature.

[0095] Nanobeam electron diffraction patterns obtained by irradiating the oxide semiconductor layer with an electron beam from the planar direction. The turn is shown in FIG. 10(A). After the oxide semiconductor layer was thinned to about 50 nm, it was cut. The nanobeam electron diffraction pattern obtained by irradiating the electron beam in the in-plane direction is shown in Figure 10(B). (A) and (B) in Fig. 10 are electron beams irradiated with an electron beam focused to a probe diameter of 1 nm. This is a sagittal diffraction pattern.

[0096] As shown in Figures 10(A) and 10(B), the electron diffraction patterns in the planar direction also show , has a ring-shaped region of high brightness similar to the electron beam diffraction pattern in the cross-sectional direction, and Therefore, in the sample 4 of this reference example, multiple spots (bright points) were observed in the high area. It was confirmed that the film contained crystalline portions uniformly without being biased in the cross-sectional or planar direction. Ta.

[0097] <X-ray diffraction analysis> Next, sample 5, which had an oxide semiconductor layer on a quartz glass substrate, was prepared. The results were analyzed using X-ray diffraction (XRD). The results of measuring the XRD spectrum using the out-of-plane method are shown in Figure 1. Sample 5 was prepared in the same manner as Sample 4 described above.

[0098] In FIG. 11, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg. The XRD spectrum was measured using an X-ray diffractometer manufactured by Bruker AXS. -8 ADVANCE was used.

[0099] As shown in Figure 11, a peak due to quartz is observed in the vicinity of 2θ = 20 to 23°. No peaks due to the crystalline parts contained in the oxide semiconductor layer can be confirmed. From the results of 11, it can be seen that the crystal parts contained in the oxide semiconductor layer of this reference example are extremely fine crystal parts. This suggests that

[0100] As described above, the size of the crystal part included in the oxide semiconductor layer according to this embodiment is, for example, For example, it is estimated to be 10 nm or less, or 5 nm or less. The nitride semiconductor layer may have a crystalline portion (nanocrystalline (nc)) of, for example, 1 nm or more and 10 nm or less. The oxide semiconductor layer includes a silicon dioxide film and a silicon dioxide crystal.

[0101] As described above, the structures, methods, etc. described in this embodiment are applicable to the structures, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0102] (Embodiment 2) In this embodiment mode, the semiconductor device having the stacked structure shown in Embodiment Mode 1 will be described with reference to FIG. The following description will be given with reference to FIGS.

[0103] <Transistor configuration example 1> An example of the configuration of a semiconductor device is shown in FIG. 12. In FIG. 12, a bottom gate FIG. 12A shows a top view of transistor 450. 12(B) is a cross-sectional view taken along line V1-W1 in FIG. 12(A), and FIG. 12(C) is a cross-sectional view taken along line V1-W1 in FIG. 12(A) is a cross-sectional view taken along the line X1-Y1 in FIG. 12(A). In order to avoid confusion, some of the components (such as the insulating layer 408) are omitted in the illustration. This also applies to the subsequent plan views.

[0104] A transistor 450 shown in FIG. 12 includes a gate electrode layer 402 provided over a substrate 400 and a A gate insulating layer 404 on the gate electrode layer 402, and a gate insulating layer 405 on the gate insulating layer 404 The oxide semiconductor layer 406 overlaps the electrode layer 402, and the oxide semiconductor layer 406 is electrically connected to the oxide semiconductor layer 406. the source electrode layer 410a and the drain electrode layer 410b connected to the oxide semiconductor layer 406 and an insulating layer 408 overlapping the gate insulating layer 404 with an insulating layer 408 interposed therebetween.

[0105] The oxide semiconductor layer 406 included in the transistor 450 is a first layer in which a channel is formed. 406a and a second layer 406b between the first layer 406a and the insulating layer 408. The first layer 406a and the second layer 406b are oxide semiconductor layers containing nanocrystals. and correspond to the first layer 106a and the second layer 106b shown in FIG.

[0106] As described above, the first layer 406a and the second layer 406b are made of indium and zinc, respectively. The second layer 406b contains lead as a constituent element, and the energy of the bottom of the conduction band of the second layer 406b is The vacuum level is in the range of 0.05 eV to 2 eV below the energy of the bottom of the conduction band of the layer 406a. It's close to that.

[0107] The first layer 406a and the second layer 406b contain nanocrystals, and thus the oxide semiconductor layer 406 The oxide semiconductor layer can have a reduced density of defect states compared to an amorphous oxide semiconductor. In addition, the first layer 406a in which a channel is formed in the oxide semiconductor layer 406 and the By including the second layer 406b between the oxide semiconductor layer 406 and the insulating layer 408, The influence of trap levels that may be formed between the silicon dioxide and the silicon dioxide and the silicon dioxide on the channel is reduced or suppressed. Therefore, the electrical characteristics of the transistor 450 can be stabilized.

[0108] In addition, the first layer 406a in which a channel is formed in the oxide semiconductor layer 406 contains hydrogen. It is preferable that the density is reduced as much as possible. Secondary Ion Mass Spectroscopy (SIMS) The hydrogen concentration obtained by the ionization method is 2×10 20 atoms / cm 3 Below, I prefer Or 5 x 10 19 atoms / cm3 Below, 1×10 19 atoms / cm 3 Below, 5 x10 18 atoms / cm 3 Below, 1×10 18 atoms / cm 3 Below, 5 x 10 1 7 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following do.

[0109] In the transistor 450, the gate insulating layer 404 includes an insulating layer 404a and an insulating layer 404b. The insulating layer 404a and the insulating layer 404b each have a stacked structure of silicon oxynitride. , silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride Aluminum, aluminum oxide nitride, hafnium oxide, gallium oxide or Ga-Zn system In this embodiment, the insulating layer 404a and the insulating film 404b can be formed of a metal oxide or the like. The case where the gate insulating layer 404 is formed of a laminated structure including the insulating layer 404b and the insulating layer 404b is shown as an example. The gate insulating layer may have a single layer structure, or may have a stacked structure of three or more layers. It may also be a layer.

[0110] In the gate insulating layer 404, an insulating layer 404a in contact with the gate electrode layer 402 is formed of a nitride. Silicon, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, and other nitride insulation By forming the film, it is possible to prevent the diffusion of the metal elements that constitute the gate electrode layer 402. Therefore, it is preferable.

[0111] The insulating layer 404a may be formed using a silicon nitride film or a silicon nitride oxide film. The silicon nitride film or silicon nitride oxide film has a relatively low dielectric constant compared to the silicon oxide film. The dielectric constant is high and the thickness required to obtain the same capacitance is large, so the gate insulating layer is physically For example, the thickness of the insulating layer 404a can be increased to 300 nm or more and 400 nm or less. Therefore, the reduction in the withstand voltage of the transistor 450 can be suppressed or the insulation The breakdown voltage can be improved, and electrostatic breakdown of the semiconductor device can be suppressed.

[0112] In addition, a nitride insulating film that can be suitably used as the insulating layer 404a forms a dense film. This can prevent the diffusion of metal elements in the gate electrode layer 402, while reducing the defect level density and Since the internal stress is large, the threshold voltage fluctuates when an interface with the oxide semiconductor layer 406 is formed. Therefore, when a nitride insulating film is formed as the insulating layer 404a, The insulating layer 404b is made of silicon oxide or silicon oxynitride. It is preferable to provide an insulating film of an oxide such as aluminum oxide or aluminum oxynitride. The oxide insulating film is not provided between the oxide semiconductor layer 406 and the insulating layer 404a made of the nitride insulating film. By forming the insulating layer 404b, the interface between the gate insulating layer 404 and the oxide semiconductor layer 406 It is possible to stabilize the

[0113] The thickness of the insulating layer 404b can be set to, for example, 25 nm or more and 150 nm or less. By using an oxide insulating film for the insulating layer 404b in contact with the oxide semiconductor layer 406, It is also possible to supply oxygen to the semiconductor layer 406. Oxygen vacancies contained in the oxide semiconductor This makes the oxide semiconductor n-type and causes fluctuations in electrical characteristics. Supplying oxygen to compensate for oxygen deficiency is effective in improving reliability.

[0114] Alternatively, the gate insulating layer 404 may be made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium Luminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. The use of -k materials can reduce gate leakage of transistors.

[0115] In the transistor 450, an insulating film provided in contact with an upper layer of the oxide semiconductor layer 406 The insulating layer 408 is an insulating layer containing oxygen (oxide insulating layer), in other words, a layer that can release oxygen. It is preferable that the insulating layer 408 includes an insulating layer that can release oxygen. Oxygen is supplied to the compound semiconductor layer 406 (more specifically, the first layer 406a in which the channel is formed). This allows oxygen vacancies in the oxide semiconductor layer 406 or at the interface thereof to be filled. Note that examples of insulating layers capable of releasing oxygen include a silicon oxide layer and an oxynitride layer. A silicon layer or an aluminum oxide layer can be applied.

[0116] In this embodiment, the insulating layer 408 has a stacked-layer structure of an insulating layer 408a and an insulating layer 408b. The insulating layer 408a may be an oxide insulating film capable of reducing oxygen vacancies in the oxide semiconductor. The insulating layer 408b is formed by using a material that prevents impurities from the outside from moving to the oxide semiconductor layer 406. The insulating layer 408a is preferably made of a nitride insulating film that can prevent the formation of a void. and a nitride insulating film that can be suitably used as the insulating layer 408b. The insulating film will now be described in detail.

[0117] The oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed by heating. Heat causes some of the oxygen to be released. Acids containing more oxygen than the stoichiometric composition The oxide insulating film has a desorption amount of oxygen of 1.0 x 10 converted to oxygen atoms by TDS analysis. 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 Acid that is more than The substrate temperature during the TDS analysis was 100°C or higher and 70°C or lower. A temperature of 0°C or lower, or a temperature in the range of 100°C to 500°C is preferred.

[0118] An oxide insulating film that can be used as the insulating layer 408a is a thin film having a thickness of 30 nm or more. 00 nm or less, preferably 50 nm to 400 nm, silicon oxide, silicon oxynitride Cone and the like can be used.

[0119] The nitride insulating film that can be used as the insulating layer 408b is a nitride insulating film that reacts with oxygen, hydrogen, water, and alkaline metals. The insulating film 124 is a nitride insulating film having a blocking effect against metals, alkaline earth metals, etc. By providing the semiconductor layer 110, oxygen can be diffused from the semiconductor layer 110 to the outside, and oxygen can be diffused from the outside to the semiconductor layer 110. The nitride insulating film can prevent hydrogen, water, etc. from penetrating into the substrate. Silicon oxide, aluminum nitride, aluminum nitride oxide, etc. Instead of a nitride insulating film that has a blocking effect against water, alkali metals, alkaline earth metals, etc. Alternatively, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of oxide insulating films having a blocking effect against hydrogen, water, and the like include aluminum oxide and oxide. Aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride Examples include tritium, hafnium oxide, and hafnium oxynitride.

[0120] <Transistor configuration example 2> FIG. 13 illustrates a transistor 460 as a variation of the transistor 450. 13(A) is a plan view of the transistor 460, and FIG. 13(B) is a plan view of the V2-W 13(C) is a cross-sectional view taken along line X2-Y2 of FIG. 13(A). be.

[0121] The transistor 460 shown in FIG. 13 includes a gate electrode layer 402 provided over a substrate 400 and a A gate insulating layer 404 on the gate electrode layer 402, and a gate insulating layer 405 on the gate insulating layer 404 The oxide semiconductor layer 406 overlaps the gate electrode layer 402, and the gate electrode layer 402 is formed by interposing the oxide semiconductor layer 406 therebetween. The insulating layer 404 and the insulating layer 408 overlap each other, and the contact hole provided in the insulating layer 408 The source electrode layer 410a and the drain electrode layer 410b are electrically connected to the oxide semiconductor layer 406. In the transistor 460, the gate insulating layer 404 includes an insulating layer The insulating layer 408 includes an insulating layer 408a and an insulating layer 404b. Includes 408b.

[0122] The transistor 460 shown in FIG. 13 includes a source electrode layer 410a and a drain electrode layer 410b. 12. The stacking order of the insulating layer 408 and the insulating layer 409 is different from that of the transistor 450 shown in FIG. In the transistor 450, the source electrode layer 41 is formed so as to cover the island-shaped oxide semiconductor layer 406. After forming a conductive film to be the source electrode layer 410a and the drain electrode layer 410b, the conductive film is processed to form the source electrode layer 410a and the drain electrode layer 410b. The source electrode layer 410a and the drain electrode layer 410b are formed. The source electrode layer 410 is formed so as to cover a part of the oxide semiconductor layer 406 exposed from the electrode layer 410b. The insulating layer 408 is formed over the a and drain electrode layers 410b of the transistor 45. In FIG. 10, the source electrode layer 406 is formed in contact with the side surface and part of the top surface of the island-shaped oxide semiconductor layer 406. A drain electrode layer 410a and a drain electrode layer 410b are formed.

[0123] On the other hand, in the transistor 460, the insulating layer 408 is formed to cover the island-shaped oxide semiconductor layer 406. After forming a contact hole in the insulating layer 408, The source electrode layer 410a and the drain electrode layer 410b connected to the oxide semiconductor layer 406 are formed. Therefore, in the transistor 460, the oxide semiconductor layer 406 is formed in contact with part of the top surface of the oxide semiconductor layer 406. The source electrode layer 410a and the drain electrode layer 410b are formed in this manner. Depending on the conditions for forming a contact hole to the oxide semiconductor layer 406, a part of the oxide semiconductor layer 406 may be formed at the same time. For example, contact holes may be formed in the second layer 406b and the insulating layer 408. The source electrode layer 410a, the drain electrode layer 410b, and the first layer 406a There may be cases where they come into contact.

[0124] The other components included in the transistor 460 are the same as those of the transistor 450. It is possible.

[0125] <Transistor manufacturing method 1> An example of a method for manufacturing the transistor 460 will be described below with reference to FIGS.

[0126] First, a gate electrode layer 402 (including wiring formed in the same layer) is formed on a substrate 400. Then, a gate insulating layer 404 is formed over the gate electrode layer 402 (see FIG. 14A).

[0127] There is no particular restriction on the material of the substrate 400, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 400. Also, silicon, silicon carbide, or the like may be used. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, S It is also possible to use OI substrates, etc., on which semiconductor elements are mounted. may be used as the substrate 400. When a glass substrate is used as the substrate 400, , 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm) , 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm) By using large area substrates such as the 10th generation (2950mm x 3400mm), it is possible to It is possible to create a display device.

[0128] In addition, a flexible substrate is used as the substrate 400, and the transistor 460 is directly formed on the flexible substrate. The oxide semiconductor layer included in the semiconductor device of one embodiment of the present invention may be formed at room temperature. Therefore, it can be suitably used even on flexible substrates with low heat resistance. Alternatively, a separation layer may be provided between the substrate 400 and the transistor 460. The delamination is performed by separating the semiconductor device from the substrate 400 after completing a part or all of the semiconductor device thereon. It can be used to transfer to another substrate. It can also be transferred onto hard or flexible substrates.

[0129] The material of the gate electrode layer 402 is molybdenum, titanium, tantalum, tungsten, aluminum, or the like. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as the main components The gate electrode layer 402 can be formed using an impurity source such as phosphorus. Semiconductor films, such as polycrystalline silicon films doped with silicon, and silicon films such as nickel silicide The gate electrode layer 402 may have a single layer structure or a stacked layer structure. The gate electrode layer 402 may have a tapered shape, for example, with a taper angle of 15° or more. The taper angle is the angle between the side surface of the layer having the tapered shape and the surface of the layer. This refers to the angle between the bottom surface of the layer.

[0130] The material of the gate electrode layer 402 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, acid Conductive materials such as silicon dioxide doped indium tin oxide can also be applied.

[0131] Alternatively, the gate electrode layer 402 may be made of a nitrogen-containing In—Ga—Zn-based oxide, ... or a nitrogen-containing In—Ga—Zn-based oxide. In-Sn oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen oxides, Sn-based oxides containing nitrogen, In-based oxides containing nitrogen, metal nitride films (indium nitride Alternatively, a film such as a titanium film, a zinc nitride film, a tantalum nitride film, or a tungsten nitride film may be used. Since the materials have a work function of 5 electron volts or more, it is possible to use these materials to fabricate gate electrodes. By forming the layer 402, the threshold voltage of the transistor can be made positive. An off-switching transistor can be realized.

[0132] The gate insulating layer 404 is formed by depositing silicon oxide by plasma CVD, sputtering, or the like. Silicon oxide layer, silicon oxynitride layer, silicon nitride oxide layer, silicon nitride layer, aluminum oxide layer, hafnium oxide layer, yttrium oxide layer, zirconium oxide layer, gallium oxide layer, a tantalum oxide layer, a magnesium oxide layer, a lanthanum oxide layer, a cerium oxide layer, and a neodymium oxide layer The gate insulating layer 404 can be an insulating layer containing one or more types of silicon layers. A laminated structure using the material of the insulating layer may also be used.

[0133] Note that the insulating layer 404b in contact with the oxide semiconductor layer 406 formed later is an oxide insulating layer. It is preferable that the oxygen content is in a region containing more oxygen than the stoichiometric composition (oxygen excess region). To form an oxygen-excess region in the insulating layer 404b, for example, an oxygen-excess region is formed by The insulating layer 404b may be formed in a nitrogen atmosphere. The oxygen-excess region may be formed by introducing oxygen. On-doping method, plasma immersion ion implantation method, plasma treatment, etc. can be used. can.

[0134] In this embodiment, a silicon nitride film is formed as the insulating layer 404a, and a silicon nitride film is formed as the insulating layer 404b. A silicon oxynitride film is formed by this.

[0135] Next, a first oxide semiconductor film 407a to be the first layer 406a was formed over the gate insulating layer 404. and a second oxide semiconductor film 407b which is to be the second layer 406b are stacked.

[0136] In this embodiment, the first oxide semiconductor film 407a is made of In-M-Zn oxide (M is Oxide semiconductors represented by Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf The atomic ratio of In to M is preferably less than 50 atomic %. M is 50 atomic % or more, and more preferably In is less than 25 atomic %; M must be 75 atomic % or more.

[0137] In this embodiment, the second oxide semiconductor film 407b contains an In-M-Zn oxide. (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) The oxide semiconductor film 407a has a higher atomic ratio of M to indium than the first oxide semiconductor film 407a. Specifically, the element M is contained in the first oxide semiconductor film 407a by 1. The oxide semiconductor is contained in an atomic ratio that is 5 times or more, preferably 2 times or more, and more preferably 3 times or more higher. It is preferable to use a conductor. Since element M binds more strongly to oxygen than indium, Therefore, the second oxide semiconductor film 407b has a function of suppressing the generation of defects. Therefore, oxygen vacancies are less likely to occur in the oxide semiconductor film 407a than in the oxide semiconductor film 407b of FIG. Cut.

[0138] The second oxide semiconductor film 407b has a conduction band minimum energy lower than that of the first oxide semiconductor. An oxide semiconductor closer to a vacuum level than the conductive film 407a is used. For example, the second oxide semiconductor The energy of the bottom of the conduction band of the conductive film 407b and the bottom of the conduction band of the first oxide semiconductor film 407a are The difference in energy between the edge and the is 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV It is preferable to do the following:

[0139] For example, in the second oxide semiconductor film 407b, the atomic ratio of In to M is preferably , In is 25 atomic % or more, M is less than 75 atomic %, and more preferably, I n is 34 atomic % or more, and M is less than 66 atomic %.

[0140] For example, the first oxide semiconductor film 407a may be formed of In:Ga:Zn=1:1:1 or The first can be made of In-Ga-Zn oxide with an atomic ratio of 3:1:2. The oxide semiconductor film 407b is made of In:Ga:Zn=1:3:2, 1:3:4, or 1:3:6 In-Ga-Zn oxides with atomic ratios of 1:6:4, 1:9:6, or 1:6:4 can be used. Note that the atoms of the first oxide semiconductor film 407a and the second oxide semiconductor film 407b The atomic ratios may vary by plus or minus 20% from the atomic ratios listed above.

[0141] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the first oxide semiconductor film 407a and the second oxide semiconductor film 407b are The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen in the semiconductor film 407b, It is preferable to make the interatomic distance, density, etc. appropriate.

[0142] The first oxide semiconductor film 407a and the second oxide semiconductor film 407b are formed by a sputtering method. Tarring method, MBE (Molecular Beam Epitaxy) method, CVD method, Pulsed laser deposition method, ALD (Atomic Layer Deposition) method, etc. can be used appropriately.

[0143] In order to reduce oxygen vacancies in the oxide semiconductor film after deposition, the oxide semiconductor film is heated under an atmosphere containing oxygen. It is preferable to form the first oxide semiconductor film 407a and the second oxide semiconductor film 407b by using the above-mentioned method. In addition, the interface between the first oxide semiconductor film 407a and the second oxide semiconductor film 407b is preferably After the first oxide semiconductor film 407a is formed, the film is exposed to the air to prevent impurities from being mixed into the oxide semiconductor film. It is preferable to deposit the second oxide semiconductor film 407b successively without a step of depositing the second oxide semiconductor film 407b.

[0144] For example, a sputtering method using a sputtering target containing polycrystals is used. The first oxide semiconductor film 407a and the second oxide semiconductor film 407b are formed by A first oxide semiconductor film 407a and a second oxide semiconductor film 407b containing nanocrystals are formed. It is possible.

[0145] When the first oxide semiconductor film 407a and the second oxide semiconductor film 407b are formed, It is preferable to reduce the hydrogen concentration in the film as much as possible. For example, when forming a film by sputtering, the film forming chamber is evacuated to a high vacuum. In addition, it is necessary to increase the purity of the sputtering gas. The dew point of the argon gas is -40°C or less, preferably -80°C or less, more preferably -1 Oxidation is achieved by using gas that has been highly purified to below 00°C, preferably below -120°C. This can prevent moisture and the like from being taken into the compound semiconductor film 208 as much as possible.

[0146] In order to remove residual moisture in the film-forming chamber, an adsorption-type vacuum pump, for example, a cryo- It is preferable to use a pump, an ion pump, or a titanium sublimation pump. A cryopump may be a turbomolecular pump with a cold trap added. For example, hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), compounds containing carbon atoms, etc. Because of the high pumping capacity of the cryopump, the gas contained in the film formed in the film formation chamber evacuated using a cryopump can be This can reduce the concentration of impurities.

[0147] The first oxide semiconductor film 407a and the second oxide semiconductor film 407b were formed by sputtering. When forming a film by the coating method, the relative density (filling rate) of the metal oxide target used for film formation is 90%. The relative density of the metal oxide is 95% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a nitride target, the deposited film can be made dense.

[0148] Note that the first oxide semiconductor film 407a and the second oxide semiconductor film 407b are The first oxide semiconductor film 407a and the second oxide semiconductor film 40 By depositing 7b at room temperature, an oxide semiconductor film containing nanocrystals can be formed with high productivity. It becomes possible to do this.

[0149] Next, the first oxide semiconductor film 407a and the second oxide semiconductor film 407b were By processing the oxide semiconductor layer 406 into an island-shaped oxide semiconductor layer including the first layer 406a and the second layer 406b, When the oxide semiconductor layer 406 is processed, the gate insulating layer 404 is formed. A part (the area exposed from the first layer 406a and the second layer 406b) is etched, and the thickness may decrease.

[0150] After the island-shaped oxide semiconductor layer 406 is formed, heat treatment is preferably performed. °C or higher and 650 °C or lower, preferably 300 °C or higher and 400 °C or lower, more preferably 320 °C or higher At temperatures up to 370°C, inert gas atmosphere, atmosphere containing oxidizing gas at 10 ppm or more, Alternatively, the heat treatment may be carried out in a reduced pressure atmosphere. After that, it is possible to perform the process in an atmosphere containing 10 ppm or more of oxidizing gas to compensate for the desorbed oxygen. By the heat treatment here, the gate insulating layer 404 and the oxide semiconductor layer 406 are slightly thinned. At the very least, impurities such as hydrogen and water can be removed from the first stage. The first oxide semiconductor film 407a and the second oxide semiconductor film 407b are processed into island shapes. That's fine.

[0151] Next, the insulating layer 408 is formed over the oxide semiconductor layer 406 (see FIG. 14C).

[0152] The insulating layer 408 is formed using a single layer or a stacked layer of the same material as the gate insulating layer 404. It is possible.

[0153] In this embodiment, the insulating layer 408 is formed by using an insulating layer 408a which is an oxide insulating layer and a nitride insulating layer The insulating layer 408a has a stacked structure of a silicon oxynitride film, an insulating layer 408b made of a silicon oxynitride film, and an insulating layer 408c made of a silicon oxynitride film. The insulating layer 408a is a silicon nitride film having a stoichiometric composition. It is more preferable that the oxygen-excess region has a region containing oxygen in excess of the oxygen-excess region.

[0154] After the insulating layer 408a is formed, heat treatment is preferably performed. Part of oxygen contained in a is transferred to the oxide semiconductor layer 406. The heat treatment can be performed under the condition that the oxide semiconductor layer 406 is formed after the formation of the oxide semiconductor layer 406. The heat treatment can be the same as that described above.

[0155] Next, the insulating layer 408 is processed into a desired region, whereby a contact that reaches the oxide semiconductor layer 406 is formed. A contact hole 409 is formed (see FIG. 14(D)).

[0156] Note that the contact hole 409 is formed so that part of the oxide semiconductor layer 406 is exposed. When the contact hole 409 is formed, the second layer 406b of the oxide semiconductor layer 406 is slightly At least a part of the second layer 406b overlapping the contact hole 409 is removed to reduce the thickness of the second layer 406b. Alternatively, when forming the contact hole 409, the first layer 406a It is preferable to form a contact hole in the second layer 406b so that a part of .

[0157] By removing a part of the second layer 406b or forming a contact hole in the second layer 406b, As a result, the source electrode layer 410a and the drain electrode layer 410b to be formed later are formed in the oxide semiconductor layer 406. The thickness of the film at the position where it contacts the electrode layer 410b can be made smaller than the other film thicknesses. As a result, the oxide semiconductor layer 406, the source electrode layer 410a, and the drain electrode layer 410b As described above, the second layer 40 is preferably formed by the above-mentioned method. 6b has a higher concentration of element M (M is Al, Ga, This is the region where the atomic ratio of indium is high. The higher the atomic ratio of element M to Since the gap between the first and second layers 406a and 406b is large, the second layer 406b has a higher insulating property than the first layer 406a. Therefore, the source electrode layer 410a and the drain electrode layer 410b formed later are In order to reduce the contact resistance between the second layer 406b and the oxide semiconductor layer 406, It is effective to reduce the film thickness of the second layer 406b or remove a part of the second layer 406b.

[0158] The contact hole 409 can be formed by, for example, dry etching. However, the method for forming the contact hole 409 is not limited to this. Wet etching or a combination of dry and wet etching methods It may also be a forming method.

[0159] Next, a conductive film is formed on the contact hole 409 and the insulating layer 408 and processed. By this, the source electrode layer 410a and the drain electrode layer 410b are formed (see FIG. 14(E)). (see).

[0160] The conductive film to be the source electrode layer 410a and the drain electrode layer 410b is made of aluminum. Aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver tantalum, or tungsten, or an alloy with this as its main component. It can be used as a layer structure or a laminate structure. For example, a titanium film on an aluminum film. Two-layer structure with a titanium film laminated on a tungsten film, two-layer structure with a copper-magnesium film laminated on a tungsten film, A two-layer structure in which a copper film is laminated on a titanium-aluminum alloy film, a titanium film or a titanium nitride film, An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and A three-layer structure in which a titanium film or titanium nitride film is formed on top of the molybdenum film or molybdenum nitride film a molybdenum film and an aluminum film or A three-layer structure in which a copper film is laminated and a molybdenum film or molybdenum nitride film is formed on top of that It should be noted that transparent conductive materials containing indium oxide, tin oxide, or zinc oxide may also be used. The conductive film can be formed by, for example, a sputtering method.

[0161] Through the above steps, a channel protective transistor 460 can be formed.

[0162] <Configuration Example 3 of Semiconductor Device> FIG. 15 shows a configuration example of the transistor 350. The transistor 350 is the same as that shown in FIG. 3. The transistor has a top-gate structure with a stacked structure as explained in FIG. 15( 15(A) is a plan view of the transistor 350, and FIG. 15(B) is a diagram showing the V3-W3 15(C) is a cross-sectional view taken along the line X3-Y3 in FIG. 15(A). .

[0163] The components of the transistor 350 are mostly the same as those shown above, except for the stacking order. This is common to the top-gate structure transistor. The description may be omitted as it is possible to refer to the explanation.

[0164] The transistor 350 shown in FIG. 15 includes an island-shaped transistor on an insulating layer 308 provided on a substrate 300. The oxide semiconductor layer 316 and the source electrode layer 31 electrically connected to the oxide semiconductor layer 316 and the source electrode layer 310a and the drain electrode layer 310b. the gate insulating layer 304 in contact with a part of the oxide semiconductor layer 316 exposed from the gate insulating layer 304; and a gate electrode layer 302 overlapping the oxide semiconductor layer 316 with the gate electrode layer 304 interposed therebetween.

[0165] The oxide semiconductor layer 316 included in the transistor 350 is a first layer in which a channel is formed. 316a, a second layer 316b between the first layer 316a and the insulating layer 308, and a second layer 316b between the first layer 316a and the insulating layer 308. and a third layer 316c between the first layer 16a and the gate insulating layer 304. The first layer 316a, the second layer 316b and the third layer 316c are each an oxide semiconductor containing nanocrystals. The first layer 106a, the second layer 106b, and the third layer 106c shown in the first embodiment are the same as those shown in the first embodiment. These correspond to 06c, respectively.

[0166] The first layer 316a, the second layer 316b, and the third layer 316c are each made of indium. The second layer 316b and the third layer 316c contain aluminum and zinc as constituent elements. The energy of the band edge is 0.5 times lower than the energy of the conduction band edge of the first layer 316a. The range of 0.5 eV to 2 eV is close to the vacuum level.

[0167] In the transistor 350, the insulating layer 308 serving as a base insulating layer is formed from the substrate 300. In addition to preventing the diffusion of impurities from the second layer 316b and / or the first layer 31 Therefore, an insulating layer containing oxygen is used for the insulating layer 308. The details can be the same as those of the insulating layer 408a. When oxygen is supplied from the oxide semiconductor layer 316, oxygen vacancies in the oxide semiconductor layer 316 can be reduced. In addition, when other semiconductor elements are formed on the substrate 300, the insulating layer 308 It also functions as an interlayer insulating film. In that case, CMP (chemical mechanical polishing) is used to make the surface flat. Flattening treatment should be performed using methods such as mechanical polishing. is preferred.

[0168] <Configuration Example 4 of Semiconductor Device> 16 shows a configuration example of the transistor 360. The transistor 360 is a transistor 35 16(A) is a top-gate transistor with a partially different structure from that of the transistor shown in FIG. 16(B) is a plan view of the transistor 360, and FIG. 16(B) is a plan view of the transistor 360 at V4-W4 in FIG. 16(A). 16(C) is a cross-sectional view taken along line X4-Y4 of FIG. 16(A).

[0169] The transistor 360 shown in FIG. 16 includes an island-shaped transistor on an insulating layer 308 provided on a substrate 300. The oxide semiconductor layer 316 and the source electrode layer 31 electrically connected to the oxide semiconductor layer 316 The gate insulating layer 304 is in contact with the oxide semiconductor layer 316. The gate electrode layer 300 overlaps the oxide semiconductor layer 316 via the gate insulating layer 304. 2 and includes.

[0170] The oxide semiconductor layer 316 includes a first layer 316a, a second layer 316b, and a third layer 316c. The second layer 316b is provided on and in contact with the insulating layer 308, and the first layer 316a is provided on the second The source electrode layer 310a and the drain electrode layer 310b are provided on and in contact with the source electrode layer 310a and the drain electrode layer 310b. , the island-shaped second layer 316b and one side of the first layer 316a and the top surface of the first layer 316a The third layer 316c is provided to cover a part of the source electrode layer 310a and the drain electrode layer 310b. The source electrode layer 310a and the drain electrode layer 310b are disposed on the The first layer 316a is in contact with a part of the first layer 316a exposed from the first layer 316a.

[0171] As shown in FIG. 16B, the transistor 360 has an island-shaped second The third layer 316c covers the side surfaces of the first layer 316b and the first layer 316a. The side surface of the gate insulating layer 304 is covered with the gate insulating layer 304. The influence of a parasitic channel that may occur at the end of the oxide semiconductor layer 316 in the W longitudinal direction is reduced. This can be done.

[0172] As shown in FIGS. 16A and 16C, the third layer 316c and the gate insulating layer The gate electrode layer 304 has the same planar shape as the gate electrode layer 302. The upper end of the third layer 316c coincides with the lower end of the gate insulating layer 304. The upper end of 304 coincides with the lower end of the gate electrode layer 302. Using the electrode layer 302 as a mask (or the same mask as that used to form the gate electrode layer 302), The third layer 316c and the gate insulating layer 304 are processed using a mask. In this specification, the expressions "same" or "match" do not mean exactly the same or is used in the sense that it does not require a match, and includes in its scope nearly identical or roughly identical. For example, the degree of coincidence in the shapes obtained by etching using the same mask is included. Includes.

[0173] <Method 2 for manufacturing semiconductor device> An example of a method for manufacturing the transistor 360 shown in FIGS. 16A and 16B will be described with reference to FIGS.

[0174] First, the insulating layer 308 and the second oxide semiconductor film 316b are formed on the substrate 300. 317b and a first oxide semiconductor film 317a to be the first layer 316a (FIG. 17 (See (A)).

[0175] The insulating layer 308 may be a single layer or a multilayer. The region in contact with the compound semiconductor layer 316 is formed of a material containing oxygen. It is preferable to form the layer.

[0176] In addition, it is preferable that the insulating layer 308 has a reduced hydrogen concentration. After the layer 308 is formed, a heat treatment (dehydration treatment or dehydrogenation treatment) is performed to remove hydrogen. Note that oxygen may be released from the insulating layer 308 by the heat treatment. Therefore, a process of introducing oxygen into the insulating layer 308 that has been subjected to dehydration or dehydrogenation treatment is performed. It is preferable to do so.

[0177] The second oxide semiconductor film 317b is formed using a material and a method similar to those of the second oxide semiconductor film 407b. The first oxide semiconductor film 317a can be formed of the first oxide semiconductor It can be formed using the same material and method as the film 407a.

[0178] After the second oxide semiconductor film 317b and the first oxide semiconductor film 317a are formed, heat treatment is performed. The heat treatment is preferably carried out at a temperature of 250°C or higher and 650°C or lower, and more preferably at a temperature of 300°C or higher and 50°C or lower. At temperatures below 0°C, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or The heat treatment can be carried out in a high pressure atmosphere. In addition, the treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas to compensate for the desorbed oxygen.

[0179] Next, the second oxide semiconductor film 317b and the first oxide semiconductor film 317a are processed to form islands. The second layer 316b and the first layer 316a are formed in a shape similar to that of the first layer 316a. The first layer 316a and the second layer 316b can be processed by etching using the same mask. Therefore, the second layer 316b and the first layer 316a have the same planar shape. The upper end of b coincides with the lower end of the first layer 316a.

[0180] Note that when processing the second layer 316b and the first layer 316a, the second oxide semiconductor film 3 By over-etching 17b, a part of the insulating layer 308 (from the island-shaped second layer 316b) The exposed areas may be etched and the film thickness reduced.

[0181] Next, a conductive film is formed over the first layer 316a and processed to form the source electrode layer 310a. A drain electrode layer 310b is formed (see FIG. 17B).

[0182] In this embodiment, the end portions of the source electrode layer 310a and the drain electrode layer 310b The edge is formed in a stepped shape with multiple steps. The process of recessing the mask and the process of etching are alternately performed multiple times. can.

[0183] In this embodiment, the ends of the source electrode layer 310a and the drain electrode layer 310b Although the example shows a shape with two steps in the part, the number of steps may be three or more. The number of stages may be one without performing resist ashing between the source electrode layer 310a and the source electrode layer 310b. It is preferable to increase the number of steps as the thickness of the drain electrode layer 310b increases. The edges of the source electrode layer 310a and the drain electrode layer 310b do not have to be symmetrical. A curved surface having an arbitrary radius of curvature may be formed between the upper surface and the cross section of each step shape. .

[0184] The source electrode layer 310a and the drain electrode layer 310b are formed in the above-described shape having a plurality of steps. By doing so, the films formed thereover, specifically, the third layer 316c, the gate insulating film The covering property of the insulating layer 304 etc. is improved, and the electrical characteristics and long-term reliability of the transistor are improved. This can be done.

[0185] When processing the source electrode layer 310a and the drain electrode layer 310b, the overcoat of the conductive film is By etching, a part of the insulating layer 308 and a part of the first layer 316a (the source electrode layer The exposed areas of the drain electrode layer 310a and the drain electrode layer 310b are etched to reduce the thickness. This may happen.

[0186] Note that the conductive film to be the source electrode layer 310a and the drain electrode layer 310b is left as residue. If the residue remains on the first layer 316a, it may cause impurities in the first layer 316a or at the interface. Alternatively, the residue may cause oxygen to be drawn from the first layer 316a. This can result in the formation of oxygen vacancies.

[0187] Therefore, after the source electrode layer 310a and the drain electrode layer 310b are formed, the first layer 316a The surface may be subjected to a residue removal treatment. The residue removal treatment may be performed by etching (e.g., wafer or plasma treatment using oxygen or nitrous oxide. The residue removal process can be carried out by removing the source electrode layer 310a and the drain electrode layer 310b. The thickness of the part of the first layer 316a exposed between the inner electrode layers 310b is 1 nm or more and 3 nm or less. may be reduced to a certain extent.

[0188] Next, a third layer 316c is formed on the source electrode layer 310a and the drain electrode layer 310b. A third oxide semiconductor film 317c and a gate insulating film 303 to be used as a gate insulating layer 304 are stacked. (See FIG. 17(C)).

[0189] Note that the third oxide semiconductor film 317c and the gate insulating film 303 are successively formed without being exposed to the air. When the third oxide semiconductor film 317c is formed in this manner, impurities such as hydrogen and moisture are adsorbed to the surface of the third oxide semiconductor film 317c. This is preferable because it can prevent this.

[0190] The third oxide semiconductor film 317c is formed using a material and a method similar to those of the second oxide semiconductor film 317b. It can be formed using:

[0191] The gate insulating film 303 is formed using the same material and method as the gate insulating layer 404. can be done.

[0192] Next, the gate electrode layer 302 is formed on the gate insulating film 403. The third oxide semiconductor film 317c and the gate insulating film 303 are processed using the layer 302 as a mask. Thus, the third layer 316c and the gate insulating layer 304 are formed (see FIG. 17D). The third layer 316c and the gate insulating layer 304 are formed in a self-aligned manner using the electrode layer 302 as a mask. This is preferable because it does not increase the number of masks.

[0193] The gate electrode layer 302 is formed using a material and a method similar to those of the gate electrode layer 402. can be done.

[0194] The third oxide semiconductor film 317c is processed into the third layer 316c, whereby the third layer 316 The out-diffusion of indium contained in c can be suppressed. This can cause fluctuations in the electrical characteristics of transistors and can also cause contamination in the film formation chamber during the process. Therefore, it is effective to process the third layer 316c using the gate electrode layer 302 as a mask.

[0195] In this manner, the transistor 360 can be manufactured.

[0196] The transistor described in this embodiment has the stacked structure described in Embodiment 1 and has an oxide semiconductor layer. By providing a third layer between the first layer in which a channel is formed and the insulating layer, oxidation can be prevented. Since the interface of the compound semiconductor layer and the channel can be separated, the influence of the interface state on the channel can be minimized. In addition, the first to third layers can be formed of an amorphous oxide semiconductor. It is made up of nanocrystalline oxide semiconductors with reduced defect state density compared to conventional semiconductors. By using the oxide semiconductor layer including the reduced first to third layers in a transistor, Fluctuations in the electrical characteristics of the transistor can be reduced, and reliability can be improved.

[0197] As described above, the structures, methods, etc. described in this embodiment are applicable to the structures, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0198] (Embodiment 3) As an example of a semiconductor device according to one embodiment of the present invention, a circuit diagram of a NOR circuit, which is a logic circuit, is shown in FIG. An example is shown in Figure 18(A), and Figure 18(B) is a circuit diagram of a NAND type circuit.

[0199] In the NOR circuit shown in FIG. 18(A), the transistor is a p-channel transistor. The transistors 801 and 802 have a channel formation region made of a semiconductor material other than an oxide semiconductor (for example, silicon The transistor is an n-channel transistor (e.g., a capacitor). The transistors 03 and 804 include an oxide semiconductor and have a structure similar to that of the transistor described in Embodiment 2. A transistor that

[0200] Transistors made of semiconductor materials such as silicon can easily operate at high speeds. A transistor using a semiconductor can retain charge for a long period of time due to its characteristics.

[0201] To miniaturize the logic circuit, n-channel transistors 803 and 8 04 is stacked on p-channel transistors 801 and 802. For example, it is preferable to form the transistors 801 and 802 using a single crystal silicon substrate. Transistors 803 and 804 are formed on the transistors 801 and 802 via an insulating layer. It is possible to achieve this.

[0202] In the NAND circuit shown in FIG. 18(B), the transistor is a p-channel transistor. The transistors 811 and 814 have channel formation regions formed of a semiconductor material other than an oxide semiconductor (for example, The transistor is an n-channel transistor, and the transistor is made of silicon. The transistors 812 and 813 include an oxide semiconductor layer and are the same as the transistors described in Embodiment 2. A transistor having a different structure is used.

[0203] In addition, similar to the NOR circuit shown in FIG. 18(A), in order to reduce the size of the logic circuit, The transistors 812 and 813 are p-channel transistors. It is preferably stacked on certain transistors 811 and 814 .

[0204] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using transistors with extremely small capacitance, power consumption can be significantly reduced. .

[0205] In addition, stacking semiconductor elements using different semiconductor materials allows for miniaturization and high integration. A semiconductor device that realizes the above and is provided with stable and high electrical characteristics, and manufacturing method of the semiconductor device A method can be provided.

[0206] Furthermore, by applying the structure of a transistor including an oxide semiconductor layer according to one embodiment of the present invention, This allows us to provide NOR and NAND circuits that are highly reliable and exhibit stable characteristics. Cut.

[0207] In this embodiment, a NOR circuit using the transistor described in Embodiment 2 and an NOR circuit using the transistor described in Embodiment 2 are used. Although an example of an AND circuit is shown, the present invention is not particularly limited to this, and the transistors shown in Embodiment 2 may be used. It is also possible to form AND circuits, OR circuits, etc.

[0208] Alternatively, the transistor described in this embodiment or another embodiment may be combined with a display element. For example, a display device can be configured by combining a display element and a device having a display element. Display devices, light emitting devices, and light emitting devices having light emitting elements are available in various forms. It can be used or have various elements. An example of a light-emitting device is an EL (electroluminescence) element (organic or inorganic material). EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green color LEDs, blue LEDs, etc.), transistors (transistors that emit light according to the current), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GL V), plasma display panel (PDP), digital micromirror device (DM D) Piezoelectric ceramic displays, carbon nanotubes, etc., which are based on electromagnetic effects Some have display media with variable contrast, brightness, reflectance, transmittance, etc. An example of a display device using an EL element is an EL display. An example of a display device using the above is a field emission display (FED) or SED type flat panel display (SED: Surface-conduction El Display devices using liquid crystal elements include An example of such a device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCDs (e.g., reflective LCDs, direct-view LCDs, projection LCDs) An example of a display device using electronic ink or electrophoretic elements is electronic paper. etc.

[0209] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0210] (Fourth embodiment) In this embodiment, the transistor described in Embodiment 2 is used, and the transistor is used in a state where power is not supplied. However, it is possible to retain memory contents and there is no limit to the number of times it can be written. An example of this will be explained with reference to the drawings.

[0211] FIG. 19A is a circuit diagram showing the semiconductor device of this embodiment.

[0212] The transistor 260 illustrated in FIG. 19A is made of a semiconductor material other than an oxide semiconductor (for example, It is possible to apply transistors using silicon or the like, which makes high-speed operation easy. The transistor 262 includes an oxide semiconductor layer of one embodiment of the present invention, and is the same as the transistor described in Embodiment 2. A transistor having a structure similar to that of a transistor can be applied, and its characteristics allow for long-term This allows for charge retention over time.

[0213] It should be noted that the above transistors are all n-channel transistors. However, the transistor used in the semiconductor device described in this embodiment is a p-channel transistor. A transistor can also be used.

[0214] In FIG. 19A, the first wiring (1st Line) and the source of the transistor 260 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 260. The drain electrode layer is electrically connected to the third wiring (3rd Line ) is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor 262. The fourth line and the gate electrode layer of the transistor 262 are electrically connected to each other. The gate electrode layer of the transistor 260 and the gate electrode layer of the transistor 26 The other of the source electrode layer and the drain electrode layer is electrically connected to one of the electrodes of the capacitor 264. The fifth wiring (5th Line) and the other electrode of the capacitor 264 are electrically connected. is connected.

[0215] In the semiconductor device shown in FIG. 19A, the potential of the gate electrode layer of the transistor 260 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0216] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor 262 is set to a potential at which the transistor 262 is turned on, thereby turning the transistor 262 on. The potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is applied to the gate electrode layer of the transistor 260. (Write). Here, charges that give two different potential levels (hereinafter referred to as Low-level charges) , High level charge) is given. Then, the fourth wiring The potential of the transistor 262 is set to a potential at which the transistor 262 is turned off. By setting the transistor 260 in this state, the charge applied to the gate electrode layer of the transistor 260 is held. (hold).

[0217] Since the off-state current of the transistor 262 is extremely small, the gate electrode layer of the transistor 260 The charge is retained for a long time.

[0218] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, Then, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 260 The second wiring has a different potential depending on the amount of charge held in the electrode layer. If the transistor 260 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 260. The apparent threshold voltage V for a given charge th_H is the gate of transistor 260. The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 260 is turned on. This refers to the potential of the fifth wiring required to achieve the "state." The potential of V th_H and V th_L By setting the potential V0 between For example, in writing, the charge given to the gate electrode layer can be determined. If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) then When a low level charge is applied, transistor 260 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 260 remains "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0219] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 260 is in the "off state" regardless of V th_H Alternatively, a smaller potential may be applied to the fifth wiring. The potential at which transistor 260 is in the "on" state, i.e., V th_L Larger potential is given to the fifth wire.

[0220] FIG. 19B shows an example of a structure of a different memory device. 19(C) is a conceptual diagram showing an example of a semiconductor device. The semiconductor device shown in FIG. 19(B) will be described first, followed by the semiconductor device shown in FIG. 19(C). The location will be explained below.

[0221] In the semiconductor device shown in FIG. 19B, the bit line BL and the source voltage of the transistor 262 The gate or drain electrode of the transistor 262 is electrically connected to the word line WL. The source electrode layer is electrically connected to the source electrode or drain electrode of the transistor 262. The first terminal of the capacitor 254 is electrically connected.

[0222] The transistor 262 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 262 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long time. It is possible to retain it.

[0223] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. 19(B). This section explains how to do this.

[0224] First, the potential of the word line WL is set to a potential at which the transistor 262 is turned on. The transistor 262 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 262 is turned off, the capacitance The potential of the first terminal of the capacitance element 254 is held (held).

[0225] Since the off-state current of the transistor 262 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitance element) can be held for a long period of time.

[0226] Next, the reading of information will be described. When the transistor 262 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0227] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB× VB0+C×V0) / (CB+C)).

[0228] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0229] As described above, in the semiconductor device illustrated in FIG. 19B, the off-state current of the transistor 262 is extremely low. Because of its small size, the charge stored in the capacitance element 254 can be maintained for a long time. In other words, refresh operations become unnecessary or the frequency of refresh operations can be reduced. This allows the power consumption to be reduced significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. be.

[0230] Next, the semiconductor device shown in FIG. 19C will be described.

[0231] The semiconductor device shown in FIG. 19C has the memory cell shown in FIG. 19B as a memory circuit thereon. The memory cell array 251a and the memory cell array 251b each have a plurality of memory cells 250. At the bottom, the memory cell array 251 (memory cell array 251a and memory cell array 25 1b) has a peripheral circuit 253 necessary for operating the memory. The memory cell array 251 is electrically connected to the memory cell array 251 .

[0232] By using the configuration shown in FIG. 19C, the peripheral circuit 253 is connected to the memory cell array 251. (memory cell array 251a and memory cell array 251b) Therefore, the semiconductor device can be made smaller.

[0233] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 262. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0234] In the semiconductor device shown in FIG. 19(C), two memory cell arrays 251 (memory cells In the illustrated example, a stacked memory cell array 251a and a stacked memory cell array 251b are used. The number of memory cell arrays to be stacked is not limited to this. It may also be configured as follows.

[0235] The transistor 262 includes an oxide semiconductor layer of one embodiment of the present invention in a channel formation region. By using transistors with this property, it is possible to retain memory contents for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low. Since it is possible to make a semiconductor memory device with the smallest possible power consumption, power consumption can be reduced sufficiently. can be done.

[0236] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0237] (Embodiment 5) In this embodiment, a structure of a display panel of one embodiment of the present invention will be described with reference to FIGS. explain.

[0238] FIG. 20A is a top view of a display panel according to one embodiment of the present invention, and FIG. 20B is a top view of a display panel according to one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention is 20C is a circuit diagram for explaining a display panel according to one embodiment of the present invention. A circuit diagram for explaining a pixel circuit that can be used when an organic EL element is used as the substrate. is.

[0239] The transistor disposed in the pixel portion can be formed according to Embodiment 2. Since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be configured with transistors of the same substrate as the transistors in the pixel section. In this way, the transistor described in Embodiment 3 is used in the pixel portion and the driver circuit. This makes it possible to provide a highly reliable display device.

[0240] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 500, a pixel section 501, a first scanning line driving circuit 502, a second scanning line driving circuit The pixel portion 501 has a signal line driver circuit 503 and a signal line driver circuit 504. A plurality of scanning lines are arranged extending from the first scanning line driving circuit 502, and The scanning line driving circuit 503 is arranged to extend from the scanning line driving circuit 503. In the display area, pixels each having a display element are arranged in a matrix. The substrate 500 is a connection board for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via .

[0241] In FIG. 20A, a first scanning line driver circuit 502, a second scanning line driver circuit 503, a signal line The driver circuit 504 is formed on the same substrate 500 as the pixel portion 501. This reduces the number of components, such as the drive circuit, that are required on the substrate 5, thereby reducing costs. 00When an external drive circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driving circuit is provided on the same substrate 500, the number of connections between the wirings can be reduced. Therefore, it is possible to improve reliability or yield.

[0242] <LCD panel> An example of the circuit configuration of a pixel is shown in Figure 20(B). 1 shows a pixel circuit that can be applied to the pixel.

[0243] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0244] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are , are separated so that different gate signals can be applied. The functional source or drain electrode layer 514 is connected to the transistor 516 and the transistor The transistors 516 and 517 are used in common. The transistors described in 2 can be used appropriately. This allows for a highly reliable liquid crystal display. A display panel can be provided.

[0245] A first pixel electrode layer electrically connected to the transistor 516 and a second pixel electrode layer electrically connected to the transistor 517 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The electrode layers are separated by slits. The first pixel electrode layer extends in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0246] The gate electrode layer of the transistor 516 is connected to the gate wiring 512, and the gate electrode layer of the transistor 517 is connected to the gate wiring 512. The gate electrode layer of this gate electrode is connected to the gate wiring 513. 13, different gate signals are applied to transistors 516 and 517. By varying the orientation, the orientation of the liquid crystal can be controlled.

[0247] Also, the capacitor wiring 510, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0248] The multi-domain structure has a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 519 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0249] Note that the pixel circuit shown in FIG. 20(B) is not limited to this. The pixel is newly equipped with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit. Any of these may be added.

[0250] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 20(C). 1 shows the pixel structure of the display panel.

[0251] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0252] FIG. 20(C) is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0253] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, I will explain.

[0254] The pixel 520 includes a switching transistor 521, a driving transistor 522, and a light-emitting element The switching transistor 521 has a gate electrode 524 and a capacitance element 523. The source electrode layer is connected to the scanning line 526, and the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the scanning line 526. ) is connected to a signal line 525, and the second electrode (the other of the source electrode layer and the drain electrode layer) is The driving transistor 522 is connected to the gate electrode layer of the driving transistor 522. The gate electrode layer is connected to a power supply line 527 via a capacitor element 523, and the first electrode is connected to the power supply line 527. 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. The second electrode of the light emitting element 524 corresponds to a common electrode 528. The common electrode 528 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed on the substrate.

[0255] The switching transistor 521 and the driving transistor 522 are the same as those described in the third embodiment. This allows for the use of transistors that illuminate the display, thereby enabling highly reliable organic EL displays. A panel can be provided.

[0256] The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential set on the power supply line 527, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 524, a current flows through the light emitting element 524, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and is at least the forward threshold. Includes low voltages.

[0257] The capacitance element 523 can be reduced by substituting the gate capacitance of the driving transistor 522. The gate capacitance of the driving transistor 522 can be omitted. A capacitance may be formed between the electrode layer and the insulating layer.

[0258] Next, a description will be given of the signal input to the driving transistor 522. In this case, the driving transistor 522 is either fully on or fully off. A video signal such as this is input to the driving transistor 522. In order to operate the drive transistor 522 in the linear region, a voltage higher than the voltage of the power supply line 527 is applied to the drive transistor 522. A signal line 525 is connected to the gate electrode layer of the transistor 522. A voltage equal to or greater than the threshold voltage Vth of the power transistor 522 is applied.

[0259] When analog gradation driving is performed, the gate electrode layer of the driving transistor 522 is connected to the light emitting element 52 A voltage equal to or greater than the sum of the forward voltage of the transistor 4 and the threshold voltage Vth of the driving transistor 522 is applied. In addition, a video signal is input so that the driving transistor 522 operates in the saturation region. A current flows through the light emitting element 524. In addition, the driving transistor 522 is operated in a saturation region. In order to achieve this, the potential of the power supply line 527 is set higher than the gate potential of the driving transistor 522. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 524. , analog gray scale driving can be performed.

[0260] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) The pixel circuit includes a switch, a resistor, a capacitor, a sensor, a transistor, or a logic Circuits etc. may be added.

[0261] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0262] (Embodiment 6) In this embodiment, a semiconductor device and an electronic device including an oxide semiconductor layer according to one embodiment of the present invention will be described. The configuration will be described with reference to FIGS. 21 and 22.

[0263] FIG. 21 shows a block diagram of an electronic device including a semiconductor device to which an oxide semiconductor layer of one embodiment of the present invention is applied. This is a block diagram.

[0264] FIG. 22 illustrates an external view of an electronic device including a semiconductor device including an oxide semiconductor layer of one embodiment of the present invention. Figure.

[0265] The electronic device shown in FIG. 21 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, and a A baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, flash memory 910, display controller 911, memory circuit 91 2. Display 913, touch sensor 919, audio circuit 917, keyboard 918, etc. It is composed of:

[0266] The application processor 906 includes a CPU 907, a DSP 908, and an interface ( The memory circuit 912 is configured by an SRAM or a DRAM. It is possible.

[0267] By applying the transistor described in Embodiment 2 to the memory circuit 912, Therefore, it is possible to provide a highly reliable electronic device capable of writing and reading data.

[0268] Furthermore, the transistor described in the second embodiment may be included in the CPU 907 or the DSP 908. By applying this to registers, etc., it is possible to write and read information with high reliability. It is possible to provide high-quality electronic equipment.

[0269] Note that when the off-leak current of the transistor described in Embodiment 2 is extremely small, It is possible to provide a memory circuit 912 that can store data for a long period of time and consumes a sufficient amount of power. During the power gating period, the state before power gating is registered. A CPU 907 or DSP 908 may be provided, which may store the data in a memory or the like.

[0270] The display 913 includes a display unit 914, a source driver 915, a gate driver 91 It consists of 6.

[0271] The display unit 914 has a plurality of pixels arranged in a matrix. Each pixel includes a pixel circuit. The pixel circuit is electrically connected to a gate driver 916 .

[0272] The transistor described in Embodiment 2 is used as appropriate in the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

[0273] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), cameras such as digital cameras and digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0274] FIG. 22A shows a portable information terminal, which includes a main body 1101, a housing 1102, a display unit 110 The display unit 1103b is a touch panel. The screen can be operated by touching keyboard buttons 1104 displayed on the display unit 1103b. Of course, the display unit 1103a can be configured as a touch panel. The transistor described in Embodiment 3 may be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 1103a and 1103b, reliability can be improved. It can be a highly portable information terminal.

[0275] The portable information terminal shown in FIG. 22(A) displays various information (still images, moving images, text images, etc.) ), calendar, date or time display function, The ability to manipulate or edit the displayed information, and to process it using various software (programs) It can also have external connection terminals ( It may also be configured to include an earphone terminal, a USB terminal, a recording medium insertion portion, etc.

[0276] The portable information terminal shown in FIG. 22(A) can also be configured to transmit and receive information wirelessly. You can purchase and download desired book data from an electronic book server wirelessly. It is also possible to configure it in this way.

[0277] FIG. 22(B) shows a portable music player, and the main body 1021 has a display unit 1023 and an earphone. A fixing part 1022 for mounting, a speaker, an operation button 1024, an external memory slot The transistor shown in the third embodiment is used as a switching element. By manufacturing a liquid crystal panel or an organic light-emitting panel as a display unit 1023, This makes it possible to make a more reliable portable music player.

[0278] Furthermore, the portable music player shown in FIG. 22(B) has an antenna, a microphone function, and a wireless function. In addition, if you connect it to a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversations are also possible via the internet.

[0279] FIG. 22C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 is provided with a display panel 1032, a speaker 1033, a microphone, and the like. 1034, pointing device 1036, camera lens 1037, external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The housing 10 is provided with an antenna. The transistor described in Embodiment 3 is built in the display panel 1032. By applying this technology, a highly reliable mobile phone can be achieved.

[0280] The display panel 1032 is equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. The operation keys 1035 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0281] For example, the power transistor used in a power supply circuit such as a booster circuit is also described in the third embodiment. The thickness of the oxide semiconductor layer of the transistor is set to 2 μm to 50 μm. It is possible.

[0282] The display direction of the display panel 1032 changes appropriately depending on the usage mode. The camera lens 1037 is located on the same surface as the camera 1032, so video calls are possible. The speaker 1033 and microphone 1034 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 1030 and the housing 1031 can be slid apart. As shown in 22(C), it can be folded from the unfolded state to the overlapping state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0283] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 1041 to accommodate the storage and transfer of larger amounts of data. do.

[0284] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0285] FIG. 22(D) shows an example of a television device. The television device 1050 includes: A display unit 1053 is built into the housing 1051. The display unit 1053 displays images. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the third embodiment is applied to the display unit 1053 and the CPU. This makes it possible to provide television device 1050 with high reliability.

[0286] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0287] The television device 1050 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0288] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable or the like. It can be connected to various cables, enabling data communication with a personal computer, etc. The storage medium playback / recording unit 1052 receives a disc-shaped recording medium and records the data on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted into the slot. It is also possible to display it on the display unit 1053.

[0289] In addition, when the off-leak current of the transistor described in Embodiment 2 is extremely small, By applying this transistor to the external memory 1056 or CPU, power consumption is sufficiently reduced. This results in a television device 1050 with reduced reliability.

[0290] As described above, the structures, methods, etc. described in this embodiment are applicable to the structures, methods, etc. described in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0291] 102 gate electrode layer 104 Gate insulating layer 106 Oxide semiconductor layer 106a layer 106b layer 106c layer 108 Insulating layer 110 Semiconductor layer 116 Oxide semiconductor layer 116a layer 116b layer 116c layer 124 insulating film 200 Quartz glass substrate 202 Dummy board 204 Oxide semiconductor layer 208 Oxide semiconductor film 208a Oxide semiconductor layer 208b Oxide semiconductor layer 210a area 210b area 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b memory cell array 253 Peripheral Circuits 254 Capacitor 260 transistors 262 transistors 264 Capacitive Element 300 boards 302 gate electrode layer 303 Gate insulating film 304 Gate insulating layer 308 Insulation Layer 310a Source electrode layer 310b drain electrode layer 314a Oxide semiconductor layer 314b Oxide semiconductor layer 316 Oxide semiconductor layer 316a layer 316b layer 316c layer 317a Oxide semiconductor film 317b Oxide semiconductor film 317c Oxide semiconductor film 350 transistors 360 Transistor 400 boards 402 gate electrode layer 403 Gate insulating film 404 Gate insulating layer 404a Insulating layer 404b Insulating layer 406 Oxide semiconductor layer 406a layer 406b layer 407a Oxide semiconductor film 407b Oxide semiconductor film 408 Insulating Layer 408a Insulating layer 408b Insulating layer 409 Contact Hole 410a Source electrode layer 410b drain electrode layer 450 transistors 460 transistors 500 boards 501 Pixel unit 502 Scanning line driving circuit 503 Scanning line driving circuit 504 Signal line driver circuit 510 Capacitance wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 pixels 521 Switching Transistor 522 Drive transistor 523 Capacitor 524 Light-emitting element 525 signal line 526 scan lines 527 Power line 528 Common electrode 801 transistors 802 transistors 803 Transistor 804 transistor 811 Transistor 812 transistors 813 Transistor 814 transistors 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 keyboard 919 Touch Sensor 1021 Main Unit 1022 Fixed part 1023 Display section 1024 operation buttons 1025 external memory slots 1030 Case 1031 Case 1032 Display Panel 1033 Speaker 1034 Microphone 1035 Operation Key 1036 Pointing Device 1037 Camera Lenses 1038 External connection terminal 1040 solar cell 1041 External memory slot 1050 Television Equipment 1051 Case 1052 Storage media playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 external memory 1101 Main unit 1102 Case 1103a Display section 1103b Display section 1104 Keyboard Buttons

Claims

1. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region disposed above the first conductive layer; an oxide semiconductor layer having a region disposed above and in contact with the first insulating layer and including a channel formation region of a transistor; a second insulating layer having a region disposed above and in contact with the oxide semiconductor layer; a second conductive layer having a region disposed above the second insulating layer and functioning as a source electrode or a drain electrode of the transistor; the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer has a region disposed above and in contact with the first oxide semiconductor layer; the first oxide semiconductor layer and the second oxide semiconductor layer each contain an In-M-Zn oxide (M is Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf); an atomic ratio of M to In in the second oxide semiconductor layer is higher than an atomic ratio of M to In in the first oxide semiconductor layer; the second insulating layer has a contact hole; the first oxide semiconductor layer has a region that overlaps with the contact hole and is in contact with the second conductive layer.

2. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region disposed above the first conductive layer; an oxide semiconductor layer having a region disposed above and in contact with the first insulating layer and including a channel formation region of a transistor; a second insulating layer having a region disposed above and in contact with the oxide semiconductor layer; a second conductive layer having a region disposed above the second insulating layer and functioning as a source electrode or a drain electrode of the transistor; the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer has a region disposed above and in contact with the first oxide semiconductor layer; the first oxide semiconductor layer and the second oxide semiconductor layer each contain an In-M-Zn oxide (M is Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf); an atomic ratio of M to In in the second oxide semiconductor layer is higher than an atomic ratio of M to In in the first oxide semiconductor layer; the second insulating layer has a contact hole; the first oxide semiconductor layer has a region that overlaps with the contact hole and is in contact with the second conductive layer; the contact hole has a shape in which, in a plan view, a width in a channel width direction of the transistor is larger than a width in a channel length direction of the transistor; the contact hole entirely overlaps with the oxide semiconductor layer in plan view.

3. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region disposed above the first conductive layer; an oxide semiconductor layer having a region disposed above and in contact with the first insulating layer and including a channel formation region of a transistor; a second insulating layer having a region disposed above and in contact with the oxide semiconductor layer; a second conductive layer having a region disposed above the second insulating layer and functioning as a source electrode or a drain electrode of the transistor; the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer has a region disposed above and in contact with the first oxide semiconductor layer; the first oxide semiconductor layer and the second oxide semiconductor layer each contain an In-M-Zn oxide (M is Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf); an atomic ratio of M to In in the second oxide semiconductor layer is higher than an atomic ratio of M to In in the first oxide semiconductor layer; the second insulating layer has a contact hole; the first oxide semiconductor layer has a region that overlaps with the contact hole and is in contact with the second conductive layer; the contact hole has a shape in which, in a plan view, a width in a channel width direction of the transistor is larger than a width in a channel length direction of the transistor; the contact hole entirely overlaps with the oxide semiconductor layer in a plan view; In a plan view, the contact hole overlaps with the first conductive layer.

Images