Semiconductor device

Abstract

To provide a semiconductor device which has a novel structure using an oxide semiconductor layer of a novel structure.SOLUTION: A semiconductor device has: a first oxide semiconductor layer which is formed on a substrate having an insulating surface and has a crystalline region grown from the surface toward the inside of the first semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer, which contact the second oxide semiconductor layer; a gate insulation layer which covers the second oxide semiconductor layer, the source electrode layer and the drain electrode layer; and a gate electrode layer on the gate insulation layer in a region which overlaps the second oxide semiconductor layer, in which the second oxide semiconductor layer is a layer having crystal grown from the crystalline region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the disclosed invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof. Here, the semiconductor device is an element or device that functions by utilizing the semiconductor characteristics. This refers to devices in general, such as power devices, thyristors, converters, and image sensors. semiconductor integrated circuits including sensors, memories, and electro-optical devices such as liquid crystal display panels BACKGROUND ART Semiconductor devices include organic light emitting devices and light emitting display devices having organic light emitting elements. [Background technology]

[0002] Field-effect transistors are one of the most widely used semiconductor devices. The materials used for the transistors vary depending on the application. Semiconductor materials containing ZnO are often used.

[0003] Silicon field-effect transistors meet the characteristics required for many applications. For example, single crystal silicon is used for integrated circuits that require high speed operation. This satisfies the demand. In addition, amorphous silicon is used for large area applications such as display devices. By using it, you can meet that requirement.

[0004] As such, silicon is highly versatile and can be used for a variety of purposes. There is a trend toward semiconductor materials that are more versatile and offer greater performance. From the viewpoint of improving the performance of display devices, large-scale switching elements are required to achieve high-speed operation. There is a need for semiconductor materials that can be easily scaled up and have performance that exceeds that of amorphous silicon. .

[0005] In addition, some metal oxides exhibit semiconducting properties, such as tungsten oxide and oxide Known examples of metals that exhibit semiconducting properties include tin oxide, indium oxide, and zinc oxide. Thin film transistors using oxide as a channel forming region are already known (Patent Documents 1 to 4, Non-patent document 1).

[0006] Metal oxides are not only mono-component oxides but also multi-component oxides. For example, homologous InGaO3(ZnO) with phase m (m: natural number) is a polycrystalline silicon containing In, Ga, and Zn. It is known as a metal oxide semiconductor (Non-Patent Documents 2 to 4).

[0007] In this situation, field-effect transistors (also called FETs) using oxide semiconductors have been developed. The technology related to the In-Ga-Zn oxide-based semiconductors mentioned above is attracting attention. It has been confirmed that the oxide semiconductor can be used as a channel layer for thin film transistors. (Non-patent documents 5 and 6).

[0008] For example, Patent Document 5 discloses a homologous compound InMO3(ZnO) m (M=In, Fe, Transparent thin film field effect transistor using Ga or Al, m = integer 1 or more but less than 50 The data is disclosed.

[0009] Patent Document 6 also describes an amorphous oxide semiconductor containing In, Ga, and Zn, which is an electron carrier. The concentration of 18 / cm 3 A field effect transistor using less than In this document, the atomic ratio of the amorphous oxide semiconductor is In:Ga:Zn. =1:1:m(m<6).

[0010] Furthermore, Patent Document 7 discloses a field-effect transistor having an active layer made of an amorphous oxide semiconductor containing microcrystals. A transistor is disclosed. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Patent Document 6] International Publication No. 05 / 088726 [Patent Document 7] Japanese Patent Application Laid-Open No. 2006-165529 [Non-patent literature]

[0012] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650―3652 [Non-patent document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315

Non-patent document 3

Non-patent document 4

Non-patented document 5

Non-patent document 6

[0013] In Patent Document 3, the composition in the crystalline state is InGaO3(ZnO) m (m=less than 6 In addition, in Example 1 of Patent Document 3, it is disclosed that InGaO3 However, the case of (ZnO)4 is disclosed. Even when they are used, the reality is that sufficient properties are not obtained.

[0014] In view of the above problems, a semiconductor device with a new structure using an oxide semiconductor layer with a new structure is provided. One of the objectives is to [Means for solving the problem]

[0015] In the disclosed invention, a semiconductor is formed using an oxide semiconductor layer that is highly purified and has a crystalline region. The crystalline region is, for example, a region that has electrical anisotropy. This is an area that prevents the intrusion of impurities.

[0016] One embodiment of the disclosed invention is a method for forming a first oxide semiconductor layer on a substrate having an insulating surface. a first oxide semiconductor layer having a crystalline region grown toward the first oxide semiconductor layer; a second oxide semiconductor layer on the oxide semiconductor layer, and a source electrode layer and a drain electrode layer in contact with the second oxide semiconductor layer; a gate electrode layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer, a gate electrode layer over the gate insulating layer in a region overlapping with the second oxide semiconductor layer, the second oxide semiconductor layer is a layer having crystals grown from a crystalline region. It is a body device.

[0017] Another embodiment of the disclosed invention is a semiconductor device including: a first gate electrode layer over a substrate having an insulating surface; a first gate insulating layer covering the first gate electrode layer; and a first oxide film on the first gate insulating layer. a first oxide semiconductor layer having a crystalline region grown from the surface toward the inside of the oxide semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; and a second oxide semiconductor layer in contact with the second oxide semiconductor layer. a source electrode layer and a drain electrode layer, a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer; a second gate insulating layer covering the drain electrode layer; and a second oxide semiconductor layer on the second gate insulating layer. a gate electrode layer in a region overlapping with the oxide semiconductor layer, and the second oxide semiconductor layer The semiconductor device is a layer having grown crystals.

[0018] In the above, the height difference of the surface of the second oxide semiconductor layer is In a semiconductor device, the thickness is 1 nm or less (preferably 0.2 nm or less) in the channel forming region. be.

[0019] Note that the crystalline region of the first oxide semiconductor layer is oriented in a direction perpendicular to the surface of the first oxide semiconductor layer. The c-axis of the crystal is oriented in the depth direction.

[0020] In the above structure, the substrate having an insulating surface is a semiconductor device having an oxide or nitride. is.

[0021] In the above structure, the crystalline region of the first oxide semiconductor layer has a thickness of 2 nm to 10 nm. The semiconductor device has the average film thickness shown below.

[0022] In the above structure, the first oxide semiconductor layer or the second oxide semiconductor layer is an In—Sn -Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Z nO, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-M Zn-O, In-O, Sn-O, or any one of metal oxides selected from the group consisting of Zn-O and In-O. It is a semiconductor device.

[0023] In the above structure, the first oxide semiconductor layer or the second oxide semiconductor layer is highly purified. The semiconductor device has an oxide semiconductor layer.

[0024] In the above structure, the first oxide semiconductor layer and the second oxide semiconductor layer contain the same main component. The semiconductor device is made of a material containing

[0025] In the above structure, the first oxide semiconductor layer and the second oxide semiconductor layer are made of different materials. The semiconductor device comprises:

[0026] In the above structure, the crystalline region of the first oxide semiconductor layer and the crystalline region of the second oxide semiconductor layer The semiconductor devices have the same electron affinity.

[0027] In the above structure, the second oxide semiconductor layer is a semiconductor device having a recessed portion.

[0028] In the above structure, the second oxide semiconductor layer is a semiconductor device having a high-purity crystalline region. .

[0029] In the above structure, the carrier density of the first oxide semiconductor layer or the second oxide semiconductor layer is 1.0 x 10 12 cm -3 less than 1.45 x 10 10 cm -3 is less than It is a semiconductor device.

[0030] In the above structure, the crystalline region of the first oxide semiconductor layer is made of a polycrystalline oxide semiconductor material. The second oxide semiconductor layer is made of a polycrystalline oxide semiconductor material. It is a semiconductor device.

[0031] In the above structure, the first oxide semiconductor layer and the second oxide semiconductor layer are both multi-layered. In the above structure, the first oxide semiconductor is a crystalline oxide semiconductor material. The sum of the thicknesses of the conductor layer and the second oxide semiconductor layer is 3 nm or more and 50 nm or less. is.

[0032] In the above structure, a source electrode layer and a drain electrode layer are provided on the source electrode layer and the drain electrode layer. The semiconductor device has an insulating layer having substantially the same shape as the inner electrode layer.

[0033] In the above structure, a material having low affinity for oxygen is used in a portion in contact with the second oxide semiconductor layer. The semiconductor device has a source electrode layer and a drain electrode layer.

[0034] Another embodiment of the disclosed invention is a method for forming a first oxide semiconductor layer over a substrate having an insulating surface. and then performing first heat treatment to form a first oxide semiconductor layer. The crystal grows in a direction perpendicular to the surface, and a crystalline region in which the c-axis is oriented in a direction substantially perpendicular to the surface is formed as the first oxide semiconductor layer. a second oxide semiconductor layer is formed on the first oxide semiconductor layer; and a second heat treatment is performed. By performing this, crystal growth is caused from the crystalline region to crystallize the second oxide semiconductor layer, and the second A conductive layer is formed over the oxide semiconductor layer, and the conductive layer is etched to form a source electrode layer. and a drain electrode layer, and a second oxide semiconductor layer, a source electrode layer, and a drain electrode layer are formed. A gate insulating layer is formed so as to cover the electrode layer, and a second oxide semiconductor layer is formed on the gate insulating layer. In this method, a gate electrode layer is formed in an overlapping region.

[0035] Another embodiment of the disclosed invention is a semiconductor device including a first gate electrode layer formed over a substrate having an insulating surface. a first gate insulating layer is formed to cover the first gate electrode layer; a first oxide semiconductor layer is formed on the first oxide semiconductor layer and subjected to first heat treatment; Crystals grow from the surface of the conductor layer toward the inside, and the c-axis is oriented in a direction approximately perpendicular to the surface. A crystalline region is formed in a first oxide semiconductor layer, and a second oxide semiconductor is formed on the first oxide semiconductor layer. A second oxide layer is formed, and a second heat treatment is performed to cause crystal growth from the crystalline region. crystallizing the oxide semiconductor layer, forming a conductive layer on the second oxide semiconductor layer, and etching the conductive layer. a source electrode layer and a drain electrode layer, a second oxide semiconductor layer, A second gate insulating layer is formed to cover the source electrode layer and the drain electrode layer. A second gate electrode layer is formed on the gate insulating layer in a region overlapping with the second oxide semiconductor layer. and a method for manufacturing a semiconductor device.

[0036] In the above structure, the thickness of the first oxide semiconductor layer is set to 3 nm to 15 nm. A method for making a body device.

[0037] In the above structure, a polycrystalline region is formed as the crystalline region of the first oxide semiconductor layer. A method for manufacturing a semiconductor device.

[0038] In the above structure, the second oxide semiconductor layer is polycrystallized by the second heat treatment. A method for making a body device.

[0039] In the above structure, the first oxide semiconductor layer is formed by the first heat treatment and the second heat treatment. The first oxide semiconductor layer and the second oxide semiconductor layer are both polycrystalline.

[0040] In the above structure, the second heat treatment causes the second oxide semiconductor layer to be This is a method for manufacturing a semiconductor device in which crystals are grown so that the c-axis is oriented in the direction perpendicular to the crystal axis.

[0041] In the above structure, the second oxide semiconductor layer is formed by a sputtering method. The composition ratio of the oxide target is In:Ga:Zn=1:x:y (x is 0 or more and 2 or less, y is 1 or more and 5 or less).

[0042] In the above configuration, the composition of the metal oxide target is In:Ga:Zn=1:x:y ( This is a method for manufacturing a semiconductor device where x=1, y=1.

[0043] In the above configuration, the composition of the metal oxide target is In:Ga:Zn=1:x:y ( This is a method for manufacturing a semiconductor device where x=0, y=1.

[0044] In the above-described configuration, a source electrode layer and a drain electrode layer are provided on the source electrode layer and the drain electrode layer. This is a method for manufacturing a semiconductor device in which an insulating layer having substantially the same shape as a drain electrode layer is formed.

[0045] In the above structure, a material having low affinity for oxygen is provided in a portion in contact with the second oxide semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device in which a source electrode layer and a drain electrode layer are formed using a silicon dioxide film.

[0046] In the above manufacturing method, annealing is performed after the first oxide semiconductor layer is formed. A second oxide semiconductor layer is formed, and then a second oxide semiconductor layer is formed above the surface of the first oxide semiconductor layer. The first oxide semiconductor layer is grown on the second oxide semiconductor layer. The crystalline ( It is important that the second oxide semiconductor layer (eg, polycrystalline) is formed.

[0047] As the crystallinity of the oxide semiconductor layer increases, the threshold voltage of the transistor before and after the BT test decreases. This suppresses the amount of pressure change and achieves high reliability. A transistor using an oxide semiconductor layer having a polycrystalline layer is The amount of change in the threshold voltage of the transistor can be reduced even before and after the BT test that is performed continuously. Therefore, a transistor having stable electrical characteristics can be manufactured.

[0048] In addition, the higher the crystallinity of the oxide semiconductor layer, the greater the temperature dependence of the electrical characteristics of the transistor. For example, the amount of change in the on-current and off-current from -30°C to 120°C can be suppressed. The normal operating temperature range of a display panel is between 0°C and 40°C. When it comes to panels, heat resistance of -30°C to 85°C, and even below 105°C is required. The oxide semiconductor layer with high crystallinity is not only used for display panels but also for switching elements, driver circuits, etc. By using this technology, it is possible to realize devices that can withstand various harsh environments, and This is useful because it can broaden the range of uses and fields of application.

[0049] In addition, the higher the crystallinity of the oxide semiconductor layer, the higher the field-effect mobility of the transistor. It is possible to realize the

[0050] The oxide semiconductor layers all contain metal oxides, and are made of quaternary metal oxides, such as In-Sn-G a-Zn-O film, ternary metal oxide films such as In-Ga-Zn-O and In-Sn-Zn -O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O system, binary metal oxide In-Zn-O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, and I Metal oxide films such as nO film, Sn—O film, and Zn—O film can be used.

[0051] The oxide semiconductor layer is InMO3(ZnO) m (m>0 and m is not a natural number) The thin film described below can be used, where M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co. Also, InGa x Zn y O z Using a material expressed as Here, x, y, and z are arbitrary numbers. Also, x, y, and z are integers. It is not necessary for x to be 0, and it can be a non-integer. For example, this notation includes In-Zn-O where x is 0. The oxide semiconductor material represented by In-Ga-Zn-O in this specification is InGaO3 ( ZnO) m (m>0 and m is not a natural number), and the fact that m is not a natural number is due to ICP -This can be confirmed using MS analysis or RBS analysis. Also, the expression x=1, y=1 This includes cases where the carrier density is expressed as x=1 and y=0.5. 1×10 12 cm -3 less than 1.45 x 10 10 cm -3 Highly purified It is preferable to use an oxide semiconductor having a high conductivity type.

[0052] Metal oxides reported so far are either amorphous or polycrystalline. In the past, single crystals were obtained by treatment at high temperatures of about 1400°C. As described above, after forming the plate-like polycrystal of the metal oxide, the plate-like polycrystal of the metal oxide is Thin polycrystalline films can be produced at relatively low temperatures by using crystals as seeds to grow crystals, and thick polycrystalline films can also be produced. Once crystals are formed, a wider range of industrial applications will be possible. It is preferable that the surface has high flatness and smoothness. This is because even slight unevenness on the substrate can cause localized This causes the c-axis to deviate, and as the crystal growth progresses, the c-axis orientation of the crystals becomes different from that of the adjacent crystals. This is because defects such as crystal dislocation occur due to the flat shape in the oxide semiconductor layer. The crystal is InGaZnO4 (In:Ga:Zn:O=1:1:1:4) Alternatively, In2Ga2ZnO7 (In:Ga:Zn:O=2:2:1:7) In addition, the crystals are preferably those having a c-axis oriented in a direction perpendicular to the surface of the oxide semiconductor layer. , for example polycrystalline.

[0053] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." If the expression "layer" is used, it excludes those that include other components between the gate insulating layer and the gate electrode layer. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation, and Except where otherwise applicable, this also includes cases where the top and bottom are reversed.

[0054] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0055] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0056] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0057] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0058] In the disclosed invention, a highly purified oxide semiconductor layer is used in a semiconductor device. hydrogen, which is a factor in making an oxide semiconductor n-type, must be eliminated from the oxide semiconductor layer as much as possible; Alternatively, oxygen that is insufficient in the oxide semiconductor layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer is free from oxygen deficiency. The concept includes at least one of: reducing defects that occur due to the

[0059] The purification is performed to make the oxide semiconductor layer intrinsic (i-type). Generally, it is n-type, so the off-current is high. If the off-current is high, the switching characteristics will be insufficient. Therefore, in one embodiment of the present invention, an oxide semiconductor The layer is purified to become i-type or close to it.

[0060] In addition, in the disclosed invention, an oxide semiconductor layer having a crystalline region is used in a semiconductor device.

[0061] In an oxide semiconductor layer including a crystalline region, the following properties are obtained compared to an oxide semiconductor layer not including a crystalline region: The electrical properties of the oxide semiconductor layer will be different. For example, if the c-axis is perpendicular to the surface, In an oxide semiconductor layer having an oriented crystalline region, the conduction direction parallel to the surface of the oxide semiconductor layer is The electrical conductivity is improved, and the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer are improved.

[0062] In this way, by using an oxide semiconductor layer having a crystalline region in a semiconductor device, electrical characteristics Therefore, a semiconductor device with excellent properties can be realized.

[0063] In addition, an oxide semiconductor layer having a crystalline region has a higher thermal conductivity than an oxide semiconductor layer having no crystalline region. As a result, the penetration of impurities into the oxide semiconductor layer is suppressed. The compound semiconductor layer prevents the penetration of water and hydrogen, which have a negative effect on the oxide semiconductor layer. can be.

[0064] This makes it possible to prevent the oxide semiconductor layer from subsequently becoming n-type. This can improve the reliability of the semiconductor device.

[0065] As described above, one embodiment of the disclosed invention provides a semiconductor device with high reliability and excellent characteristics. It is served.

[0066] As described above, by using an oxide semiconductor, in particular, a highly purified and intrinsic oxide semiconductor, It is understood that various effects can be obtained. By realizing a crystalline structure of an oxide semiconductor layer, a new semiconductor device with excellent characteristics can be developed. The placement is realized. [Brief explanation of the drawings]

[0067] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 5] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 14] FIG. 1 is a cross-sectional view showing one embodiment of the invention. [Figure 15] 1 shows a cross-sectional TEM photograph and its schematic diagram. [Figure 16] 3A and 3B are cross-sectional TEM photographs and their schematic diagrams after the second heat treatment. [Figure 17] 1A and 1B are cross-sectional TEM photographs and schematic diagrams of comparative examples. [Figure 18] FIG. 10 is a longitudinal cross-sectional view of a transistor including an oxide semiconductor. [Figure 19] 19 is an energy band diagram (schematic diagram) taken along line A-A' in FIG. 18. [Figure 20] (A) shows the state when a positive potential (+VG) is applied to the gate (GE), and (B) shows the state when a negative potential (-VG) is applied to the gate (GE). [Figure 21] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 22] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon (Si). [Figure 23] This is a diagram showing the energy required for hot carrier injection in an In-Ga-Zn-O oxide semiconductor (IGZO). [Figure 24]FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 25] FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 26] A diagram showing CV (Capacitance-Voltage) characteristics. [Figure 27] A graph showing the relationship between Vg and (1 / C)2. [Figure 28] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 29] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 30] 1A and 1B are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0068] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown below.

[0069] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0070] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0071] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0072] <Configuration of Semiconductor Device> FIG. 1 is a cross-sectional view showing a transistor 150, which is an example of the configuration of a semiconductor device. The transistor 150 is an n-channel IGFET (insulator field effect transistor) in which the carriers are electrons. ed Gate Field Effect Transistor) As will be explained, it is also possible to fabricate a p-channel IGFET.

[0073] The transistor 150 is formed of a first oxide semiconductor layer provided on a substrate 100 with an insulating layer 102 interposed therebetween. a conductive layer 104a and a second oxide semiconductor layer provided on the first oxide semiconductor layer 104a; and a source electrode layer or a drain electrode layer electrically connected to the second oxide semiconductor layer 106a. a source or drain electrode layer 108a, and a source or drain electrode layer 108b; a source or drain electrode layer 108a; and a source electrode layer 109a. a gate insulating layer 112 covering the gate electrode layer 108b; and a gate electrode layer 114 (see FIGS. 1A and 1B).

[0074] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components. , may be omitted as appropriate.

[0075] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are made of a quaternary metal oxide. In-Sn-Ga-Zn-O based materials, which are oxides, and In-Ga -Zn-O based materials, In-Sn-Zn-O based materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O In-Zn-O and Sn-Zn-O materials are binary metal oxides. , Al-Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In- Mg-O based materials, In-O based materials, Sn-O based materials, Z nO-based materials are used.

[0076] Alternatively, an oxide semiconductor material expressed as In-ABO may be used, where A is Group 13 elements such as gallium (Ga) and aluminum (Al), silicon (Si) and germanium It represents one or more elements selected from the group 14 elements, such as germanium (Ge). In addition, B is one or more elements selected from the group 12 elements represented by zinc (Zn). Represents an element. The contents of In, A, and B are arbitrary, including the case where the content of A is zero. On the other hand, the content of In and B is not zero. That is, the above notation includes In-Ga -Zn-O and In-Zn-O.

[0077] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0078] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) mThere are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0079] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are free of impurities such as hydrogen. It is desirable that the material be highly purified by sufficiently removing substances and supplying oxygen. Specifically, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a The hydrogen concentration is 5×10 19 / cm 3 Below 5×10 18 / cm 3 Below, more hope Preferably 5 x 10 17 / cm 3 In addition, the hydrogen concentration is sufficiently reduced and oxygen is supplied. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are purified by the above-mentioned method. The conductor layer 106a is made of a silicon wafer (containing trace amounts of impurity elements such as phosphorus and boron) Carrier density (1×10 14 / cm 3 Compared to and a sufficiently small carrier density (e.g., 1×10 12 / cm 3 Less than, more preferred 1.45 x 10 10 / cm 3 In this way, it is possible to make it i-type or essentially i By using a gate-type oxide semiconductor, a transistor with excellent off-state current characteristics was developed. For example, if the drain voltage Vd is +1 V or +10 V, When the gate voltage Vg is in the range of -5V to -20V, the off-state current is 1×10 -13 Below A The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106 The hydrogen concentration in a was measured by secondary ion mass spectrometry (SIMS). The measurements were taken using spectroscopy.

[0080] Here, the first oxide semiconductor layer 104a has a crystalline region. A region including the surface of the oxide semiconductor layer 104a, that is, an interface with the second oxide semiconductor layer 106a The c-axis of the oxide semiconductor layer 104a is aligned in a direction substantially perpendicular to the surface of the oxide semiconductor layer 104a. For example, the crystalline region may be a region having a c-axis of the first oxide semiconductor. The region may be a region including crystal grains oriented in a direction substantially perpendicular to the surface of the layer 104a. Here, "substantially perpendicular" refers to a state within ±10° from the perpendicular direction. The crystalline region is formed in the vicinity of the surface of the first oxide semiconductor layer 104a (for example, in the vicinity of the surface (depth ) may be 2 nm or more and 10 nm or less, or the back surface of the first oxide semiconductor layer 104a may be It may also be configured to reach the surface.

[0081] Moreover, the crystalline region is preferably a plate-shaped crystal (plate-shaped crystal). A plate-like crystal is a crystal that has developed in a plane and has a thin plate-like shape. The crystalline region is preferably polycrystalline.

[0082] The second oxide semiconductor layer 106a is formed by dissolving the crystalline region of the first oxide semiconductor layer 104a. It consists of crystals formed by crystal growth.

[0083] Here, the second oxide semiconductor layer 106a is formed from the crystalline region of the first oxide semiconductor layer 104a. Since the oxide semiconductor layer 104a is made of crystals grown from the first oxide semiconductor layer 104b, the crystals are The crystals are oriented such that the c-axis is substantially perpendicular to the interface with the first oxide semiconductor layer 104a. Here, "substantially perpendicular" refers to a state within ±10° from the perpendicular direction.

[0084] The second oxide semiconductor layer 106a has the same crystalline structure as the first oxide semiconductor layer 104a. Similarly, the second oxide semiconductor layer is preferably made of a plate-like crystal (plate-like crystal). Preferably, 106a is polycrystalline.

[0085] The second oxide semiconductor layer 106a contains crystalline regions of the first oxide semiconductor layer 104a. In addition to the crystals grown from the surface of the second oxide semiconductor layer 106a, Crystals may be included.

[0086] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are made of the same material. In the case of homo-epitaxial growth, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are The boundary of the compound semiconductor layer 106a may become difficult to distinguish, so it is shown by a dotted line in FIG. 1(A). However, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are regarded as the same layer. In addition, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b may be formed by the same method as in the first embodiment (see FIG. 1A). The nitride semiconductor layer 106a is polycrystalline.

[0087] Of course, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a may be made of different materials. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b may be formed as a single layer (see FIG. 1B). When the semiconductor layer 106a is made of a different material (so-called hetero epitaxial growth), For example, the first oxide semiconductor layer 104a is made of a binary metal oxide, such as an In—Zn—O system. The second oxide semiconductor layer 106a is made of the above material, and the second oxide semiconductor layer 106a is made of a ternary metal oxide, In-Ga-Z A configuration using an nO-based material can be adopted.

[0088] The second oxide semiconductor layer 10 is grown by crystal growth from the crystalline region of the first oxide semiconductor layer 104a. By forming the second oxide semiconductor layer 6a, electrical anisotropy is imparted to the second oxide semiconductor layer 106a. For example, when the c-axes of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are aligned, Since the crystalline silicon is oriented in a direction substantially perpendicular to the interface between the first oxide semiconductor layer 106a and the second oxide semiconductor layer 106b, the crystalline silicon is flat on the surface of the second oxide semiconductor layer 106a. On the other hand, the conductivity in the direction perpendicular to the surface of the second oxide semiconductor layer 106a is increased. In this regard, the insulating properties are improved.

[0089] A region of the oxide semiconductor layer that serves as a channel formation region has at least a flat surface. It is also preferable that the first oxide semiconductor layer and the second oxide semiconductor layer have the same c-axis orientation. The second oxide semiconductor layer is a polycrystalline body having a height difference between the gate electrode layer and the second oxide semiconductor layer. In the overlapping region (channel formation region), 1 nm or less (preferably 0.2 nm or less) It is preferable that:

[0090] As described above, crystals are grown from the crystalline region of the highly purified first oxide semiconductor layer 104a. By using the second oxide semiconductor layer 106a, a semiconductor device having favorable electrical characteristics can be obtained. This can be achieved.

[0091] In addition, since the second oxide semiconductor layer 106a is relatively stable, It is possible to prevent impurities (such as water) from entering 106a. This can improve the reliability of the second oxide semiconductor layer 106a.

[0092] Below, we will explain the significance of purifying oxide semiconductors and making them intrinsic (i-type), as well as the advantages of such oxides. We will briefly explain the advantages of using nitride semiconductors to construct semiconductor devices. .

[0093] <Intrinsic oxide semiconductor> There has been much research into the properties of oxide semiconductors, such as DOS (density of state). However, these studies include the idea of ​​sufficiently reducing the defect level itself. In one embodiment of the disclosed invention, water and hydrogen, which may cause an increase in DOS, are removed from an oxide semiconductor. By removing the oxide from the inside, a highly purified and intrinsic (i-type) oxide semiconductor is manufactured. This is based on the idea of ​​sufficiently reducing DOS itself. This makes it possible to manufacture extremely excellent industrial products.

[0094] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and D By reducing the OS, oxide semiconductors can be further purified and made intrinsic (i-type). For example, an oxide film containing excess oxygen is formed in close proximity to the channel forming region, and By performing heat treatment at a temperature between 0°C and 400°C, typically around 250°C, Oxygen is supplied from the oxide film into the oxide semiconductor, reducing DOS caused by oxygen defects. During the heat treatment, the inert gas may be replaced with a gas containing oxygen. Following the heat treatment, the temperature is lowered in an oxygen atmosphere or an atmosphere from which hydrogen and water have been sufficiently removed. By undergoing this process, oxygen can be supplied into the oxide semiconductor.

[0095] The factor that deteriorates the properties of oxide semiconductors is the lower 0.0 region of the conduction band formed by excess hydrogen. These include shallow levels of 1 to 0.2 eV and deep levels formed by oxygen vacancies. To eliminate these defects, hydrogen must be thoroughly removed and oxygen must be provided in sufficient amounts. The technical idea of ​​providing this is probably correct.

[0096] Note that oxide semiconductors are generally n-type. However, in one embodiment of the disclosed invention, By removing impurities such as those mentioned above and supplying oxygen, which is a constituent element of the oxide semiconductor, This is not achieved by adding impurity elements as in silicon, but by It can be said that it contains a technological concept that has never been seen before.

[0097] In addition, by making the oxide semiconductor i-type, the temperature characteristics of the transistor are improved. Generally speaking, the current-voltage characteristics of a transistor in the temperature range from -25°C to 150°C In this case, the on-current, off-current, field-effect mobility, S value, and threshold voltage fluctuate little. There is almost no deterioration in the current-voltage characteristics due to temperature.

[0098] Note that the transistor including an oxide semiconductor described in this embodiment is a transistor including an oxide semiconductor. Although the mobility is about two orders of magnitude lower than that of the transistors used, the Increasing the channel width (W) increases the transistor current value and improves device characteristics. It can be done.

[0099] The technical idea of ​​this embodiment is to form an oxide semiconductor without adding any impurities to the oxide semiconductor. On the other hand, by intentionally removing impurities such as water and hydrogen that are unintentionally present, oxide semiconductors can be The goal is to purify the body itself. In other words, to remove water or hydrogen that constitutes the donor level. Furthermore, by supplying sufficient oxygen to the main component material that constitutes the oxide semiconductor, oxygen deficiency can be prevented. The objective is to reduce the loss and to highly purify the oxide semiconductor.

[0100] At the time of oxide semiconductor film formation, the 20 cm -3 level of hydrogen in the oxide semiconductor The presence of these donor levels is measured by SIMS (Secondary Ion Mass Spectroscopy). The water or hydrogen that is generated is intentionally removed, and the amount of water or hydrogen that is simultaneously reduced as the water or hydrogen is removed is also reduced. By adding oxygen (one of the components of oxide semiconductors) to an oxide semiconductor, The body is highly purified to make it an electrically intrinsic (i-type) semiconductor.

[0101] In this embodiment, the smaller the amount of water and hydrogen in the oxide semiconductor, the better. The fewer carriers, the better. That is, the carrier density is 1×10 1 2 cm -3 less than 1.4 × 10 10 cm -3 Less than what is required Furthermore, in terms of the technical concept of this embodiment, it is ideal that the value is close to zero or zero. In particular, oxide semiconductors are heated in oxygen, nitrogen, or ultra-dry air (water content of 20 ppm or less, Preferably, the concentration is 1 ppm or less, and more preferably 10 ppb or less in air. By performing a heat treatment at 50°C or less, preferably 550°C to 750°C, an n-type impurity It is possible to remove pure water or hydrogen and achieve high purity. By removing impurities such as SiO2, the oxide semiconductor can be highly purified, and the carrier density can be increased. 1×10 12 cm -3 less than 1.4 × 10 10 cm -3 It can be less than.

[0102] Furthermore, the heat treatment is carried out at a high temperature of 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. In this case, the oxide semiconductor can be highly purified and crystallized. Crystal growth occurs from the surface of the semiconductor toward the interior, forming a polycrystalline layer with the c-axis oriented.

[0103] The present invention uses the polycrystalline layer having the c-axis direction as a seed crystal, and grows a second oxide semiconductor thereon. and heat treatment at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. By this, the second oxide semiconductor is made into a polycrystalline layer in which the c-axis is oriented similarly to the seed crystal. That is, an ideal axial alignment can be achieved in which the c-axes of the seed crystal and the second oxide semiconductor are coaxial. It can be grown by evaporation or epitaxial growth.

[0104] In addition, the second oxide semiconductor, which is coaxial with the seed crystal, can be grown by solid phase growth only by heat treatment after film formation. The second oxide semiconductor is formed by heating at a temperature of 200°C to 600°C. By sputtering, crystal growth can be achieved while depositing.

[0105] Furthermore, by reducing, preferably eliminating, carriers in the oxide semiconductor, In the transistor, the oxide semiconductor functions as a path through which carriers pass. As a result, oxide semiconductors are highly purified intrinsic (i-type) semiconductors, and have no carriers. By making the value of the gate resistance extremely small, the off-state current of the transistor is extremely low. The technical idea of ​​this embodiment is that this is possible.

[0106] In addition, the oxide semiconductor functions as a path, and the oxide semiconductor itself does not have carriers. If the carriers are highly purified to have no or very few intrinsic (i-type) The electron affinity χ and Fermi level of the oxide semiconductor are supplied by the electrode and drain electrode. Ideally, the Fermi level should be the same as the intrinsic Fermi level, and the source and drain electrodes should be By appropriately selecting the work function of the electrode, carriers can be injected from the source electrode and the drain electrode. This allows n-type and p-type transistors to be fabricated appropriately. can.

[0107] In a lateral transistor in which the channel is formed approximately parallel to the substrate, In addition to the gate, a source and drain must be provided, and the area occupied by the transistor on the substrate must be However, in vertical transistors, In this case, the source, channel, and drain are stacked, thereby reducing the area occupied on the substrate surface. As a result, transistors can be miniaturized.

[0108] In this way, impurities other than the main components of the oxide semiconductor film, typically hydrogen, water, a hydroxyl group, or By purifying the material to the extent possible so that it does not contain hydrides, etc., and by having a polycrystalline region, This improves the transistor's operation. The on-off ratio can be increased by reducing the channel effect. This makes it possible to suppress the amount of change in the threshold voltage of the transistor, thereby achieving high reliability. In addition, the temperature dependence of the electrical properties can be suppressed. A transistor using an oxide semiconductor layer having a polycrystalline layer is irradiated with light. The amount of change in the threshold voltage of the transistor can be reduced before and after the BT test, Therefore, a transistor having predetermined electrical characteristics can be manufactured.

[0109] <Process advantages compared to other semiconductor materials> Semiconductor materials that can be compared to oxide semiconductors include silicon carbide (e.g., 4H-Si C). Oxide semiconductors and 4H-SiC have several things in common. The carrier density of oxide semiconductors is one example. Rear is 10 -7 / cm 3 This is estimated to be about 6.7× in 4H-SiC. 10 -11 / cm 3 This is an extremely low value, similar to the intrinsic carrier density of silicon (1.4 x10 10 / cm 3 When compared to the level of do.

[0110] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have in common this point as well.

[0111] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The process temperature is 1500℃ to 2000℃. However, it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because the semiconductor substrate and semiconductor elements are destroyed. It can be manufactured by heat treatment at temperatures between 300 and 800°C, and is different from other semiconductor materials. After forming an integrated circuit using the oxide semiconductor, it is possible to form a semiconductor element using the oxide semiconductor. do.

[0112] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced. In silicon, crystal defects and trace impurities that are unintentionally mixed in can cause carrier generation. Theoretically, silicon carbide can achieve a low carrier density equivalent to that of the oxide semiconductor of the present invention. In reality, for the reasons mentioned above, 12 / cm 3 To obtain the following carrier density The above is difficult to understand. The same can be said for comparison with oxide semiconductors.

[0113] Conduction mechanism of transistors using oxide semiconductors The conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. In the following explanation, ideal situations are assumed for ease of understanding. However, this does not necessarily reflect the actual situation. Also, the following explanation is merely a consideration. It should be noted that there is no

[0114] FIG. 18 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE) via a gate insulating film (GI). , on which a source electrode (S) and a drain electrode (D) are provided.

[0115] FIG. 19 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. In Figure 19, black circles (●) represent electrons, white circles (○) represent holes, and each represents a charge (-q , +q). A positive voltage (V D >0), the dashed line indicates the gate When no voltage is applied to the port electrode (V G =0), the solid line indicates a positive voltage (V G >0 When no voltage is applied to the gate electrode, the potential barrier is high. Therefore, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, allowing current to flow. Indicates the on state.

[0116] FIG. 20 shows an energy band diagram (schematic diagram) in the cross section taken along the line B-B' in FIG. Figure 20(A) shows the gate electrode (GE) with a positive potential (V G >0) is given This shows the on-state where carriers (electrons) flow between the source and drain electrodes. . Also, FIG. 20(B) shows the gate electrode (GE) with a negative potential (V G <0) is applied and indicates the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0117] Figure 21 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0118] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the reasons for their n-type properties. It is also known that oxygen vacancies are a factor in the formation of n-type semiconductors.

[0119] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying the material so that it is not susceptible to oxygen deficiency, it is made into an intrinsic (i-type) material, or by removing the oxygen deficiency, it is made into an intrinsic (i-type) material. That is, instead of adding impurity elements to make it i-type, hydrogen By removing impurities such as silicon dioxide and water, and oxygen vacancies as much as possible, a highly purified i-type (intrinsic semiconductor) ) or close to it. This allows the Fermi level (E F ) is true Fermi level (E i ) can be made to the same extent as

[0120] The band gap (E g) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0121] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. They move near the interface with the body (the lowest energetically stable part of the oxide semiconductor).

[0122] Also, as shown in FIG. 20(B), when a negative potential is applied to the gate electrode (GE), Since the number of holes, which are carriers, is substantially zero, the current is a value that is infinitely close to zero.

[0123] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0124] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor can be reduced to 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) is achieved. It can be done.

[0125] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0126] <Resistance to Hot Carrier Degradation of Transistors Using Oxide Semiconductors> Next, the resistance to hot carrier degradation of a transistor including an oxide semiconductor is shown in FIGS. 22 and 23. The following explanation will be given with reference to Figure 23. In the following explanation, an ideal situation is assumed for ease of understanding. The following explanation is based on the actual situation and may not reflect all of the information. I would like to add that this is merely one consideration.

[0127] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons are considered.

[0128] CHE injection is an injection into the semiconductor layer that has energy greater than or equal to the barrier of the gate insulating layer. This refers to the phenomenon in which electrons that have become electrons are injected into the gate insulating layer, etc. This is achieved by accelerating electrons through a low electric field.

[0129] DAHC injection is a method in which new electrons generated by the collision of electrons accelerated by high voltage are injected into the gate. The difference between DAHC injection and CHE injection is that the impact ions The question is whether or not avalanche breakdown occurs due to the breakdown of the semiconductor. Electrons with kinetic energy greater than the band gap are required.

[0130] Figures 22 and 23 show the structure of silicon (Si) and In-Ga-Zn-O oxide semiconductor (I The energy required for various hot carrier injections estimated from the band structure of GZO is shown. In Figures 22 and 23, the left side represents CHE injection and the right side represents DAHC injection.

[0131] In silicon, the degradation caused by DAHC implantation is more severe than that caused by CHE implantation. This is because the band gap of silicon is small and avalanche breakdown occurs easily. Since only a small number of carriers (e.g., electrons) are accelerated without collisions in the electron chamber, Although the probability of CHE injection due to this is low, the gate insulating layer is The increased number of electrons that can cross the barrier easily exceeds the probability of CHE injection. That is why.

[0132] In the case of In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon The energy required for DAHC injection is not significantly different from that in the case of Therefore, the energy required for CHE injection is approximately the same as that required for DAHC injection. stomach.

[0133] On the other hand, just like silicon, only a small number of carriers (e.g., electrons) are accelerated without collisions. Therefore, the probability of CHE injection is low. Therefore, it has high resistance to carrier degradation.

[0134] <Short-Channel Effect in Transistors Using Oxide Semiconductors> Next, the short-channel effect in a transistor using an oxide semiconductor will be explained with reference to FIG. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the above necessarily reflect the actual situation. Also, the following explanation is only a guide. Please note that this is merely speculation.

[0135] The short channel effect becomes apparent as transistors become smaller (reduced channel length (L)). The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and an S value. Increased current and leakage current.

[0136] Here, a device simulation is used to determine a structure that can suppress short channel effects. Specifically, we investigated the structure of the oxide semiconductor layer by varying the carrier density and the thickness of the oxide semiconductor layer. Four types of models were prepared to confirm the relationship between channel length (L) and threshold voltage (Vth). The model used a bottom-gate transistor with a carrier density of 1. 7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 and an oxide semiconductor. The thickness of the layer was set to either 1 μm or 30 nm. A Ga-Zn-O oxide semiconductor is used as the gate insulating layer, and a 100 nm thick silicon oxynitride layer is used as the gate insulating layer. A bare membrane was used.

[0137] There is no significant difference in the calculation results between the top gate structure and the bottom gate structure.

[0138] The calculation results are shown in Figures 24 and 25. Figure 24 shows the results for a carrier density of 1.7 × 10 -8 / c m 3 In the case of , Figure 25 shows that the carrier density is 1.0 × 10 15 / cm 3 This is the case. As a result, in a transistor using an oxide semiconductor, the thickness of the oxide semiconductor layer is reduced. This shows that the short channel effect can be suppressed by using In the case of an oxide semiconductor layer with a sufficiently low carrier density, the thickness of the oxide semiconductor layer is about 3 μm. nm to 50 nm, preferably 3 nm to 20 nm, typically about 20 nm. It is understood that the short channel effect can be sufficiently suppressed if the thickness is increased.

[0139] <Carrier density of oxide semiconductors> One of the technical ideas of the disclosed invention is to make the carrier density in the oxide semiconductor layer sufficiently small. The aim is to obtain the intrinsic (i-type) state as close as possible. The method of measurement and the carrier density measured in the oxide semiconductor layer are shown in FIGS. 7 for further explanation.

[0140] The carrier density in the oxide semiconductor layer was measured by fabricating a MOS capacitor using the oxide semiconductor layer. , CV measurement of the MOS capacitor (Capacitance Voltage Mea This can be determined by evaluating the results (CV characteristics) of the confirmation test.

[0141] Carrier density is measured by the following steps (1)-(3): (1) MOS capacitor gate (2) Obtain the CV characteristics by plotting the relationship between the gate voltage Vg and the capacitance C. From the V characteristics, the gate voltage Vg and (1 / C) 2and obtain a graph that shows the relationship between In the weak inversion region, (1 / C) 2 (3) The obtained differential value is Rear Density N d In equation (1), e is the elementary charge. , ε0 is the dielectric constant of a vacuum, and ε is the relative dielectric constant of the oxide semiconductor.

[0142]

number

[0143] The MOS capacitor used for the measurement had the following structure: As a result, a 300 nm thick titanium layer was formed on a glass substrate, and a 100 nm thick titanium layer was formed on the titanium layer. The titanium nitride layer has a thickness of 1000 nm, and an In-Ga-Zn-O oxide semiconductor ( It has a 2 μm thick oxide semiconductor layer using a-IGZO, and the oxide semiconductor layer is The silicon oxynitride layer had a thickness of 300 nm, and a silver layer of 300 nm was formed on the silicon oxynitride layer.

[0144] The oxide semiconductor layer was formed using a target for forming an oxide semiconductor film containing In, Ga, and Zn. By sputtering using (In:Ga:Zn=1:1:0.5[atom%]) The oxide semiconductor layer was formed in a mixed atmosphere of argon and oxygen (flow ratio: The gas flow rate was Ar:O2=30(sccm):15(sccm).

[0145] Figure 26 shows the CV characteristics, and Figure 27 shows the relationship between Vg and (1 / C) 2 The relationship between these is shown in the figure. (1 / C) in the weak inversion region of 27 2 The carrier obtained from the differential value of The density is 6.0 x 10 10 / cm3 It was.

[0146] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, an oxide semiconductor having a carrier density of 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) By using such a gate insulating film, a transistor with excellent off-state current characteristics can be obtained.

[0147] As described above, by using an oxide semiconductor, in particular, a highly purified and intrinsic oxide semiconductor, It is understood that various effects can be obtained. By realizing a crystalline structure of an oxide semiconductor layer, a new semiconductor device with excellent characteristics can be developed. The placement is realized.

[0148] <Method for manufacturing semiconductor device> Next, a method for manufacturing the transistor 150 will be described with reference to FIGS.

[0149] First, an insulating layer 102 is formed on a substrate 100. Then, a first oxide film is formed on the insulating layer 102. a first oxide semiconductor layer, and a first heat treatment is performed to form a first oxide semiconductor layer including a surface of the first oxide semiconductor layer; The region containing the oxide semiconductor layer 104 is crystallized to form the first oxide semiconductor layer 104 (see FIG. 2A).

[0150] The substrate 100 may be any substrate having an insulating surface, and may be, for example, a glass substrate. The glass substrate can be used for mass production of semiconductor devices according to one embodiment of the present invention. It is preferable that the glass substrate is an alkali-free glass substrate. The glass substrate may be made of, for example, aluminosilicate glass, aluminoborosilicate glass, or A glass material such as sodium borosilicate glass is used as the substrate 100. insulating substrates such as silicon substrates, quartz substrates, and sapphire substrates; The surface of a semiconductor substrate made of a conductive material is covered with an insulating material, and the surface of a conductive material such as metal or stainless steel is covered with an insulating material. A conductive substrate made of a material having its surface covered with an insulating material can be used. A plastic substrate can also be used, provided that it can withstand such a heat treatment.

[0151] The insulating layer 102 functions as a base and is formed by using a CVD method, a sputtering method, or the like. The insulating layer 102 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or nitride. The film is formed to contain silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. The insulating layer 102 may have a single-layer structure or a stacked-layer structure. The thickness of the insulating layer 102 is not particularly limited, but is, for example, 10 nm or more and 500 nm or less. Here, the insulating layer 102 is not an essential component, so the insulating layer 10 It is also possible to configure the system without providing 2.

[0152] Note that if the insulating layer 102 contains hydrogen, water, or the like, hydrogen may enter the oxide semiconductor layer or water may be released from the insulating layer 102. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 102 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0153] For example, when using a sputtering method, remove any remaining moisture in the processing chamber. It is desirable to form an insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, Adsorption type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a pump. A turbo pump with a cold trap is used. The processing chamber is evacuated using a cryopump or the like to ensure that hydrogen, water, etc. are sufficiently removed. Therefore, the concentration of impurities contained in the insulating layer 102 can be reduced.

[0154] Furthermore, when forming the insulating layer 102, impurities such as hydrogen and water are preferably present at a concentration of about several ppm. It is preferable to use a high purity gas whose concentration has been reduced to about several ppb.

[0155] The first oxide semiconductor layer is made of a quaternary metal oxide, In-Sn-Ga-Zn-O-based material. and ternary metal oxide materials such as In-Ga-Zn-O and In-Sn-Zn-O. Materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials, Al-Ga-Z nO-based materials, Sn-Al-Zn-O-based materials, and binary metal oxides such as In-Zn -O based materials, Sn-Zn-O based materials, Al-Zn-O based materials, Zn-Mg-O based materials Materials, Sn-Mg-O based materials, In-Mg-O based materials, In-O based materials, Sn- It can be formed using an O-based material, a Zn—O-based material, or the like.

[0156] Alternatively, an oxide semiconductor material expressed as In-ABO may be used, where A is Group 13 elements such as gallium (Ga) and aluminum (Al), silicon (Si) and germanium It represents one or more elements selected from the group 14 elements, such as germanium (Ge). In addition, B is one or more elements selected from the group 12 elements represented by zinc (Zn). Represents an element. The contents of In, A, and B are arbitrary, including the case where the content of A is zero. On the other hand, the content of In and B is not zero. That is, the above notation includes In-Ga -Zn-O and In-Zn-O.

[0157] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0158] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0159] In this embodiment, the first oxide semiconductor layer is an In—Ga—Zn—O-based oxide semiconductor material. The film is formed by sputtering using a film target.

[0160] Examples of targets for forming the first oxide semiconductor layer by a sputtering method include: A metal oxide target containing zinc oxide as the main component can be used. The composition ratio of the oxide semiconductor film formation target containing Ga and Zn is In:Ga:Zn= The formula is 1:x:y (x is 0 or more and 2 or less, y is 1 or more and 5 or less). For example, In:Ga:Zn =1:1:1 [atom ratio] (x=1, y=1) (i.e., In2O3:Ga2O3: A target having a composition ratio of ZnO=1:1:2 (molar ratio) may also be used. In addition, a target for oxide semiconductor film formation was prepared using In:Ga:Zn=1:1:0.5[atom m ratio] or In:Ga:Zn=1:1:2 [atom ratio] ], and has a composition ratio of In:Ga:Zn=1:0:1 [atom ratio] (x=0, y=1) In this embodiment, a target is intentionally crystallized by performing heat treatment later. In order to crystallize the oxide semiconductor film, it is preferable to use a target for forming an oxide semiconductor film that is prone to crystallization. stomach.

[0161] The relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 90% or more. 5% or more, more preferably 99.9% or more. For forming oxide semiconductor films with high relative density By using the target, a dense first oxide semiconductor layer is formed. In this embodiment, the first oxide semiconductor layer is intentionally crystallized by performing heat treatment later. It is preferable to use a target for forming an oxide semiconductor film that is likely to crystallize.

[0162] The atmosphere for forming the first oxide semiconductor layer may be a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of about several ppm. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to a level of about several ppb. be.

[0163] When the first oxide semiconductor layer is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Then, the sputtering gas from which hydrogen and water have been removed while removing the remaining moisture in the processing chamber. The first oxide semiconductor layer is formed by introducing a metal oxide as a target. By forming the oxide semiconductor layer while the first oxide semiconductor layer is being formed, the impurities contained in the first oxide semiconductor layer can be removed. The first oxide semiconductor can be reduced. Water remaining in the sputtering device before, during, or after the deposition of the conductor layer In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type It is preferable to use an air pump. For example, a cryopump, an ion pump, or a titanium sub-pump. A cold trap can be used in a turbo pump. The processing chamber evacuated using a cryopump can be filled with hydrogen, water, etc. Since the impurity concentration in the first oxide semiconductor layer is reduced, the impurity concentration in the first oxide semiconductor layer can be reduced.

[0164] The conditions for forming the first oxide semiconductor layer include, for example, a distance between the substrate and the target of 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen flow rate It is possible to apply conditions such as a 100% ratio atmosphere. ) power supply reduces dust (powder or flake-like material formed during film formation). The thickness of the first oxide semiconductor layer is preferably 3 nm or more and 100 nm or less. It is preferable to set the thickness to 5 nm or less, and in this embodiment, it is set to 5 nm as an example. The appropriate thickness varies depending on the oxide semiconductor material and the application. The material may be selected depending on the material and application.

[0165] Before the first oxide semiconductor layer was formed by sputtering, argon gas was introduced. The deposition on the surface of the insulating layer 102 is removed by reverse sputtering, which generates plasma. Here, the reverse sputtering is a method of sputtering a sputter target in a normal sputtering. On the other hand, by bombarding the surface with ions, the surface is This refers to a method of modifying the surface. The method of bombarding the treated surface with ions is called argon bombardment. A method of applying a high frequency voltage to the surface to be treated in an atmosphere to generate plasma near the substrate. In addition, an atmosphere of nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. That's fine.

[0166] Before the first oxide semiconductor layer was formed, the inner wall of the sputtering apparatus, the surface of the target, and the -Preheating is performed to remove any moisture or hydrogen remaining in the target material. The preheating process involves heating the film deposition chamber to 200 to 600°C under reduced pressure. There are methods such as repeatedly introducing and exhausting nitrogen or inert gas while heating. After the sputtering process is completed, the substrate or sputtering equipment is cooled and then the oxide is removed without contact with the atmosphere. In this case, it is better to use oil or fat as the target coolant instead of water. Repeated nitrogen introduction and evacuation without heating can produce a certain effect, but It's even better if you do.

[0167] Next, a first heat treatment is performed on the first oxide semiconductor layer, and at least the first oxide semiconductor layer The region including the surface is crystallized to form the first oxide semiconductor layer 104. By this heat treatment, water (including a hydroxyl group), hydrogen, and the like in the first oxide semiconductor layer can be removed. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher. The heating temperature is set to 750°C or less. The heating time is set to 1 minute or more and 24 hours or less. As the first heat treatment, a heat treatment is performed at 700° C. for 1 hour in a dry air atmosphere.

[0168] In the first heat treatment, nitrogen, oxygen, or a dilute gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the nitrogen introduced into the heat treatment device The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.999%). 9%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm It is preferable that the concentration of H2O is 20 ppm or less. In ultra-dry air with an H2O content of 1 ppm or less, more preferably in ultra-dry air with an H2O content of 1 ppm or less, The first heat treatment may be performed. It is possible to remove water (including hydroxyl groups) and hydrogen from 4. This reduces impurities, Since the first oxide semiconductor layer 104 can be made i-type or substantially i-type, Therefore, the transistor 150 can have excellent characteristics.

[0169] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise of the first heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be switched, and after dehydration or dehydrogenation is performed in a nitrogen atmosphere, Then, the atmosphere is changed to an oxygen atmosphere, whereby oxygen is supplied to the inside of the first oxide semiconductor layer. It can also be made into an i-type.

[0170] A first oxide semiconductor having a crystalline region at least in a region including a surface thereof by a first heat treatment. The crystalline region formed in the region including the surface is a layer 104. The crystal region is formed by crystal growth. The average thickness of the crystal region is 2 nm to 10 nm. The crystal region includes a plate-like crystal, and the c-axis of the crystal region is oriented in a direction substantially perpendicular to the surface. Here, "substantially perpendicular" refers to a state within ±10° from the perpendicular direction. It shall be.

[0171] In this embodiment, the first oxide semiconductor layer is entirely crystallized by the first heat treatment. However, the present invention is not limited to this example. For example, the first oxide semiconductor layer 104 may have a first crystalline region. The oxide semiconductor layer 104 is formed so as to have an amorphous region on the lower surface thereof, that is, at the interface with the insulating layer 102. By having an amorphous region at the interface with the insulating layer 102, a crystalline region This is preferable because the carriers flowing through the insulating layer 102 are not directly affected by the interface with the insulating layer 102. .

[0172] The heat treatment device used for the first heat treatment is not particularly limited, and may be any device that uses a heat generating element such as a resistance heating element. For example, a device that heats the object to be treated by thermal conduction or thermal radiation can be used. For example, electric furnaces and GRTA (Gas Rapid Thermal Anneal) equipment , LRTA (Lamp Rapid Thermal Anneal) equipment and other RTA ( A Rapid Thermal Anneal (LRTA) device can be used. halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps The radiation of light (electromagnetic waves) emitted from lamps such as high-pressure sodium lamps and high-pressure mercury lamps The GRTA device is a device that heats the object to be treated by irradiation. It is a device that performs processing.

[0173] Next, a crystalline layer is formed on the first oxide semiconductor layer 104 having a crystalline region at least in a region including a surface thereof. A second oxide semiconductor layer 105 is formed (see FIG. 2B).

[0174] The second oxide semiconductor layer 105 is a quaternary metal oxide, similar to the first oxide semiconductor layer. In-Sn-Ga-Zn-O based materials and ternary metal oxides such as In-Ga-Zn- O-based materials, In-Sn-Zn-O-based materials, In-Al-Zn-O-based materials, Sn-G a-Zn-O based materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al- Zn-O based materials, Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O In-O based materials, Sn-O based materials, Zn-O based materials, and monometallic oxides The material can be used.

[0175] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0176] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). In the above, M is used instead of Ga, and I nMO3(ZnO) m (m>0), where M is the Ga, Al, Fe, Ni, Mn , cobalt (Co), etc. , M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and M The above composition can be derived from the crystal structure. Please note that these are merely examples.

[0177] The second oxide semiconductor layer 105 is made of a material having the same main component as the first oxide semiconductor layer 104. or the same crystal structure and close lattice constants (mismatch of 1% or less) Alternatively, the insulating layer 12 may be formed using materials with different main components.

[0178] When materials having the same main component are used, the second oxide semiconductor layer 105 is crystallized later. In this case, crystal growth can be easily performed using the crystalline region of the first oxide semiconductor layer 104 as a seed. In addition, since the effective film thickness can be increased, it is suitable for applications such as power devices. Furthermore, when the main component materials are the same, the interface properties such as adhesion and electrical properties are also good. That's good.

[0179] When materials with different main components are used, the electrical properties of each layer can be made different. For example, a material having high electrical conductivity is used for the second oxide semiconductor layer, and a material having high electrical conductivity is used for the first oxide semiconductor layer. A semiconductor device that reduces the influence of the underlying interface by using a material with low electrical conductivity for the conductor layer In addition, when a material that is easily crystallized is used for the first oxide semiconductor layer, Then, a second oxide semiconductor layer is formed and crystallized. Regardless of the ease of crystallization of the second oxide semiconductor layer, the second oxide semiconductor layer is formed to have good crystallinity. It can be of the following type.

[0180] In this embodiment, the second oxide semiconductor layer 105 is made of an In—Ga—Zn—O-based oxide semiconductor. The film is formed by sputtering using a conductor film formation target. The conductive layer 105 is formed by sputtering in the same manner as the first oxide semiconductor layer. However, the thickness of the second oxide semiconductor layer 105 is the same as that of the first oxide semiconductor layer. It is preferable that the thickness of the first oxide semiconductor layer 104 is thicker than that of the first oxide semiconductor layer 104. the sum of the thicknesses of the oxide semiconductor layer 104 and the second oxide semiconductor layer 105 is 3 nm to 50 nm. It is preferable to form the second oxide semiconductor layer 105. The appropriate thickness varies depending on the material and application, so the thickness should be adjusted according to the material used and the application. Just select it.

[0181] Next, the second oxide semiconductor layer 105 is subjected to a second heat treatment, and the first oxide semiconductor layer 104 The crystalline region is used as a seed for crystal growth to form the second oxide semiconductor layer 106 (FIG. 2( See C).

[0182] The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heating time of the second heat treatment is 1 hour or more and 100 hours or less, preferably 5 hours or less. The time should be between 20 hours and 10 hours, typically.

[0183] In the second heat treatment, nitrogen, oxygen, or a dilute gas such as helium, neon, or argon may also be used. It is preferable that the gas does not contain water, hydrogen, etc. Alternatively, the nitrogen introduced into the heat treatment device The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.999%). 9%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm It is preferable that the concentration of H2O is 20 ppm or less. In ultra-dry air with an H2O content of 1 ppm or less, more preferably in ultra-dry air with an H2O content of 1 ppm or less, The second heat treatment may be performed. It is possible to remove water (including hydroxyl groups) and hydrogen from 6. This reduces impurities, Since the second oxide semiconductor layer 106 can be made i-type or substantially i-type, Therefore, the transistor 150 can have excellent characteristics.

[0184] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the temperature rise of the second heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. The atmosphere may be changed, and after dehydration or dehydration is performed in a nitrogen atmosphere, By changing the atmosphere to an oxygen atmosphere, oxygen is replenished inside the second oxide semiconductor layer 106. It can be made into an i-type by supplying

[0185] In this way, by performing the second heat treatment for a long time, the second oxide semiconductor layer 105 and the first oxide semiconductor layer 106 are bonded to each other. The crystalline region formed at the interface of the first oxide semiconductor layer 104 is then transferred to the entire second oxide semiconductor layer 105. The second oxide semiconductor layer 106 can be formed by crystallizing the oxide semiconductor layer. The first oxide semiconductor layer 104 is formed of a crystal layer having a higher crystal orientation by the treatment. It is possible.

[0186] The second oxide semiconductor layer 106 is a crystalline region of the first oxide semiconductor layer 104. The crystals are oriented with their c-axes in a direction substantially perpendicular to the interface with the oxide semiconductor layer 104. "Approximately perpendicular" refers to a state within ±10° from the perpendicular direction.

[0187] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the second oxide semiconductor layer 106. InGaO3(ZnO) m (m>0 and m is not a natural number) and crystals expressed as In2Ga2ZnO7 (In:Ga:Zn:O=2:2:1:7). Such crystals may have their c-axes aligned with the oxide semiconductor layer by the second heat treatment. The orientation is such that the direction is approximately perpendicular to the surface of 106 .

[0188] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or Zn are stacked in the c-axis direction.

[0189] In the In-Ga-Zn-O oxide semiconductor crystal, the a-axis and The conductivity in the direction parallel to the b-axis is good. In semiconductor crystals, electrical conduction is mainly controlled by In, and The 5s orbital of In overlaps with the 5s orbital of the adjacent In, forming a carrier path. On the other hand, in the direction perpendicular to the layer (i.e., the c-axis direction), , the insulation properties are improved.

[0190] In addition, the first oxide semiconductor layer 104 has an amorphous region near the interface with the insulating layer 102. In such a structure, the second heat treatment is performed to form a layer on the surface of the first oxide semiconductor layer 104. crystal growth occurs from the formed crystalline region toward the bottom surface of the first oxide semiconductor layer; The amorphous region may be crystallized. Depending on the conditions, the amorphous region may remain.

[0191] The first oxide semiconductor layer 104 and the second oxide semiconductor layer 105 are made of oxide semiconductors having the same main component. When a crystalline oxide semiconductor material is used, the first oxide semiconductor layer 104 is grown by crystal growth as shown in FIG. The crystals grow upward toward the surface of the second oxide semiconductor layer 105 as seeds of the second oxide. The oxide semiconductor layer 106 is formed on the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106. 105 has the same crystal structure. The boundary between the oxide semiconductor layer 104 and the second oxide semiconductor layer 106 becomes indistinguishable. The oxide semiconductor layer 104 and the second oxide semiconductor layer 106 can sometimes be considered as the same layer.

[0192] In this way, the second oxide semiconductor layer 104 is grown by crystal growth from the crystalline region of the first oxide semiconductor layer 104. By forming the conductor layer 106, the second oxide semiconductor layer 106 has electrical anisotropy. In the above example, the conductivity in the direction parallel to the surface of the second oxide semiconductor layer 106 is On the other hand, the insulating property is increased in the direction perpendicular to the surface of the second oxide semiconductor layer 106. Therefore, crystals are grown from the highly purified crystalline region of the first oxide semiconductor layer 104. By using the second oxide semiconductor layer 106 having a thickness of 100 nm, a semiconductor device having favorable electrical characteristics can be manufactured. It can be realized.

[0193] The heat treatment device used for the second heat treatment is not particularly limited, and may be a heat treatment device using a heat source such as a resistance heat source. The apparatus may be provided with a device for heating the object to be treated by thermal conduction or thermal radiation from the apparatus. An electric furnace or an RTA device such as a GRTA device or an LRTA device can be used.

[0194] Next, the first oxide semiconductor layer 104 and the The second oxide semiconductor layer 106 is processed into the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106b, which are island-shaped. Then, an oxide semiconductor layer 106a is formed (see FIG. 2D).

[0195] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0196] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) In this case, the etching conditions are (The amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the amount of power applied to the substrate-side electrode Temperature, etc. must be set appropriately.

[0197] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. Also, gases containing fluorine (fluorine-based gases) , such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride Fluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and A gas containing a rare gas such as helium (He) or argon (Ar) may also be used. .

[0198] The etching solution that can be used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia solution, hydrogen peroxide solution (31% by weight: 28% by weight ammonia solution, 5% by weight ammonia solution) :2:2) and other etching solutions such as ITO07N (Kanto Chemical Co., Ltd.) are also available. That's fine.

[0199] Next, the conductive layer 108 is formed so as to be in contact with the second oxide semiconductor layer 106a (FIG. 2(E)). )reference).

[0200] The conductive layer 108 is formed by a PVD method such as a sputtering method, or a CVD method such as a plasma CVD method. The conductive layer 108 can be formed using a method such as a metal thin film deposition (MgSO 4 ) or a metal thin film deposition (MgSO 4 ). An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements It can be formed using alloys containing manganese, magnesium, zirconium, etc. Alternatively, a material containing one or more of aluminum and beryllium may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing one or more elements selected from the above may be used.

[0201] The conductive layer 108 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0202] The conductive layer 108 may be formed by depositing an aluminum layer on a titanium layer and a titanium layer on the aluminum layer. or a molybdenum layer on an aluminum layer and a molybdenum layer on the aluminum layer. It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a metal layer. The film has a two-layer laminated structure of an aluminum layer and a tungsten layer, and a copper layer and a tungsten layer. Two-layer laminated structure with a silicon layer and a molybdenum layer, two-layer laminated structure with an aluminum layer and a molybdenum layer Of course, it can be a single layer of metal conductive film or a laminated structure of four or more layers. In the case of a single layer structure, it is preferable to use a single layer structure of, for example, a titanium layer. The use of a single-layer titanium layer structure allows for an etching process that forms a good tapered shape during subsequent etching. Here, the etching is performed by using three layers of titanium film, aluminum film and titanium film. A layer structure will be applied.

[0203] Note that a material such as titanium that has the effect of extracting oxygen from the second oxide semiconductor layer 106a is used. The conductive layer 108 is provided with a conductive material (a material having a high affinity for oxygen) in contact with the second oxide semiconductor layer 106a. When the second oxide semiconductor layer 106a is used in a portion where the conductive layer 108 is in contact with the second oxide semiconductor layer 106a, The lack of oxygen makes it n-type. This can be used to reduce the resistance of the source or drain region. It is possible to achieve this.

[0204] On the other hand, a material having an effect of extracting oxygen from the second oxide semiconductor layer 106a is not used. An oxide conductor layer may be formed between the second oxide semiconductor layer 106a and the conductive layer 108. Even when such an oxide conductive layer is provided, the resistance of the source region or the drain region can be reduced. This can be achieved.

[0205] In addition, in the case where it is not necessary to make the contact region of the second oxide semiconductor layer 106a with the conductive layer 108 n-type, In this case, the conductive layer 108 is provided with a portion thereof in contact with the second oxide semiconductor layer 106a, which is formed by extracting oxygen. It is advisable to use a material with low effect (a material with low affinity for oxygen). For example, titanium nitride is used. The conductive layer 108 has a single layer structure, as described above. When the conductive layer 108 has a layered structure, for example, titanium nitride a two-layer structure of a titanium nitride film and a tungsten film; a two-layer structure of a titanium nitride film and a tungsten film; Two-layer structure of copper-molybdenum alloy film, two-layer structure of tantalum nitride film and tungsten film, tantalum nitride film Two-layer structure of titanium nitride film and copper film, three-layer structure of titanium nitride film, tungsten film and titanium film, etc. can be adopted.

[0206] By using a material with a low oxygen-extracting effect as described above for the conductive layer 108, the oxide semiconductor This prevents the transistor from becoming n-type due to oxygen extraction from the semiconductor layer, and prevents the transistor from becoming n-type due to uneven n-type This can suppress adverse effects on the characteristics.

[0207] As described above, a material with high barrier properties, such as a titanium nitride film or a tantalum nitride film, is used as the second By using the conductive layer 108 in contact with the oxide semiconductor layer 106a, This can prevent impurities from entering the insulating layer 106a and prevent adverse effects on the transistor characteristics. Cut.

[0208] Next, the conductive layer 108 is selectively etched to form the source or drain electrode layer 10 8a, a source electrode layer or a drain electrode layer 108b is formed (see FIG. 3A). An insulating layer is formed on the conductive layer 108, and the insulating layer is etched to form a source electrode layer or An insulating layer having substantially the same shape as the source and drain electrode layers is provided on the drain electrode layer. In this case, the capacitance between the source electrode layer or the drain electrode layer and the gate electrode is It should be noted that in this specification, the term "almost the same" means that the amount of The expression " " is used in the sense that it does not require strict identity, and it is not necessary to regard them as identical. For example, the difference between the case where the film is formed by a single etching process is included. Also, the thickness does not have to be the same.

[0209] For exposure when forming the mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. Therefore, the channel length (L) of the transistor to be formed later can be It is also possible to make the thickness between 10 nm and 1000 nm (1 μm). By reducing the channel length, the operating speed can be improved. Since transistors using semiconductors have a small off-state current, they are less susceptible to the increase in power consumption due to miniaturization. It can suppress the large

[0210] When the conductive layer 108 is etched, the second oxide semiconductor layer 106a is not removed. The materials and etching conditions are adjusted accordingly. Depending on the conditions, a part of the second oxide semiconductor layer 106a may be etched in this step. As a result, the oxide semiconductor layer may have a groove (depression).

[0211] In addition, on the side surfaces of the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, The source or drain electrode layer 108a and the source or drain electrode layer 1 The crystalline layer in contact with 08b may become amorphous.

[0212] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used for multiple etching processes. It is possible to form resist masks corresponding to at least two different patterns. This reduces the number of exposure masks and the corresponding photolithography process. This allows for simplification of the process.

[0213] Here, the second oxide semiconductor layer 106a may be subjected to heat treatment (third heat treatment). By the third heat treatment, the source electrode layer and the drain electrode layer 108a and 108b are not overlapped with each other. First, a high-purity crystalline region is formed in a region including the exposed surface of the second oxide semiconductor layer 106a. Here, the high-purity crystalline region is formed from a crystal that is more crystalline than other regions of the second oxide semiconductor layer 106a. The range of the high purity crystalline region is the range of the second oxide It varies depending on the material that constitutes the semiconductor layer 106a, the conditions of the heat treatment, etc. It is also possible to form a high-purity crystalline region up to the lower interface of the second oxide semiconductor layer 106a. is.

[0214] The third heat treatment can be the same as the first heat treatment. Heat treatment using an electric furnace, heat treatment using heat conduction from a medium such as heated gas, heat radiation Heat treatment by irradiation or the like can be applied.

[0215] For example, high-temperature inert gas (nitrogen, rare gas, etc.) is used at temperatures between 400°C and 900°C. The GRTA treatment can be applied at a temperature of 1000 K. Regarding the upper limit of the heat treatment temperature, Although there is no essential requirement, if the heat resistance of the substrate 100 is low, the temperature may be increased above the heat treatment temperature. The limit must be within the range of its heat resistance.

[0216] When GRTA treatment is applied, the heat treatment time is preferably 1 minute or more and 100 minutes or less. For example, it is recommended to carry out GRTA treatment at 650°C for about 3 to 6 minutes. By applying the GRTA treatment, the heat treatment can be performed in a short time, so that the substrate 100 In other words, compared to when heat treatment is performed for a long time, In addition, the upper limit of the heat treatment temperature can be increased. It is easy to form a high-purity crystalline region in the region including the surface of a.

[0217] In the third heat treatment, it is desirable that the treatment atmosphere does not contain hydrogen (including water). For example, the purity of the inert gas introduced into the heat treatment device is set to 6N (99.9999%, i.e., no impurities). The impurity concentration is 1 ppm or less), preferably 7N (99.99999%, i.e., impurity concentration In addition, hydrogen (including water) may be used instead of inert gas. Sufficiently reduced oxygen gas, N2O gas, ultra-dry air (dew point below -40°C, preferably - 60°C or less) may also be used.

[0218] In this embodiment, the GRTA treatment is applied as the third heat treatment. The treatment is not limited to GRTA treatment. For example, heat treatment using an electric furnace or LRTA treatment is also possible. can also be applied.

[0219] In this manner, by performing the third heat treatment, the second oxide semiconductor layer 106 having crystallinity is formed. In a, a high purity crystalline region, which is a crystalline region with a higher purity, can be recrystallized. , the second oxide semiconductor when the source electrode layer or the drain electrode layer 108a or 108b is formed. If the surface of the layer 106a is damaged, the damaged portion can be repaired.

[0220] In the high-purity crystalline region thus formed, as in the above-mentioned crystals, the crystals of the oxide semiconductor The crystals are oriented such that their c-axes are substantially perpendicular to the surface of the oxide semiconductor layer. Here, "substantially perpendicular" refers to a state within ±10° from the perpendicular direction.

[0221] By including such a high-purity crystalline region, the second oxide semiconductor layer 106a can be given a high degree of electrical conductivity. The electrical anisotropy can be improved.

[0222] By providing such a high-purity crystalline region in the second oxide semiconductor layer 106a, The electrical properties can be further improved.

[0223] Next, without exposing the gate electrode to the air, the gate electrode was removed from the gate electrode in contact with a part of the second oxide semiconductor layer 106a. An insulating layer 112 is formed (see FIG. 3B). The gate insulating layer 112 is formed by a CVD method or a sputtering method. The gate insulating layer 112 can be formed by a deposition method or the like. Silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, titanium oxide The gate insulating layer 112 is preferably formed to include a single layer structure. The thickness of the gate insulating layer 112 is not particularly limited. However, for example, it is 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less. It is possible.

[0224] Note that an oxide semiconductor that has been made i-type or substantially i-type by removing impurities or the like is (Highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, high quality is required for the gate insulating layer 112.

[0225] In this embodiment mode, the gate insulating layer 112 is formed using a high-density plasma apparatus. Here, the high-density plasma device is 1×10 11 / cm 3 Plasma density above For example, a device that generates plasma by applying microwave power of 3kW to 6kW. This allows the formation of an insulating film.

[0226] For example, high density plasma CVD using microwaves (e.g., 2.45 GHz) can This is advantageous in that it allows the formation of a high-quality gate insulating layer 112 that is dense and has a high dielectric strength. The oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, reducing the interface state density. This is because it is possible to improve the interface characteristics.

[0227] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma was generated under a pressure of 10 Pa to 30 Pa to form a gate insulating layer 1. Then, the supply of monosilane gas was stopped, and the nitrous oxide was formed without exposure to the atmosphere. The surface of the insulating film may be subjected to plasma treatment by introducing nitrogen (N2O) and a rare gas. In particular, plasma treatment performed on the surface of an insulating film by introducing nitrous oxide (N2O) and rare gases The insulating film that has undergone the above process sequence has a thin film thickness, e.g., 100 This is an insulating film that can ensure reliability even at thicknesses of less than nm.

[0228] When forming the gate insulating layer 112, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar include helium, argon, krypton, and xenon. Among these, it is preferable to use argon, which is inexpensive.

[0229] In addition, the insulating film obtained by the high density plasma device can be formed with a consistent thickness. The insulating film obtained by the high density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0230] The insulating film obtained through the above process sequence is different from the insulating film obtained using a conventional parallel plate PCVD device. The etching rates are significantly different when the same etchant is used. The insulating film obtained by the parallel plate PCVD equipment is 10% or more or 20% slower and more highly The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0231] In this embodiment, the gate insulating layer 112 is formed by a high density plasma device to a thickness of 100 nm. A silicon oxynitride film (also called SiOxNy, where x>y>0) is used.

[0232] Of course, if a good insulating layer can be formed as the gate insulating layer 112, sputtering is also possible. It is also possible to apply other methods such as a coating method or a plasma CVD method. An insulating layer whose film quality or interface characteristics are modified by treatment may also be applied. In addition, the quality of the gate insulating layer 112 is good and the interface state with the oxide semiconductor layer is low. It is sufficient to provide a material that can reduce density and form a good interface.

[0233] In this way, the interface characteristics with the gate insulating layer 112 are improved, and impurities in the oxide semiconductor are removed. By excluding substances, especially hydrogen and water, the gate bias and thermal stress test (BT test: For example, at 85°C, 2 x 10 6 V / cm, 12 hours, etc.), the threshold voltage (Vt It is possible to obtain a stable transistor in which h) does not fluctuate.

[0234] Thereafter, it is desirable to perform a fourth heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. For example, the heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere. By using the fourth heat treatment, it is possible to reduce variations in the electrical characteristics of the transistors. Depending on the theory, oxygen can also be supplied to the oxide semiconductor layer 106a.

[0235] In this embodiment, the fourth heat treatment is performed after the gate insulating layer 112 is formed. The timing of the fourth heat treatment is not particularly limited as long as it is performed after the third heat treatment. The heat treatment is not an essential step.

[0236] Next, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b on the gate insulating layer 112 are A gate electrode layer 114 is formed in a region overlapping with the gate electrode 106a (see FIG. 3C). The electrode layer 114 is formed by forming a conductive layer on the gate insulating layer 112 and then selectively paving the conductive layer. It can be formed by turning.

[0237] The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed using aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or a material containing the above elements. The alloy may be formed using titanium nitride, which is a nitride of the above-mentioned elements. It may be formed using manganese, magnesium, zirconium, etc. Alternatively, a material containing one or more of aluminum and beryllium may be used. , titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Materials containing one or more selected elements may also be used.

[0238] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0239] The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing titanium, and two layer structure of titanium film laminated on aluminum film. Two-layer structure with titanium film stacked on titanium nitride film, tungsten film on titanium nitride film A two-layer structure in which a tungsten film is laminated on a nitride film containing tantalum and silicon. and a three-layer structure consisting of a titanium film, an aluminum film, and another titanium film. Here, a conductive layer is formed using a material containing titanium and processed into the gate electrode layer 114. do.

[0240] Next, an interlayer insulating layer 116 and an interlayer insulating layer 117 are formed on the gate insulating layer 112 and the gate electrode layer 114. The insulating layer 118 is formed (see FIG. 3(D)). The film can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, nitride Inorganic materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating layer 100 can be formed using a material containing an organic insulating material. The insulating layer 116 and the interlayer insulating layer 118 are stacked in a layered structure. There are no limitations on the number of layers, and the structure may be a single layer or a laminated structure of three or more layers.

[0241] For example, the interlayer insulating layer 118 has a thickness of at least 1 nm, and is formed by a method such as sputtering. The insulating layer 118 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer 118. In this embodiment, a silicon oxide film having a thickness of 300 nm is formed by sputtering as the interlayer insulating layer 118. The substrate temperature during film formation should be between room temperature and 300°C. In this case, the temperature is set to 100°C. The silicon oxide film is formed by sputtering using a rare gas (typically Argon) atmosphere, oxygen atmosphere, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or A silicon target can be used. For example, a silicon target can be used to oxidize oxygen and nitrogen. Silicon oxide can be formed by sputtering in a nitrogen atmosphere. The interlayer insulating layer 118 provided on the conductor layer is resistant to impurities such as moisture, hydrogen ions, and OH − . The inorganic insulating film does not contain these substances and blocks their penetration from the outside. Silicon oxide film, silicon nitride oxide film, aluminum oxide film, aluminum oxynitride film, etc. Furthermore, a protective insulating film such as a silicon nitride film or an aluminum nitride film is formed on the interlayer insulating layer 118. A border layer may be formed.

[0242] Before forming the interlayer insulating layer 118, the inner wall of the sputtering device, the target surface, and the target It is advisable to perform a preheat treatment to remove any moisture or hydrogen remaining in the material. After the preheating process is complete, cool the substrate or sputtering equipment and then store it in a cool, dry place without exposing it to the air. The interlayer insulating layer 118 is formed. In this case, the target coolant is not water but oil or the like. Repeated introduction and evacuation of nitrogen without heating can also produce a certain effect, but It's even better if you do it while it's hot.

[0243] After the interlayer insulating layer 118 is formed, a silicon nitride film is formed by sputtering without being exposed to the air. Alternatively, a laminated structure may be formed.

[0244] In addition, the interlayer insulating layer 118 and the interlayer insulating layer 116 are provided with a contact that reaches the gate electrode layer 114. A contact hole is formed, electrically connected to the gate electrode layer 114, and a contact for applying a gate potential is formed. A connection electrode may be formed on the interlayer insulating layer 118. Alternatively, the gate electrode may be formed after the interlayer insulating layer 116 is formed. A contact hole is formed on the source electrode layer 114, and a source electrode layer or a drain electrode layer is formed on the contact hole. A connection electrode is formed using the same material as the connection electrode layer, an interlayer insulating layer 118 is formed on the connection electrode, and the interlayer insulating layer 118 is formed on the connection electrode. After forming a contact hole in the insulating layer 118 that reaches the connection electrode, the insulating layer 118 is electrically connected to the connection electrode. An electrode for connecting to the gate electrode and applying a gate potential may be formed on the interlayer insulating layer 118 .

[0245] It is desirable that the interlayer insulating layer 118 be formed so that its surface is flat. By forming the interlayer insulating layer 118 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 118. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0246] As a result, the second oxide semiconductor layer 104a was grown as a crystal from the crystalline region of the first oxide semiconductor layer 104a. A transistor 150 using the semiconductor layer 106a is completed.

[0247] By manufacturing the transistor 150 by the above-described method, the second oxide semiconductor layer 1 The crystallinity of O6a allows it to achieve good electrical properties.

[0248] The first and second heat treatments are used to crystallize the semiconductor and oxidize hydrogen, which is an n-type impurity. It is highly purified so that impurities other than the main component of oxide semiconductors are removed as much as possible. In other words, impurities are added to the Instead of simply converting it to i-type, impurities such as hydrogen and water are removed as much as possible to achieve high purity. By purifying the oxide semiconductor layer, the oxide semiconductor layer can be made into an i-type (intrinsic semiconductor) or close to it. The threshold voltage of the transistor can be made positive, so that it is a so-called normally-off transistor. A star rating of 150 can be achieved.

[0249] In addition, when the transistor 150 is manufactured by the above-described method, the first oxide semiconductor layer 1 The hydrogen concentrations in the oxide semiconductor layers 104a and 106a were 5×10 18 / cm 3 The following is true: , and the off-current of the transistor 150 is the measurement limit of 1 × 10 -13 A or less. As described above, the hydrogen concentration is sufficiently reduced, and the first purified gas is obtained by supplying oxygen. By using the oxide semiconductor layer 104a and the second oxide semiconductor layer 106a, excellent characteristics can be obtained. Thus, a transistor 150 having a high conductivity can be obtained.

[0250] Conventional oxide semiconductors are generally n-type, and even when the gate voltage is 0 V, the source and drain electrodes Even if the field-effect mobility is high, the current tends to flow between the electrodes, which is called a normally-on state. If the transistor is normally on, it is difficult to control it as a circuit. When the conductor is n-type, the Fermi level (Ef) is the intrinsic Fermi level located in the center of the band gap. It is located away from the Elmi level (Ei) and closer to the conduction band. It is known that some of the hydrogen atoms act as donors and are one of the factors that cause the material to become n-type.

[0251] Therefore, in order to make the oxide semiconductor layer i-type, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor. By purifying the oxide semiconductor to the extent possible, impurities other than the main component of the oxide semiconductor are minimized. It is made intrinsic (i-type) or substantially intrinsic, i.e., it is made i-type by adding impurities. By removing impurities such as hydrogen and water as much as possible, it is possible to obtain a highly purified i-type (intrinsic semiconductor). The feature of this method is that the Fermi level ( Ef) can be made to be at the same level as the intrinsic Fermi level (Ei).

[0252] By highly purifying the oxide semiconductor layer, the threshold voltage of the transistor can be increased. This makes it possible to realize a so-called normally-off switching element.

[0253] As one of the processes for increasing the purity, a process for increasing the purity is carried out before or after the formation of an oxide semiconductor film. It is preferable to remove any moisture remaining in the sputtering device during or after film formation. To remove residual moisture in the sputtering device, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. As an exhaust means, a turbo pump with a cold trap is preferably used. The deposition chamber of the sputtering apparatus evacuated using a cryopump may be, for example, , hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) are exhausted. In this case, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. The relative density of the oxide semiconductor in the oxide semiconductor film formation target is 80% or more, preferably 95%. % or more, and more preferably 99.9% or more. By using the ion implantation pot, the impurity concentration in the oxide semiconductor film to be formed can be reduced.

[0254] If impurities are mixed into the oxide semiconductor film to be formed, the oxide semiconductor film may be damaged during subsequent heat treatment for crystallization. In this case, there is a risk that unidirectional crystal growth, i.e., crystal growth from the surface downward, will be hindered. It is ideal to have no impurities in the semiconductor film, and it is difficult to achieve high purity. It is extremely important.

[0255] In addition, before the oxide semiconductor film is formed, the inner wall of the sputtering apparatus, the surface of the target, and the target A preheat treatment may be carried out to remove any moisture or hydrogen remaining in the material. The preheating process involves heating the film-forming chamber to 200 to 600°C under reduced pressure. There are other methods, such as repeatedly introducing and exhausting nitrogen or inert gas while heating. It is recommended to use oil or fat as the target coolant instead of water. Repeating this process will produce a certain effect, but it is even better if you do it while heating. After the above steps are completed, the substrate or the sputtering apparatus is cooled, and an oxide semiconductor film is formed.

[0256] In addition, a sputtering agent used in forming an oxide semiconductor film or a material film formed in contact therewith is Tagas also contains impurities such as hydrogen, water, hydroxyl groups, and hydrides at a concentration of about several ppm (preferably It is preferable to use a high-purity gas in which the concentration has been reduced to about several ppb.

[0257] In addition, during the deposition of the oxide semiconductor film by sputtering, the substrate is heated to a temperature above room temperature and below the strain point of the substrate. May be heated.

[0258] In addition, one of the processes for achieving high purity is to use an atmosphere containing almost no hydrogen or moisture. Under atmospheric conditions (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, moisture dew point -40℃ Hereinafter, the first heat treatment is preferably performed at a temperature of a dew point of −50° C. or lower. This process is also called dehydration or dehydrogenation, which involves the desorption of H, OH, and the like from the oxide semiconductor layer. The temperature is raised in an inert atmosphere, and then switched to an oxygen-containing atmosphere during the heating process. When the above treatment is carried out or when heat treatment is carried out in an oxygen atmosphere, it can also be called an oxidation treatment.

[0259] The first heat treatment is a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Annealing (LRTA) method or lamp light Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. In addition, the first heat treatment can be performed simultaneously with heating by irradiating light of 450 nm or less. The oxide semiconductor layer that has been subjected to the first heat treatment for purification may be purified after the first heat treatment. The thermal desorption spectroscopy (TDS) was performed on the oxide semiconductor layer after the treatment. Even when measurements were taken up to 450°C using spectroscopy, at least one of the two water peaks was observed. The heat treatment conditions should be such that the single peak appearing around 300°C is not detected. , T for a transistor using an oxide semiconductor layer that has been subjected to heat treatment for purification. Even when measurements were taken up to 450°C with DS, the water peak that appears around 300°C was not detected. I can't.

[0260] The first heat treatment is performed at a high temperature in order to grow crystals without a polycrystalline layer serving as a seed for crystal growth. It is preferable to heat the substrate for a short time so that crystal growth only occurs from the surface. When the surface of the oxide semiconductor layer is flat, a good plate-like polycrystalline layer can be obtained. It is desirable that the underlying member, for example, the insulating layer or the substrate, be as flat as possible. By increasing the height, it is easy to form a polycrystalline layer that contacts the entire surface of the underlying material, which is useful. For example, the surface roughness is 1μm, which is the same as that of a commercially available silicon wafer. The height difference in an area of ​​1 m square measured by AFM is 1 nm or less, preferably 0.2 nm. .

[0261] The polycrystalline layer is formed by the In electron clouds in the oxide semiconductor overlapping and connecting with each other. Therefore, a transistor with a polycrystalline layer has a high field effect transistor. High mobility can be achieved.

[0262] A method of further growing crystals using the plate-shaped polycrystalline layer formed by the first heat treatment as a seed. One example is shown below using Figures 14(A), 14(B), and 14(C).

[0263] The process sequence is as follows: after forming a first oxide semiconductor layer on a base member, The first heat treatment is carried out to purify the material, and the second heat treatment is carried out in the same process as the first heat treatment to purify the material. A polycrystalline layer having a uniform crystal orientation is formed on the surface of the first oxide semiconductor layer, and a second An oxide semiconductor layer is stacked on the first insulating film. The second oxide semiconductor layer is crystallized using the polycrystalline layer on the surface of the first oxide semiconductor layer as a seed.

[0264] In the first heat treatment, crystal growth occurs from the surface without a crystal layer serving as a seed for crystal growth. In contrast, the second heat treatment allows crystal growth because of the presence of a plate-shaped polycrystalline layer that serves as a seed. It is preferable to heat the mixture at the lowest possible temperature for a long time, as this will result in good crystallinity. The crystallization direction caused by the heat treatment is from bottom to top, from the substrate side to the surface side (recrystallization direction). This is also called the crystal orientation, which is different from the crystal orientation in the first heat treatment. The polycrystalline layer obtained by the thermal treatment is heated again in the second heat treatment, which further improves the crystallinity. .

[0265] FIG. 14(A) shows the crystallization of the first oxide semiconductor layer formed on the base member 500. 1 shows the state after the first heat treatment for the purpose of

[0266] 14B is a cross-sectional view of the second oxide semiconductor layer 502 immediately after its deposition. The oxide semiconductor layer 502 is formed by sputtering, and the metal oxide target is In: Metal oxide target with Ga:Zn=1:1:1 [atom ratio] and In:Ga:Zn= A metal oxide target with a ratio of 1:1:2 may be used.

[0267] FIG. 14(C) is a cross-sectional view after the second heat treatment. The polycrystalline layer of the first oxide crystal layer (first oxide crystal layer 501) is used as a seed to form a second oxide semiconductor. Crystals grow upward toward the surface of the oxide layer 502, forming a second oxide crystal layer 503b. The crystalline members have the same crystal structure.

[0268] A structure corresponding to FIG. 14(B) was actually fabricated, and a TEM photograph of the cross section was taken as shown in FIG. 15. (A). A schematic diagram is shown in Figure 15(B). The TEM photograph was taken at an accelerating voltage of 3 The voltage was set to 0.00 kV, and a high-resolution transmission electron microscope (Hitachi "H9000-NAR": TEM The sample used for the photograph in Figure 15(A) is a glass. An insulating layer is formed on a silicon substrate, and a first In-Ga-Zn-O film with a thickness of 5 nm is formed on the insulating layer. The sample was then heat-treated at 700°C for 1 hour in a dry air atmosphere. ) the first In-Ga-Zn-O film is The c-axis is oriented vertically and the interface between the first In-Ga-Zn-O film and the insulating layer is It can be seen that the crystal is also crystallized and the c-axis is oriented perpendicular to the surface. As shown in A), a first oxide crystal layer 501 containing flat polycrystals is formed on a base member. This flat polycrystal is InGaZnO4 (In:Ga:Zn:O=1:1:1: 4) The c-axis direction of the crystal coincides with the depth direction.

[0269] The first In-Ga-Zn-O film of the sample from which FIG. 15(A) was taken was formed by sputtering. Using this device, a target for oxide semiconductor film formation (In-Ga-Zn-O system oxide semiconductor film formation Target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio], In:Ga Zn=1:1:1 [atom ratio]) at a substrate temperature of 200°C and a deposition rate of 4 nm / m The film is formed using In. The material and composition of the target are not limited to this, and for example, In When a target with a molar ratio of 2O3:Ga2O3:ZnO=1:1:1 was used, I It is easy to obtain polycrystalline n2Ga2ZnO7.

[0270] The crystal structure of In2Ga2ZnO7 contains either In, Ga, or Zn and has an a-axis (aa It can be considered as a stacking structure of layers parallel to the x-axis and b-axis. The electrical conductivity of In2Ga2ZnO7 crystals is mainly controlled by In. The electrical properties of the In-containing layer in the directions parallel to the a-axis and b-axis are good. In the In2Ga2ZnO7 crystal, the electron clouds of In overlap and connect with each other, Apus is formed.

[0271] In addition, instead of the above target, In2O3:Ga2O3:ZnO=2:1:8 [mol A metal oxide target having a ratio of [amount of metal oxide] may be used.

[0272] In addition, a metal oxide target containing no Ga, In2O3:ZnO=1:2 [molar ratio], was used. In the case of a bottom gate transistor, the oxide of Ga is an insulator. Therefore, it is preferable to use the In-Zn-O film rather than the first In-Ga-Zn-O film. This can increase the field effect mobility.

[0273] In addition, the polycrystals obtained in the first heat treatment are heated again in the second heat treatment, This results in a third oxide crystal layer 503a with improved crystallinity.

[0274] In the structure shown in FIG. 14(C), a third oxide crystal is formed on and in contact with the base member 500. The first oxide crystal layer 503a and the second oxide crystal layer 503b are stacked in this order. The materials of the oxide crystal layer 501 and the second oxide semiconductor layer 502 are c As long as axially oriented polycrystals can be obtained, there is no particular limitation, and different materials may be used. Alternatively, materials having the same main component may be used.

[0275] Note that when oxide semiconductor materials having the same main component are used, as shown by the dotted line in FIG. In addition, the boundary between the third oxide crystal layer 503a and the second oxide crystal layer 503b becomes unclear. It can be considered as a single layer structure.

[0276] Thus, a multilayer structure consisting of a stack of the third oxide crystal layer 503a and the second oxide crystal layer 503b was formed. The crystal layer can be grown by two separate heat treatments.

[0277] Note that in FIG. 14A, the relatively thin film formed on at least the surface of the first oxide semiconductor layer The polycrystalline layer has a relatively uniform crystal orientation, and the crystals grow from the surface in the depth direction, so they are not affected by the underlying material. It can be formed without any impact.

[0278] In fact, after the deposition of the second In-Ga-Zn-O film, the film was heated at 650°C for 6 minutes in a nitrogen atmosphere. The TEM photograph of the cross section after the treatment is shown in Figure 16(A). In FIG. 16(A), the entire second In-Ga-Zn-O film is crystallized. The crystal structure of the second In-Ga-Zn-O film is similar to that of the second In-Ga-Zn-O film. It can be seen that the c-axis is oriented perpendicular to the surface of the nO film. Even after the treatment, the area near the interface between the insulating layer and the first In-Ga-Zn-O film was not crystallized. can be confirmed.

[0279] The first oxide semiconductor layer, for example, an In-Ga-Zn-O film, has a relatively uniform crystal orientation on its surface. The mechanism by which the In-Ga-Zn-O crystal layer is formed is explained. The zinc contained in the film diffuses and gathers near the surface, becoming seeds for crystal growth. The crystal growth in the direction (parallel to the surface) is faster than the crystal growth in the depth direction (perpendicular to the surface). This is because the thickness is stronger than the length, forming a flat polycrystalline layer. In the case of the Zn-based ferroelectric, In and Ga were not detected, but Zn was detected under vacuum heating conditions, especially at 300℃. This is inferred from the fact that a peak is observed around the It has been confirmed that lead can be detected at temperatures around 200°C.

[0280] As a comparative example, an In-Ga-Zn-O film having a thickness of 50 nm was formed, and then the film was heated at 700°C. The TEM photograph of the cross section of the sample after heating for 1 hour is shown in Figure 17(A). A schematic diagram is shown in FIG. 17(B). The TEM photograph in FIG. 17(A) was taken at an acceleration voltage of 300 kV, and a high-resolution transmission electron microscope (Hitachi "H9000-NAR": TEM) was used. From Figure 17(A), it is clear that the In-Ga-Zn-O film Approximately 5 nm from the surface is crystallized, and there are many amorphous regions inside the In-Ga-Zn-O film. It can be seen that multiple crystals with no uniform orientation exist randomly. Therefore, after forming a thick film with a thickness of 50 nm, it was heated at 700°C, which is higher than 650°C, for more than 6 minutes. Even if a single heat treatment of one hour is performed, the entire thick film can be made into a crystalline layer with high orientation. It can be said that this is difficult.

[0281] Based on these experimental results, we decided to perform film formation in two steps to form a polycrystalline layer that would serve as a seed for crystal growth. After that, a thick polycrystalline layer can be formed by forming a film again and then growing the crystals. It can be seen that the method disclosed in this specification is extremely useful. Only after two heat treatments is a highly oriented crystal layer formed, i.e., the surface of the oxide semiconductor layer. A thick polycrystalline layer with the c-axis oriented perpendicular to the surface can be obtained.

[0282] In addition, devices using metal oxides, typically In-Ga-Zn-O films, are also susceptible to single-crystal Si It is completely different from devices that use silicon dioxide, SiC, or GaN. It is.

[0283] Known wide-gap semiconductors are SiC (3.26 eV) and GaN (3.39 eV). However, SiC and GaN are expensive materials. To selectively form the region, phosphorus or aluminum is doped and then activated. In addition, GaN requires a temperature of 1200°C or higher for epitaxial growth. The epitaxial growth process involves heating at temperatures above 00°C for a long period of time. However, a processing temperature of 1000°C or higher is required, making it virtually impossible to form a thin film on a glass substrate. It is Noh.

[0284] In addition, SiC and GaN are only available as single crystals, and control by PN junction is required, making it difficult to achieve a more complete single crystal structure. Therefore, there is a risk of unintentional contamination during the manufacturing process. By introducing the electrons, they become donors or acceptors, so there is no lower limit to the carrier density. On the other hand, metal oxides can exist in all crystalline structures, whether amorphous, polycrystalline, or single crystal. This is because φ can be used without using PN junction control. MS Against χ OS + 1 / 2Eg OS , φ MD Against χ OS +1 / 2Eg OS and the work functions of the source and drain ( φ MS and φ MD ) and the electron affinity of the metal oxide (χ OS ) and energy bandwidth (Eg OS ) is used to control the band equivalent to controlling a PN junction. These are some of the characteristics of metal oxides.

[0285] The band gap of metal oxides, typically In-Ga-Zn-O films, is also approximately that of single-crystal silicon. It is three times wider and is a cheaper material than SiC, as it has lower manufacturing costs.

[0286] The band gap of In-Ga-Zn-O is 3.05 eV, and based on this value, the intrinsic capacitance The electron energy distribution f(E) in a solid is calculated by the following formula: It is known to follow the Milieu-Dirac statistics.

[0287]

number

[0288] In ordinary semiconductors where the carrier density is not extremely high (not degenerate), the following relationship holds: do.

[0289]

number

[0290] Therefore, the Fermi-Dirac distribution in equation (1) can be expressed as the Boltzmann distribution in the following equation: is approximated.

[0291]

number

[0292] Using equation (3), we can calculate the intrinsic carrier density (n i ) gives the following formula:

[0293]

number

[0294] Then, in equation (4), the effective densities of state (Nc, Nv) of Si and In-Ga-Zn-O, The intrinsic carrier density was calculated by substituting the value of the gate gap (Eg). The results are shown in Table 1. .

[0295] [Table 1]

[0296] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. When the band gap of IGZO is selected as 3.05 eV, Si and In-Ga-Zn- In O, we assume that the intrinsic carrier density approximately follows the Fermi-Dirac distribution law, The former has a carrier density about 10 17 It can be said to be twice as big.

[0297] In addition, oxide semiconductors are formed into thin films by sputtering at temperatures ranging from room temperature to 400°C. The maximum process temperature is less than 850°C, typically between 450°C and 700°C. When the maximum process temperature is set to the strain point of the glass or lower, it is possible to form a large-area glass. Therefore, for industrialization, the maximum process temperature is 850 ℃, typically between 450℃ and 700℃, to produce wide bandgap metal oxides. It is important to be able to do it.

[0298] Furthermore, even when silicon integrated circuits are made three-dimensional, the processing temperature for oxide semiconductors is low. Since the temperature is lower than the temperature (1050°C) that would destroy the bond on the silicon side, it is possible to It is also possible to apply this technology to three-dimensional integrated circuits.

[0299] As described above, the disclosed invention realizes a semiconductor device with a new structure having excellent characteristics. will be done.

[0300] <Variations> Next, modifications of the semiconductor device shown in FIGS. 1 to 3 will be described with reference to FIGS. 4 to 6. Note that many of the components of the semiconductor device shown in FIGS. 4 to 6 are the same as those shown in FIGS. Since the semiconductor device is the same as that shown in the previous section, only the differences will be described here.

[0301] The transistor 150 illustrated in FIG. 4A includes an oxide semiconductor layer 106a having a recess (groove). The recessed portion is provided with the source or drain electrode layer 108a and the This is formed by etching when forming the source electrode layer or the drain electrode layer 108b. Therefore, the recess is formed in the region overlapping the gate electrode layer 114. The recessed portion makes it possible to reduce the thickness of the semiconductor layer in the channel forming region. This contributes to suppressing the short channel effect.

[0302] The transistor 150 shown in FIG. 4B includes an oxide semiconductor layer having a high-purity crystalline region 110. The high-purity crystalline region 110 is a source electrode layer or a drain electrode layer. After forming the electrode layer 108a and the source or drain electrode layer 108b, Therefore, the high purity crystalline region 11 0 is the exposed second electrode layer that does not overlap with the source or drain electrode layer 108a, 108b. The high-purity oxide semiconductor layer 106a is formed in a region including the surface thereof. The crystalline region 110 is a region in which the crystallinity is higher than that of other regions of the second oxide semiconductor layer 106a. The high-purity crystalline region 110 provides the second oxide semiconductor layer 106a with This can improve the electrical anisotropy of the semiconductor device, thereby further improving the electrical characteristics of the semiconductor device. It is possible.

[0303] The transistor 150 illustrated in FIG. 4C includes an oxide semiconductor layer 106a having a recess (groove). and the source electrode layer or the drain electrode layer 108a, 108b is not overlapped with the exposed The second oxide semiconductor layer 106a has a high-purity crystalline region 110 in a region including the surface thereof. That is, the characteristics of the transistor 150 according to FIG. 4(A) and the transistor according to FIG. The effects resulting from this configuration are as shown in FIG. This is the same as in the case of FIG. 4(B).

[0304] The transistor 150 illustrated in FIG. 5A includes a source or drain electrode layer 108a, An insulating film having substantially the same shape as the source electrode layer or the drain electrode layer 108b is formed on the source electrode layer or the drain electrode layer 108b. In this case, the source electrode layer or the drain electrode layer is a layer 109a and an insulating layer 109b. The capacitance between the gate electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. In this specification, the expression "substantially the same" does not mean "strickenly the same." It is used for the purpose of not requiring that there be one, and includes a range that can be considered the same. For example, differences in thickness are allowed when formed by a single etching process. It is not necessary that the

[0305] The transistor 150 illustrated in FIG. 5B includes an oxide semiconductor layer 106a having a recess (groove). and a source or drain electrode layer 108a and a source or drain electrode layer On the drain electrode layer 108b, an insulating layer 109a having substantially the same shape as the drain electrode layer 108b and an insulating layer 109b are formed. 4A and 5B. The transistor 150 has the characteristics of the transistor 150 according to (A) and the transistor 150 according to (B). The results are the same as those in FIG. 4(A) and FIG. 5(A).

[0306] The transistor 150 shown in FIG. 5C includes a source or drain electrode layer 108a, and the exposed second oxide layer that does not overlap the source electrode layer or the drain electrode layer 108b. The semiconductor layer 106a has a high-purity crystalline region 110 in a region including the surface thereof, and the source electrode a source or drain electrode layer 108a and a source or drain electrode layer 108b On top of these, insulating layers 109a and 109b having substantially the same shape are provided. That is, the characteristics of the transistor 150 according to FIG. 4(B) and the characteristics of the transistor 150 according to FIG. 50. The effects resulting from this configuration are also shown in FIG. 4(B) and FIG. The same as in 5(A).

[0307] The transistor 150 shown in FIG. 6A has a single-layer structure for the source electrode layer or the drain electrode layer. 108a and a source or drain electrode layer 108b. A single layer structure of a titanium layer can be adopted. In the case of using a structure, etching that forms a good tapered shape is possible compared to the case of using a laminated structure. This makes it possible to achieve this.

[0308] In the transistor 150 shown in FIG. 6B, the source or drain electrode layer 108a and the source or drain electrode layer 108b in contact with the oxide semiconductor layer 106a. A conductive layer 1 made of a material with low oxygen-removing effect (a material with low affinity for oxygen) is formed in the portion where the conductive layer 1 is to be formed. The conductive layer 107a and the conductive layer 107b have a low oxygen extraction effect. By having such a structure, it is possible to prevent the oxide semiconductor layer from becoming n-type due to oxygen extraction, and It is possible to suppress adverse effects on transistor characteristics caused by non-uniform n-type doping, etc.

[0309] In FIG. 6B, the source or drain electrode layer 108a and , the source electrode layer or the drain electrode layer 108b is employed. The present invention is not limited to this. A single layer structure of a conductive layer made of a material with a low oxygen-extracting effect can also be used. In the case of a single layer structure, for example, titanium nitride In the case of a laminated structure, for example, a titanium nitride film can be used. A two-layer structure of a film and a titanium film can be adopted.

[0310] The transistor 150 illustrated in FIG. 28A is a transistor formed of a first oxide semiconductor in which an amorphous portion remains in the lower portion. Here, the region including the first oxide semiconductor layer 104a in FIG. An enlarged view of the first oxide semiconductor is shown in FIG. 28(B). The layer 104a is composed of a lower amorphous region 104aa and an upper crystalline region 104ab. In this way, the channel formation region of the transistor 150 is By leaving an amorphous region below the functional crystalline region, carriers flowing through the crystalline region This is preferable because it is not affected by the interface with the insulating layer 102 .

[0311] 29 is a cross-sectional view showing an example of the configuration of a semiconductor device. The transistor 250 is formed in the lower part using a material other than an oxide semiconductor (for example, silicon). The transistor 150 using an oxide semiconductor is provided in the upper portion. The transistor 150 using the above is the transistor 150 shown in FIG. Both transistor 250 and transistor 150 are described as n-type transistors. However, p-type transistors may also be used. In particular, transistor 250 is a p-type transistor. It is easy to do.

[0312] The transistor 250 includes a channel forming region 21 provided in a substrate 200 including a semiconductor material. 6, and the impurity region 214 and the high concentration impurity region 215 provided so as to sandwich the channel forming region 216. The pure region 220 (collectively referred to as the impurity region) and the channel forming region 21 6, and a gate insulating layer 208a provided on the gate insulating layer 208a. The electrode layer 210a and the source electrode layer or the drain electrode layer electrically connected to the impurity region 214 are 29, the source electrode layer 230a and the drain electrode layer 230b. (see).

[0313] Here, a sidewall insulating layer 218 is provided on the side surface of the gate electrode layer 210a. In addition, in the region of the substrate 200 that does not overlap with the sidewall insulating layer 218 in plan view, A metal compound region 224 having a high concentration impurity region 220 and contacting the high concentration impurity region 220 In addition, an element isolation insulating layer 20 is formed on the substrate 200 so as to surround the transistor 250. 6 is provided, and an interlayer insulating layer 226 and an interlayer insulating layer 228 are provided to cover the transistor 250. The source or drain electrode layer 230a, the source electrode The layer or drain electrode layer 230b is formed by the interlayer insulating layer 226, the interlayer insulating layer 228, and the insulating An opening formed in layer 234 provides electrical contact with metal compound region 224 . That is, the source or drain electrode layer 230a, the source or drain electrode layer The layer 230b is connected to the high concentration impurity region 220 and the impurity region 224 via the metal compound region 224. 214 is electrically connected to the

[0314] The transistor 150 includes an oxide semiconductor layer 106a provided over the insulating layer 102 and an oxide semiconductor layer 106b. A source electrode provided on the semiconductor layer 106a and electrically connected to the oxide semiconductor layer 106a a source or drain electrode layer 108a, a source or drain electrode layer 108b, and , the oxide semiconductor layer 106a, the source or drain electrode layer 108a, and the source a gate insulating layer 112 provided to cover the electrode layer or drain electrode layer 108b; a gate electrode provided on the gate insulating layer 112 in a region overlapping with the oxide semiconductor layer 106a; layer 114 (see FIG. 29).

[0315] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Here, the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118 have , the source or drain electrode layer 108a, the source or drain electrode layer 10 8b, and electrodes 254d and 254 e are the source or drain electrode layer 108a, the source or drain electrode layer 108b, The electrode 254d is formed in contact with the inner electrode layer 108b. , openings provided in the gate insulating layer 112, the interlayer insulating layer 116, and the interlayer insulating layer 118. Electrodes 254a and 254b are in contact with electrodes 236a, 236b, and 236c through the 4b, an electrode 254c is formed.

[0316] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 106a and oxygen is supplied to the oxide semiconductor layer 106a. It is desirable that the oxide semiconductor layer 1 is highly purified by the above-mentioned method. The hydrogen concentration of 06a is 5×10 19 / cm 3 Below 5×10 18 / cm 3 below, More preferably 5 x 10 17 / cm 3 The hydrogen concentration must be sufficiently reduced and the acid must be In the oxide semiconductor layer 106a that is highly purified by supplying silicon, silicon wafers (silicon wafers doped with trace amounts of impurity elements such as phosphorus and boron) Carrier density (1×10 14 / cm 3 A sufficiently small carrier density value compared to (e.g., 1×10 12 / cm 3 Less than 1.45 x 10 10 / cm 3 below) In this way, by using an i-type or substantially i-type oxide semiconductor, The transistor 150 can have excellent off-state current characteristics. When the voltage Vd is +1V or +10V, the gate voltage Vg is -5V to -20V In the range, the off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently low. The oxide semiconductor layer 106a is reduced and highly purified, and the off-state current of the transistor 150 is By reducing the current, a semiconductor device with a new configuration can be realized. The hydrogen concentration in the oxide semiconductor layer 106a was measured by secondary ion mass spectrometry (SIMS). The results were measured by General Ion Mass Spectroscopy.

[0317] The oxide semiconductor forming the oxide semiconductor layer is not particularly limited as long as it has a non-single-crystal structure. For example, amorphous structure, microcrystalline (microcrystal, nanocrystal, etc.) structure, polycrystalline Crystalline structure, structure containing microcrystals or polycrystals in amorphous, microcrystals or polycrystals on the surface of amorphous structure Various structures can be applied, such as a structure in which crystals are formed.

[0318] An insulating layer 256 is provided on the interlayer insulating layer 118, and a buried insulating layer 256 is provided on the insulating layer 256. Electrodes 258a, 258b, 258c, and 258d are provided so that the electrodes are embedded in the Here, electrode 258a is in contact with electrode 254a, and electrode 258b is in contact with electrode 254. b, electrode 258c is in contact with electrode 254c and electrode 254d, and electrode 2 58d is in contact with the electrode 254e. It is preferable to use a material containing copper for the electrode 258a and a part of the electrode 258d. By using a material containing copper for a part of the electrode 258b, the electrode 258c, and the electrode 258d, The conductivity can be improved.

[0319] That is, the source electrode layer or drain electrode layer 108a of the transistor 150 is 0c, electrode 236c, electrode 254c, electrode 258c, and electrode 254d, and (e.g., a transistor using a material other than an oxide semiconductor) (Figure 29 Further, the source or drain electrode layer 108b of the transistor 150 is It is electrically connected to other elements via electrodes 254e and 258d. The electrodes (electrode 230c, electrode 236c, electrode 254c, electrode 258c, electrode 254d The configuration of the components (e.g., components) is not limited to the above, and additions, omissions, etc. may be made as appropriate.

[0320] Although one example of a typical connection relationship has been shown above, one embodiment of the disclosed invention is For example, the gate electrode layer 210a of the transistor 250 and the The source electrode layer 150 may be electrically connected to the drain electrode layer 108a. .

[0321] As described above, one embodiment of the disclosed invention can be modified and used in various ways. In addition, the modified examples are not limited to the above examples. For example, the modified examples shown in FIGS. 4(A), 4(B), and 4(C) can be used. , Figure 5(A), Figure 5(B), Figure 5(C), Figure 6(A), Figure 6(B), Figure 28, Figure 29 are applied. It is possible to use the same in any suitable combination as another modified example. You are free to make changes, omissions, etc. within the scope of the content.

[0322] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0323] (Embodiment 2) In this embodiment, a semiconductor device having a different configuration from the semiconductor device according to the previous embodiment and A manufacturing method thereof will be described with reference to FIGS. The configuration is similar to that of the previous embodiment in many respects, so the following mainly focuses on the configuration of the previous embodiment. Only the differences will be explained.

[0324] <Configuration of Semiconductor Device> FIG. 7 is a cross-sectional view showing a transistor 150, which is an example of the configuration of a semiconductor device.

[0325] The difference from the configuration shown in FIG. 1 is that a gate electrode layer 101 is provided below the first oxide semiconductor layer 104a. That is, the transistor 150 shown in FIG. a gate electrode layer 101a, an insulating layer 102 covering the gate electrode layer 101a, and a second insulating layer 103 on the insulating layer 102. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are formed on the first oxide semiconductor layer 104a. a source electrode electrically connected to the second oxide semiconductor layer 106a; a source or drain electrode layer 108a and a source or drain electrode layer 108b. b, the second oxide semiconductor layer 106a, the source or drain electrode layer 108a, and A gate insulating layer 112 covering the source or drain electrode layer 108b, and a gate insulating layer 112 covering the source or drain electrode layer 108b. and a gate electrode layer 114 on the insulating layer 112 (see FIGS. 7A and 7B). Here, the insulating layer 102 also functions as a gate insulating layer.

[0326] Moreover, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150. Note that the interlayer insulating layer 116 and the interlayer insulating layer 118 are not essential components. , may be omitted as appropriate.

[0327] As described in Embodiment 1, the first oxide semiconductor layer 104a has a crystalline structure in a region including a surface. The second oxide semiconductor layer 106a has a crystalline region of the first oxide semiconductor layer 104a. It is formed by crystal growth from the crystalline region.

[0328] The gate electrode layer 101a shown in FIGS. 7A and 7B serves as a so-called back gate. The potential of the back gate is fixed, for example, 0 V, or the ground potential. The practitioner may appropriately determine the gate electrodes above and below the oxide semiconductor layer. By providing a pole, it is possible to carry out bias-thermal stress tests to investigate the reliability of thin film transistors. In the BT test, the characteristics of the thin film transistor before and after the BT test were That is, the gate electrodes are formed above and below the oxide semiconductor layer, and the amount of change in the threshold voltage can be reduced. By providing a gate, reliability can be improved. By controlling the gate voltage, the threshold voltage can be controlled. The value voltage can be set to positive, allowing it to function as an enhancement type transistor. , the threshold voltage can be made negative to function as a depletion type transistor. For example, by combining enhancement and depletion type transistors, An inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured using these elements and used in a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above-mentioned EDMOS circuit.

[0329] Note that the region of the oxide semiconductor layer that overlaps with the irregularities of the insulating layer 102 has a grain boundary and is polycrystalline. In addition, a region of the oxide semiconductor layer that serves as a channel formation region is formed by at least The first oxide semiconductor layer and the second oxide semiconductor layer have a flat surface and the same c-axis orientation. The second oxide semiconductor layer is a polycrystalline body. In the region (channel formation region), the thickness is 1 nm or less (preferably 0.2 nm or less). It is preferable that:

[0330] Details of each component can be found in the previous embodiment and will be omitted here.

[0331] As shown in FIG. 7, the crystalline region of the highly purified first oxide semiconductor layer 104a By using the second oxide semiconductor layer 106a grown from the oxide semiconductor layer 106a, the oxide semiconductor layer 106a can have favorable electrical characteristics. It is possible to realize a semiconductor device.

[0332] The first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a are made of the same material. In the case of homo-epitaxial growth, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are The boundary between the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a becomes indistinguishable. The oxide semiconductor layer 106a and the oxide semiconductor layer 106b can sometimes be regarded as the same layer (see FIG. 7A).

[0333] Of course, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106a may be made of different materials. The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b may be formed as a single layer (see FIG. 7B). When the semiconductor layer 106a is made of a different material (so-called hetero epitaxial growth), For example, the first oxide semiconductor layer 104a is formed of a binary metal oxide, In—Zn—O. The second oxide semiconductor layer 106a is made of a ternary metal oxide, In—Ga—Zn—O. The configuration to be used can be adopted.

[0334] In addition, since the second oxide semiconductor layer 106a is relatively stable, It is possible to prevent impurities (such as moisture) from entering 106a. This can improve the reliability of the second oxide semiconductor layer 106a.

[0335] Furthermore, by having the gate electrode layer 101a, which is a so-called back gate, This makes it easy to adjust the electrical characteristics of the transistor 150. The potential of the gate electrode layer 114 may be the same as that of the gate electrode layer 114, or may be different from that of the gate electrode layer 114. A potential may be applied, or the electrode may be in a floating state.

[0336] <Method for manufacturing semiconductor device> Next, a method for manufacturing a transistor 150, which is an example of a semiconductor device, will be described with reference to FIGS. 10 for further explanation.

[0337] First, a conductive layer 101 is formed on a substrate 100 (see FIG. 8(A)). The details can be referred to in the previous embodiment, so they will be omitted here.

[0338] The conductive layer 101 is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer 101 can be formed by a method. An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements It can be formed using alloys containing manganese, magnesium, zirconium, etc. Materials containing one or more of aluminum, beryllium, and thorium may also be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scum A material containing one or more elements selected from indium may also be used.

[0339] The conductive layer 101 may be formed using a conductive metal oxide. Materials include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). , indium oxide tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO) , indium oxide zinc oxide alloy (In2O3-ZnO), or these metal oxide materials The material may contain silicon or silicon oxide.

[0340] The conductive layer 101 may have a single-layer structure or a stacked structure of two or more layers. In one embodiment of the disclosed invention, after the conductive layer 101 is formed, a heat treatment is performed at a relatively high temperature. Therefore, it is desirable to form the conductive layer 101 using a material with high heat resistance. Suitable materials include titanium, tantalum, tungsten, and molybdenum. It is also possible to use polysilicon or the like in which the conductivity is increased by adding a pure element.

[0341] Next, the conductive layer 101 is selectively etched to form a gate electrode layer 101a. An insulating layer 102 is formed to cover the base electrode layer 101a (see FIG. 8(B)).

[0342] For exposure when forming the mask used for etching, ultraviolet light, KrF laser light, or ArF laser light is used. It is preferable to use the following. In particular, when performing exposure with a channel length (L) of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. It is preferable to use ultraviolet light to expose the mask. It has a high resolution and a large depth of focus, making it suitable for miniaturization.

[0343] The gate electrode layer 101a is a so-called back gate. By this, it is possible to control the electric field in the oxide semiconductor layer 106a. The electrical characteristics of the transistor 150 can be controlled. The wiring may be electrically connected to other wirings or electrodes and be given a certain potential, or may be insulated. It may be in a floating state.

[0344] Incidentally, the "gate electrode" usually refers to a gate electrode whose potential can be intentionally controlled. In the specification, the term "gate electrode" is used even when the potential is not intentionally controlled. For example, for an isolated, floating conductive layer as described above, The gate electrode layer is also sometimes called a "gate electrode layer."

[0345] The insulating layer 102 functions as a base and also as a gate insulating layer. The insulating layer 102 can be formed by using a CVD method, a sputtering method, or the like. Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide The insulating layer 102 is preferably formed to contain tantalum oxide, tantalum oxide, or the like. The insulating layer 102 may have a single layer structure or a multilayer structure. However, it can be set to, for example, 10 nm or more and 500 nm or less.

[0346] Note that if the insulating layer 102 contains hydrogen, water, or the like, hydrogen may enter the oxide semiconductor layer or water may be released from the insulating layer 102. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, which deteriorates the characteristics of the transistor. Therefore, the insulating layer 102 is formed so as to contain as little hydrogen and water as possible. It is desirable.

[0347] For example, when using a sputtering method, remove any remaining moisture in the processing chamber. It is desirable to form an insulating layer 102. In addition, in order to remove residual moisture in the processing chamber, Adsorption type vacuum pumps such as cryopumps, ion pumps, and titanium sublimation pumps It is preferable to use a pump. A turbo pump with a cold trap is used. The processing chamber is evacuated using a cryopump or the like to ensure that hydrogen, water, etc. are sufficiently removed. Therefore, the concentration of impurities contained in the insulating layer 102 can be reduced.

[0348] Furthermore, when forming the insulating layer 102, impurities such as hydrogen and water are preferably present at a concentration of about ppm (preferably It is desirable to use a high purity gas with a concentration reduced to about ppb.

[0349] The insulating layer 102 is required to have high quality, similar to the gate insulating layer 112. Therefore, it is preferable to form the insulating layer 102 by a method similar to that for the gate insulating layer 112. Details are omitted since the previous embodiment can be referred to.

[0350] Next, the first oxide semiconductor layer 104 is formed over the insulating layer 102 and is slightly thinned by a first heat treatment. At least a region including the surface of the first oxide semiconductor layer is crystallized to form the first oxide semiconductor layer. 104 is formed (see FIG. 8C). The above embodiment can be referred to for the conditions and the details of the first oxide semiconductor layer 104. This can be done.

[0351] Note that the region of the first oxide semiconductor layer 104 that overlaps with the irregularities of the gate insulating layer is a grain boundary. In addition, the channel formation region of the first oxide semiconductor layer 104 is The region where the first oxide semiconductor layer and the second oxide semiconductor layer are to be formed has at least a flat surface. are polycrystalline bodies with the same C-axis orientation.

[0352] Next, a second oxide semiconductor layer 104 having a crystalline region at least in a region including a surface thereof is formed on the first oxide semiconductor layer 104. The second oxide semiconductor layer is formed, and the crystal of the first oxide semiconductor layer 104 is formed by the second heat treatment. The region is used as a seed for crystal growth to form the second oxide semiconductor layer 106 (see FIG. 8(D)). (See reference). The method for forming the second oxide semiconductor layer, the conditions for the second heat treatment, and the method for forming the second oxide semiconductor layer For details of 106, the above embodiment can be referred to.

[0353] Next, the first oxide semiconductor layer 104 and the The second oxide semiconductor layer 106 is processed into the first oxide semiconductor layer 104a and the second oxide semiconductor layer 106b, which are island-shaped. The oxide semiconductor layer 106a is formed as follows (see FIG. 9A). The layer 104a and the second oxide semiconductor layer 106a overlap with the gate electrode layer 101a. It should be noted that the above embodiment can be referred to for details.

[0354] Next, the conductive layer 108 is formed so as to be in contact with the second oxide semiconductor layer 106a (FIG. 9(B) )). Then, the conductive layer 108 is selectively etched to form a source electrode layer or a drain electrode layer. A source electrode layer 108a and a source or drain electrode layer 108b are formed (FIG. 9(C)). The conductive layer 108, the source or drain electrode layer 108a, the source or drain electrode layer 108b, The drain electrode layer 108b, the etching process, and other details are the same as those of the previous embodiment. can be taken into consideration.

[0355] As shown in FIG. 9C, the gate electrode layer 101a is a source electrode layer or a drain electrode layer. The region overlapping with the electrode layer 108a (or the source electrode layer or the drain electrode layer 108b) The present invention is also characterized in that it has an edge portion of the source or drain electrode layer 108a, The step of the insulating layer 102, that is, the tapered surface from the flat surface of the gate insulating layer in the cross section, The area between the change points (here, the L shown in Figure 9(C)) OV L OV The region prevents carriers from flowing through the grain boundaries that are generated by the unevenness at the edge of the gate electrode layer. It is important for

[0356] Next, similarly to the above embodiment, the second oxide semiconductor layer 106a is subjected to heat treatment (third heat treatment The third heat treatment may be performed on the source or drain electrode layer 10. 8a and 108b and including the exposed surface of the second oxide semiconductor layer 106a. In this case, a high-purity crystalline region is formed. The thickness varies depending on the material that constitutes the conductor layer 106a, the conditions of the heat treatment, etc. For example, It is also possible to form a high-purity crystalline region up to the lower interface of the second oxide semiconductor layer 106a. For details of the third heat treatment and other details, the previous embodiments can be referred to. .

[0357] Next, without exposing the gate electrode to the air, the gate electrode was removed from the gate electrode in contact with a part of the second oxide semiconductor layer 106a. An insulating layer 112 is formed (see FIG. 10A). Then, a first insulating layer 112 is formed on the gate insulating layer 112. A gate electrode is formed in a region overlapping with the oxide semiconductor layer 104a and the second oxide semiconductor layer 106a. Then, the gate insulating layer 112 and the gate electrode 114 are formed (see FIG. 10(B)). On the electrode layer 114, an interlayer insulating layer 116 and an interlayer insulating layer 118 are formed (see FIG. 10(C)). For details of the above steps, the above embodiment can be referred to.

[0358] By the method described in this embodiment, crystal growth occurs from the crystalline region of the first oxide semiconductor layer 104a. Therefore, the second oxide semiconductor layer 106a can be formed by the above-mentioned method. A conductor device can be realized.

[0359] In addition, the first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are formed by the method described in this embodiment. The hydrogen concentration in the semiconductor layer 106a is 5×10 19 / cm 3 The following is true, and the transistor Off-state current is 1×10 -13 In this way, the hydrogen concentration is sufficiently reduced and the oxygen concentration is The first oxide semiconductor layer 104a and the second oxide semiconductor layer 104b are purified by supplying By using the semiconductor layer 106a, a semiconductor device with excellent characteristics can be realized.

[0360] Furthermore, by having a gate electrode layer, which is a so-called back gate, the electric potential of the semiconductor device can be increased. This makes it easier to adjust the atmospheric properties.

[0361] As described above, the disclosed invention realizes a semiconductor device with a new structure having excellent characteristics. will be done.

[0362] <Variations> Next, regarding a modified example of the semiconductor device shown in FIGS. 7 to 10, FIGS. 11 to 13 will be described. 11 to 13. Most of the components of the semiconductor device shown in FIG. 10. Therefore, only the differences will be described here. explain.

[0363] The transistor 150 illustrated in FIG. 11A includes an oxide semiconductor layer 106 having a recess (groove). The recess includes the source or drain electrode layer 108a and This is formed by etching when forming the source or drain electrode layer 108b. For this reason, the recess is formed in the region overlapping the gate electrode layer 114. The recessed portion makes it possible to reduce the thickness of the semiconductor layer in the channel forming region. This contributes to suppressing short channel effects.

[0364] The transistor 150 shown in FIG. 11B is an oxide semiconductor having a high-purity crystalline region 110. The high-purity crystalline region 110 includes a source electrode layer or a drain electrode layer. After forming the electrode layer 108a and the source or drain electrode layer 108b, The high purity crystalline region 1 is formed by the heat treatment of 3. 10 does not overlap with the source electrode layer or the drain electrode layer 108a, 108b, and is exposed The high-purity oxide semiconductor layer 106a is formed in a region including the surface of the oxide semiconductor layer 106a. The crystalline region is a region having higher crystallinity than other regions of the second oxide semiconductor layer 106a. The high-purity crystalline region 110 provides the second oxide semiconductor layer 106a with The electrical anisotropy can be improved, and the electrical characteristics of the semiconductor device can be further improved. can be done.

[0365] The transistor 150 shown in FIG. 11C includes an oxide semiconductor layer 106 having a recess (groove). a, and does not overlap with the source or drain electrode layers 108a and 108b, The high-purity crystalline region 110 is formed in the region including the exposed surface of the second oxide semiconductor layer 106a. That is, the characteristics of the transistor 150 shown in FIG. 11(A) and the characteristics of the transistor shown in FIG. The effect resulting from this configuration is also shown in FIG. A) and the same as in FIG. 11(B).

[0366] The transistor 150 shown in FIG. 12A includes a source electrode layer or a drain electrode layer 108a. and an insulating film having substantially the same shape as the source electrode layer or the drain electrode layer 108b is formed on the source electrode layer or the drain electrode layer 108b. In this case, the source electrode layer or the drain electrode layer is formed of an insulating layer 109a. The capacitance between the drain electrode layer and the gate electrode layer (so-called gate capacitance) can be reduced. In this specification, the expression "substantially the same" does not mean "strictly the same." It is used in a way that does not necessarily mean that the two are the same, and includes a range in which they can be considered the same. For example, differences in thickness are allowed when the layers are formed by a single etching process. It is not necessary that they be identical.

[0367] The transistor 150 shown in FIG. 12B includes an oxide semiconductor layer 106 having a recess (groove). a, and a source or drain electrode layer 108a and a source electrode layer Alternatively, an insulating layer 109a having substantially the same shape as the drain electrode layer 108b and The insulating layer 109b is included. That is, the features of the transistor 150 in FIG. This structure has the same characteristics as the transistor 150 shown in FIG. The effect is the same as that in the cases of FIG. 11(A) and FIG. 12(A).

[0368] The transistor 150 shown in FIG. 12C includes a source electrode layer or a drain electrode layer 108a. , and a highly pure oxide semiconductor layer was formed in a region including the exposed surface of the second oxide semiconductor layer 106a, which did not overlap with the oxide semiconductor layer 108b. a source or drain electrode layer 108a, a highly crystalline region 110, and On the source electrode layer or drain electrode layer 108b, an insulating layer 10 having substantially the same shape as these is formed. 11B. 12A. The transistor 150 shown in FIG. The effects resulting from this configuration are similar to those in the cases of FIG. 11(B) and FIG. 12(A).

[0369] In the transistor 150 shown in FIG. 13, the source or drain electrode layer 108a and In addition, a portion of the source or drain electrode layer 108b in contact with the oxide semiconductor layer 106a In particular, the conductive layer 107 is made of a material that has a low oxygen-removing effect (a material that has a low affinity with oxygen). The conductive layer 107a has a low oxygen-extracting effect. This prevents the oxide semiconductor layer from becoming n-type due to oxygen extraction, and prevents unevenness in the oxide semiconductor layer. This can suppress the adverse effects on transistor characteristics caused by uneven n-type conversion.

[0370] In FIG. 13, the source electrode layer or drain electrode layer 108a and the The source electrode layer or the drain electrode layer 108b is used in the present invention. The present invention is not limited to the above, and may be applied to a single layer structure of a conductive layer made of a material having a low oxygen-removing effect. However, it may also have a laminated structure of three or more layers. In the case of a single layer structure, for example, a titanium nitride film In the case of a laminated structure, for example, a titanium nitride film and A two-layer structure of titanium film can be used.

[0371] As described above, one embodiment of the disclosed invention can be modified and used in various ways. In addition, the modified examples are not limited to the above examples. For example, the modified examples shown in FIGS. 11(A), 11(B), and 11 (C), Fig. 12(A), Fig. 12(B), Fig. 12(C), Fig. 13 can be combined appropriately to create another variation. It is possible to use it as an example. Of course, within the scope of the description, etc., modifications and You are free to add omissions, etc.

[0372] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0373] (Embodiment 3) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment has an excellent property not found in the prior art. Therefore, electronic devices with new configurations can be provided using the semiconductor device. It is possible to provide

[0374] FIG. 30A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like. The display unit 30 is mounted inside the housing 302. The semiconductor device according to the disclosed invention can be applied to an integrated circuit board or the like. By applying the present invention to the above, high speed operation of the circuit can be realized. By applying the semiconductor device according to the present invention to the display portion 303, a high-quality image can be displayed. In this way, the semiconductor device according to the disclosed invention can be applied to a personal computer. This makes it possible to provide a personal computer with excellent performance.

[0375] FIG. 30B shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. The disclosed invention also includes a stylus 312 as an accessory for operation. Such a semiconductor device is integrated and mounted on a circuit board or the like, and is then mounted on the main body 311. In addition, the semiconductor device according to the present invention can be applied to the display portion 313. By applying the semiconductor device of the present invention to a circuit board or the like, high-speed operation of the circuit can be realized. In addition, the semiconductor device according to the present invention can be applied to the display portion 313. As a result, a high-quality image can be displayed. By applying this device to a personal digital assistant (PDA), it is possible to achieve a highly functional personal digital assistant (PDA). can be provided.

[0376] FIG. 30C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the axis 337. 320 can be used like a paper book.

[0377] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The semiconductor device according to the disclosed invention is integrated and mounted on a circuit board or the like, and is housed in a housing 3. 23 or the inside of the housing 321. The display unit 327 is The display unit 325 and the display unit 327 can display a continuous screen. Alternatively, a different screen may be displayed. By configuring it this way, for example, text can be displayed on the display unit on the right (display unit 325 in FIG. 30(C)). In addition, an image can be displayed on the left display unit (display unit 327 in FIG. 30(C)). By applying this to integrated circuit boards, high-speed circuit operation can be achieved. By applying the semiconductor device according to the present invention to the display portion 327, high-quality images can be displayed. It can be shown.

[0378] FIG. 30C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0379] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0380] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to the display of various cards such as credit cards. By applying the semiconductor device according to the present invention to electronic paper, it is possible to obtain electronic paper with excellent performance. can be provided.

[0381] FIG. 30D shows a mobile phone including the semiconductor device according to the above embodiment. The phone is made up of two housings, housing 340 and housing 341. Housing 341 has a front display panel 342, speaker 343, microphone 344, pointing device 3 46, a camera lens 347, an external connection terminal 348, etc. The mobile phone includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341. The semiconductor device is integrated and mounted on a circuit board or the like, and is installed inside the housings 340 and 341. can be.

[0382] The display panel 342 has a touch panel function, and in FIG. 30(D) an image is displayed. The display panel 342 displays the operation keys 345 according to the present invention. The display panel 342 can be applied with a semiconductor device according to the present invention. By applying this setting, high-quality images can be displayed. A booster circuit is implemented to boost the voltage output from the solar battery cell 349 to the voltage required for each circuit. In addition to the above configuration, it is equipped with a non-contact IC chip, a small recording device, etc. It can also be configured as:

[0383] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0384] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, The device may also have an infrared communication function, a television receiving function, etc. By applying the semiconductor device to a mobile phone, it is possible to provide a mobile phone with excellent performance. Cut.

[0385] FIG. 30(E) shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc. Such a semiconductor device can be applied to the display portion (A) 367 and the display portion (B) 365. The semiconductor device according to the invention disclosed herein is applied to the display portion (A) 367 and the display portion (B) 365. As a result, a high-quality image can be displayed. By applying this device to a digital camera, it is possible to provide a digital camera with excellent performance. Cut.

[0386] FIG. 30F shows a television set including the semiconductor device according to the above embodiment. In the vision device 370, a display unit 373 is built into a housing 371. In this case, the stand 375 is used to hold the case in place. The display portion 373 is provided with a semiconductor device according to the present invention. By applying this, high-speed operation of the switching element becomes possible, and the area of ​​the display unit 373 can be increased. It can be realized.

[0387] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information may be provided.

[0388] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). In this way, the semiconductor device according to the disclosed invention can be applied to a television set. This makes it possible to provide a television device with excellent performance.

[0389] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Explanation of symbols]

[0390] 100 boards 101 Conductive layer 101a gate electrode layer 102 Insulating layer 104 Oxide semiconductor layer 104a Oxide semiconductor layer 104aa amorphous region 104ab Crystal region 105 Oxide semiconductor layer 106 Oxide semiconductor layer 106a Oxide semiconductor layer 107a Conductive layer 107b Conductive layer 108 Conductive layer 108a Source electrode layer or drain electrode layer 108b Source electrode layer or drain electrode layer 109a Insulating layer 109b Insulating layer 110 High purity crystal region 112 Gate insulating layer 114 gate electrode layer 116 Interlayer insulating layer 118 Interlayer insulating layer 150 transistors 200 boards 206 Element isolation insulating layer 208a Gate insulating layer 210a gate electrode layer 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulation layer 228 Interlayer Insulation Layer 230a Source electrode layer or drain electrode layer 230b Source electrode layer or drain electrode layer 230c electrode 230c electrode 234 Insulating Layer 236a Electrode 236b Electrode 236c electrode 250 transistors 254a electrode 254b electrode 254c electrode 254d electrode 254e electrode 256 insulating layer 258a electrode 258b Electrode 258c electrode 258d electrode 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 500 Base material 501 Oxide crystal layer 502 Oxide semiconductor layer 503a Oxide crystal layer 503b Oxide crystal layer

Claims

[Claim 1] a first oxide semiconductor layer provided over a substrate having an insulating surface and having a crystalline region grown inward from a surface of the first oxide semiconductor layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer having a region in contact with the second oxide semiconductor layer; a gate insulating layer having a region covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate electrode layer provided over the gate insulating layer and having a region overlapping with the second oxide semiconductor layer, the second oxide semiconductor layer has crystals grown from the crystalline region.

Images