Semiconductor device

Abstract

To provide a technique of suppressing a switching loss while reducing an on-resistance.SOLUTION: A semiconductor device includes: a semiconductor substrate having an element region and a peripheral region; and a plurality of trenches extending in a first direction in an upper surface of the semiconductor substrate and arranged in a second direction with a space in between. The element region includes: an n-type source region; a p-type contact region; a p-type body region; an n-type drift region; a p-type bottom region; and a plurality of p-type connection regions. The bottom region is arranged in the lower part of the trenches with intervals in between from the bottom surface of the trenches. The connection region is connected to the body region and the bottom region, extend in the first direction, and are arranged in the second direction with intervals in between. The element region has an outside part located on both sides of the element region in the second direction and the center part arranged between the outside parts. The interval of the connection region in the outside part in the second direction is larger than the interval of the connection region in the center part in the second region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, multiple trenches formed on the upper surface of the semiconductor substrate, gate insulating films covering the inner surfaces of the trenches, and gate electrodes disposed in the trenches. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type contact region, a p-type body region, an n-type drift region, a p-type bottom region, and multiple p-type connection regions. The source region is exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film. The contact region is exposed on the upper surface of the semiconductor substrate. The body region is in contact with the gate insulating film below the source region and in contact with the contact region. The drift region is in contact with the gate insulating film below the body region. The bottom region is disposed below the trench and spaced apart from the bottom surface of the trench. Each connection region connects the body region and the bottom region, extends parallel to the trench, and is disposed at intervals in a direction perpendicular to the extension direction of the trench.

[0003] When the semiconductor device of Patent Document 1 is turned off, a depletion layer extends from the bottom region into the drift region. The depletion layer extending from the bottom region into the drift region suppresses electric field concentration at the bottom end of the trench.

[0004] In the semiconductor device of Patent Document 1, a pn diode (hereinafter referred to as the body diode) is formed parasitically by a p-type contact region, a body region, and an n-type drift region. When a forward bias voltage is applied to the body diode during operation of the semiconductor device, the body diode turns on, and holes flow from the contact region through the body region into the drift region. When the voltage applied to the body diode is then switched to a reverse bias, the holes accumulated in the drift region flow into the contact region through the body region as the body diode turns off. In other words, a recovery current flows.

[0005] In the semiconductor device of Patent Document 1, a bottom region connected to the body region via a connection region is provided inside the drift region. Therefore, when reverse bias is applied, holes accumulated in the drift region tend to flow from the drift region to the bottom region, and most of the holes flow into the body region via the bottom region and the connection region. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2019-46908 Summary of the Invention [Problem to be solved by the invention]

[0007] In the semiconductor device of Patent Document 1, when the semiconductor device is turned on, the depletion layer that spreads from the connection region into the drift region contracts. Until the depletion layer completely contracts, the depletion layer restricts the path through which the main current of the semiconductor device flows. In the semiconductor device of Patent Document 1, the connection regions are densely arranged, so the on-resistance is high immediately after the semiconductor device is turned on.

[0008] If the connection regions are spaced apart to reduce on-resistance, when the voltage applied to the body diode is switched to reverse bias, the current density increases in each connection region as holes accumulated in the drift region flow toward the body region. This increases the electrical resistance when the recovery current flows, causing the temperature of the semiconductor device to rise. As a result, switching losses increase.

[0009] This specification provides a technique for reducing switching loss while reducing on-resistance. [Means for solving the problem]

[0010] The semiconductor device (10, 100, 200, 300) disclosed in this specification comprises a semiconductor substrate (12) having an element region (62) and a peripheral region (64) arranged around the element region, a plurality of trenches (22) provided on an upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction on the upper surface perpendicular to the first direction, a gate insulating film (24) covering the inner surface of each of the trenches, and a gate electrode (26) arranged in each of the trenches and insulated from the semiconductor substrate by the gate insulating film. The device region includes an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches, a p-type contact region (31) exposed on the upper surface of the semiconductor substrate, a p-type body region (32) in contact with the gate insulating film in each of the trenches below the source region and in contact with the contact region, an n-type drift region (34) in contact with the gate insulating film in each of the trenches below the body region and separated from the source region by the body region, a p-type bottom region (36) disposed in a lower portion of the trench at a space from the bottom surface of the trench and surrounded by the drift region, and a plurality of p-type connection regions (38) connecting the body region and the bottom region, each extending in the first direction and arranged at intervals in the second direction. The device region has outer portions (62a) located at both ends of the device region in the second direction and a central portion (62b) disposed between the outer portions. The interval in the second direction between the connection regions in the outer portions is wider than the interval in the second direction between the connection regions in the central portion.

[0011] In this semiconductor device, the element region has outer portions located at both ends of the element region in the direction in which the trenches and connection regions are arranged, and a central portion located between the outer portions. The spacing between the connection regions in the outer portions is wider than the spacing between the connection regions in the central portion. Because the spacing between the connection regions is wider in the outer portions, the on-resistance is low. Therefore, the on-resistance of the entire element region can be reduced. The outer portion is adjacent to the peripheral region. In the peripheral region, a voltage is less likely to be applied to the body diode, so holes are less likely to accumulate in the drift region under forward bias. In other words, almost no holes flow into the outer portion from the peripheral region, so the density of holes accumulated in the drift region under forward bias is low in the outer portion. Therefore, the recovery current is small in the outer portion, and the temperature of the semiconductor device is less likely to rise even if the spacing between the connection regions in the outer portion is wider. Therefore, the switching loss of the entire element region is small. As described above, this semiconductor device can reduce switching loss while reducing on-resistance. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. [Figure 2] FIG. 2 is an enlarged plan view including the boundary between the element region and the peripheral region of the semiconductor device of the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. 10 is an enlarged plan view including the boundary between the element region and the peripheral region of the semiconductor device of the second embodiment. [Figure 6] FIG. 11 is an enlarged plan view including the boundary between the element region and the peripheral region of the semiconductor device of Example 3. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 10 is an enlarged plan view including the boundary between the element region and the peripheral region of the semiconductor device of Example 4. [Figure 10]FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11] FIG. 4 is a cross-sectional view of a semiconductor device according to a modified example, corresponding to FIG. 3. [Figure 12] 10 is a cross-sectional view corresponding to FIG. 3 of a semiconductor device according to another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0013] In the semiconductor device disclosed in the present specification as an example, the spacing in the second direction between the connection regions in the outer portion may become wider toward the end of the element region.

[0014] The amount of holes that accumulate in the drift region when the body diode is forward biased decreases toward the edge of the element region. In the above configuration, by increasing the spacing between the connection regions toward the edge of the element region, it is possible to more effectively reduce the on-resistance and the switching loss.

[0015] In the semiconductor device disclosed in this specification as an example, the bottom regions may extend in the second direction and be arranged at intervals in the first direction.

[0016] In this configuration, the direction in which the bottom region extends intersects with the direction in which the connection region extends, which allows the bottom region and the connection region to be more reliably connected than, for example, a configuration in which the bottom region and the connection region extend parallel to each other.

[0017] In one example semiconductor device disclosed in this specification, the outer portion may further have a plurality of p-type connection auxiliary regions, each connecting the body region and the bottom region and spaced apart in the first direction.

[0018] In this configuration, when a reverse bias is applied to the body diode in the outer portion, holes flow from the bottom region to the body region via the connection auxiliary region in addition to the connection region. Because the holes can branch into many paths, switching loss can be further reduced. Furthermore, because the connection auxiliary regions are spaced apart in the first direction, the depletion layer extending from the connection auxiliary region into the drift region is narrow, making it difficult for the path of the main current to be restricted when the semiconductor device is turned on. This makes it possible to suppress an increase in on-resistance.

[0019] In the semiconductor device disclosed in the present specification as an example, the interval between the trenches in the second direction in the outer portions may be narrower than the interval between the trenches in the second direction in the central portion.

[0020] In such a configuration, the channel density in the outer portion is increased, and therefore the channel resistance (ie, on-resistance) can be reduced.

[0021] Example 1 1 to 4 show a semiconductor device 10 according to a first embodiment. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 12. The semiconductor substrate 12 includes an element region 62 and a peripheral region 64. A MOSFET structure is formed in the element region 62 of the semiconductor substrate 12. The peripheral region 64 is disposed around the element region 62. Although not shown, a peripheral breakdown voltage structure such as a guard ring is formed in the peripheral region 64 of the semiconductor substrate 12. The semiconductor substrate 12 is made of silicon carbide (SiC). However, the material of the semiconductor substrate 12 is not particularly limited and may be other semiconductor materials such as silicon (Si) or gallium nitride (GaN). Hereinafter, a direction parallel to an upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the semiconductor substrate 12 and perpendicular to the direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction.

[0022] As shown in FIG. 1, a plurality of trenches 22 are provided in the upper surface 12a of the semiconductor substrate 12 within the element region 62. Each trench 22 extends longitudinally along the y direction. Each trench 22 extends parallel to one another. The trenches 22 are arranged at intervals in the x direction. FIG. 2 is an enlarged view including the boundary in the x direction between the element region 62 and the peripheral region 64 of FIG. 1. Note that in FIGS. 1 and 2, the configurations (insulating films, electrodes, etc.) on the upper surface 12a of the semiconductor substrate 12 are not shown. As shown in FIGS. 2 to 4, a gate insulating film 24 and a gate electrode 26 are arranged within each trench 22. The gate insulating film 24 covers the inner surface of each trench 22. The gate electrode 26 is arranged inside each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

[0023] As shown in FIGS. 3 and 4 , the upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. In the peripheral region 64, substantially the entire upper surface 12a of the semiconductor substrate 12 is covered with an insulating film 65. An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 contacts the upper surface 12a of the semiconductor substrate 12 in a portion of the element region 62 where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 contacts substantially the entire lower surface 12b of the semiconductor substrate 12.

[0024] The element region 62 includes a plurality of source regions 30, a plurality of contact regions 31, a body region 32, a drift region , a drain region 35, a plurality of bottom regions , and a plurality of connection regions .

[0025] Each source region 30 is an n-type region. Each source region 30 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 in the trench 22 on the side surface of the trench 22.

[0026] Each contact region 31 is a p-type region. Each contact region 31 is provided at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each contact region 31 is disposed at a position sandwiched between two source regions 30. Each contact region 31 is in ohmic contact with the upper electrode 70.

[0027] The body region 32 is a p-type region. The body region 32 has a lower p-type impurity concentration than the contact region 31. The body region 32 contacts the source region 30 and the contact region 31 from below. The body region 32 contacts the gate insulating film 24 in each trench 22 below the source region 30. The body region 32 is arranged across from the element region 62 into the peripheral region 64.

[0028] The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32. The drift region 34 contacts the body region 32 from below. The drift region 34 contacts the gate insulating film 24 in each trench 22 below the body region 32. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is disposed across from the element region 62 into the peripheral region 64.

[0029] The drain region 35 is an n-type region. The drain region 35 is disposed below the drift region 34. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 contacts the drift region 34 from below. The drain region 35 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72 at the lower surface 12b of the semiconductor substrate 12. The drain region 35 is disposed across from the element region 62 into the peripheral region 64.

[0030] Each bottom region 36 is a p-type region. Each bottom region 36 extends in a direction (x direction) perpendicular to the trench 22. As shown in FIG. 2, each bottom region 36 is arranged at intervals in the y direction. Each bottom region 36 is disposed below the trench 22 at an interval from the lower surface of the trench 22. Each bottom region 36 is surrounded by the drift region 34. Each bottom region 36 extends from the element region 62 into the peripheral region 64.

[0031] Each connection region 38 is a p-type region. As shown in FIG. 2, each connection region 38 extends parallel to each trench 22 (i.e., in the y direction). The connection regions 38 are arranged at intervals in a direction perpendicular to each trench 22. When viewed from above, each connection region 38 is disposed in a range between two trenches 22. As shown in FIG. 3, each connection region 38 connects the body region 32 and the bottom region 36. The connection region 38 is also disposed in the peripheral region 64.

[0032] As described above, each bottom region 36 is connected to the body region 32 via each connection region 38. Therefore, each bottom region 36 is connected to the upper electrode 70 via the connection region 38, the body region 32, and the contact region 31. Therefore, the potential of each bottom region 36 is approximately equal to the potential of the upper electrode 70.

[0033] As shown in Fig. 1, the element region 62 has two outer portions 62a and a central portion 62b. The outer portions 62a are located at both ends of the element region 62 in the x direction. Although Figs. 2 to 4 only show one end of the element region 62 in the x direction, an outer portion 62a is also located at the other end of the element region 62 in the x direction. The central portion 62b is located between the two outer portions 62a.

[0034] As shown in FIG. 3, in the central portion 62b, a connection region 38 is provided in each of the ranges between the multiple trenches 22. That is, in the central portion 62b, the connection regions 38 and the trenches 22 are alternately arranged along the x direction. On the other hand, in the outer portion 62a, the connection regions 38 are not provided in the range between two trenches 22. In the peripheral region 64, the connection regions 38 are provided at the same intervals as in the central portion 62b. Therefore, the interval d1 between the connection regions 38 in the outer portion 62a is wider than the interval d2 between the connection regions 38 in the central portion 62b. Although not shown, the intervals between the connection regions 38 are similarly wider in the other outer portion 62a. The intervals between two adjacent trenches 22 are approximately equal in the outer portion 62a and the central portion 62b.

[0035] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a voltage equal to or greater than the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area in contact with the gate insulating film 24, and the semiconductor device 10 is turned on. When the voltage applied to the gate electrode 26 is reduced to a level below the gate threshold, the channel disappears and the semiconductor device 10 is turned off.

[0036] When the semiconductor device 10 is off, the potential of the bottom electrode 72 is much higher than the potential of the top electrode 70. In this state, the drift region 34 has a potential close to that of the bottom electrode 72. As described above, the bottom region 36 has a potential substantially equal to that of the top electrode 70. Therefore, a high reverse voltage is applied to the p-n junction at the interface between the drift region 34 and the bottom region 36. As a result, a depletion layer spreads over a wide area from each bottom region 36 into the drift region 34. This suppresses electric field concentration near the bottom end of the trench 22, ensuring the breakdown voltage of the semiconductor device 10. In addition, a reverse voltage is also applied to the p-n junction at the interface between the connection region 38 and the drift region 34. As a result, a depletion layer spreads from the connection region 38 into the drift region 34.

[0037] When the semiconductor device 10 is turned on, holes are supplied from the upper electrode 70 to each bottom region 36 via the contact region 31, the body region 32, and the connection region 38. This causes the depletion layer that had spread from the connection region 38 and the bottom region 36 into the drift region 34 to contract. Until the holes are supplied to the connection region 38 and the bottom region 36, the depletion layer spreads from the connection region 38 and the bottom region 36 into the drift region 34. Therefore, immediately after the semiconductor device 10 is turned on, the depletion layer restricts the path of the main current. However, in this embodiment, the spacing d1 between the connection regions 38 is wide in the outer portion 62a of the element region 62. Therefore, a relatively wide area of ​​the drift region 34 is not depleted in the outer portion 62a. Therefore, even immediately after the semiconductor device 10 is turned on, a wide area of ​​the drift region 34 (particularly, the drift region 34 located between the trenches 22) can be used as the path of the main current. Therefore, in the semiconductor device 10 of this embodiment, the on-resistance of the entire element region 62 can be reduced.

[0038] Here, a pn diode (hereinafter referred to as the body diode) is parasitically formed inside the semiconductor substrate 12 by the p-type contact region 31 and body region 32 and the n-type drift region 34 and drain region 35. During operation of the semiconductor device 10, a higher potential may be applied to the upper electrode 70 than to the lower electrode 72. When the upper electrode 70 has a higher potential (forward bias) than the lower electrode 72, the body diode turns on. That is, holes flow from the upper electrode 70 into the drift region 34 via the contact region 31 and the body region 32.

[0039] Thereafter, when the bottom electrode 72 is switched to a higher potential (reverse bias) than the top electrode 70, holes accumulated in the drift region 34 flow to the top electrode 70 via the body region 32 and contact region 31 while the body diode is turned off. That is, a recovery current flows. In the semiconductor device 10, a plurality of bottom regions 36 connected to the body region 32 via the connection regions 38 are provided inside the drift region 34. Therefore, during reverse bias, holes accumulated in the drift region 34 tend to flow from the drift region 34 into the bottom regions 36, and most of the holes flow into the body region 32 via the bottom regions 36 and the connection regions 38.

[0040] In this embodiment, the spacing d2 between the connection regions 38 in the central portion 62b of the element region 62 is narrow. That is, the connection regions 38 are densely arranged in the central portion 62b. Therefore, there are many paths for holes to flow from the bottom region 36 to the body region 32, and the holes are quickly discharged to the upper electrode 70. Therefore, switching loss occurring in the central portion 62b is small, and temperature rise in the central portion 62b is suppressed. On the other hand, the spacing d1 between the connection regions 38 in the outer portion 62a of the element region 62 is wide. Therefore, there are few paths for holes to flow from the bottom region 36 to the body region 32. However, the outer portion 62a is adjacent to the peripheral region 64. Because the peripheral region 64 does not have a contact region 31, holes are less likely to accumulate in the drift region 34 of the peripheral region 64 under forward bias. Therefore, the density of holes accumulated in the drift region 34 under forward bias is lower in the outer portion 62a than in the central portion 62b. Therefore, the recovery current in the outer portion 62a is small, and even if the interval d1 between the connection regions 38 in the outer portion 62a is wide, the density of the recovery current flowing through each connection region 38 is not so high. As a result, switching loss occurring in the outer portion 62a is small, and a temperature rise in the outer portion 62a is suppressed. In this way, in this embodiment, a temperature rise in the entire element region 62 when a recovery current flows is suppressed, and switching loss is suppressed.

[0041] As described above, when the semiconductor device 10 is turned off, a depletion layer spreads from the body region 32, the connection region 38, and the bottom region 36 to the drift region 34. This depletes the drift region 34 across the entire surface. When a high voltage is applied to the bottom electrode 72 while the semiconductor device 10 is turned off, an avalanche current flows from the drift region 34 to the top electrode 70 via the bottom region 36, the connection region 38, the body region 32, and the contact region 31. In the central portion 62b, the spacing between the connection regions 38 is narrow, so the density of the avalanche current flowing through each connection region 38 is low. This suppresses a temperature rise in the central portion 62b. In the outer portion 62a, the spacing between the connection regions 38 is wide, so the density of the avalanche current flowing through each connection region 38 is high. However, because the outer portion 62a is adjacent to the outer peripheral portion 64, the outer peripheral portion 62a has high heat dissipation properties. Therefore, a temperature rise in the outer portion 62a is suppressed. In this way, when an avalanche current flows, the temperature rise in each of the central portion 62b and the outer portion 62a is suppressed. In this way, in this embodiment, when an avalanche current flows, the temperature rise in the entire element region 62 is suppressed. Therefore, the semiconductor device 10 has a high avalanche resistance.

[0042] Furthermore, when the semiconductor device 10 is in operation, the semiconductor substrate 12 generates heat, but the heat dissipates more easily from the outer portion 62a of the element region 62 than from the central portion 62b. The outer portion 62a is adjacent to the peripheral region 64, through which no main current flows. Therefore, the temperature of the outer portion 62a is less likely to rise than that of the central portion 62b, and the temperature of the outer portion 62a is lower than that of the central portion 62b. Therefore, even if the temperature rises in the outer portion 62a, the impact is small. As described above, the semiconductor device 10 can reduce the on-resistance while suppressing an increase in switching loss and a decrease in avalanche resistance.

[0043] Furthermore, in this embodiment, the direction in which the bottom region 36 extends (x direction) and the direction in which the connection region 38 extends (y direction) intersect, so that the bottom region 36 and the connection region 38 can be more reliably connected compared to, for example, a configuration in which the bottom region 36 and the connection region 38 extend parallel to each other.

[0044] Example 2 The semiconductor device 100 of Example 2 differs from Example 1 in the configuration of the connection regions 38. In Example 2, the spacing between the connection regions 38 in the outer portion 62a increases toward the end of the element region 62. As shown in FIG. 5, in this example, nine trenches 22 are arranged in the outer portion 62a. Four connection regions 38 are arranged in the outer portion 62a. In Example 2, the width of the outer portion 62a in the x-direction is wider than that of Example 1. For convenience, the following description will refer to the connection regions 38 as 38a, 38b, 38c, and 38d in order from the outermost connection region 38 (i.e., closest to the peripheral region 64) toward the central portion 62b. As shown in FIG. 5, the spacing d3 between the connection regions 38a and 38b is wider than the spacing d4 between the connection regions 38b and 38c. The spacing d4 is wider than the spacing d5 between the connection regions 38c and 38d. Furthermore, the intervals d3, d4, and d5 are greater than the interval d6 of the connection region 38 in the central portion 62b.

[0045] Four trenches 22 are arranged between connection region 38a and connection region 38b, three trenches 22 are arranged between connection region 38b and connection region 38c, and two trenches 22 are arranged between connection region 38c and connection region 38d. The intervals between two adjacent trenches 22 are approximately equal in outer portion 62a and central portion 62b.

[0046] When a forward bias voltage is applied to the body diode, the amount of holes accumulated in the drift region 34 decreases toward the end of the element region 62. In the semiconductor device 100 of Example 2, the spacing between the connection regions 38 in the outer portion 62a gradually increases from the central portion 62b toward the peripheral region 64. In Example 2, the connection regions 38 are arranged more sparsely than in Example 1, which makes it possible to further reduce the on-resistance. Furthermore, the spacings d3 to d5 between the connection regions 38 are adjusted in accordance with the distribution of the amount of holes accumulated in the drift region 34, which makes it possible to efficiently reduce switching loss.

[0047] Example 3 The semiconductor device 200 of Example 3 differs from Example 1 in that a plurality of p-type connection auxiliary regions 39 are further provided in the outer portion 62a. As shown in FIGS. 6 and 7, each connection auxiliary region 39 is arranged in the outer portion 62a in a range between two trenches 22. As shown in FIG. 6, the connection auxiliary regions 39 are arranged at intervals in the y direction. As shown in FIG. 7, each connection auxiliary region 39 connects the body region 32 and the bottom region 36. As shown in FIG. 8, the connection auxiliary region 39 is not arranged in a cross section where the bottom region 36 is not provided.

[0048] In the third embodiment, when a reverse bias voltage is applied to the body diode in the outer portion 62a, holes flow from the bottom region 36 to the body region 32 via the connection auxiliary region 39 in addition to the connection region 38. In the third embodiment, holes can branch into more paths than in the first embodiment, thereby further reducing switching loss. Furthermore, the connection auxiliary regions 39 are spaced apart in the y direction. Specifically, as shown in FIGS. 8 and 9 , the connection auxiliary regions 39 are arranged only in the area directly above the bottom region 36. Therefore, when the semiconductor device 200 is off, the depletion layer extending from the connection auxiliary region 39 to the drift region 34 does not extend over a wide area within the drift region 34. Therefore, even if the connection auxiliary region 39 is present, the path of the main current is unlikely to be restricted when the semiconductor device 200 is on. Furthermore, the connection auxiliary region 39 is arranged only in the area directly above the bottom region 36, which does not function as a path of the main current when the semiconductor device 200 is on. Therefore, the on-resistance hardly increases even with the presence of the connection auxiliary region 39. As described above, in the semiconductor device 200 of the third embodiment, it is possible to further reduce the switching loss while suppressing an increase in the on-resistance.

[0049] Example 4 In the semiconductor device 300 of Example 4, the intervals between the trenches 22 in the outer portion 62a are different from those in Example 1. As shown in Fig. 9, in Example 4, three trenches 22 are arranged in the range between two connection regions 38 in the outer portion 62a. The interval D1 between the trenches 22 in the outer portion 62a is narrower than the interval D2 between the trenches 22 in the central portion 62b. As shown in Fig. 10, the source region 30, the contact region 31, the body region 32, and the drift region 34 are respectively provided in the semiconductor region between two adjacent trenches 22 in the outer portion 62a.

[0050] In Example 4, the interval D1 between the trenches 22 in the outer portion 62a is narrow (i.e., the trenches 22 are densely arranged), so the channel density in the outer portion 62a is higher than in Example 1. Therefore, in Example 4, the channel resistance (i.e., the on-resistance) can be further reduced. Note that, in this example as well, the interval between the connection regions 38 in the outer portion 62a is wider than the interval between the connection regions 38 in the central portion 62b, so the path of the main current is less likely to be restricted in the outer portion 62a. Therefore, even if the interval D1 between the trenches 22 in the outer portion 62a is narrowed, the on-resistance caused by the presence of the connection regions 38 hardly increases.

[0051] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples exemplified above. Modifications of the above-described embodiments will be described below.

[0052] (Variation) In the above-described embodiments, the connection region 38 is disposed in a range between the trenches 22. That is, the connection region 38 is disposed at a distance from the trench 22. However, for example, as shown in FIG. 11 , the connection region 38 may be disposed at a position where it contacts the side surface of the trench 22. The connection region 38 may be disposed at a position where it contacts the gate insulating film 24 in the trench 22 below the body region 32. The connection region 38 may extend in the y direction along the side surface of the trench 22. Furthermore, in this modification, the contact region 31 may be disposed at a position where it contacts the side surface of the trench 22. The contact region 31 may be disposed at a position where it contacts the gate insulating film 24 in the trench 22 on the side surface of the trench 22.

[0053] In the above-described embodiment, the bottom region 36 extends in a direction perpendicular to the trench 22. However, as shown in Fig. 12, the bottom region 36 may extend parallel to the trench 22 (y direction). The bottom region 36 may extend along the bottom surface of the trench 22 at a distance from the bottom surface of the trench. The bottom region 36 may also be arranged at intervals in a direction perpendicular to the trench 22 (x direction).

[0054] The technical elements described in this specification or drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings simultaneously achieve multiple objectives, and achieving one of those objectives is itself technically useful. [Explanation of symbols]

[0055] 10, 100, 200, 300: Semiconductor device 12: Semiconductor substrate 12a:Top surface 12b: Bottom surface 22: Trench 24: Gate insulating film 26: Gate electrode 30: Source area 31: Contact area 32: Body area 34: Drift region 35: Drain region 36: Bottom area 38: Connection area 39: Connection auxiliary area 62: Element area 62a:Outer part 62b: Central part 64: Surrounding area

Claims

1. a semiconductor substrate (12) having an element region (62) and a peripheral region (64) arranged around the element region; a plurality of trenches (22) provided on an upper surface (12a) of the semiconductor substrate, each extending in a first direction on the upper surface and arranged at intervals in a second direction on the upper surface perpendicular to the first direction; a gate insulating film (24) covering the inner surface of each trench; a gate electrode (26) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; It is equipped with The element region is an n-type source region (30) exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film in each of the trenches; a p-type contact region (31) exposed on the upper surface of the semiconductor substrate; a p-type body region (32) in contact with the gate insulating film in each of the trenches below the source region and in contact with the contact region; an n-type drift region (34) in contact with the gate insulating film in each trench below the body region and separated from the source region by the body region; a p-type bottom region (36) disposed at a lower portion of the trench and spaced apart from a bottom surface of the trench, the p-type bottom region being surrounded by the drift region; a plurality of p-type connection regions (38) each connecting the body region and the bottom region, each extending in the first direction and arranged at intervals in the second direction; It is equipped with the element region has outer portions (62a) located at both ends of the element region in the second direction and a central portion (62b) disposed between the outer portions, the interval in the second direction of the connection regions in the outer portions is wider than the interval in the second direction of the connection regions in the central portion; Semiconductor device (10, 100, 200, 300).

2. 2. The semiconductor device according to claim 1, wherein the intervals in the second direction between the connection regions in the outer portion become wider toward the end of the element region.

3. The semiconductor device according to claim 1 , wherein the bottom regions extend in the second direction and are arranged at intervals in the first direction.

4. 4. The semiconductor device of claim 3, wherein the outer portion further includes a plurality of p-type connection assist regions (39) each connecting the body region and the bottom region and spaced apart in the first direction.

5. 5. The semiconductor device according to claim 1, wherein the interval between the trenches in the second direction in the outer portions is narrower than the interval between the trenches in the second direction in the central portion.

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