Manufacturing method for infrared device

Abstract

To provide an infrared device with improved a photoelectric conversion efficiency and a manufacturing method of the infrared device.SOLUTION: An infrared device includes a first mesa part including a first semiconductor layer of a first conductivity type provided on one surface side of a substrate, a second semiconductor layer to be an active layer stacked on the first semiconductor layer, and a third semiconductor layer of a second conductivity type stacked on the second semiconductor layer, and a side surface of the first mesa part includes a first side surface located on a side close to a lower surface of the first mesa part, a second side surface located on an upper side of the first side surface, and a third side surface located on an upper side of the second side surface. A first angle θ1 formed by the first side surface and the one surface of the substrate is 0.6° or more and less than 45°, a second angle θ2 formed by the second side surface and the one surface of the substrate is 45° or more and less than 90°, a third angle θ3 formed by the third side surface and the one surface of the substrate is 0.6° or more and less than 45°, W3 / W2 is 0.15 or more, and W1 / W2 is 0.2 or more and 3.0 or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD The present disclosure relates to infrared devices and methods for manufacturing infrared devices. [Background technology]

[0002] Known infrared devices include infrared receiving elements that output signals corresponding to received infrared rays and infrared emitting elements that emit infrared rays according to input power. A quantum infrared receiving element detects infrared rays by a photocurrent generated when a semiconductor having a pn junction or a pin junction absorbs the infrared rays. An infrared receiving element is also called an infrared sensor. Quantum infrared receiving elements are also used in human sensors that detect infrared rays emitted from the human body and non-contact temperature sensors. An infrared emitting element emits infrared rays when a voltage is applied in the forward direction. An infrared emitting element is also called an infrared emitting diode or an infrared LED (light emitting diode). These elements can be used, for example, in NDIR (non-dispersive infrared) gas sensors (see, for example, Patent Document 1). An NDIR gas sensor can measure gas concentrations using an infrared receiving element that receives infrared rays in an absorption wavelength band corresponding to the target gas and an infrared emitting element that emits infrared rays in the absorption wavelength band. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-271518 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, infrared devices have become increasingly popular, with a wide range of applications. In particular, in the field of sensing technology, there is a demand for even higher accuracy in sensors, necessitating improved performance in infrared light-receiving elements and infrared light-emitting elements. Quantum-type infrared light-receiving elements and infrared light-emitting elements include those with a pin diode structure made of compound semiconductors using materials such as Al, P, Ga, As, In, and Sb. In these cases, photoelectric conversion occurs in the i-layer, or active layer, and increasing the volume of the active layer is an effective way to improve photoelectric conversion efficiency.

[0005] On the other hand, if the thickness of the i-layer is increased in order to increase the volume of the active layer, processing problems arise, such as a deterioration in the coverage of the insulating layer and electrode portion.

[0006] Furthermore, when a compound semiconductor layer is provided on a substrate and a diode shape is formed by wet etching, corrosion holes called etch pits are generated on the surface, originating from lattice defects introduced between the substrate and the semiconductor layer. Furthermore, when wet etching is used, etching proceeds isotropically, so a gentle tapered shape is formed on the etched side, reducing the volume of the active layer.

[0007] In view of the above, an object of the present disclosure is to provide an infrared device with improved photoelectric conversion efficiency and a method for manufacturing the infrared receiving element thereof. [Means for solving the problem]

[0008] An infrared device according to one embodiment comprises: a first mesa portion including a first semiconductor layer of a first conductivity type provided on one surface of a substrate, a second semiconductor layer that serves as an active layer and is stacked on the first semiconductor layer, and a third semiconductor layer of a second conductivity type that is stacked on the second semiconductor layer; the side surfaces of the first mesa portion include a first side surface located closer to a lower surface of the first mesa portion, a second side surface located higher than the first side surface, and a third side surface located higher than the second side surface; a first angle formed between the first side surface and one surface of the substrate is 0.6° or more and less than 45°, a second angle formed between the second side surface and one surface of the substrate is 45° or more and 90° or less, and a third angle formed between the third side surface and one surface of the substrate is 0.6° or more and less than 45°, When the length of the first side surface parallel to the surface of the substrate is W1, the length of the second side surface parallel to the surface of the substrate is W2, and the length of the third side surface parallel to the surface of the substrate is W3, W3 / W2 is 0.15 or more, and W1 / W2 is 0.2 or more and 3.0 or less.

[0009] A method for manufacturing an infrared device according to one embodiment includes the steps of: forming a first semiconductor layer of a first conductivity type on one surface of a substrate; forming a second semiconductor layer on the first semiconductor layer to be an active layer; forming a third semiconductor layer of a second conductivity type on the second semiconductor layer; a first etching step of performing a dry etching process with an inter-electrode voltage of 330 V or more to form a first mesa portion including an upper portion of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; and a second etching step of performing dry etching at an inter-electrode voltage of less than 330V. [Effects of the Invention]

[0010] According to the infrared device of the embodiment of the present disclosure, it is possible to provide an infrared device with improved photoelectric conversion efficiency and a method for manufacturing the infrared receiving element thereof. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing an example of the configuration of an infrared device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically illustrating an example of the configuration of a first mesa portion and a second mesa portion of an infrared device according to an embodiment. [Figure 3A]FIG. 3A is a cross-sectional view showing a method for manufacturing an infrared device. [Figure 3B] FIG. 3B is a cross-sectional view showing a method for manufacturing an infrared device. [Figure 3C] FIG. 3C is a cross-sectional view showing a method for manufacturing an infrared device. [Figure 3D] FIG. 3D is a cross-sectional view showing a method for manufacturing an infrared device. [Figure 4] FIG. 4 is a diagram illustrating a cross section of an infrared device produced by the method of Comparative Example 1. As shown in FIG. [Figure 5] FIG. 5 is a diagram showing differential values ​​of the shape of the first mesa portion of the infrared device of FIG. [Figure 6] FIG. 6 is a diagram illustrating a cross section of an infrared device produced by the method of Example 1. [Figure 7] FIG. 7 is a diagram showing differential values ​​of the shape of the first mesa portion of the infrared device of FIG. [Figure 8] FIG. 8 is a plot of W3 / W2 against V2. [Figure 9A] FIG. 9A is a diagram comparing the shapes of the first mesa portion under each condition of V2. [Figure 9B] FIG. 9B is a diagram comparing the shapes of the first mesa portion under each condition of V2. DETAILED DESCRIPTION OF THE INVENTION

[0012] An infrared light receiving element 100 according to an embodiment of the present disclosure will be described below with reference to the drawings. An infrared light emitting element 200 may be configured with the same structure as the infrared light receiving element 100 described below. That is, the structure of the infrared light receiving element 100 described in this embodiment can be directly used as the structure of the infrared light emitting element 200. In other words, in this embodiment, the structures of these infrared devices will be described using the infrared light receiving element 100 as a representative. Furthermore, the infrared light emitting element 200 can be manufactured using the same method as the manufacturing method of the infrared light receiving element 100 described below. That is, the manufacturing method of the infrared light receiving element 100 described below can be directly used as the manufacturing method of the infrared light emitting element 200, and a manufacturing method of the infrared device will also be described.

[0013] In the drawings described below, corresponding parts are assigned the same reference numerals, and explanations of overlapping parts will be omitted as appropriate. Furthermore, this embodiment exemplifies a configuration for embodying the technical idea of ​​the present disclosure, and the material, shape, structure, arrangement, dimensions, etc. of each part are not specified as described below. Various modifications can be made to the technical idea of ​​the present disclosure within the technical scope defined by the claims.

[0014] <Infrared receiving element> (1) Composition 1 is a cross-sectional view showing an example of the configuration of an infrared receiving element 100 according to an embodiment of the present disclosure (hereinafter, this embodiment). As shown in FIG. 1, the infrared receiving element 100 includes a first mesa 10 provided on one surface (hereinafter, front surface) 1a of a substrate 1, a second mesa 20 provided below the first mesa 10 on the front surface 1a of the substrate 1, an insulating film 30 continuously covering the first mesa 10 and the second mesa 20, a first electrode 41 bonded to an upper surface of the second mesa 20 through a first contact hole 35 provided in the insulating film 30, a second electrode 42 bonded to the upper surface of the first mesa 10 through a second contact hole 36 provided in the insulating film 30, and a wiring portion 43 formed integrally with the first electrode 41 and the second electrode 42. 1 shows a state in which a passivation film 50 covering the infrared receiving element 100 is provided on the surface 1a side of the substrate 1. The passivation film 50 is an insulating protective film. Here, the boundary surface between the first mesa portion 10 and the second mesa portion 20 is sometimes referred to as the underside of the first mesa portion 10. In FIG. 1, the underside of the first mesa portion 10 is indicated by a dashed line.

[0015] FIG. 2 is a cross-sectional view schematically illustrating an example of the configuration of the first mesa portion 10 and the second mesa portion 20 of the infrared receiving element 100. The first mesa portion 10 includes an upper portion 111 of a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 12 stacked on the first semiconductor layer 11, and a third semiconductor layer 13 of a second conductivity type stacked on the second semiconductor layer 12. The second semiconductor layer 12 is an active layer in which photoelectric conversion occurs. The first semiconductor layer 11 and the third semiconductor layer 13 are a combination of a p-type semiconductor layer and an n-type semiconductor layer. The order in which the p-type semiconductor layer and the n-type semiconductor layer are stacked does not matter. Here, the phrase "stacked on the first semiconductor layer 11" regarding the second semiconductor layer 12 means that the second semiconductor layer 12 is formed on the first semiconductor layer 11, but this expression also includes the case in which another layer exists between the first semiconductor layer 11 and the second semiconductor layer 12. The term "above" has the same meaning when used to describe the relationship between other layers. For example, another semiconductor layer 132 may be included between the third semiconductor layer 13 and the second semiconductor layer 12. The second mesa portion 20 includes the lower portion 112 of the first semiconductor layer 11.

[0016] The materials of the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 are not limited. The first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 may contain materials such as Al, P, Ga, As, In, and Sb. The ratio of each element can also be adjusted appropriately. As an example, the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 may be an In compound, which is a compound containing at least In.

[0017] The first mesa portion 10 of this infrared receiving element 100 includes, in order from the substrate 1 side toward the top, a first flat portion 101a, a first side surface 101b, a second side surface 102b, a third side surface 103b, and a second flat portion 102a.

[0018] The angle formed between the first flat portion 101a and the surface 1a of the substrate 1 is equal to or greater than 0° and less than 0.6°. An extension line of the first flat portion 101a is the boundary between the upper portion 111 and the lower portion 112 of the first semiconductor layer 11.

[0019] From the viewpoint of coverage of the insulating film 30 and the first electrode portion 41, it is preferable that the first flat portion 101a does not have corrosion pits with a diameter of 1 μm or more.

[0020] If the angle formed between the first side surface 101b and the surface 1a of the substrate 1 is defined as a first angle θ1, the first angle θ1 is equal to or greater than 0.6° and less than 45°. The first side surface 101b is formed by only a part of the side surface of the upper portion 111 of the first semiconductor layer 11. The first side surface 101b is located closer to the lower surface of the first mesa portion 10.

[0021] If the angle formed between the second side surface 102b and the surface 1a of the substrate 1 is defined as a second angle θ2, the second angle θ2 is 45° or more and 90° or less. The second side surface 102b is composed of another part of the side surface of the upper portion 111 of the first semiconductor layer 11, the entire side surface of the second semiconductor layer 12, and part of the side surface of the third semiconductor layer 13. In other words, the second semiconductor layer 12, which is the active layer, is entirely surrounded by the second side surface 102b.

[0022] If the angle formed between the third side surface 103b and the surface 1a of the substrate 1 is a third angle θ3, the third angle θ3 is equal to or greater than 0.6° and less than 45°. The third side surface 103b is formed only by another portion of the side surface of the third semiconductor layer 13.

[0023] The angle formed between the second flat portion 102a and the surface 1a of the substrate 1 is equal to or greater than 0° and less than 0.6°. The second flat portion 102a is the top of the first mesa portion 10.

[0024] Thus, the first mesa portion 10 has at least two flat portions and a three-step tapered shape.

[0025] The length of the second side surface 102b parallel to the surface 1a of the substrate 1 is defined as W2, and the length of the third side surface 103b parallel to the surface 1a of the substrate 1 is defined as W3. Here, to increase the volume of the second semiconductor layer 12 (active layer) and improve the light-receiving efficiency, θ2 should be increased and W2 should be reduced. Furthermore, in the manufacturing process of the infrared receiving element 100, to improve the coverage of the insulating film 30 and wiring portion 43 on the upper part of the first mesa portion 10, θ3 should be reduced and W3 should be increased. Therefore, increasing W3 / W2 can simultaneously improve the light-receiving efficiency and the coverage of the insulating film 30 and wiring portion 43. The W3 / W2 ratio of the infrared receiving element 100 according to this embodiment is 0.15 or greater. While the upper limit is not particularly limited, it may be 1.0 or less, or 0.65 or less, from the viewpoint of the manufacturing process.

[0026] The length of the first side surface 101b parallel to the surface 1a of the substrate 1 is defined as W1. If W1 is large, the distance between the first contact hole 35 formed on the first flat portion 101a and the second semiconductor layer 12 (active layer) increases, reducing the volume ratio of the active layer in the infrared receiving element 100 and resulting in a decrease in light-receiving efficiency. By reducing W1 / W2, the volume ratio of the active layer in the infrared receiving element 100 can be increased, improving light-receiving efficiency. On the other hand, if W1 / W2 is too small, the coverage of the insulating film 30 deteriorates. Therefore, W1 / W2 is preferably 0.1 or greater. The W1 / W2 ratio of the infrared receiving element 100 according to this embodiment is 0.2 or greater and 3.0 or less. The above description of light-receiving efficiency also applies to the light-emitting efficiency of an infrared light-emitting element 200, which has the same structure as the infrared receiving element 100.

[0027] Increasing θ2 and decreasing W2 improves the light receiving efficiency, but a large θ2 reduces the coverage of the insulating film 30 and wiring portion 43 on the second side surface 102b, so θ2 is preferably between 45° and 75°. θ2 of the infrared receiving element 100 according to this embodiment may be between 45° and 75°.

[0028] There is no particular limitation on the shape of the second mesa 20 provided below the first mesa 10. The area from the second mesa 20 to the substrate 1 may have any shape.

[0029] (2) Manufacturing method Next, a method for manufacturing the infrared receiving element 100 shown in FIG. 2 will be described.

[0030] 3A, 3B, and 3C are cross-sectional views showing the manufacturing method of the infrared receiving element 100 according to this embodiment in the order of steps.

[0031] (2.1) Semiconductor stacking process 3A, first, a first semiconductor layer 11 of a first conductivity type is formed on the surface side of a substrate 1. Next, an intrinsic second semiconductor layer 12 is formed on the first semiconductor layer 11. Then, a third semiconductor layer 13 of a second conductivity type is formed on the second semiconductor layer 12. That is, the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 are formed in this order on the substrate 1. The formation of the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13 is performed successively, for example, in a chamber of an epitaxial growth apparatus while maintaining a preset degree of vacuum.

[0032] (2.2) First Mesa Formation Process 3B, a resist pattern 31 is formed on the third semiconductor layer 13 using photolithography. Prior to the masking step of forming a mask for the resist pattern 31, a hard mask such as SiO2 may be formed on the third semiconductor layer 13 to prevent the resist pattern 31 from coming into direct contact with the third semiconductor layer 13.

[0033] Next, using the resist pattern 31 as a mask, dry etching is sequentially performed on the third semiconductor layer 13, the second semiconductor layer 12, and the upper portion 111 of the first semiconductor layer 11. In this dry etching process, a first etching step in which the inter-electrode voltage in a dry etching apparatus is set to 330 V or more and a second etching step in which the inter-electrode voltage is set to 120 V or more but less than 330 V are performed consecutively. As a result, a first mesa portion 10 is formed as shown in FIG. 3C. Hereinafter, the inter-electrode voltage in the etching apparatus in the first etching step is represented as V1, and the inter-electrode voltage in the etching apparatus in the second etching step is represented as V2.

[0034] In the process of forming the first mesa portion 10, a halogen gas or a gas containing a halogen (hereinafter referred to as a halogen-based gas) or a mixture thereof is used as an etching gas for etching the third semiconductor layer 13, the second semiconductor layer 12, and the upper portion 111 of the first semiconductor layer 11. Examples of halogen gas include chlorine gas (Cl2). Examples of halogen-based gas include hydrogen chloride gas (HCl) and hydrogen bromide gas (HBr).

[0035] In the manufacturing method of the infrared receiving element 100 according to this embodiment, the etching gas does not contain a gas with an oxidizing effect, such as oxygen gas, and therefore, in the etching process for forming the first mesa portion 10, the selectivity between the resist and the semiconductor layer is improved, and loss of the resist during the etching process can be prevented.

[0036] Fig. 3D shows the details of the shape of the first mesa portion 10 in Fig. 3C. If V1 is high, θ2 can be made large, that is, W2 can be made small. Also, if V2 is low, W3 can be made large.

[0037] [Comparative Example 1] FIG. 4 shows an electron microscope photograph of a cross section of an infrared receiving element 100 having a first mesa portion 10 formed thereon. In Comparative Example 1, an n-type semiconductor layer, an intrinsic semiconductor layer, and a p-type semiconductor layer of InSb were formed to a total thickness of 3.6 μm on a GaAs substrate. A photoresist "THMR-ip5700HP" manufactured by Tokyo Ohka Kogyo Co., Ltd. was then applied to a thickness of 3.5 μm and exposed to light to form a photoresist pattern. Subsequently, a first etching step was performed using chlorine gas with V1 set to 740 V. Subsequently, a second etching step was performed using chlorine gas while keeping V2 at 740 V without changing the inter-electrode voltage in the dry etching apparatus. An FEI Helios 650 was used for electron microscope observation, and observations were performed at a magnification of 20,000x with an accelerating voltage of 2.0 kV.

[0038] The solid line in Fig. 5 shows the result of extracting the surface shape of the first mesa portion 10 in Fig. 4 using the image processing software "ImageJ" (open source software, version 1.52u17). Here, the following steps [1], [2], [3], and [4] were carried out as the steps for extracting the shape. [1] Find Edges processing was performed to highlight sudden changes in brightness in the electron micrograph. [2] The image was smoothed using Gaussian Blur processing. The standard deviation of the Gaussian function can be set to any value appropriate for the electron micrograph. [3]Threshold processing and clear processing were performed on unnecessary areas other than the extracted shape, and only the extracted shape was specified as the foreground color. [4] Analyze Line Graph processing was performed, and the coordinate information of the shape to be extracted, specified as the foreground color, was obtained.

[0039] The dashed line in FIG. 5 indicates the result of differentiating the extracted shape of the surface of the first mesa portion 10 with respect to the direction parallel to the surface 1a of the substrate 1 (hereinafter referred to as the shape differential value).

[0040] Here, first side surface 101b in first mesa portion 10 is a portion where first angle θ1 is equal to or greater than 0.6° and less than 45°, and therefore is a portion between the point where the derivative of the shape first becomes equal to or greater than 0.01 (tan(0.6°)) with respect to the direction of first mesa portion 10 and the point where the derivative becomes greater than 1 (tan(45°)). Second side surface 102b in first mesa portion 10 is located above first side surface 101b and is a portion where second angle θ2 is equal to or greater than 45° and less than 90°, and therefore is a portion between the end point of first side surface 101b and the point where the derivative of the shape is less than 1. The third side surface 103b in the first mesa portion 10 is located above the second side surface 102b and is a portion where the third angle θ3 is equal to or greater than 0.6° and less than 45°, and is therefore a portion between the end point of the second side surface 102b and the point where the derivative of the shape with respect to the direction of the first mesa portion 10 is 0.01 or less. In this way, the start points and end points of the first side surface 101b, the second side surface 102b, and the third side surface 103b can be clearly determined using the derivative of the shape.

[0041] The ratio W3 / W2, which is the ratio of the length W2 of the second side surface 102b in the direction parallel to the surface 1a of the substrate 1 to the length W3 of the third side surface 103b in the direction parallel to the surface 1a of the substrate 1, obtained by the above procedure, was 0.14. In addition, W1 / W2, which is the ratio of W2 to the length W1 of the first side surface 101b in the direction parallel to the surface 1a of the substrate 1, was 0.90.

[0042] [Example 1] An infrared receiving element 100 was obtained in the same manner as in Comparative Example 1, except that V2 was set to 190V.

[0043] FIG. 6 shows an electron microscope photograph of the cross section of the infrared receiving element 100. The solid line in FIG. 7 shows the result of extracting the surface shape of the first mesa portion 10 in FIG. 6 using the image processing software ImageJ in the same manner as in Comparative Example 1. The dashed line in FIG. 7 shows the result of differentiating the extracted surface shape of the first mesa portion 10 with respect to the direction parallel to the surface 1a of the substrate 1. When W3 / W2 was calculated in the same manner as in Comparative Example 1, it was found to be 0.51. When W1 / W2 was calculated, it was found to be 1.06.

[0044] Comparative Example 2 The black triangles in Figure 8 represent the results of measuring W3' / W2' by scanning the first mesa portion 10 immediately after dry etching using an OLYMPUS laser microscope OLS4000, after fabricating an infrared receiving element 100 using the same method as in Comparative Example 1. The surface shape was extracted and W3' / W2' was calculated. The scanning of the first mesa portion 10 was performed using a 100x objective lens. The imaging mode was set to high precision mode. The W3' / W2' ratio obtained by measurement using the laser microscope when V2 was set to 740V was 1.86.

[0045] Furthermore, an infrared receiving element 100 was obtained in the same manner as in Comparative Example 2, except that V2 was set to 450 V and 330 V. In this case, when V2 was set to 450 V and 330 V, W3' / W2' measured with a laser microscope was 1.63 and 1.71.

[0046] [Example 2] An infrared receiving element 100 was obtained in the same manner as in Comparative Example 2 except that V2 was set to 190 V and 120 V, and W3' / W2' was calculated using a laser microscope in the same manner as in Comparative Example 2. In this case, when V2 was set to 190 V and 120 V, W3' / W2' was 2.29 and 2.57.

[0047] The results of Comparative Example 2 and Example 2 (black triangles and dashed line in FIG. 8 ) show that when V2 is 330 V or higher, W3′ / W2′ is independent of V2, but when V2 is 120 V or higher but less than 330 V, W3′ / W2′ increases linearly with V2 and has a negative correlation (dashed line in FIG. 8 ). Considering the results of W3 / W2 calculated from electron micrographs in Comparative Example 1 (black circles and dashed-dotted line in FIG. 8 ), W3 / W2 is 0.14 when V2 is 330 V or higher. Furthermore, considering the results of W3 / W2 calculated from electron micrographs in Example 1, W3 / W2 is at least 0.15 when V2 is less than 330 V. Furthermore, because W3 / W2 increases linearly with V2 in a negative correlation when V2 is in the range of 120 V or more and less than 330 V, it can be calculated that W3 / W2 is 0.65 when V2 is 120 V (dotted line in Figure 8). In other words, when V2 is 120 V or more and less than 330 V, W3 / W2 is 0.15 or more and 0.65 or less.

[0048] 9A and 9B show the results of comparing the shape of the first mesa portion 10 (electron microscope photographs in the figures) when V2 is set to 740 V and 190 V, respectively, as shown in Comparative Example 1, with the shape of the first mesa portion 10 (white lines in the figures) when V2 is set to 190 V and 120 V, respectively. As such, W3 / W2 can be increased by setting V2 to 120 V or more and less than 330 V.

[0049] In any of the above examples, θ2 is between 45° and 75°. For example, when V2 shown in FIG. 9B is 190V, θ2 is 54°.

[0050] In addition, in all of the above examples, the surface of the first mesa portion 10 is flat, and no corrosion holes with a diameter of 1 μm or more, known as etch pits, which are introduced when forming a mesa shape by wet etching, are observed.

[0051] <Effects of this embodiment> The infrared receiving element 100 according to this embodiment has the following advantages.

[0052] 2, the second semiconductor layer 12, which is the active layer, is included in the steeply inclined second side surface 102b, which increases the volume of the second semiconductor layer 12. This increases the efficiency of photoelectric conversion and improves the infrared light receiving efficiency.

[0053] Furthermore, since the top of the first mesa portion 10 has a gently sloping third side surface 103b, the coverage (i.e., step coverage) of the insulating film 30 and wiring portion 43 on the top of the first mesa portion 10 can be improved.

[0054] Furthermore, the ratio W3 / W2, which is the ratio of the length W3 of the third side surface 103b located at the top of the first mesa portion 10 in the direction parallel to the surface 1a of the substrate 1 to the length W2 of the second side surface 102b in the direction parallel to the surface 1a of the substrate 1, is 0.15 or more and 0.65 or less, so that the volume ratio of the active layer in the infrared receiving element 100 can be increased. This increases the efficiency of photoelectric conversion and improves the infrared receiving efficiency.

[0055] Furthermore, the ratio W1 / W2, which is the ratio of the length W1 of the first side surface 101b located at the bottom of the first mesa portion 10 in the direction parallel to the surface 1a of the substrate 1 to the length W2 of the second side surface 102b in the direction parallel to the surface 1a of the substrate 1, is 0.2 or more and 3.0 or less, so that the volume ratio of the active layer in the infrared receiving element 100 can be increased, thereby increasing the photoelectric conversion efficiency and improving the infrared receiving efficiency.

[0056] Furthermore, the infrared light emitting element 200 according to this embodiment, which has the same structure as the infrared light receiving element 100, exhibits the above-mentioned effects similar to those of the infrared light receiving element 100. However, the "light receiving efficiency" in the above-mentioned effects is replaced with "light emitting efficiency." [Explanation of symbols]

[0057] 1 board 1a surface 10 First Mesa 11 First semiconductor layer 12 Second semiconductor layer 13 Third semiconductor layer 20 Second Mesa 31 Resist Pattern 35 First contact hole 36 Second contact hole 41 first electrode part 42 Second electrode part 43 Wiring section 50 Passivation film 100 Infrared receiving element 101a First flat section 101b First Aspect 102a Second flat section 102b Second Aspect 103b The Third Aspect

Claims

1. a first mesa portion including a first semiconductor layer of a first conductivity type provided on one surface side of a substrate, a second semiconductor layer serving as an active layer stacked on the first semiconductor layer, and a third semiconductor layer of a second conductivity type stacked on the second semiconductor layer; the side surfaces of the first mesa portion include a first side surface located closer to a lower surface of the first mesa portion, a second side surface located higher than the first side surface, and a third side surface located higher than the second side surface; a first angle formed between the first side surface and one surface of the substrate is 0.6° or more and less than 45°, a second angle formed between the second side surface and one surface of the substrate is 45° or more and 90° or less, and a third angle formed between the third side surface and one surface of the substrate is 0.6° or more and less than 45°, The length of the first side surface in a direction parallel to the surface of the substrate is defined as W １ , the length of the second side surface in a direction parallel to the surface of the substrate is W ２ , the length of the third side surface in a direction parallel to the surface of the substrate is W ３ When W ３ / W ２ is 0.15 or more, and W １ / W ２ An infrared device with a value between 0.2 and 3.

0.

2. the first side surface is a part of a side surface of an upper portion of the first semiconductor layer, the second side surface is another part of the side surface of the upper portion of the first semiconductor layer, the entire side surface of the second semiconductor layer, and a part of the side surface of the third semiconductor layer; The infrared device according to claim 1 , wherein the third side surface is another part of the side surface of the third semiconductor layer.

3. The W ３ / W ２ 3. The infrared device according to claim 1, wherein the value of .lambda. is 0.15 or more and 1 or less.

4. The infrared device according to claim 1 , wherein the second angle is equal to or greater than 45° and equal to or less than 75°.

5. The infrared device according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contain Al, P, Ga, As, In, or Sb.

6. The infrared device according to claim 1 , wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are an In compound.

7. The infrared device according to claim 1 , wherein a first flat portion provided on the surface of the lower portion of the first semiconductor layer is free from corrosion pits having a diameter of 1 μm or more.

8. A method for manufacturing an infrared device according to any one of claims 1 to 7, comprising the steps of: forming a first semiconductor layer of a first conductivity type on one surface of a substrate; forming a second semiconductor layer on the first semiconductor layer to be an active layer; forming a third semiconductor layer of a second conductivity type on the second semiconductor layer; a first etching step of performing a dry etching process with an inter-electrode voltage of 330 V or more to form a first mesa portion including an upper portion of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; a second etching step of performing a dry etching process with an inter-electrode voltage of less than 330 V.

9. The method for manufacturing an infrared device according to claim 8 , wherein the second etching step performs dry etching at an inter-electrode voltage of 120 V or more and less than 330 V.

10. The method for manufacturing an infrared device according to claim 8 or 9, further comprising a masking step of forming a resist pattern mask on the third semiconductor layer between the step of forming the third semiconductor layer and the first etching step.

11. The method for manufacturing an infrared device according to claim 10 , further comprising forming a hard mask on the third semiconductor layer.

12. 12. The method for manufacturing an infrared device according to claim 8, wherein the etching gas in the first etching step and the second etching step is either a halogen gas or a halogen-based gas, or a mixed gas thereof.

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