Semiconductor device

Abstract

To provide a semiconductor device that suppresses both reduction in channel area and a bipolar degradation phenomenon.SOLUTION: A semiconductor device comprises: a drift region of a first conductivity type; a body region of a second conductivity type contacting the drift region; a source region of a first conductivity type separated from the drift region by the body region; an insulating gate facing a portion separating the drift region and the source region within the body region; and a pillar region of a first conductivity type arranged away from the insulating gate with a part of the body region interposed therebetween, one end contacting the source region and the other end contacting the drift region. A bandgap of the source region is narrower than that of the pillar region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices manufactured using silicon carbide semiconductor substrates are known to have many dislocations within the semiconductor substrate. When the pn diode built into the semiconductor device operates during reverse conduction, electrons and holes recombine at dislocations present in the semiconductor substrate. This recombination can cause dislocations to grow, degrading the characteristics of the semiconductor device (i.e., bipolar degradation).

[0003] Patent Document 1 discloses a technique for forming a heterojunction diode in a semiconductor substrate to suppress the operation of a pn diode. The heterojunction diode operates unipolarly. Therefore, when the heterojunction diode operates during reverse conduction, hole injection by the pn diode is suppressed, thereby suppressing bipolar degradation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-9745 Summary of the Invention [Problem to be solved by the invention]

[0005] The semiconductor device disclosed in Patent Document 1 has a configuration in which some of the gate electrodes, among those repeatedly provided, are replaced with the anodes of heterojunction diodes. A semiconductor device with such a configuration has a problem in that the channel area is reduced and the on-resistance is increased. This specification provides a semiconductor device that can suppress the reduction in channel area while also suppressing bipolar degradation. [Means for solving the problem]

[0006] One embodiment of the semiconductor device disclosed in this specification may include a drift region of a first conductivity type, a body region of a second conductivity type in contact with the drift region, a source region of the first conductivity type in contact with the body region and separated from the drift region by the body region, an insulated gate facing a portion of the body region separating the drift region and the source region, and a pillar region of the first conductivity type disposed apart from the insulated gate with a portion of the body region interposed therebetween, one end in contact with the source region and the other end in contact with the drift region, wherein the bandgap width of the source region is narrower than the bandgap width of the pillar region.

[0007] In the semiconductor device, the source region and pillar region form a heterojunction diode. The heterojunction diode operates during reverse conduction, suppressing the operation of the built-in pn diode, thereby suppressing bipolar degradation. Furthermore, the pillar region is positioned away from the insulated gate with a portion of the body region interposed therebetween, allowing a portion of the body region to function as a channel. Therefore, even with the pillar region provided, the semiconductor device can suppress reduction in channel area. The semiconductor device can suppress bipolar degradation while suppressing reduction in channel area. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a main part of a half cell of a semiconductor device according to a first embodiment. [Figure 2] (A) An example of the concentration distribution of n-type impurities in the source region and pillar region along the depth direction of the semiconductor substrate is shown. (B) A band gap diagram of the source region and pillar region for the concentration distribution shown in (A) above is shown. [Figure 3] 2 is a schematic cross-sectional view of a main part of a semiconductor device according to a modified example of the first embodiment. [Figure 4] 10 is a schematic cross-sectional view of a main part of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (First embodiment) 1 shows a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is a type of semiconductor device known as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor substrate 10 having a first main surface 10a and a second main surface 10b, a drain electrode 22 covering the first main surface 10a of the semiconductor substrate 10, a source electrode 24 covering the second main surface 10b of the semiconductor substrate 10, and a trench-type insulated gate 30 provided in an upper layer portion of the semiconductor substrate 10. The first main surface 10a and the second main surface 10b are a pair of surfaces extending parallel to one another on the surface of the semiconductor substrate 10, and are surfaces perpendicular to the thickness direction of the semiconductor substrate 10 (in this example, the vertical direction on the page).

[0010] The semiconductor substrate 10 is + a drain region 11 of n type; - a p-type drift region 12, a p-type body region 13, and a p + contact region 14 and n + The semiconductor substrate 10 has an n-type source region 15 and an n-type pillar region 16. The material of the semiconductor substrate 10 is silicon carbide (SiC) except for the source region 15, which is polycrystalline silicon. As will be described later, the contact region 14 may also be made of polycrystalline silicon.

[0011] Drain region 11 is provided in a lower layer portion of semiconductor substrate 10, and is arranged at a position exposed to first main surface 10a, which is the lower surface of semiconductor substrate 10. Drain region 11 contains a high concentration of n-type impurities and is in ohmic contact with drain electrode 22. As will be described later, drain region 11 is a silicon carbide substrate for epitaxially growing drift region 12.

[0012] The drift region 12 is disposed between the drain region 11 and the body region 13 and is in contact with both the drain region 11 and the body region 13. The drift region 12 is also in contact with the bottom surface and lower side surfaces of the insulated gate 30. The concentration of n-type impurities in the drift region 12 is lower than the concentration of n-type impurities in the drain region 11. The drift region 12 is not particularly limited, and may be formed, for example, by epitaxial growth from the upper surface of the drain region 11.

[0013] The body region 13 is provided in contact with the upper surface of the drift region 12, and is provided between the drift region 12 and the contact region 14, and between the drift region 12 and the source region 15. The body region 13 also contacts the side surface of the insulated gate 30. The body region 13 is not particularly limited, and may be formed, for example, by ion implantation of p-type impurities from the second main surface 10b of the semiconductor substrate 10.

[0014] The contact region 14 is in contact with the upper surface of the body region 13, is provided in an upper layer portion of the semiconductor substrate 10, and is disposed at a position exposed to the second main surface 10b, which is the upper surface of the semiconductor substrate 10. The layout of the contact region 14 when the semiconductor substrate 10 is viewed in plan is not particularly limited and may be designed appropriately depending on the desired characteristics. The contact region 14 contains a high concentration of p-type impurities and is in ohmic contact with the source electrode 24. The contact region 14 is not particularly limited, and may be formed, for example, by ion implantation of p-type impurities from the second main surface 10b of the semiconductor substrate 10.

[0015] The source region 15 is provided in contact with the upper surface of the body region 13, is provided in an upper layer of the semiconductor substrate 10, and is positioned at a position exposed on the second major surface 10b, which is the upper surface of the semiconductor substrate 10. The source region 15 is in contact with the upper side of the insulated gate 30. The layout of the source region 15 when viewed from above the semiconductor substrate 10 is not particularly limited and can be designed appropriately depending on the desired characteristics. The source region 15 contains a high concentration of n-type impurities and is in ohmic contact with the source electrode 24. The source region 15 may be formed by forming a groove in a portion of the second major surface 10b of the semiconductor substrate 10 and filling the groove with n-type polycrystalline silicon using, for example, chemical vapor deposition (CVD) technology. Alternatively, the source region 15 may be formed by depositing an n-type polycrystalline silicon layer on the body region 13 using CVD technology. In this case, the contact region 14 may be formed by ion-implanting p-type impurities into a portion of the polycrystalline silicon layer.

[0016] The pillar regions 16 are provided in the body region 13 so as to penetrate the body region 13, and are positioned away from the side of the insulated gate 30 with a portion of the body region 13 interposed therebetween. One end of the pillar region 16 contacts the lower surface of the source region 15, and the other end contacts the upper surface of the drift region 12. One end of the pillar region 16 does not contact the contact region 14. Alternatively, one end of the pillar region 16 may also contact the contact region 14. The layout of the pillar regions 16 when viewed from above the semiconductor substrate 10 is not particularly limited and can be designed appropriately depending on the desired characteristics. The concentration of n-type impurities in the pillar regions 16 is higher than the concentration of n-type impurities in the drift region 12 and lower than the concentration of n-type impurities in the source region 15. The pillar regions 16 are not particularly limited, and may be formed, for example, by ion-implanting n-type impurities from the second main surface 10b of the semiconductor substrate 10.

[0017] The pillar region 16 is disposed a distance D1 away from the side surface of the insulated gate 30. The distance D1 is measured as the distance between the side surface of the insulated gate 30 and the pillar region 16 along a direction perpendicular to the side surface of the insulated gate 30. Because the distance D1 is sufficiently secured, a portion of the body region 13 existing between the side surface of the insulated gate 30 and the pillar region 16 can function as a channel region 13a in which an inversion layer is formed when a gate-on voltage is applied to the insulated gate 30. Note that the distance D1 can function as the channel region 13a by satisfying the following formula:

number

[0018] ε s is the dielectric constant of the channel region 13a, and C ox is the capacitance per unit area of ​​the gate insulating film 32, and V g is the gate voltage, q is the elementary electron quantity, and N p is the concentration in the channel region 13a.

[0019] The insulated gate 30 is provided in a trench that extends from the second main surface 10b of the semiconductor substrate 10, through the source region 15 and the body region 13, and reaches the drift region 12. The insulated gate 30 has a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 contacts the side and bottom surfaces of the trench. The gate electrode 34 is provided inside the gate insulating film 32, and its side and bottom surfaces are covered with the gate insulating film 32. The gate electrode 34 is insulated from the source electrode 24 by an interlayer insulating film.

[0020] The semiconductor device 1 includes a pn diode with the n-type drift region 12 as the cathode and the p-type body region 13 as the anode. The semiconductor device 1 also includes a heterojunction diode with the pillar region 16, which has a relatively wide bandgap width, as the cathode and the source region 15, which has a relatively narrow bandgap width, as the anode. When the semiconductor device 1 is connected to an inductive load such as a motor or coil, a reverse conduction mode occurs in which the source electrode 24 has a higher potential than the drain electrode 22. In the reverse conduction mode, the pn diode and heterojunction diode included in the semiconductor device 1 are forward biased, and a reflux current flows through these diodes.

[0021] Here, a comparative example will be described in which no pillar regions 16 are provided and the material of the source region 15 is also silicon carbide, i.e., a comparative example in which only a pn diode is built in. In this comparative example, the pn diode operates during reverse conduction, and a large amount of electrons and holes are injected into the drift region 12. Many dislocations exist near the interface between the drain region 11 and the drift region 12, both of which are made of silicon carbide. Therefore, the electrons and holes injected into the drift region 12 recombine at dislocations that exist near the interface between the drain region 11 and the drift region 12. This recombination can cause dislocations to grow, degrading the characteristics of the semiconductor device (i.e., bipolar degradation).

[0022] On the other hand, the semiconductor device 1 of this embodiment includes a heterojunction diode composed of the source region 15 and the pillar region 16. The heterojunction diode operates unipolarly. Therefore, when the heterojunction diode operates during reverse conduction, the operation of the pn diode is suppressed, and the number of holes injected into the drift region 12 is reduced. As a result, the recombination of electrons and holes at dislocations present near the interface between the drain region 11 and the drift region 12 is suppressed, thereby suppressing bipolar degradation. Furthermore, as described above, the semiconductor device 1 includes a channel region 13a between the side surface of the insulated gate 30 and the pillar region 16. Therefore, the semiconductor device 1 includes a heterojunction diode without reducing the channel area. In this way, the semiconductor device 1 can suppress bipolar degradation without reducing the channel area.

[0023] 2(A) shows an example of the concentration distribution of n-type impurities in the pillar region 16 in the depth direction of the semiconductor substrate 10. The pillar region 16 in this example has a low-concentration pillar portion 16a and a high-concentration pillar portion 16b. The n-type impurity concentration in the low-concentration pillar portion 16a is lower than the n-type impurity concentration in the high-concentration pillar portion 16b. The low-concentration pillar portion 16a contacts the source region 15. The high-concentration pillar portion 16b is separated from the source region 15 by the low-concentration pillar portion 16a. In this way, the pillar region 16 is configured so that the n-type impurity concentration in the portion contacting the source region 15 is lower than the n-type impurity concentration in other portions.

[0024] As shown in FIG. 2B, when the concentration of n-type impurities in the pillar region 16 is adjusted to be low in the portion in contact with the source region 15, the valence band (E v ) and conduction band (E c ) potential barriers are formed in each of the conduction bands (E c) prevents electrons from flowing from the source region 15 to the pillar region 16, improving the rectification of the heterojunction diode. Note that, in order to improve the rectification, it is sufficient that the concentration of n-type impurities in the portion of the pillar region 16 that contacts the source region 15 is lower than the concentration of n-type impurities in other portions. For example, the concentration of n-type impurities in the pillar region 16 may increase continuously from the heterojunction in the depth direction.

[0025] When the heterojunction diode operates, a built-in voltage occurs at the heterojunction between the source region 15 and the pillar region 16, and a voltage drop occurs due to the resistance of the pillar region 16. If the sum of these voltages is smaller than the built-in voltage at the pn junction between the drift region 12 and the body region 13, the operation of the pn diode can be almost completely suppressed, and the number of holes injected into the drift region 12 can be reduced to almost zero. In the semiconductor device 1, the area, height, and impurity concentration of the pillar region 16 may be adjusted so that the above relationship holds. When the concentration distribution of the n-type impurity in the pillar region 16 is as shown in FIG. 2, the rectification effect can be improved and the voltage drop due to the resistance of the pillar region 16 can be suppressed. The concentration distribution shown in FIG. 2 is also useful in this respect.

[0026] FIG. 3 shows a modified example of the semiconductor device 1. The semiconductor device 1 of this modified example is characterized by further including deep p-layers 17 and 18. The first deep p-layer 17 is a p-type region provided in contact with the bottom surface of the insulated gate 30. The second deep p-layer 18 is a p-type region provided in contact with the bottom surface of the body region 13 at a position farther from the side surface of the insulated gate 30 than the pillar region 16. These deep p-layers 17 and 18 are structured to alleviate the electric field applied to the gate insulating film 32 of the insulated gate 30. Even when such deep p-layers 17 and 18 are provided, a heterojunction diode formed by the source region 15 and the pillar region 16 is built in, so the above-described effects of the heterojunction diode are exhibited.

[0027] (Second embodiment) 4 shows a semiconductor device 2 according to the second embodiment. Note that components having the same functions as those of the semiconductor device 1 according to the first embodiment are given the same reference numerals, and the description thereof will be omitted.

[0028] The semiconductor device 2 is characterized in that the insulated gate 30 is a planar type. In this example, too, a heterojunction diode composed of a source region 15 and a pillar region 16 is built in. The pillar region 16 is disposed away from the bottom surface of the insulated gate 30, and a channel region 13a exists between the bottom surface of the insulated gate 30 and the pillar region 16. In the semiconductor device 2, too, the bipolar degradation phenomenon can be suppressed without reducing the channel area. As such, the technology disclosed in this specification is applicable whether the insulated gate 30 is a trench type or a planar type.

[0029] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness either alone or in various combinations.

[0030] (Feature 1) a drift region of a first conductivity type; a body region of a second conductivity type in contact with the drift region; a source region of the first conductivity type in contact with the body region and separated from the drift region by the body region; an insulating gate facing a portion of the body region that separates the drift region and the source region; a pillar region of a first conductivity type, the pillar region being spaced apart from the insulated gate with a portion of the body region interposed therebetween, the pillar region having one end in contact with the source region and the other end in contact with the drift region; The semiconductor device, wherein the bandgap of the source region is narrower than the bandgap of the pillar region.

[0031] (Feature 2) the drift region, the body region, and the pillar region are made of silicon carbide; 2. The semiconductor device according to Feature 1, wherein the source region is polycrystalline silicon.

[0032] (Feature 3) 3. The semiconductor device according to feature 1 or 2, wherein the impurity concentration of the pillar region is higher than the impurity concentration of the drift region.

[0033] (Feature 4) 4. The semiconductor device according to any one of Features 1 to 3, wherein the pillar region has a lower impurity concentration in a portion in contact with the source region than in other portions.

[0034] (Feature 5) The pillar region is A low-concentration pillar portion, a high-concentration pillar portion having a higher impurity concentration than the low-concentration pillar portion, 5. The semiconductor device according to Feature 4, wherein the low concentration pillar portion is in contact with the source region.

[0035] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0036] 1: semiconductor device, 10: semiconductor substrate, 11: drain region, 12: drift region, 13: body region, 14: contact region, 15: source region, 16: pillar region, 22: drain electrode, 24: source electrode, 30: insulated gate, 32: gate electrode, 34: gate insulating film

Claims

1. a drift region of a first conductivity type; a body region of a second conductivity type in contact with the drift region; a source region of the first conductivity type in contact with the body region and separated from the drift region by the body region; an insulating gate facing a portion of the body region that separates the drift region and the source region; a pillar region of a first conductivity type, the pillar region being spaced apart from the insulated gate with a portion of the body region interposed therebetween, the pillar region having one end in contact with the source region and the other end in contact with the drift region; The semiconductor device, wherein the bandgap width of the source region is narrower than the bandgap width of the pillar region.

2. the drift region, the body region, and the pillar region are made of silicon carbide; 2. The semiconductor device of claim 1, wherein said source region is made of polycrystalline silicon.

3. The semiconductor device according to claim 1 , wherein the impurity concentration of said pillar region is higher than the impurity concentration of said drift region.

4. 4. The semiconductor device according to claim 1, wherein the pillar region has a lower impurity concentration in a portion in contact with the source region than in other portions.

5. The pillar region is A low-concentration pillar portion, a high-concentration pillar portion having a higher impurity concentration than the low-concentration pillar portion, The semiconductor device according to claim 4 , wherein the low concentration pillar portion is in contact with the source region.

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