Semiconductor device

Abstract

To provide a semiconductor storage device with a high-speed operation and low consumption power, and a semiconductor storage device with capacitance of a capacitor increased by increasing the storage capacity per unit area.SOLUTION: A semiconductor storage device 300 includes a memory cell including two or more sub-memory cells SCL each including a word line WL, a bit line BL, a first capacitor, a second capacitor, and a transistor. In the memory cell, the sub-memory cells are stacked and formed. In the transistor, a first gate and a second gate are provided through a semiconductor film. The first gate and the second gate are connected to the word line. One of a source and a drain of the transistor is connected to the bit line. The other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor. The first gate and the second gate in the transistor in each sub-memory cell overlap and connect with each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This relates to a semiconductor memory device. [Background technology]

[0002] Semiconductor memory devices (also called memory devices or memory cells) include volatile memory called DR AM (Dynamic Random Access Memory) and DR AM can store one bit of data using one transistor and one capacitor. It is a semiconductor memory device that can be modularized and has a small area per unit memory cell. This makes it easy to integrate and inexpensive to manufacture.

[0003] In addition, by using a transistor including an oxide semiconductor in a DRAM, the low The low off-current characteristics allow the charge stored in the capacitor in the DRAM to be retained for a long time. This allows the refresh operation cycle to be extended. This can reduce the force (see Patent Document 1).

[0004] Furthermore, in order to increase the operating speed and storage capacity of semiconductor memory devices, microfabrication technology However, as the microfabrication of semiconductor memory devices advances, The channel length of the transistor used in the memory device is short, and the gate insulating layer The various insulating layers become thinner, which increases the leakage current of transistors and reduces power consumption. The power consumption will increase.

[0005] In addition, in order to reduce the area occupied by the semiconductor memory device, the circuit layout is devised. It is possible to reduce the occupied cell area (see Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-109084 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-42050 Summary of the Invention [Problem to be solved by the invention]

[0007] The miniaturization and high integration of semiconductor memory devices has increased the speed and storage capacity of memory devices. However, for example, DRAM is made up of transistors and capacitors. With miniaturization and high integration, the area of ​​the capacitor has also been reduced, and its capacitance value has become smaller. Therefore, the difference in the amount of charge between the written state and the erased state in the memory device As the memory size becomes smaller, it becomes difficult to accurately retain stored information.

[0008] Furthermore, transistors using oxide semiconductors are suitable for use in DRAM due to their low off-state current. The charge stored in the capacitor can be maintained for a long time, reducing power consumption. On the other hand, the on-current is higher in transistors using single crystal silicon or polycrystalline silicon. This is a disadvantage in terms of the operating speed of the memory device. It ends up like this.

[0009] In view of the above, one embodiment of the present invention is to provide a semiconductor memory device that operates at high speed and consumes low power. This is one of the challenges.

[0010] Furthermore, one embodiment of the present invention provides a semiconductor memory device with an increased memory capacity per unit area. One of our goals is to provide

[0011] Another object is to increase the capacitance of a capacitor in a semiconductor memory device. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. The memory cell has two or more sub-memory cells each having a transistor. The sub-memory cells are stacked and formed, and the transistors are connected to the first gate through a semiconductor film. A first gate and a second gate are formed, and the first gate and the second gate are connected to a word line. One of the source and drain of the transistor is connected to a bit line. The other of the source and drain is connected to a first capacitor and a second capacitor. a first gate and a second gate of the semiconductor device overlapping and connected to each other; It is a body memory device.

[0013] Furthermore, one aspect of the present invention is a first capacitor and a second capacitor in each of the sub-memory cells. Two capacitors may be formed in an overlapping manner.

[0014] In one aspect of the present invention, the memory cells are formed in a matrix on a plane. That's fine.

[0015] In one embodiment of the present invention, an oxide semiconductor is used for the transistor.

[0016] In one embodiment of the present invention, sub-memory cells can be stacked in an overlapping manner to form a memory cell. This is because an oxide semiconductor is used for the active layer of the transistor in the sub-memory cell. This is because oxide semiconductors can be formed by deposition methods such as sputtering. By stacking memory cells, a small memory cell area can be created, and the unit area The storage capacity per memory module can be further increased.

[0017] Furthermore, one embodiment of the present invention provides a transistor having silicon stacked with a sub-memory cell. The silicon-based transistor can be a stacked semiconductor memory device. It is preferable to provide it at the bottom layer of the device, and it can be formed using, for example, a silicon substrate. Moreover, the number of the layers is not limited to one layer, and the layers may be formed in a plurality of locations between the sub-memory cells.

[0018] One aspect of the present invention is a semiconductor memory device characterized in that the sub-memory cells are DRAMs. be. [Effects of the Invention]

[0019] According to one embodiment of the present invention, an oxide having both a high on-current and a low off-current is provided. By using a transistor having a semiconductor, high-speed operation and low power consumption are achieved. A storage device may be provided.

[0020] According to one aspect of the present invention, the sub-memory cells are stacked in a plurality of layers, thereby forming a unit surface It is possible to provide a semiconductor memory device with an increased memory capacity per unit area.

[0021] According to one aspect of the present invention, the capacitance of a capacitor in a semiconductor memory device can be increased. Cut. [Brief explanation of the drawings]

[0022] [Figure 1]1A and 1B are a perspective view and a circuit diagram illustrating an example of a semiconductor memory device of one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating an example of a memory cell in a semiconductor memory device according to one embodiment of the present invention. [Figure 3] 1A and 1B are a top view and a cross-sectional view illustrating an example of a submemory cell in a semiconductor memory device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a memory cell according to one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a memory cell according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor memory device according to one embodiment of the present invention. [Figure 7] 1A and 1B are a block diagram and a partial circuit diagram illustrating a specific example of a CPU including a semiconductor memory device according to one embodiment of the present invention. [Figure 8] 1A and 1B are perspective views illustrating examples of electronic devices including a semiconductor memory device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. It should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. These are commonly used, and repeated explanations will be omitted.

[0024] In each of the drawings described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0025] In addition, terms such as first, second, and third used in this specification are used in order to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0026] In this specification, one of the source and drain of a transistor is referred to as the drain. The other is the source. In other words, there is no distinction between them based on whether the potential is high or low. In this specification, the part referred to as a source can also be read as a drain.

[0027] In this specification, the gate of a transistor is called a gate or a gate electrode. Furthermore, the source and drain of a transistor are referred to as source and drain, The source and drain regions, or source and drain electrodes, are distinguished from each other. do not have.

[0028] In this specification, even when the term "connect" is used, in an actual circuit, In some cases, there are no physical connections and only wiring is extended. In a metal-insulated field-effect transistor (MISFET) circuit, one wire connects multiple MISFs. In some cases, the gate also serves as the ET gate. In this case, the circuit diagram shows a single wire It may be written so that multiple branches occur. In this specification, even in such cases, The expression "the wiring connects to the gate" is sometimes used.

[0029] (Embodiment 1) In this embodiment, an example of the configuration and operation of a memory cell, which is a semiconductor memory device, will be described. This will be explained using Figures 1 and 2 etc.

[0030] A semiconductor memory device 300 according to one embodiment of the present invention illustrated in FIG. 1A includes a transistor, a first A capacitor (also called a front capacitor (Cf)) and a second capacitor (back capacitor The sub-memory cells SCL each consisting of a capacitor (Cb) are stacked to form a memory cell CL. The memory cells CL are arranged in a matrix of a horizontal x b vertical (a and b are natural numbers) on a plane. It is configured in a risk-like arrangement.

[0031] The sub-memory cell SCL is composed of a transistor, a front capacitor, and a back capacitor. It is a memory device that consists of a DRAM.

[0032] CL consists of c layers (c is a natural number) stacked SCL_1 to SCL_c, and each SCL_j( j=a natural number from 1 to c) is the transistor Tr_j (j=a natural number from 1 to c), Cf_j (j Tr_j (j = a natural number from 1 to c) and Cb_j (j = a natural number from 1 to c). represents the gate of Tr_j (also referred to as the first gate or front gate) and the semiconductor film The gate of Tr_(j-1) overlaps with the gate through It is a so-called dual gate transistor, controlled by In the case of Tr_1, the back gate is not the gate of Tr_(j-1), but Tr_ The wiring that overlaps with the gate through the semiconductor film of 1 is used as a back gate. The front gate and back gate of the transistor in the memory cell are electrically connected. are.

[0033] Cf_j is formed of the same material and the same layer as the front gate in Tr_j. The capacitance of the gate insulating film between the capacitance electrode and one of the source and drain of Tr_j is Cb_j is formed by the capacitance electrode of Cf_(j-1) and the solution of Tr_j. It is formed by the capacitance of the insulating film between the source and one of the drain.

[0034] Cb_1 is set separately on one of the source and drain of Tr_1 and on the lower layer of SCL_1. This may be formed by the capacitance of the insulating film between the gate capacitance wiring.

[0035] As shown in FIG. 1(B), in CL consisting of SCL_1 to SCL_c, For example, if we look at SCL_1, the front gate and back gate of Tr_1 are connected to the Tr_1 is connected to the bit line WL, and one of the source and drain of Tr_1 is connected to the bit line BL_1. The other end of the source and drain of Tr_1 is connected to one end of Cf_1 and one end of Cb_1. The other end of Cb_1 is grounded (connected to GND). It is connected to the other end of Cb_2 in SCL_2.

[0036] In addition, the gate and wire of the transistor in each of the sub-memory cells formed by stacking are The word lines are connected. Therefore, by inputting a signal to the word line, each stacked The transistors in the sub-memory cells can be driven simultaneously.

[0037] As shown in Figure 1(B), the other end of Cb_j is grounded when j is 1, and when j is greater than 1, If it is greater than 1, it is connected to the other end of Cf_(j-1).

[0038] The transistor Tr_j is a transistor with a small off-state current. By using a wide-gap semiconductor with a gap of 2.5 eV or more, a low off-state current can be achieved. In particular, an oxide semiconductor can be preferably used as the transistor.

[0039] By using a transistor with a small off-state current in the sub-memory cell, the front capacitor and and the charge stored in the back capacitor leaks through the transistor Tr_j. Therefore, the potential retention period is extended, and the refresh time in the DRAM is reduced. Since the frequency of the queuing can be reduced, power consumption can be reduced.

[0040] The transistor Tr_j described in this embodiment has a front gate and a back gate. This is a so-called dual gate transistor. When a voltage higher than the threshold voltage is applied to the gate, the transistor turns on and the back The threshold voltage is shifted negatively by applying a similar voltage to the gate. As a result, the on-current at gate voltages above a certain threshold is In addition, the front gate of the transistor has a voltage smaller than the threshold voltage. When a large voltage is applied, the transistor turns off, and a similar voltage is applied to the back gate. The applied pressure causes a positive shift in the threshold. The off-state current at a low gate voltage is smaller than that of a transistor without a back gate. become.

[0041] That is, the semiconductor memory device described in this embodiment uses a transistor including an oxide semiconductor. By combining a high on-current and a low off-current, high-speed operation and Power consumption can be reduced.

[0042] Furthermore, by adjusting the capacitance of the capacitor in each sub-memory cell, the stored This allows the memory cell to have multiple potentials, making it possible to fabricate a multi-valued memory cell. Cut.

[0043] Next, a method for writing and reading data to and from a memory cell will be described below.

[0044] First, data can be written to a memory cell for each sub-memory cell. The potential of the word line is set to VH (threshold voltage (Vth) of the transistor) and VDD (power supply voltage Next, an arbitrarily selected bit line is set to VDD, and The other bit lines are set to GND. This allows the sub-memory connected to the selected bit line to The capacitor in the memory cell is charged to VDD. Next, the word line potential is set to GND. By doing so, the data is retained in the corresponding sub-memory cell. The above is the method for writing data to a memory cell.

[0045] The data written in this manner can be read from a memory cell using an oxide semiconductor film according to one embodiment of the present invention. Since the off-current of the transistor is small, it is possible to hold the transistor for a long period of time.

[0046] Next, a data read method will be described. Data is read for each sub-memory cell. First, a bit line selected arbitrarily is set to a predetermined potential (constant potential). Next, the word line By setting VH, a potential corresponding to the data written in the capacitor is applied to the bit line. After that, the applied potential is read out by a sense amplifier (not shown). The data is lost as soon as it is read, but is amplified by the sense amplifier and then resampled. Then, by changing the sub-memory cell, data can be written to the This completes the method for reading data from a memory cell.

[0047] The method of writing and reading data to and from the memory cells is the method for each sub-memory cell. However, they may be performed simultaneously.

[0048] Next, as shown in FIG. 1, the memory cell CL is stacked with the sub-memory cells SCL. The cross-sectional structure of the memory cell CL shown in FIG. The memory cell is made up of c sub-memory cells SCL_1 to SCL_c, and each sub-memory cell has a transistor. Tr_j (j = natural number from 1 to c), front capacitor Cf_j (j = natural number from 1 to c) The capacitors are composed of a capacitor Cb_j (j=a natural number between 1 and c) and a back capacitor Cb_j (j=a natural number between 1 and c). FIG. 2(A) is a top view of the sub-memory cell SCL_j, and FIG. 2(B) is a top view of the sub-memory cells SCL_1 to SCL_S A cross-sectional view of CL_c is shown.

[0049] FIG. 2A shows the transistor Tr_j and the front gate of the sub-memory cell SCL_j. The top view of the capacitor Cf_j is shown. Cb_j is not shown. Also, a point on the top view of SCL_j shown in FIG. The AB, CD and EF cross sections correspond to the dashed line AB, the dotted line CD and the dotted line EF. The surface is shown in Figure 2(B).

[0050] As shown in FIG. 2B, the sub-memory cells are stacked one on top of the other. The films in the transistors and capacitors that make up the memory cell are also formed in an overlapping manner. In addition, the front gate (including the back gate) of the transistor in each sub-memory cell ) are all electrically connected.

[0051] Next, the cross-sectional structure of Tr_1, Cf_1, and Cb_1 in SCL_1 is shown in Figure 3. This will be explained in detail using the following.

[0052] FIG. 3A shows the transistor Tr_1 and the front gate of the sub-memory cell SCL_1. The top view of the capacitor Cf_1 is shown. Cb_1 is not shown. Also, a point on the top view of SCL_1 shown in FIG. The AB, CD and EF cross sections correspond to the dashed line AB, the dotted line CD and the dotted line EF. The surface is shown in Figure 3(B).

[0053] The transistor Tr_1 shown in FIG. 3B includes a substrate 100 and a second The first wiring 101 and the third wiring 140, and the first wiring 101 and the third wiring 140 are provided on the a first interlayer insulating film 102 formed on the first interlayer insulating film 102 and a base insulating film formed on the first interlayer insulating film 102; 104, a channel forming region 106a provided on the base insulating film 104, a source region and The oxide semiconductor film 106 having the drain region 106b and the gate electrode 106a on the oxide semiconductor film 106 are a gate insulating film 108, a gate electrode 110 and a capacitance electrode 130 on the gate insulating film 108, and a gate electrode 110 and a capacitance electrode 130 on the gate insulating film 108. The second interlayer insulating film 112 on the port electrode 110 and the capacitance electrode 130, and the second interlayer insulating film 113 on the second interlayer insulating film 114 are The source and drain regions 106b are connected to the contact holes formed in the contact hole 12. and a second wiring 114 connected to the first wiring 114 .

[0054] The capacitance electrode 130 of the capacitor Cf_1 is made of the same material and the same layer as the gate electrode 110. It can be formed in one layer.

[0055] The third wiring 140 in the capacitor Cb_1 is made of the same material as the first wiring 101. They can be formed from the same layer.

[0056] The first wiring 101 also functions as the back gate of the transistor Tr_1.

[0057] It is also possible to use a structure in which the base insulating film 104 is not provided and the base insulating film 104 also serves as the first interlayer insulating film 102. No.

[0058] Furthermore, the formation of the contact holes is not limited to that shown in this embodiment. For example, contact holes may be formed through multiple layers at once, or one layer at a time. The contact holes may be formed in a plurality of steps.

[0059] The oxide semiconductor film 106 in this embodiment has a channel formation region 106a and a The source and drain regions 106b have a lower resistance than the hole formation region 106a. By providing the source region and the drain region 106b as described above, the second wiring 114 This reduces the contact resistance with the semiconductor substrate, thereby improving the on-state characteristics of the transistor. However, the oxide film on which the source and drain regions 106b are formed can be removed. The present invention is not limited to the oxide semiconductor film 106, and may be applied to any oxide semiconductor film that does not have a low resistance region. This may also be configured as follows.

[0060] The source and drain regions 106b are formed of a material selected from phosphorus, boron, nitrogen, and fluorine. By adding the above elements to the oxide semiconductor film, Therefore, the resistance value of the oxide semiconductor film can be reduced.

[0061] There are no particular limitations on the substrate 100, but it should at least have heat resistance to the extent that it can withstand subsequent heat treatment. For example, glass substrate, ceramic substrate, quartz substrate, sapphire substrate Alternatively, a single crystal semiconductor such as silicon or silicon carbide may be used as the substrate 100. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as GaN, SOI (Silicon It is also possible to apply a substrate such as a silicon-on-insulator (Si-on-insulator) substrate. It is preferable to use a substrate provided with a semiconductor element as the substrate 100 .

[0062] A flexible substrate may also be used as the substrate 100. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 100. A release layer may be provided between the non-flexible substrate and the transistor.

[0063] The substrate 100 may be heat-treated. For example, the substrate 100 may be heat-treated using a high-temperature gas. Gas Rapid Thermal Annealing (GRTA) equipment The material may be heat-treated at 650°C for 1 to 5 minutes. The high-temperature gases used include rare gases such as argon, or nitrogen, which are suitable for heat treatment. An inert gas that does not react with the material is used. Also, in an electric furnace, it is heated at 500°C for 30 minutes to 1 hour. Heat treatment may be carried out during this time.

[0064] The first wiring 101 and the third wiring 140 are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as nickel, aluminum, copper, chromium, neodymium, scandium, etc., or materials mainly containing these The first wiring 101 can be formed using an alloy material containing rib. Semiconductor films, such as polycrystalline silicon films doped with impurity elements such as silicon, nickel silicon, A silicide film such as a silicide may be used. The layer 40 may have a single layer structure or a laminated structure.

[0065] Furthermore, the first wiring 101 and the third wiring 140 are made of indium oxide, tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium oxide oxide Conductive materials such as zinc oxide and indium tin oxide doped with silicon oxide can also be used. Cut.

[0066] The first interlayer insulating film 102 and the base insulating film 104 are made of silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide , zirconium oxide, yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide, At least one of tantalum oxide and magnesium oxide may be selected and used in a single layer or a laminated layer. stomach.

[0067] In addition, hydrogen or moisture contained in the first interlayer insulating film 102 or the base insulating film 104 may be In order to remove impurities, heat treatment is preferably performed after the base insulating film 104 is formed. The temperature of the heat treatment is 350°C or higher and lower than the strain point of the substrate, preferably 450°C or higher and 650°C or lower. The heat treatment may be carried out in an inert atmosphere, an oxidizing atmosphere, or the like.

[0068] In addition, it is preferable that the first interlayer insulating film 102 and the base insulating film 104 have sufficient flatness. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably 1 nm or less. A base film is provided so that the thickness is preferably 0.1 nm or less. By setting the temperature to 1000°C, a crystalline region is easily formed in the oxide semiconductor film. Arithmetic mean roughness defined in SB 0601:2001 (ISO4287:1997) It is a three-dimensional extension of the method that can be applied to curved surfaces, and is called "the distance from the reference surface to the specified surface." It can be expressed as "the average of the absolute values ​​of the deviations of the

[0069]

number

[0070] Here, the specified surface is the surface to be measured for roughness, and has coordinates ((x1, y1, f(x1, y1))(x1,y2,f(x1,y2))(x2,y1,f(x2,y1))(x2, The specified surface is projected onto the xy plane as a rectangular area represented by four points (x2, y2, f(x2, y2)). The area of ​​the rectangle is S0, and the average height of the specified surface is Z0. Ra is measured by an atomic force microscope (AF It can be measured using an Atomic Force Microscope (AFM).

[0071] Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less , silicon is in the range of 25 atomic % to 35 atomic % and hydrogen is in the range of 0 atomic % to 10 atomic % Silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 10 atomic % or more and 25 atomic % or less. However, the above range is based on the Rutherford method. Rutherford Backscattering Spectroscopy (RBS) rometry) and Hydrogen Forward Scattering (HFS) This is measured using Scattering Spectrometry (SCST). The composition of the constituent elements has a value in which the total does not exceed 100 atomic %.

[0072] The first interlayer insulating film 102 and the base insulating film 104 release oxygen by heat treatment. It is preferable to use an insulating film.

[0073] "Oxygen is released by heat treatment" refers to TDS (Thermal Desorption / Stimulation Spectroscopy (thermal desorption spectroscopy) analysis, converted to oxygen atoms The amount of oxygen released is 1.0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 This means that the above is the case.

[0074] Here, the method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis is as follows: will be explained.

[0075] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of released gas is calculated by the ratio of the integral value of the spectrum obtained to the reference value of the standard sample. The reference value of the standard sample is the integral value of the spectrum of the sample containing the specified atom. is the atomic density ratio.

[0076] For example, the TDS analysis results of a silicon wafer containing a predetermined density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using formula 2 Here, all of the spectra detected at mass number 32 obtained by TDS analysis can be It is assumed that the mass number is derived from oxygen molecules. There is also CH3OH, which has a mass number of 32. It is unlikely that this will occur, so it will not be considered here. The existence of oxygen molecules containing oxygen atoms with mass numbers 7 and 18 in nature is also unknown. Not considered as the ratio is extremely small.

[0077]

number

[0078] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the material is subjected to TDS analysis is shown in Fig. 1. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating film is Using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Corporation, 1×10 16 atoms / cm 2 Measurement is performed using a silicon wafer containing hydrogen atoms. .

[0079] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0080] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0081] In the case of a transistor using an oxide semiconductor film, oxygen is supplied to the oxide semiconductor film from a base insulating film. By supplying the oxide semiconductor film with the insulating film, the interface state density between the oxide semiconductor film and the base insulating film can be reduced. Due to the operation of a transistor, carriers are generated at the interface between the oxide semiconductor film and the base insulating film. This makes it possible to suppress the capture of .

[0082] Furthermore, charges may be generated due to oxygen vacancies in the oxide semiconductor film. Oxygen vacancies in the conductive film act as donors and release electrons, which are carriers. The threshold voltage of the transistor shifts in the negative direction. Oxygen is sufficiently supplied to the oxide semiconductor film, and preferably, the oxide semiconductor film does not contain excessive oxygen. The oxide semiconductor, which is the cause of the threshold voltage shift in the negative direction, The oxygen vacancy density of the membrane can be reduced.

[0083] The oxide semiconductor film 106 is made of at least indium (In) or nickel. It is preferable that lead (Zn) is contained. It is particularly preferable that In and Zn are contained. A stabilizer for reducing variations in the electrical characteristics of a transistor using the compound semiconductor film 106. It is preferable to have gallium (Ga) as a stabilizer in addition to the above. As the catalyst, tin (Sn), hafnium (Hf), aluminum (Al), titanium (Ti ) or zirconium (Zr).

[0084] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0085] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. substances, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO and (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Z n-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides Oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides , In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn -Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide Compounds can be used.

[0086] The oxide semiconductor film 106 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0087] The oxide semiconductor film 106 is preferably a CAAC-OS (C Axis Aligned Oxide Semiconductor) film. The film is a Crystalline Oxide Semiconductor.

[0088] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often sized to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image using a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS film was The grain boundaries in the CAAC-OS film were not clearly observed by TEM. Therefore, the CAAC-OS film is not affected by electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0089] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the b-axis may be different. In this specification, when simply referring to a vertical axis, it means that the This also includes the range of -5° to 95°. This also includes the range of 5° or less.

[0090] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0091] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0092] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0093] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0094] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk can be further reduced. Furthermore, by improving the surface flatness, the amorphous state It is possible to obtain a mobility higher than that of an oxide semiconductor. It is preferable to form an oxide semiconductor on the surface. Specifically, it is preferable that the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less It would be good to do so.

[0095] The oxide semiconductor film is formed by sputtering, MBE (Molecular Beam Epi Taxy method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) The oxide semiconductor film can be formed by a sputtering method or the like. Film deposition is performed with multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed using a sputtering apparatus that performs the above process.

[0096] In addition, the oxide semiconductor film contains almost no impurities such as copper, aluminum, or chlorine. It is desirable that the material be highly purified so that it is not easily broken down. It is necessary to appropriately select a process that does not involve the risk of these impurities being mixed into or adhering to the surface of the oxide semiconductor film. When the oxide semiconductor film is adhered to the surface, it is preferable to expose the oxide semiconductor film to oxalic acid or dilute hydrofluoric acid. Alternatively, a plasma treatment (such as N2O plasma treatment) may be performed to form a thin oxide semiconductor film. It is preferable to remove impurities from the surface of the oxide semiconductor film. 18 atoms / cm 3 Less than 1 × 10 17 atoms / cm 3 The following applies. The aluminum concentration in the oxide semiconductor film is 1×10 18 atoms / cm 3 The following The chlorine concentration in the oxide semiconductor film is 2×10 18 atoms / cm 3 The following applies.

[0097] The gate insulating film 108 can be formed by a plasma CVD method, a sputtering method, or the like. silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, Hafnium oxide, gallium oxide, magnesium oxide, tantalum oxide, yttrium oxide, a single layer of one or more materials selected from the group consisting of zirconium oxide, lanthanum oxide, and neodymium oxide; Alternatively, they may be used in a laminated state.

[0098] The gate insulating film 108 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and high-k materials such as lanthanum oxide can be used to Furthermore, when the gate insulating film 108 is used as a capacitor, the capacitance can be increased. The gate insulating film 108 may have a single layer structure. Alternatively, a laminated structure may be used.

[0099] The gate electrode 110 and the capacitor electrode 130 are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or materials mainly composed of these The gate electrode 110 can be formed using an alloy material containing phosphorus or the like. Semiconductor films, such as polycrystalline silicon films doped with impurity elements, nickel silicide films, The gate electrode 110 may have a single layer structure. , and may have a laminated structure.

[0100] The gate electrode 110 and the capacitor electrode 130 are made of indium oxide, tin oxide, or tungsten oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide containing titanium dioxide, indium oxide Conductive materials such as indium tin oxide doped with zinc or silicon oxide can also be used. do.

[0101] In addition, a layer of the gate electrode 110 in contact with the gate insulating film 108 is made of a metal oxide containing nitrogen. Specifically, nitrogen-containing In-Ga-Zn-O films, nitrogen-containing In-Sn-O films, , In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, and Sn-O films containing nitrogen. films, In-O films containing nitrogen, and metal nitride films (InN, SnN, etc.) can be used. These films have a specific resistance of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the threshold voltage of the transistor is can be made positive.

[0102] The second interlayer insulating film 112 is formed from the same material as the base insulating film 104 .

[0103] The second interlayer insulating film 112 preferably has a small relative dielectric constant and a sufficient thickness. For example, a silicon oxide film with a relative dielectric constant of about 3.8 is used, and the thickness is 300 nm to 1000 nm. The surface of the interlayer insulating film 112 may be slightly solidified due to the influence of atmospheric components, etc. It has a constant charge, which can cause the threshold voltage of the transistor to fluctuate. Therefore, the interlayer insulating film 112 is formed in a range in which the influence of the charge generated on the surface is sufficiently small. The dielectric constant and thickness are preferred.

[0104] The second wiring 114 is made of aluminum (Al), chromium (Cr), copper (Cu), tantalum ( Elements selected from the group consisting of Ta, titanium (Ti), molybdenum (Mo), and tungsten (W) Metal films containing the above elements, or metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, etc.) Also, metal films such as Al and Cu can be used. High melting point metal film such as Ti, Mo, W or the like on either the top or bottom or both sides A structure in which metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) are stacked Alternatively, the conductive metal oxide may be used. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide (In2O3-SnO2, abbreviated as ITO), indium oxide Zinc (In2O3-ZnO) or these metal oxide materials containing silicon oxide can be used.

[0105] (Method of Manufacturing a Transistor) Next, a point on the sub-memory cell SCL_1 shown in FIG. The transistor Tr_1, front capacitor Cf_1, and back capacitor Cf_2 are shown in the dashed line AB cross section. A method for manufacturing the capacitor Cb_1 will be described with reference to FIGS.

[0106] First, the first wiring 101 and the third wiring 140 are formed on the substrate 100 (FIG. 4(A)). The first wiring 101 and the third wiring 140 are formed by depositing a conductive film on the substrate 100. The conductive film is processed to form the first wiring 101 and the third wiring 140. Depending on the substrate 100, another wiring 101 may be provided between the substrate 100 and the first wiring 101 and the third wiring 140. For example, a blocking layer may be provided to prevent impurities from diffusing from the substrate. Alternatively, a silicon nitride film having a blocking ability may be formed.

[0107] Unless otherwise specified, "processing" refers to forming a film by photolithography. This refers to the process of using a resist mask and performing an etching process to obtain a film of the desired shape.

[0108] The etching of the conductive film may be dry etching or wet etching. may also be used.

[0109] Next, a first interlayer insulating film 102 is formed on the substrate 100, the first wiring 101, and the third wiring 140. and a base insulating film 104 is formed (see FIG. 4(B)). The base insulating film 104 is formed by chemical vapor deposition (CVD). ition method, sputtering method, molecular beam epitaxy (MBE) Beam Epitaxy or Pulsed Laser Deposition (PLD) The film can be formed by the sputtering method. It's nice.

[0110] The first interlayer insulating film 102 is formed on the substrate 100, the first wiring 101, and the third wiring 140. After forming the layer, it is preferable to planarize the surface. The planarization may be performed by, for example, chemical mechanical polishing. Chemical Mechanical Polishing (CMP) is used. The surface of the first interlayer insulating film 102 is planarized, and then the base insulating film 104 is formed. By flattening the surface in this way, it is possible to prevent the thin film formed in the subsequent process from being broken down. This can reduce the exposure time and improve the exposure accuracy in the photolithography method. After the interlayer insulating film 102 and the base insulating film 104 are formed, planarization treatments are performed. Alternatively, the planarization treatment may be performed only after the base insulating film 104 is formed.

[0111] The planarization process is not particularly limited, but may be a CMP process, a dry etching process, Plasma treatment or the like can be used.

[0112] In addition, hydrogen or moisture contained in the first interlayer insulating film 102 or the base insulating film 104 In order to remove impurities, the first interlayer insulating film 102 or the base insulating film 104 is subjected to heat treatment after being formed. The temperature of the heat treatment is preferably 350° C. or higher and lower than the distortion point of the substrate. The heat treatment is carried out at a temperature between 450℃ and 650℃. The heat treatment atmosphere can be an inert atmosphere, an oxidizing atmosphere, etc. This can be done by

[0113] Next, an oxide semiconductor film is formed on the base insulating film 104. The oxide semiconductor film is formed by CV The film can be formed by the D method, sputtering method, MBE method or PLD method. It is preferable to use

[0114] In forming the oxide semiconductor film, hydrogen or water is preferably not contained in the oxide semiconductor film. In order to achieve this, a base film is formed in a treatment chamber of a sputtering apparatus as a pretreatment for forming an oxide semiconductor film. The plate is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 100 and the underlying insulating film 104. It is preferable to remove it.

[0115] Further, before the oxide semiconductor film is formed, planarization treatment may be performed on the surface of the base insulating film 104. stomach.

[0116] As the plasma treatment, reverse sputtering can be performed. For example, in an argon atmosphere, a voltage is applied to the substrate side using an RF power supply, and This is a method of forming plasma to modify the surface to be treated. Note that the nitrogen atmosphere is used instead of the argon atmosphere. , helium, oxygen, etc. may also be used.

[0117] Note that the oxide semiconductor film is formed under conditions in which a large amount of oxygen is contained (for example, 100% oxygen). % atmosphere)).

[0118] After the oxide semiconductor film is formed, heat treatment may be performed. The crystallinity of the film is increased. In addition, the concentration of impurities (such as hydrogen and moisture) in the oxide semiconductor film is reduced. This reduces the defect level.

[0119] Heat treatment may be performed in one of an oxidizing atmosphere, an inert atmosphere, a reduced pressure atmosphere, or a dry air atmosphere. Preferably, the heat treatment is carried out in an inert atmosphere, and After that, heat treatment is carried out in an oxidizing atmosphere. The temperature of the heat treatment is 150°C or higher and 650°C or lower. Preferably, the temperature is 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower. Heat treatment can be carried out by a resistance heating method, a lamp heater method, a heated gas method, or the like. Just use it.

[0120] An oxidizing atmosphere is an atmosphere containing an oxidizing gas, such as oxygen, ozone, or It is preferable that the gas is nitrous oxide or the like and does not contain water, hydrogen, etc. For example, The purity of oxygen, ozone, and nitrous oxide introduced into the equipment must be 8N (99.999999%) or higher. The oxidizing atmosphere is preferably 9N (99.9999999%) or more. In this case, the oxidizing gas must be at least 10 ppm. By performing heat treatment in an oxidizing atmosphere, the oxide semiconductor film can be oxidized. The density of electron defects can be reduced.

[0121] The inert atmosphere refers to an atmosphere whose main component is an inert gas such as nitrogen or a rare gas. The atmosphere should contain less than 10 ppm of reactive gases such as oxidizing gases. By performing heat treatment at 100° C., the impurity concentration in the oxide semiconductor film can be reduced. .

[0122] A reduced pressure atmosphere is an atmosphere in which the pressure in the processing chamber is 10 Pa or less. By performing this treatment, the impurity concentration in the oxide semiconductor film can be further reduced compared to when an inert atmosphere is used. It is possible.

[0123] Dry air atmosphere means a dew point of -40°C or less, preferably a dew point of -50°C or less, with approximately 20% oxygen. It is a type of oxidizing atmosphere, but it is relatively low cost. It is suitable for mass production because it is

[0124] Next, the oxide semiconductor film is processed to form the oxide semiconductor film 103 (see FIG. 4C). .

[0125] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. The etching solution used for wet etching of the oxide semiconductor film may be used. For example, a solution of phosphoric acid, acetic acid, and nitric acid can be used. N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Dry etching using an inductively coupled plasma (Inductively Coupled Plasma) etching system You may go.

[0126] In addition, oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions) is added to the oxide semiconductor film. Oxygen may be supplied to the film by introducing oxygen.

[0127] By introducing oxygen into the oxide semiconductor film and supplying oxygen into the film, This compensates for oxygen vacancies in the oxide semiconductor, making it closer to an intrinsic semiconductor. To positively shift the threshold voltage of a transistor using a conductive film, thereby further improving reliability. can be done.

[0128] Oxygen can be introduced by ion implantation, ion doping, plasma treatment, etc. It is possible.

[0129] Next, the gate insulating film 108 is formed on the oxide semiconductor film 103. The film can be formed by CVD, sputtering, MBE, or PLD. It is preferable to use the coating method.

[0130] Next, a resist mask 107 is formed on the gate insulating film 108. is formed by applying a resist, followed by exposure and development treatment.

[0131] Next, the oxide semiconductor film 103 was doped with a dopant using the resist mask 107 as a mask. The resistance of the oxide semiconductor film 103 to which the dopant is added is reduced. By adding a dopant to the oxide semiconductor film 103 as described above, The source and drain regions 106b are doped with a dopant and have a low resistance. The oxide semiconductor film 106 having the channel formation region 106a is formed (FIG. 5A). reference.).

[0132] Dopants are impurities that reduce the resistance of the oxide semiconductor film, and include phosphorus (P), boron ( B), nitrogen (N) and fluorine (F) can be used.

[0133] The dopant can be added by ion implantation, ion doping, or the like. In addition, the substrate 100 may be heated during this process.

[0134] The dopant addition process may be carried out multiple times, and multiple types of dopants may be used. It's fine.

[0135] After doping, a heat treatment may be carried out. The heating conditions are 300° C. or higher. The heating is carried out at a temperature of 300 to 450°C for 1 hour in an oxygen atmosphere. It is also preferable to carry out the heat treatment under a nitrogen atmosphere, under reduced pressure, or in the air (ultra-dry air). Good too.

[0136] Next, after removing the resist mask 107, a conductive film is formed on the gate insulating film and then etched. The gate electrode 110 and the capacitor electrode 130 are formed by etching (see FIG. 5(B)). .).

[0137] Next, a second interlayer insulating film is formed on the gate insulating film 108, the gate electrode 110, and the capacitor electrode 130. The second interlayer insulating film 112 is formed by a CVD method, a sputtering method, an MBE method, or the like. The insulating film 104 may be formed by PLD or spin coating. Furthermore, a contact hole is formed in the second interlayer insulating film 112. Then, a part of one of the source and drain regions 106b is exposed to form a A second wiring 114 is formed to connect to one side of the drain region 106b (see FIG. 5(C)). .

[0138] The transistor structure in this embodiment is a planar type transistor structure. However, the present invention is not limited to this. Top gate top contact type and top gate bottom contact type with a silicon electrode formed , bottom gate top contact type, bottom gate bottom contact type, etc. Furthermore, in this embodiment, the top surface shape of the transistor is rectangular. However, it may be formed in a circular shape or the like.

[0139] As described above, the gate electrode 110 (front gate electrode) overlapping the channel forming region 106a A dual gate having a first wiring 101 (also called a back gate) and a second wiring 102 (also called a back gate). A transistor Tr_1 having a gate structure can be formed. The front capacitor Cf_1 formed by the other side of the in-region 106b and the capacitance electrode 130 and a barrier formed by the other of the source region and drain region 106b and the third wiring 140. A block capacitor Cb_1 can be formed.

[0140] According to this embodiment, in a transistor in which a channel region is provided in an oxide semiconductor film, By providing a front gate and a back gate, a high on-current and a low off-current can be achieved. It is possible to provide a transistor having both of these characteristics. This makes it possible to provide a semiconductor memory device that operates at high speed and consumes less power.

[0141] According to one aspect of the present invention, a front capacitor and a back capacitor can be formed. This allows the capacitance of the capacitor in the semiconductor memory device to be increased.

[0142] By using the transistor and the capacitor according to one embodiment of the present invention, it is possible to realize a DRAM or the like. Furthermore, a plurality of semiconductor memory devices can be stacked one on top of the other. By doing so, it is possible to provide a semiconductor memory device with an increased memory capacity per unit area. This can be done.

[0143] This embodiment mode can be used in combination with other embodiment modes as appropriate.

[0144] (Embodiment 2) In this embodiment, a semiconductor memory device having a different structure from that of the first embodiment will be described with reference to FIG. The difference from Embodiment 1 is that a transistor including an oxide semiconductor is used. Semiconductor memory device having silicon transistors in addition to memory cells is.

[0145] A transistor containing silicon has a field effect Because of its high mobility, it is preferable to use it in peripheral circuits of memory cells. The silicon-containing transistor is a lower layer of a memory cell formed by stacking sub-memory cells. However, it may be provided in a layer between stacked sub-memory cells. A single layer or multiple layers may be used.

[0146] In this embodiment, a transistor having silicon is formed in the bottom layer, and A semiconductor memory device in which memory cells shown in the first embodiment are stacked will be described.

[0147] 6A and 6B show a top view and a cross-sectional view of the semiconductor memory device according to this embodiment. 6B is a top view of the sub-memory cell SCL_j, and FIG. 6C is a top view of the sub-memory cells SCL_1 to SCL_j. As shown in FIG. 6(B), a memory in which sub-memory cells are stacked one on top of another is shown. A layer having a transistor 800 made of silicon is formed below the cell CL.

[0148] FIG. 6A shows the transistor Tr_j and the front gate of the sub-memory cell SCL_j. The top view of the capacitor Cf_j is shown. Cb_j is not shown. Also, a point on the top view of SCL_j shown in FIG. The AB, CD and EF cross sections correspond to the dashed line AB, the dotted line CD and the dotted line EF. The surface is shown in Figure 6(B).

[0149] FIG. 6C is a cross-sectional view of a transistor 800 including silicon.

[0150] The transistor 800 includes a channel forming region 201 provided in a silicon substrate 200 and a The impurity regions 206 are provided so as to sandwich the channel forming region 201, and the channel forming region 2 A gate insulating layer 208 is provided on the gate electrode 201, and a gate electrode 203 is provided on the gate insulating layer 208. a first interlayer insulating film 212 on the gate electrode 210 and the impurity region; The source electrode 204 is connected to the impurity region 206 through a contact hole formed in the interlayer insulating film 212. the first interlayer insulating film 212, the source and drain electrodes 214, and a second interlayer insulating film 216 on the substrate 14.

[0151] Moreover, an element isolation insulating layer 203 is formed on the silicon substrate 200 so as to surround the transistor 800. is provided.

[0152] A sidewall insulating film is formed on the sidewall of the gate electrode 210 to form an LDD region. However, in order to achieve high integration, it is necessary to use a transistor as shown in FIG. It is desirable that the transistor 800 does not have a sidewall insulating layer.

[0153] Next, as shown in the first embodiment, the second interlayer insulating film 216 in the transistor 800 The first wiring 101 and the third wiring 140 may be formed in this order on top of each other.

[0154] As shown above, a transistor 800 having silicon and a The dual-gate oxide semiconductor transistor described in Embodiment 1 is formed by stacking the oxide semiconductor layers. Furthermore, the other of the source region and the drain region 106b can be formed. and the front capacitor Cf_j formed by the capacitor electrode 130, and the source region and the drain region The back capacitor Cb_j formed by the other of the in-region 106b and the third wiring 140 can be formed.

[0155] According to this embodiment, a transistor 800 including silicon and a transistor including an oxide semiconductor film A transistor having an oxide semiconductor film can be formed. By providing a front gate and a back gate, a high on-current and a low on-current can be obtained. It is possible to provide a transistor having characteristics of both high current and low current. By using this, it is possible to provide a semiconductor memory device that operates at high speed and consumes less power. Cut.

[0156] According to one aspect of the present invention, a front capacitor and a back capacitor are provided in a sub-memory cell. A semiconductor memory device having two capacitors can be formed. This makes it possible to increase the capacitance of all capacitors in the semiconductor memory device.

[0157] By using the transistor and the capacitor according to one embodiment of the present invention, it is possible to realize a DRAM or the like. Furthermore, a plurality of semiconductor memory devices can be stacked one on top of the other. By doing so, it is possible to provide a semiconductor memory device with an increased memory capacity per unit area. This can be done.

[0158] Furthermore, a transistor including silicon has a higher Because of its large field-effect mobility, it can be used in peripheral circuits of memory cells, and The cells and peripheral circuits can be fabricated on the same substrate.

[0159] This embodiment mode can be used in combination with other embodiment modes as appropriate.

[0160] (Embodiment 3) A CP using at least a part of the semiconductor memory device shown in the first or second embodiment It is possible to configure a Central Processing Unit (U).

[0161] 7A is a block diagram showing a specific configuration of the CPU. On the substrate 1190, an arithmetic logic unit (ALU) is installed. t) 1191, ALU controller 1192, instruction decoder 1193, Interrupt controller 1194, timing controller 1195, register 1196 , register controller 1197, bus interface (Bus I / F) 1198, Rewritable ROM 1199 and ROM interface (ROM I / F) 118 9. The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Figure 7(A) is merely an example of a simplified configuration, and the actual CPU PU has a wide variety of configurations depending on its application.

[0162] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0163] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0164] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by an internal clock generator. Supply to the seed circuit.

[0165] In the CPU shown in FIG. 7A, a register 1196 is provided with a storage element. The memory element of the memory cell 1196 is the semiconductor memory device shown in the first or second embodiment. You can be there.

[0166] In the CPU shown in FIG. 7A, the register controller 1197 In accordance with the instruction from the register 1196, the register 1196 performs the hold operation. In the memory element, data is held by a logic element that inverts the logic (value) The data is stored by a capacitor. The data is stored by a logic element that inverts the logic (value). If the data is held, the power supply voltage is supplied to the storage element in the register 1196. If data is being held by a capacitor, rewriting the data to the capacitor is performed, and the supply of the power supply voltage to the storage element in the register 1196 can be stopped.

[0167] Regarding the power supply shutdown, as shown in FIG. 7(B) or FIG. 7(C), the memory element group and the power supply voltage A switching element is provided between the nodes to which the power supply potential VDD or VSS is applied. The circuits in Figures 7(B) and 7(C) will be explained below.

[0168] 7B and 7C, a switching element that controls the supply of a power supply potential to a memory element is shown. An example of a structure using the transistor described in Embodiment 1 or 2 will be described below.

[0169] The memory device shown in FIG. 7B includes a switching element 1141 and a memory element 1142. Specifically, each of the storage elements 1142 has: The memory elements described in Embodiment 1 or 2 can be used. Each memory element 1142 of the memory 43 is connected to the handheld terminal 1141 via a switching element 1141. The power supply potential VDD of the memory element group 1143 is supplied with the same level as the power supply potential VDD of the memory element group 1143. Each memory element 1142 stores the potential of the signal IN and the potential of the low-level power supply potential VSS. It is given.

[0170] In FIG. 7B, a switching element 1141 is formed of a material having a band gap of an oxide semiconductor or the like. The transistor has a semiconductor with a large capacitance in the active layer. The switching is controlled by a signal SigA applied to the port.

[0171] In FIG. 7B, the switching element 1141 has only one transistor. However, the present invention is not limited to this and may have a plurality of transistors. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0172] 7C, each memory element 1142 included in the memory element group 1143 is A low-level power supply potential VSS is supplied to the memory through the switching element 1141. The switching element 1141 controls the memory elements 1143. The supply of the low-level power supply potential VSS to each memory element 1142 can be controlled. do.

[0173] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. When a switching element is provided and the CPU operation is temporarily stopped and the supply of power voltage is stopped, It is possible to retain data even in this state, and power consumption can be reduced. For example, a user of a personal computer may input information into an input device such as a keyboard. Even during a shutdown, the CPU can be stopped, thereby reducing power consumption. It is possible.

[0174] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0175] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0176] (Fourth embodiment) In this embodiment, the semiconductor memory device shown in the first or second embodiment and the embodiment An example of an electronic device including one or more CPUs shown in the third embodiment will be described.

[0177] 8A shows a portable information terminal. The portable information terminal shown in FIG. 8A includes a housing 9300. , a button 9301, a microphone 9302, a display unit 9303, and a speaker 930 4 and a camera 9305, and has the functionality of a mobile phone.

[0178] FIG. 8B shows a display. The display shown in FIG. 8B includes a housing 9310 and , and a display portion 9311.

[0179] FIG. 8(C) is a digital still camera. The digital still camera shown in FIG. , a housing 9320, a button 9321, a microphone 9322, a display unit 9323, It is equipped with:

[0180] FIG. 8(D) shows a foldable mobile information terminal. The information terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a fastener 9633, an operation It has an operating switch 9638.

[0181] The display unit 9631a and / or the display unit 9631b may be partly or entirely a touch panel. By touching the displayed operation keys, data can be input.

[0182] By using one embodiment of the present invention, the performance of an electronic device can be improved.

[0183] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0184] 100 boards 101 First Wiring 102 Interlayer insulating film 103 Oxide semiconductor film 104 Undercoat insulating film 106 Oxide semiconductor film 106a Channel formation region 106b Source and drain regions 107 Resist mask 108 Gate insulating film 110 gate electrode 112 Interlayer insulating film 114 Second Wiring 130 Capacitive electrode 140 Third Wiring 200 silicon substrate 201 Channel formation region 203 Element isolation insulating layer 206 Impurity region 208 Gate insulating layer 210 gate electrode 212 Interlayer insulating film 214 Drain electrode 216 Interlayer insulating film 300 Semiconductor memory device 800 transistors 1141 Switching element 1142 Memory element 1143 Memory Element Group 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 9300 chassis 9301 Button 9302 Microphone 9303 Display section 9304 Speaker 9305 Camera 9310 chassis 9311 Display section 9320 chassis 9321 Button 9322 Microphone 9323 Display section 9630 chassis 9631a Display section 9631b Display section 9633 Fasteners 9638 Operation switch

Claims

1. A semiconductor device having a first transistor and a second transistor, a first semiconductor film having a channel formation region of the first transistor; a first conductive film having a region disposed above the first semiconductor film, the first conductive film functioning as a front gate of the first transistor and a back gate of the second transistor; a second conductive film having a region disposed above the first semiconductor film; an insulating film having a region disposed above the first conductive film and a region disposed above the second conductive film; a second semiconductor film having a region disposed above the insulating film and having a channel formation region of the second transistor; a third conductive film having a region disposed above the second semiconductor film and functioning as a front gate of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film; the second semiconductor film overlaps with the second conductive film via the insulating film, the second conductive film forms a first capacitance between itself and the first semiconductor film; the second conductive film has a region overlapping with the fourth conductive film with the second semiconductor film interposed therebetween; the first conductive film and the third conductive film are always electrically connected to each other, the second conductive film and the fourth conductive film are always electrically connected to each other; Semiconductor device.

2. A semiconductor device having a first transistor and a second transistor, a first semiconductor film having a channel formation region of the first transistor; a first conductive film having a region disposed above the first semiconductor film, the first conductive film functioning as a front gate of the first transistor and a back gate of the second transistor; a second conductive film having a region disposed above the first semiconductor film; an insulating film having a region disposed above the first conductive film and a region disposed above the second conductive film; a second semiconductor film having a region disposed above the insulating film and having a channel formation region of the second transistor; a third conductive film having a region disposed above the second semiconductor film and functioning as a front gate of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film; a fifth conductive film having a region disposed below the first semiconductor film; the second semiconductor film overlaps with the second conductive film via the insulating film, the second conductive film forms a first capacitance between itself and the first semiconductor film; the fifth conductive film forms a second capacitance between itself and the first semiconductor film; the second conductive film has a region overlapping with the fifth conductive film with the first semiconductor film interposed therebetween; the second conductive film has a region overlapping with the fourth conductive film with the second semiconductor film interposed therebetween; the first conductive film and the third conductive film are always electrically connected to each other, the second conductive film and the fourth conductive film are always electrically connected to each other; Semiconductor device.

3. A semiconductor device having a first transistor and a second transistor, a first semiconductor film having a channel formation region of the first transistor; a first conductive film having a region disposed above the first semiconductor film, the first conductive film functioning as a front gate of the first transistor and a back gate of the second transistor; a second conductive film having a region disposed above the first semiconductor film; an insulating film having a region disposed above the first conductive film and a region disposed above the second conductive film; a second semiconductor film having a region disposed above the insulating film and having a channel formation region of the second transistor; a third conductive film having a region disposed above the second semiconductor film and functioning as a front gate of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film; the second semiconductor film overlaps with the second conductive film via the insulating film, the second conductive film forms a first capacitance between itself and the first semiconductor film; the second conductive film has a region overlapping with the fourth conductive film with the second semiconductor film interposed therebetween; the first conductive film and the third conductive film are always electrically connected to each other, the second conductive film and the fourth conductive film are always electrically connected to each other, the second semiconductor film includes an oxide semiconductor; Semiconductor device.

4. A semiconductor device having a first transistor and a second transistor, a first semiconductor film having a channel formation region of the first transistor; a first conductive film having a region disposed above the first semiconductor film, the first conductive film functioning as a front gate of the first transistor and a back gate of the second transistor; a second conductive film having a region disposed above the first semiconductor film; an insulating film having a region disposed above the first conductive film and a region disposed above the second conductive film; a second semiconductor film having a region disposed above the insulating film and having a channel formation region of the second transistor; a third conductive film having a region disposed above the second semiconductor film and functioning as a front gate of the second transistor; a fourth conductive film having a region disposed above the second semiconductor film; a fifth conductive film having a region disposed below the first semiconductor film; the second semiconductor film overlaps with the second conductive film via the insulating film, the second conductive film forms a first capacitance between itself and the first semiconductor film; the fifth conductive film forms a second capacitance between itself and the first semiconductor film; the second conductive film has a region overlapping with the fifth conductive film with the first semiconductor film interposed therebetween; the second conductive film has a region overlapping with the fourth conductive film with the second semiconductor film interposed therebetween; the first conductive film and the third conductive film are always electrically connected to each other, the second conductive film and the fourth conductive film are always electrically connected to each other, the second semiconductor film includes an oxide semiconductor; Semiconductor device.

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