Image sensor and method for forming the same

Abstract

To provide an image sensor and a method for forming the same that reduces the number of conductive structures between stacked chips, thereby reducing the resistivity between the stacked chips.SOLUTION: In a stacked CMOS image sensor, an imaging chip 102 includes an imaging substrate 106, a plurality of photodetectors 132 provided on the imaging substrate, an imaging connection structure 118 provided on the front side of the imaging substrate, and an imaging interconnect structure 110 provided on the imaging connection structure. A logic chip 104 is located below the imaging chip and includes a logic substrate 108, a plurality of logic elements 140 provided on the logic substrate, a logic interconnect structure 112 provided on the front side of the logic substrate, and a logic connection structure 120 provided on the logic interconnect structure. A bond interface 119 is provided between the logic connection structure and the imaging connection structure. The logic interconnect structure is electrically coupled to the imaging interconnect structure by imaging bond pads 126 and logic bond pads 128.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Many modern electronic devices (e.g., smartphones, digital cameras, biometric imagers, vehicle imagers, etc.) include image sensors. Image sensors include one or more light-receiving elements (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output an electrical signal corresponding to the incident radiation. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. CMOS image sensors are increasingly preferred due to their lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing costs compared to CCD image sensors. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. Summary of the Invention [Problem to be solved by the invention]

[0002] The CMOS image sensor may include a stacked imaging chip and a logic chip. The imaging chip includes a plurality of pixel sensors, each including a light-receiving element, and a plurality of pixel elements configured to facilitate readout of accumulated electrical charges. The logic chip includes a plurality of logic elements. The plurality of logic elements and the plurality of pixel elements are electrically coupled to each other via an imaging junction structure and a logic junction structure. The imaging junction structure and the logic junction structure each include a conductive junction layer configured to promote good electrical connection and good bonding adhesion between the logic chip and the imaging chip. However, typically, the imaging junction structure and the logic junction structure each include two or more conductive junction structures. Providing two or more conductive junction structures in each junction structure may increase the resistivity between the imaging chip and the logic chip and / or increase the manufacturing cost of the stacked CMOS image sensor.

[0003] To increase the number of pixel sensors on the imaging chip, the CMOS image sensor can further include a pixel element chip disposed between the imaging chip and the logic chip, with multiple pixel elements transferred from the imaging chip to the pixel element chip. The pixel element chip may include an interconnect structure and a pixel element junction structure disposed thereon, facing the logic junction structure at a junction interface. The interconnect structure of the pixel element chip may further include one or more large conductive contacts extending continuously from the interconnect structure of the pixel element chip to the doped region of the imaging chip. While the one or more large conductive contacts can promote good electrical coupling between the pixel elements and the pixel sensors, the one or more large conductive contacts may be disposed in the device region of the stacked CMOS image sensor. The one or more large conductive contacts may occupy a relatively large area of ​​the device region, thereby increasing the distance between adjacent pixel sensors and reducing the ability to scale down device features. As a result, the design complexity of the stacked CMOS image sensor increases and the area available for multiple pixel sensors decreases, thereby increasing manufacturing costs and reducing device density. [Means for solving the problem]

[0004] The present invention provides a first chip including a first substrate, a plurality of light-receiving elements provided on the first substrate, a first interconnect structure provided on a front side of the first substrate, and floating diffusion nodes provided on the first substrate and at the centers of four adjacent light-receiving elements; a second chip below the first chip, the second chip including a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bonding structure disposed on the second interconnect structure; Including, a first bonding interface between the second bonding structure and the first interconnect structure; the second interconnect structure is electrically coupled to the first interconnect structure by the second joining structure; The first interconnect structure comprises: a first interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of first conductive vias and a plurality of first conductive wires disposed in the first interconnect structure; Including, The second interconnect structure comprises: a second interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of second conductive vias and a plurality of second conductive wires disposed in the second interconnect structure; Including, the second bonding structure includes a single conductive bonding layer, the single conductive bonding layer including a plurality of bonding contacts disposed on a bonding dielectric, the bonding dielectric including silicon dioxide, silicon nitride, silicon carbide, or silicon oxynitride; each of the plurality of bonding contacts directly contacts a top layer of the first conductive wire in the first interconnect structure and a top layer of the second conductive wire in the second interconnect structure; An image sensor is provided.

[0005] The present invention provides a first chip including a first interconnect structure provided on a first substrate, a plurality of light-receiving elements provided on the first substrate, a first junction structure on the first interconnect structure, and floating diffusion nodes provided on the first substrate and at the centers of four adjacent light-receiving elements; a second chip including a second interconnect structure provided on a front side of a second substrate, a plurality of pixel elements provided on the front side of the second substrate, a second bonding structure provided on the second interconnect structure, and a third bonding structure provided on a back side of the second substrate, the second chip being bonded to the first chip; a third chip including a third interconnect structure provided on a third substrate, a plurality of semiconductor devices on the third substrate, and a fourth bonding structure provided on the third interconnect structure, the third chip being bonded to the second chip; Including, The first interconnect structure comprises: a first interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of first conductive vias and a plurality of first conductive wires disposed in the first interconnect structure; Including, The second interconnect structure comprises: a second interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of second conductive vias and a plurality of second conductive wires disposed in the second interconnect structure; Including, The third interconnect structure is a third interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of third conductive vias and a plurality of third conductive wires disposed in the third interconnect structure; Including, At least one of the second bonding structure, the third bonding structure, and the fourth bonding structure includes a single conductive bonding layer disposed on a bonding dielectric, the bonding dielectric including silicon dioxide, silicon nitride, silicon carbide, or silicon oxynitride; the first bonding structure includes a plurality of first bonding contacts and a plurality of first bonding pads; the second junction structure includes a plurality of second junction contacts; each of the plurality of first bonding pads in physical contact with one of the plurality of first bonding contacts and one of the plurality of second bonding contacts; a height of each of the plurality of second junction contacts is equal to a height of the first junction structure; a width of each of the plurality of second bonding contacts is less than a width of each of the plurality of first bonding contacts; An image sensor is provided.

[0006] The present invention 1. A method for forming an image sensor, comprising: forming a plurality of light receiving elements in a first substrate; forming floating diffusion nodes disposed on the first substrate and disposed at the centers of four adjacent light receiving elements; forming a first interconnect structure on the first substrate; The first interconnect structure comprises: a first interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of first conductive vias and a plurality of first conductive wires disposed in the first interconnect structure; and forming a first bonding structure on the first interconnect structure; forming a plurality of semiconductor devices on a second substrate; forming a second interconnect structure on the second substrate; The second interconnect structure comprises: a second interconnect dielectric structure comprising a dielectric material having a dielectric constant less than 3.9; a plurality of second conductive vias and a plurality of second conductive wires disposed in the second interconnect structure; and forming a second bonding structure on the second interconnect structure, the second bonding structure including a single conductive bonding layer, the single conductive bonding layer including a plurality of bonding contacts disposed in a bonding dielectric, the bonding dielectric including silicon dioxide, silicon nitride, silicon carbide, or silicon oxynitride; performing a first bonding process to bond the first substrate to the second substrate such that a bonding interface is provided between the first bonding structure and the second bonding structure; each of the plurality of bonding contacts directly contacts a top layer of the first conductive wire in the first interconnect structure and a top layer of the second conductive wire in the second interconnect structure; The present invention provides a method comprising:

[0007] The present invention provides a first chip including a first substrate, a plurality of light receiving elements provided on the first substrate, a first interconnect structure provided on a front side of the first substrate, and a first junction structure provided on the first interconnect structure; a second chip below the first chip, the second chip including a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bonding structure disposed on the second interconnect structure; Including, a first bonding interface is provided between the second bonding structure and the first bonding structure; the second interconnection structure is electrically connected to the first interconnection structure by the first junction structure and the second junction structure; the first interconnect structure includes a plurality of first conductive vias and a plurality of first conductive wires disposed within a first interconnect dielectric structure; the second interconnect structure includes a plurality of second conductive vias and a plurality of second conductive wires disposed within a second interconnect dielectric structure; the first bonding structure includes a single first conductive bonding layer, the single first conductive bonding layer including a plurality of first bonding pads disposed within a first bonding dielectric, each of the plurality of first bonding pads directly contacting a top layer of the first conductive wire disposed in the first interconnect dielectric structure; the second bonding structure includes a single second conductive bonding layer, the single second conductive bonding layer includes a plurality of second bonding contacts disposed in a second bonding dielectric, each of the plurality of second bonding contacts directly contacting a top layer of the second conductive wire disposed in the second interconnect dielectric structure; An image sensor is provided in which each of the plurality of first bonding pads is in direct contact with one of the plurality of second bonding contacts.

[0008] The present invention provides a first chip including a first interconnect structure provided on a first substrate, a plurality of light receiving elements provided on the first substrate, and a first junction structure on the first interconnect structure; a second chip including a second interconnect structure provided on a front side of a second substrate, a plurality of pixel elements provided on the front side of the second substrate, a second bonding structure provided on the second interconnect structure, and a third bonding structure provided on a back side of the second substrate, the second chip being bonded to the first chip; a third chip including a third interconnect structure provided on a third substrate, a plurality of semiconductor devices on the third substrate, and a fourth bonding structure provided on the third interconnect structure, the third chip being bonded to the second chip; a plurality of through-substrate vias (TSVs) disposed in the second substrate and extending continuously from the third bonding structure to the second interconnect structure; a plurality of upper bonding pads provided on the first substrate; Including, the upper bond pad is electrically coupled to the first interconnect structure and laterally aligned with the TSV; at least one of the second junction structure, the third junction structure, and the fourth junction structure includes a single conductive junction layer; The third bonding structure provides an image sensor including a plurality of bonding pads that are directly electrically coupled to the TSVs.

[0009] The present invention provides 1. A method for forming an image sensor, comprising: forming a plurality of light receiving elements in a first substrate; forming a first interconnect structure on the first substrate, the first interconnect structure including a plurality of first conductive vias and a plurality of first conductive wires disposed within a first interconnect dielectric structure; forming a first bonding structure on the first interconnect structure; forming a plurality of semiconductor devices on a second substrate; forming a second interconnect structure on the second substrate, the second interconnect structure including a plurality of second conductive vias and a plurality of second conductive wires disposed within a second interconnect dielectric structure; forming a second bonding structure on the second interconnect structure; performing a bonding process to bond the first substrate to the second substrate such that a bonding interface is provided between the first bonding structure and the second bonding structure; Including, the first bonding structure includes a single first conductive bonding layer, the single first conductive bonding layer including a plurality of first bonding pads disposed within a first bonding dielectric, each of the plurality of first bonding pads directly contacting a top layer of the first conductive wire disposed within the first interconnect dielectric structure; the second bonding structure includes a single second conductive bonding layer, the single second conductive bonding layer including a plurality of second bonding contacts disposed in a second bonding dielectric, each of the plurality of second bonding contacts directly contacting a top layer of the second conductive wire disposed in the second interconnect dielectric structure; wherein each of the plurality of first bonding pads is in direct contact with one of the plurality of second bonding contacts. [Effects of the Invention]

[0010] By having at least one bonding structure having one or less conductive bonding layer, the number of conductive structures between stacked chips is reduced, thereby reducing the resistivity between the stacked chips and lowering the manufacturing cost of the stacked CMOS image sensor. [Brief explanation of the drawings]

[0011] Aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, according to standard practice in the industry, various features have not been drawn to scale. In fact, the dimensions of various features shown in the accompanying drawings may be arbitrarily increased or reduced for clarity of illustration.

[0012] [Figure 1A] 1A-1C illustrate various cross-sectional views of several embodiments of a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 1B] 1A-1C illustrate various cross-sectional views of several embodiments of a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 1C] 1A-1C illustrate various cross-sectional views of several embodiments of a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 2] 1C taken along line AA' of FIG. 1C. [Figure 3]1A-1D illustrate circuit diagrams of several embodiments of a stacked CMOS image sensor that includes an imaging chip stacked on a logic chip. [Figure 4] 1A-1C illustrate cross-sectional views of several embodiments of a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 5A] 1A-1C illustrate cross-sectional views of several embodiments of a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of each other. [Figure 5B] 5B illustrates cross-sectional views of some embodiments of regions of the stacked CMOS image sensor of FIG. 5A. [Figure 5C] 5B taken along line AA' of FIG. 5B. [Figure 5D] 5B taken along line AA' of FIG. 5B. [Figure 6A] 5B illustrates cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 5A. [Figure 6B] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 6C] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 6D] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 6E] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 6F] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 6G] 6B illustrates various layout diagrams of some embodiments of the stacked CMOS image sensor of FIG. 6A. [Figure 7A]5B illustrates cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 5A. [Figure 7B] 7B illustrates cross-sectional views of some embodiments of regions of the stacked CMOS image sensor of FIG. 7A. [Figure 7C] 7B taken along line AA' of FIG. 7B. [Figure 7D] 7B taken along line AA' of FIG. 7B. [Figure 8A] 7B-7C illustrate cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 7A. [Figure 8B] 8B illustrates cross-sectional views of some embodiments of regions of the stacked CMOS image sensor of FIG. 8A. [Figure 8C] 8B taken along line AA' of FIG. 8B. [Figure 8D] 8B taken along line AA' of FIG. 8B. [Figure 9A] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9B] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9C] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9D] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9E]5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9F] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9G] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 9H] 5A, 6A, 7A, and / or 8A depict cross-sectional views of several more detailed embodiments of the structure of one or more of the stacked CMOS image sensors of FIG. [Figure 10A] 5B-5C illustrate cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 5A. [Figure 10B] 10B-10C depict various top views of several embodiments of the cross-sectional view of FIG. 10A. [Figure 10C] 10B-10C depict various top views of several embodiments of the cross-sectional view of FIG. 10A. [Figure 11A] 5B illustrates cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 5A. [Figure 11B] 11B-11C depict various top views of several embodiments of the cross-sectional view of FIG. 11A. [Figure 11C] 11B-11C depict various top views of several embodiments of the cross-sectional view of FIG. 11A. [Figure 12A] 10B illustrates various cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 10A. [Figure 12B] 10B illustrates various cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 10A. [Figure 12C]10B illustrates various cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 10A. [Figure 12D] 10B illustrates various cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 10A. [Figure 12E] 10B illustrates various cross-sectional views of several embodiments of a stacked CMOS image sensor corresponding to several other embodiments of the stacked CMOS image sensor of FIG. 10A. [Figure 13A] 5A, 6A, 7A, 8A, 10A, and / or 12A-12E show circuit diagrams of several embodiments of stacked CMOS image sensors corresponding to several embodiments of the stacked CMOS image sensors of FIGS. [Figure 13B] 11B illustrates circuit diagrams of some embodiments of stacked CMOS image sensors corresponding to some embodiments of the stacked CMOS image sensor of FIG. 11A. [Figure 14] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 15] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 16] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 17] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 18]1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 19] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 20] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 21] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 22] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 23] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 24] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 25] 1A-1D depict various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 26] 1 illustrates a flow diagram according to some embodiments of a method for forming a stacked CMOS image sensor that includes an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. [Figure 27]1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 28] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 29] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 30] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 31] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 32] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 33] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 34] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 35] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 36]1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 37] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 38] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 39] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 40] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 41] 1A-1D illustrate various cross-sectional views of several embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. [Figure 42] 1 illustrates a flow diagram according to some embodiments of a method for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention provides many different embodiments or examples for implementing different features of the present invention. To simplify the present invention, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact with each other, or may include an embodiment in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact with each other. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations referenced.

[0014] Additionally, spatially relative terms such as "below," "lower," "bottom," "upper," "top," etc. may be used to facilitate the description to explain the relationship of one element or feature depicted in the figures to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] A stacked complementary metal-oxide semiconductor (CMOS) image sensor may include a stacked imaging chip and a logic chip. The imaging chip includes a plurality of pixel sensors, each including a light-receiving element, and the logic chip includes a plurality of logic elements configured as an application-specific integrated circuit (ASIC). The light-receiving elements are configured to accumulate charge in response to incident radiation. The plurality of pixel elements may be provided on the imaging chip and configured to facilitate reading of the accumulated charge. The imaging chip includes an imaging junction structure, and the logic chip includes a logic junction structure, where the imaging junction structure and the logic junction structure face each other at a junction interface. Furthermore, the imaging chip and the logic chip each include an interconnect structure provided on a corresponding substrate. The interconnect structures of the imaging chip and the logic chip are coupled to the imaging junction structure and the logic junction structure.

[0016] The plurality of logic elements of the logic chip and the plurality of pixel elements of the imaging chip are electrically coupled to each other by the imaging junction structure and the logic junction structure. The imaging junction structure and the logic junction structure each include a conductive bonding layer configured to promote good electrical connection and good bonding adhesion between the logic chip and the imaging chip. However, typically, the imaging junction structure and the logic junction structure each include two or more conductive junction structures. For example, the imaging junction structure and the logic junction structure each include a bond wire disposed on a bond via. Having two or more conductive junction structures in each junction structure may increase the resistivity between the imaging chip and the logic chip and / or increase the manufacturing cost of the stacked CMOS image sensor.

[0017] To increase the number of pixel sensors provided on the imaging chip, the stacked CMOS image sensor may further include a pixel element chip provided between the imaging chip and the logic chip. In such an embodiment, multiple pixel elements are moved from the imaging chip to the pixel element chip, thereby increasing the number of light-receiving elements provided on the imaging chip and / or improving the performance of the light-receiving elements (e.g., by reducing dark current, electrical crosstalk, etc.). The pixel element chip may include an interconnect structure and a pixel element junction structure provided on the interconnect structure and facing the logic junction structure at a junction interface. Furthermore, the interconnect structure of the pixel element chip may include one or more large conductive contacts extending continuously from the interconnect structure of the pixel element chip to a doped region (e.g., a floating diffusion node) of the imaging chip. The one or more large conductive contacts may promote good electrical coupling between the pixel elements and the pixel sensors. For example, the one or more large conductive contacts may electrically couple a gate of a first pixel element (e.g., configured as a source follower transistor) of the pixel element chip to a corresponding first floating diffusion node of the imaging chip. While one or more large conductive contacts can facilitate good electrical coupling between the pixel element and the pixel sensor, the one or more large conductive contacts may be provided in the device region of the stacked CMOS image sensor (e.g., aligned with a corresponding floating diffusion node). The one or more large conductive contacts may occupy a relatively large area of ​​the device region, thereby increasing the distance between adjacent pixel sensors and reducing the ability to scale down device features. As a result, the design complexity of the stacked CMOS image sensor increases and the area available for multiple pixel sensors decreases, thereby increasing manufacturing costs and reducing device density.

[0018] Various embodiments of the present invention are directed to a stacked CMOS image sensor including a junction structure between stacked chips. The stacked CMOS image sensor includes an imaging chip stacked with a logic chip. The imaging chip includes a plurality of light receiving elements disposed on an imaging substrate, an interconnect structure on the imaging substrate, and an imaging junction structure on the interconnect structure. The logic chip includes a plurality of logic elements disposed on the logic substrate, an interconnect structure on the logic substrate, and a logic junction structure on the interconnect structure. A junction interface is provided between the imaging junction structure and the logic junction structure. Furthermore, at least one of the imaging junction structure and / or the logic junction structure includes one or less conductive junction layers. For example, the imaging junction structure includes a single layer of imaging junction pads, and the logic junction structure includes logic junction pads disposed on logic junction contacts. By having at least one junction structure include one or less conductive junction layers, the number of conductive structures between the stacked chips is reduced, thereby reducing the resistivity between the stacked chips and lowering the manufacturing cost of the stacked CMOS image sensor.

[0019] The stacked CMOS image sensor further includes a pixel element chip disposed between the imaging chip and the logic chip. The pixel element chip includes a plurality of pixel elements disposed on a pixel element substrate, a first pixel element bonding structure disposed on a front side of the pixel element substrate, and a second pixel element bonding structure disposed on a back side of the pixel element substrate. The first pixel element bonding structure faces the imaging junction structure at a first bonding interface, and the second pixel element bonding structure faces the logic junction structure at a second bonding interface. At least one of the first pixel element bonding structure and / or the second pixel element bonding structure includes one or less conductive bonding layers, thereby reducing the number of conductive structures in the stacked CMOS image sensor. The pixel element chip further includes a plurality of through-substrate vias (TSVs) extending through the pixel element substrate and disposed in a peripheral region laterally offset from the pixel elements. The TSVs electrically connect the first pixel element bonding structure to the second pixel element bonding structure. By utilizing the first pixel element junction structure, the second pixel element junction structure, and the TSVs, one or more large conductive vias can be eliminated from the device area of ​​the stacked CMOS image sensor, resulting in increased area for multiple light receiving elements and reduced design complexity, which increases device density and reduces manufacturing costs.

[0020] FIG. 1A illustrates a cross-sectional view 100 a of some embodiments of a stacked CMOS image sensor including an imaging chip 102 with an imaging junction structure 118 stacked on a logic chip 104 with a logic junction structure 120 .

[0021] The logic chip 104 includes a logic substrate 108, a logic interconnect structure 112 disposed on the logic substrate 108, and a logic junction structure 120 disposed on the logic interconnect structure 112. Additionally, a plurality of logic elements 140 are disposed on a front side 108f of the logic substrate 108. In some embodiments, the logic elements 140 may refer to semiconductor elements, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), logic gates, flip-flops, and other suitable logic elements. The logic interconnect structure 112 includes an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The plurality of conductive vias 114 and the plurality of conductive wires 116 are disposed within the interconnect dielectric structure 113 and are configured to facilitate electrical connections between the logic elements 140 and other elements (e.g., in the imaging chip 102). The logic junction structure 120 is disposed on the logic interconnect structure 112.

[0022] The imaging chip 102 includes an imaging substrate 106, an imaging interconnect structure 110 provided on a front side 106f of the imaging substrate 106, and an imaging junction structure 118 provided on the imaging interconnect structure 110. The imaging substrate 106 includes a semiconductor body (e.g., single crystal silicon, CMOS bulk, silicon-germanium) and may have a first doping type (e.g., p-type). A plurality of photodetectors 132 are provided in the imaging substrate 106, and the photodetectors 132 may have a second doping type (e.g., n-type) opposite to the first doping type. A floating diffusion node 131 is provided in the imaging substrate 106 and may have a second doping type (e.g., n-type). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. A backside isolation structure 134 extends into the backside 106b of the imaging substrate 106 and is disposed between adjacent light-receiving elements 132. The backside isolation structure 134 includes a trench fill layer 138 and a liner layer 136 disposed between the imaging substrate 106 and the trench fill layer 138. A grid structure 144 is disposed on the backside 106b of the imaging substrate 106, and a plurality of optical filters 142 are disposed on the light-receiving elements 132. Furthermore, a plurality of microlenses 146 are disposed on the plurality of optical filters 142.

[0023] A plurality of pixel elements 129 and a plurality of transfer transistors 130 are provided on the front side 106f of the imaging substrate 106. Each of the pixel elements 129 and the transfer transistors 130 includes a gate electrode provided on the pixel substrate 106 and a gate dielectric layer provided between the gate electrode and the imaging substrate 106. In some embodiments, the transfer transistors 130 each include a protrusion extending from the front side 106f of the imaging substrate 106 toward a corresponding light-receiving element 132. The plurality of pixel elements 129 may include, for example, a reset transistor, a source follower transistor, a select transistor, etc. The light-receiving elements 132 are configured to absorb incident radiation (e.g., photons) and generate respective electrical signals corresponding to the incident radiation. For example, the light-receiving elements 132 may generate electron-hole pairs from the incident radiation. In some embodiments, the transfer transistors 130 are configured to control current flow between the floating diffusion nodes 131 and the corresponding light-receiving elements 132. For example, the transfer transistor 130 may be configured to selectively form a conductive channel in the imaging substrate 106 between the floating diffusion node 131 and an adjacent photosensitive element 132 to transfer the accumulated charge in the photosensitive element 132 to the floating diffusion node 131. The pixel element 129 is configured to read out the transferred accumulated charge from the floating diffusion node 131.

[0024] In some embodiments, the imaging junction structure 118 includes an imaging junction dielectric 122 and a plurality of imaging junction pads 126. In various embodiments, the logic junction structure 120 includes a logic junction dielectric 124, a plurality of logic junction pads 128, and a plurality of logic junction contacts 127. The imaging junction structure 118 faces the logic junction structure 120 at a junction interface 119, which may include a conductor-to-conductor junction, a dielectric-to-dielectric junction, etc. The imaging junction structure 118 and the logic junction structure 120 are configured to facilitate electrical connection between the logic element 140 and the pixel element 129 and / or the transfer transistor 130. In various embodiments, at least one of the imaging junction structure 118 and / or the logic junction structure 120 includes one or less conductive bonding layers. For example, the imaging junction structure 118 may include a single conductive bonding layer (e.g., the imaging bond pad 126), and the logic junction structure 120 may include at least two conductive bonding layers (e.g., the logic bond pad 128 and the logic junction contacts 127). By including no more than one conductive bonding layer in at least one of the imaging junction structure 118 and / or the logic junction structure 120, the conductive structures between elements of the logic chip 104 and the imaging chip 102 are reduced, thereby reducing the resistivity and RC delay between the stacked chips. Furthermore, having fewer conductive wiring structures facilitates reducing the size and / or spacing between conductive features in the stacked chips, which can improve the performance of the stacked CMOS image sensor as device features are scaled down.

[0025] 1B illustrates a cross-sectional view 100b of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 1A, in which the logic junction structures 120 include a single conductive bonding layer (e.g., multiple logic junction contacts 127). Thus, in some embodiments, the logic junction structures 120 and the imaging junction structures 118 each include a single conductive bonding layer, thereby further reducing resistivity and RC delay between stacked chips. In such embodiments, the multiple imaging bond pads 126 face the logic junction contacts 127 at bonding interfaces 119, and conductor-to-conductor junctions exist at bonding interfaces 119 between the imaging bond pads 126 and the logic junction contacts 127. In various embodiments, the width of the imaging bond pads 126 is wider than the width of the corresponding logic junction contacts 127, and at least a portion of the underside of the imaging bond pads 126 directly contacts the logic junction dielectric 124.

[0026] FIG. 1C illustrates a cross-sectional view 100c of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 1A, omitting the imaging junction structure (118 in FIG. 1A). In various embodiments, the imaging interconnect structure 110 includes a top layer 116t of conductive wires that is part of the plurality of conductive wires 116. The top layer 116t of conductive wires of the imaging interconnect structure 110 is defined as the layer of conductive wires in the imaging interconnect structure 110 that has the longest distance from the front side 106f of the imaging substrate 106. In various embodiments, the logic junction contact 127 of the logic junction structure 120 directly contacts the top layer 116t of conductive wires of the imaging interconnect structure 110, thereby further reducing resistivity and RC delay between stacked chips. Thus, the logic junction contact 127 faces the top layer 116t of conductive wires at the junction interface 119. Additionally, the interconnect dielectric structure 113 of the imaging interconnect structure 110 directly contacts the logic junction dielectric 124. The logic junction structure 120 directly contacting the top layer 116t of conductive wires of the imaging interconnect structure 110 improves the performance of stacked CMOS image sensors while increasing device miniaturization and reducing design complexity.

[0027] In some embodiments, the imaging chip 102 includes a first pixel element 129a, a second pixel element 129b, and a third pixel element 129c disposed on a front side 106f of the imaging substrate 106. A plurality of transfer transistors 130 may be disposed laterally between a floating diffusion node 131 and the first pixel element 129a to the third pixel element 129c.

[0028] Figure 2 depicts a top view 200 of some embodiments of the stacked CMOS image sensor of Figure 1C taken along line A-A' of Figure 1C. It should be understood that for ease of illustration, the interconnect dielectric structure (113 in Figure 1C) and the plurality of conductive vias (114 in Figure 1C) of the imaging interconnect structure (110 in Figure 1C) have been omitted from top view 200 of Figure 2.

[0029] As shown in FIG. 2, a floating diffusion node 131 is provided at the intersection of adjacent light receiving elements 132. A transfer transistor 130 is located directly above the corresponding light receiving element 132. The first through third pixel elements 129a through 129c are laterally offset from the light receiving element 132 and include a plurality of source / drain regions 204 located on opposite sides of the respective gate electrodes. In some embodiments, the first pixel element 129a is configured as a reset transistor, the second pixel element 129b is configured as a select transistor, and may include a first source / drain region 204a directly electrically coupled to a logic element (e.g., 140 in FIG. 1C) of a logic chip (104 in FIG. 1C), and the third pixel element 129c is configured as a source follower transistor. In various embodiments, a well region 202 is laterally adjacent to the first pixel element 129a. The well region 202 may have a first doping type (e.g., p-type).

[0030] 3 illustrates a circuit diagram 300 of some embodiments of a stacked CMOS image sensor. In various embodiments, the circuit diagram 300 can correspond to some embodiments of the stacked CMOS image sensor of FIGS. 1A-1C.

[0031] The stacked CMOS image sensor includes an imaging chip 102 electrically coupled to a logic chip 104. In various embodiments, the imaging chip 102 includes a light receiving element 132, a first pixel element 129a, a second pixel element 129b, and a third pixel element 129c. The logic chip 104 includes an ASIC circuit 302. In some embodiments, the imaging chip 102 is configured to read out the light receiving elements 132, such that charge accumulated by the light receiving elements 132 from incident radiation can be read out as a corresponding electrical signal. The electrical signal may be provided to the ASIC circuit 302 for downstream signal processing. For example, the ASIC circuit 302 may be configured to perform analog-to-digital conversion (ADC), image processing, buffering, etc., or any combination thereof.

[0032] In some embodiments, the photosensitive element 132 is coupled between ground and a first source / drain region of the transfer transistor 130. The transfer transistor 130 is configured to be gated by a transfer signal TX and to selectively transfer charge accumulated in the photosensitive element 132 to the floating diffusion node 131. The first pixel element 129a may be configured as a reset transistor and is coupled between the floating diffusion node 131 and a reset voltage Vrst. The first pixel element 129a is configured to be gated by a reset signal RST and to selectively electrically couple the floating diffusion node 131 to the reset voltage Vrst for resetting the floating diffusion node 131 to the reset voltage Vrst. Furthermore, the first pixel element 129a may be configured in cooperation with the transfer transistor 130 to selectively electrically couple the photosensitive element 132 to the reset voltage Vrst.

[0033] The third pixel element 129c may be configured as a source follower transistor and is gated by the charge at the floating diffusion node 131. For example, the gate of the source follower transistor is electrically coupled to the floating diffusion node 131 and / or the source / drain region of the first pixel element 129a. The third pixel element 129c is coupled between a supply voltage Vdd and the source / drain region of the second pixel element 129b. The second pixel element 129b is configured as a select transistor. The third pixel element 129c is configured to buffer and / or amplify the voltage at the floating diffusion node 131 for readout. The second pixel element 129b is configured to selectively pass the buffered and / or amplified voltage from the third pixel element 129c to an output of the imaging chip 102.

[0034] FIG. 4 illustrates a cross-sectional view 400 of some embodiments of a stacked CMOS image sensor including an imaging chip 102 with an imaging junction structure 118 stacked on a logic chip 104 with a logic junction structure 120 .

[0035] The logic chip 104 includes a logic substrate 108, a logic interconnect structure 112, and a logic junction structure 120. A plurality of logic elements 140 are disposed on a front side 108f of the logic substrate 108. In various embodiments, each logic element 140 includes a gate electrode above a gate dielectric, a plurality of source / drain regions disposed on opposite sides of the gate electrode, and a well region disposed in the logic substrate 108. Additionally, first isolation structures 402 are disposed within the logic substrate 108 and configured to electrically isolate the logic elements 140 from one another. The first isolation structures 402 may be configured as shallow trench isolation (STI) structures and may be or include silicon dioxide, silicon nitride, silicon carbide, other dielectric materials, or any combination thereof.

[0036] The imaging chip 102 includes an imaging substrate 106, an imaging interconnect structure 110, and an imaging junction structure 118. The logic substrate 108 and the imaging substrate 106 may each be or include, for example, silicon, single crystal silicon, CMOS bulk, silicon-germanium, epitaxial silicon, silicon-on-insulator (SOI) substrate, or other suitable types of semiconductor substrates. The imaging interconnect structure 110 and the logic interconnect structure 112 each include an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The interconnect dielectric structure 113 may each include multiple dielectric layers, for example, or including, silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, other suitable dielectric materials, or any combination thereof. As used herein, a low-k dielectric material is a dielectric having a dielectric constant less than about 3.9. The conductive vias 114 and conductive wires 116 may be or include, for example, copper, aluminum, titanium nitride, tantalum nitride, tungsten, ruthenium, other suitable conductive materials, or any combination thereof.

[0037] A plurality of light receiving elements 132 are provided in the imaging substrate 106. The light receiving elements 132 may be arranged in an array consisting of a plurality of columns and rows of light receiving elements 132. A plurality of pixel elements 129 (e.g., reset transistors, select transistors, source follower transistors, etc.) and a plurality of transfer transistors 130 are provided on the front side 106f of the imaging substrate 106. Each transfer transistor in the plurality of transfer transistors 130 is aligned with a corresponding light receiving element in the plurality of light receiving elements 132. Each of the pixel elements 129 and the transfer transistor 130 includes a gate electrode provided on the front side 106f of the imaging substrate 106 and a gate dielectric provided between the gate electrode and the imaging substrate 106.

[0038] The backside isolation structure 134 extends into the backside 106b of the imaging substrate 106. The backside isolation structure 134 may include a trench fill layer (e.g., 138 in FIG. 1A ) and a liner layer (e.g., 136 in FIG. 1A ) disposed between the imaging substrate 106 and the trench fill layer. In some other embodiments, the trench fill layer may be or include, for example, a conductive material (e.g., copper, aluminum, tungsten, etc.), a dielectric material (e.g., aluminum oxide, silicon dioxide, silicon nitride, silicon carbide, etc.), or other suitable material. In various embodiments, the liner layer may be or include, for example, a high-k dielectric material, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, other suitable dielectric material, or any combination thereof. As used herein, a high-k dielectric material is a dielectric having a dielectric constant greater than about 3.9. The backside isolation structure 134 may have a grid structure in a top view and laterally surrounds each light-receiving element in the plurality of light-receiving elements 132. The backside isolation structure 134 is configured to enhance electrical and / or optical isolation between adjacent light-receiving elements 132.

[0039] Additionally, an upper dielectric layer 408 is provided along the backside 106b of the imaging substrate 106. The upper dielectric layer 408 may be configured as a passivation layer. The upper dielectric layer 408 may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, etc. A grid structure 144 is provided on the upper dielectric layer 408 and includes sidewalls that define a plurality of openings overlying the light-receiving elements 132. In various embodiments, the grid structure 144 may include a metallic material (e.g., copper, tungsten, aluminum, etc.) and / or a dielectric material (e.g., silicon nitride, silicon carbide, metal oxide, etc.) and is configured to reduce crosstalk between adjacent light-receiving elements 132. An upper dielectric structure 410 is provided on the grid structure 144 and fills the openings defined by the sidewalls of the grid structure 144. A plurality of optical filters 142 are provided above the upper dielectric structure 410. In various embodiments, each optical filter 142 includes a material configured to pass a first range of wavelengths while blocking a second range of wavelengths. A plurality of microlenses 146 are provided on the optical filters 142 and configured to direct incident light to the underlying photodetectors 132.

[0040] A plurality of top bond pads 406 extend into the backside 106b of the imaging substrate 106 toward the imaging interconnect structure 110. The top bond pads 406 may comprise, for example, aluminum, copper, tungsten, etc. The top bond pads 406 are provided in a peripheral region of the imaging substrate 106. The photodetector elements 132 are provided in a device region of the imaging substrate 106, and the peripheral region of the imaging substrate 106 laterally surrounds the device region. The top bond pads 406 are configured to provide electrical connections to elements of the stacked CMOS image sensor (e.g., pixel elements 129, transfer transistors 130, logic elements 140, etc.) and other integrated circuit (IC) elements (not shown). Second isolation structures 404 are provided in the imaging substrate 106. The second isolation structures 404 may be configured as shallow trench isolation (STI) structures and may be or include, for example, silicon dioxide, silicon nitride, silicon carbide, etc. The second isolation structure 404 may be provided along the sidewall of the upper bond pad 406 and is configured to increase electrical isolation between the upper bond pad 406 and other elements (e.g., pixel element 129, transfer transistor 130, photodetector element 132) provided on and / or within the imaging substrate 106.

[0041] In some embodiments, imaging junction structure 118 includes imaging junction dielectric 122 and a plurality of imaging junction pads 126. In various embodiments, logic junction structure 120 includes logic junction dielectric 124, a plurality of logic junction pads 128, and a plurality of logic junction contacts 127. Imaging junction structure 118 faces logic junction structure 120 at junction interface 119, which may include a conductor-to-conductor junction, a dielectric-to-dielectric junction, etc. Imaging junction dielectric 122 and logic junction dielectric 124 may each have one or more dielectric layers, which may include, for example, an oxide (e.g., silicon dioxide), silicon nitride, silicon carbide, silicon oxynitride, etc. Imaging bond pad 126, logic junction contact 127, and logic junction pad 128 may each be or include, for example, copper, tungsten, titanium, tantalum, other conductive material, or any combination thereof. In various embodiments, the imaging junction structure 118 includes a single layer of conductive junction structures (e.g., imaging junction pads 126), thereby reducing the number of conductive structures between the logic chip 104 and the imaging chip 102. As a result, the resistivity and RC delay between the logic chip 104 and the imaging chip 102 are reduced, thereby increasing the performance of the stacked CMOS image sensor while reducing design cost and complexity.

[0042] FIG. 5A illustrates a cross-sectional view 500a of some embodiments of a stacked CMOS image sensor including an imaging chip 102, a pixel element chip 502, and a logic chip 104 stacked vertically on top of one another.

[0043] The logic chip 104 includes a logic substrate 108, a logic interconnect structure 112, and a logic junction structure 120. A plurality of logic elements 140 are provided on a front side 108f of the logic substrate 108. The logic junction structure 120 is provided on the logic interconnect structure 112 and is electrically coupled to the logic junction structure 112.

[0044] The imaging chip 102 includes an imaging substrate 106, an imaging interconnect structure 110, and an imaging junction structure 118. The imaging junction structure 118 is disposed on the imaging interconnect structure 110 and is electrically coupled to the imaging interconnect structure 110. The imaging substrate 106 may have a first doping type (e.g., p-type). A plurality of photo-receiving elements 132 are disposed on the imaging substrate 106, and the photo-receiving elements 132 may have a second doping type (e.g., n-type) opposite to the first doping type. A floating diffusion node 131 is disposed on the imaging substrate 106 and may have a second doping type (e.g., n-type). A plurality of well regions 503 are disposed in the substrate opposite the floating diffusion node 131 and have a first doping type (e.g., p-type).

[0045] A backside isolation structure 134 extends into the backside 106b of the imaging substrate 106. The backside isolation structure 134 includes a trench fill layer 138 and a liner layer disposed between the imaging substrate 106 and the trench fill layer. A grid structure 144 is disposed on the backside 106b of the imaging substrate 106, and a plurality of optical filters 142 are disposed on the photo-sensitive elements 132. A plurality of microlenses 146 are disposed on the plurality of optical filters 142. Furthermore, a plurality of transfer transistors 130 are disposed on the front side 106f of the imaging substrate 106, and the transfer transistors 130 are configured to control current flow between the floating diffusion nodes 131 and corresponding photo-sensitive elements 132.

[0046] A pixel element chip 502 is disposed between the imaging chip 102 and the logic chip 104. In some embodiments, the pixel element chip 502 includes a pixel element substrate 504, a pixel element interconnect structure 506, a first pixel element junction structure 510, and a second pixel element junction structure 516. A plurality of pixel elements 129 are disposed on a front side 504f of the pixel element substrate 504. In various embodiments, the plurality of pixel elements 129 may include, for example, reset transistors, source follower transistors, select transistors, etc., and are configured to read out accumulated charge from the light-receiving elements 132. By disposing the pixel elements 129 on the pixel element substrate 504 rather than, for example, the imaging chip 102, an area for the light-receiving elements 132 is increased and electrical crosstalk across the imaging chip 102 is reduced. As a result, the number of light-receiving elements 132 provided in the stacked CMOS image sensor can be increased and / or the performance of the stacked CMOS image sensor is improved (e.g., by reducing dark current and electrical crosstalk).

[0047] A plurality of through-substrate vias (TSVs) 508 are provided in the pixel element chip 502. The TSVs 508 extend through the pixel element substrate 504 from the second pixel element bonding structure 516 to the pixel element interconnect structure 506. The TSVs 508 are configured to electrically couple the second pixel element bonding structure 516 to the pixel element interconnect structure 506. In various embodiments, the pixel elements 129 are provided in a device region (i.e., a central region) of the pixel element substrate 504, and the TVSs 508 are provided in a peripheral region of the pixel element substrate 504 that laterally surrounds the device region. By providing the TSVs 508 in the peripheral region of the pixel element substrate 504 and away from the device region, an area for the pixel elements 129 is increased, thereby increasing the device density of the pixel element chip 502.

[0048] In various embodiments, the imaging interconnect structure 110, the logic interconnect structure 112, and the pixel element interconnect structure 506 each include an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The imaging interconnect structure 110 includes a top layer of conductive wires 116t and a first layer of conductive wires 116a. The top layer of conductive wires 116t of the imaging interconnect structure 110 is defined as the layer of conductive wires in the imaging interconnect structure 110 that has the longest distance from the front side 106f of the imaging substrate 106. The first layer of conductive wires 116a of the imaging interconnect structure 110 is defined as the layer of conductive wires in the imaging interconnect structure 110 that has the shortest distance from the front side 106f of the imaging substrate 106. While each interconnect structure 110, 112, 506 in FIG. 5A includes two layers of conductive wires 116 and two layers of conductive vias 114, it should be understood that this is a non-limiting example and that each interconnect structure 110, 112, 506 may include any number of layers of conductive wires 116 and / or conductive vias 114.

[0049] A first pixel element bonding structure 510 is provided on the pixel element interconnect structure 506 and is configured to electrically couple the imaging chip 102 to the pixel element chip 502 and / or the logic chip 104. A second pixel element bonding structure 516 is provided on the back side 504b of the pixel element substrate 504 and is configured to electrically couple the pixel element chip 502 to the logic chip 104.

[0050] In some embodiments, the imaging junction structure 118 includes an imaging junction dielectric 122, a plurality of imaging junction pads 126, and a plurality of imaging junction contacts 125. In various embodiments, the first pixel element junction structure 510 includes a first pixel element junction dielectric 512 and a plurality of first pixel element junction contacts 514. The imaging junction structure 118 faces the first pixel element junction structure 510 at a first junction interface, thereby defining a first bonded structure 522, where the first junction interface includes a conductor-to-conductor junction and a dielectric-to-dielectric junction. The imaging junction structure 118 and the first pixel element junction structure 510 are configured to promote good electrical connection between the imaging chip 102 and the pixel element chip 502. In some embodiments, at least one of the imaging junction structure 118 and / or the first pixel element junction structure 510 has less than one conductive junction layer. For example, the first pixel element junction structure 510 may include a single conductive junction layer (e.g., the first pixel element junction contact 514). By having at least one of the imaging junction structure 118 and / or the first pixel element junction structure 510 have one or less conductive bonding layers, the number of conductive structures between the elements of the imaging chip 102 and the pixel element chip 502 is reduced, thereby lowering the resistivity and RC delay between the stacked chips. Furthermore, having fewer conductive structures between the imaging chip 102 and the pixel element chip 502 facilitates reducing the size and / or spacing between conductive features in the stacked chips, thereby improving the performance of the stacked CMOS image sensor while facilitating device miniaturization and reduced manufacturing costs. In addition, the first pixel element junction contact 514 is directly electrically coupled to the floating diffusion node 131 of the imaging chip 102 in region 526 of the stacked CMOS image sensor.

[0051] In a further embodiment, the logic junction structure 120 includes a logic junction dielectric 124, a plurality of logic junction pads 128, and a plurality of logic junction contacts 127. In yet a further embodiment, the second pixel element junction structure 516 includes a second pixel element junction dielectric 518 and a plurality of second pixel element junction contacts 520. The logic junction structure 120 faces the second pixel element junction structure 516 at a second junction interface, thereby defining a second bonded structure 524, the second junction interface including a conductor-to-conductor junction and a dielectric-to-dielectric junction. The logic junction structure 120 and the second pixel element junction structure 516 are configured to facilitate good electrical connection between the logic chip 104 and the pixel element chip 502. In some embodiments, at least one of the logic junction structure 120 and / or the second pixel element junction structure 516 has one or less conductive junction structures. For example, the second pixel element junction structure 516 includes a single conductive junction layer (e.g., the second pixel element junction contact 520). By having at least one of the logic junction structure 120 and / or the second pixel element junction structure 516 have one or less conductive junction structure, the number of conductive structures between elements of the logic chip 104 and the pixel element chip 502 is reduced, thereby reducing the resistivity and RC delay between the stacked chips. Furthermore, having fewer conductive structures between the imaging chip 102 and the pixel element chip 502 facilitates reducing the size and / or spacing between conductive features in the stacked chips, thereby further enhancing the performance of the stacked CMOS image sensor while facilitating device scaling and reducing manufacturing costs.

[0052] Figure 5B illustrates a cross-sectional view 500b of some embodiments of a region of the stacked CMOS image sensor of Figure 5 A. In some embodiments, cross-sectional view 500b of Figure 5B corresponds to the region (526 in Figure 5A) of the stacked CMOS image sensor, which region (526 in Figure 5A) is inverted in Figure 5B for ease of illustration.

[0053] As shown in FIG. 5B , the imaging interconnect structure 110 includes a first top wire 530 disposed between two adjacent top wires. The first top wire 530 has a width 531, which may be, for example, about 0.25 micrometers (um), in a range of about 0.2 um to about 0.3 um, or other suitable value. The first top wire 530 is separated from the two adjacent top wires by a first distance d1. In some embodiments, the first distance d1 is about 0.27 um, in a range of about 0.25 um to about 0.29 um, or other suitable value. In further embodiments, the width 531 of the top wire 530 is less than the first distance d1.

[0054] The imaging junction structure 118 includes a first imaging junction contact 125a and a first imaging junction pad 126a. The first imaging junction contact 125a has a width 532, and the first imaging junction pad 126a has a width 534. In further embodiments, the width 532 is about 0.2 um, in a range of about 0.15 um to about 0.25 um, or other suitable values. In still further embodiments, the width 534 is about 0.3 um, about 0.4 um, in a range of about 0.3 um to about 0.4 um, or other suitable values. The first pixel element junction structure 510 includes a first junction contact 514a having a width 536. In various embodiments, the width 536 is about 0.1 um, in a range of about 0.075 um to about 1.25 um, or other suitable values. In some embodiments, the height of the first junction contact 514a is greater than the height of the first imaging junction contact 125a. In further embodiments, the height of the first bond contact 514a may be equal to the height of the imaging bond structure 118. In various embodiments, the width 536 of the first bond contact 514a is less than the width 532 of the first imaging bond contact 125a.

[0055] The pixel element interconnect structure 506 includes a first top wire 538 disposed between a first pair of top wires 542 and a second pair of top wires 544. The width 540 of the first top wire 538 may be, for example, about 0.15 um, in a range of about 0.1 um to about 0.2 um, or other suitable value. Thus, in some embodiments, the width 540 of the first top wire 538 of the pixel element interconnect structure 506 is less than the width 531 of the first top wire 530 of the imaging interconnect structure 110. The first top wire 538 is separated from the first pair of top wires 542 by a second distance d2, and the first pair of top wires 542 are separated from the second pair of top wires 544 by a third distance d3. In various embodiments, the second distance d2 is about 0.15 um, in a range of about 0.1 um to about 0.2 um, or other suitable value. The third distance d3 is about 0.1 um, in the range of about 0.075 um to about 1.25 um, or other suitable value. By having at least one of the imaging junction structure 118 and / or the first pixel element junction structure 510 have one or less conductive bonding layers, the width and / or distance between conductive routing features in the imaging chip 102 and the pixel element chip 502 can be relatively small and / or reduced. This enhances the performance of the stacked CMOS image sensor (e.g., by reducing the RC delay in the imaging chip 102 and / or the pixel element chip 502) while facilitating device scaling and reduced manufacturing costs.

[0056] FIG. 5C illustrates a top view 500c of some embodiments of the cross-section 500b taken along line AA' of FIG. 5B, where each of the first imaging bond pads 126a and first imaging bond contacts 125a exhibits a circular shape in the top view.

[0057] FIG. 5D illustrates a top view 500d of some embodiments of the cross-section 500b taken along line AA' of FIG. 5B, where each of the first imaging bond pads 126a and first imaging bond contacts 125a exhibits a rectangular shape in top view.

[0058] 6A illustrates a cross-sectional view 600a of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 5A , where the first pixel element junction structure 510 and the second pixel element junction structure 516 each include two conductive bonding layers, and the imaging junction structure 118 and the logic junction structure 120 each include at least one conductive bonding layer. In various embodiments, the first pixel element junction structure 510 includes a first pixel element junction dielectric 512, a plurality of first pixel element junction contacts 514, and a plurality of first pixel element junction pads 515. In some embodiments, the imaging junction structure 118 includes an imaging junction dielectric 122 and a plurality of imaging junction contacts 125. In further embodiments, the second pixel element junction structure 516 includes a second pixel element junction dielectric 518, a plurality of second pixel element junction contacts 520, and a plurality of second pixel element junction pads 521. In yet a further embodiment, the logic junction structure 120 includes a logic junction dielectric 124 and a plurality of logic junction contacts 127 .

[0059] The pixel element interconnect structure 506 includes a top layer conductive wire 116t, which is the layer of conductive wires in the pixel element interconnect structure 506 that has the longest distance from the front side 504f of the pixel element substrate 504. In various embodiments, the first pixel element bond contact 514 directly contacts the top layer conductive wire 116t of the pixel element interconnect structure 506. Furthermore, the pixel element interconnect structure 506 includes a first layer conductive wire 116a that is disposed between the top layer conductive wire 116t of the pixel element interconnect structure 506 and the pixel element substrate 504. In various embodiments, the plurality of pixel elements 129 includes a first pixel element 129a, a second pixel element 129b, and a third pixel element 129c. In some embodiments, the first pixel element 129a is configured as a reset transistor, the second pixel element 129b is configured as a select transistor, and the third pixel element 129c is configured as a source follower transistor.

[0060] Figure 6B shows a layout diagram 600b of some embodiments of the cross-sectional diagram 600a of Figure 6A taken along line 602 of Figure 6A. The layout diagram 600b of Figure 6B shows some embodiments of the layout of the shared pixel structure 614 of the imaging chip (102 of Figure 6A).

[0061] In some embodiments, the shared pixel structure 614 includes a floating diffusion node 131 disposed at the center of four adjacent light receiving elements 132 and a well region disposed on the opposite side of the floating diffusion node 131. In various embodiments, the pitch P of the shared pixel structures 614 is about 0.86 μm, in a range of about 0.8 μm to about 0.9 μm, or other suitable values. In further embodiments, the distance ds between laterally adjacent transfer transistors 130 in the shared pixel structure 614 is about 0.11 μm, in a range of about 0.09 μm to about 0.13 μm, or other suitable values. In still further embodiments, the distance dd between diagonally separated transfer transistors 130 in the shared pixel structure 614 is about 0.26 μm, in a range of about 0.2 μm to about 0.32 μm, or other suitable values. In some embodiments, the width 616 of each conductive via 114 is about 0.06 μm, in a range of about 0.04 μm to about 0.08 μm, or other suitable values.

[0062] Figure 6C shows a layout view 600c of some embodiments of the cross-sectional view 600a of Figure 6A taken along line 604 in Figure 6A. The layout view 600c in Figure 6C shows some embodiments of the layout of the first layer conductive wires 116a of the imaging interconnect structure (110 in Figure 6A) above the shared pixel structure 614.

[0063] In some embodiments, the width 618 of each conductive wire in the first layer 116a of conductive wires is about 0.07 um, in a range of about 0.05 um to about 0.09 um, or other suitable value. In various embodiments, the distance 620 between adjacent conductive wires in the first layer 116a of conductive wires of the imaging interconnect structure (110 in FIG. 6A) is about 0.1 um, about 0.105 um, in a range of about 0.08 um to about 0.12 um, or other suitable value.

[0064] Figure 6D shows a layout view 600d of some embodiments of the cross-sectional view 600a of Figure 6A taken along line 606 in Figure 6A. The layout view 600d in Figure 6D shows some embodiments of the layout of the conductive wires 116t of the top layer of the imaging interconnect structure (110 in Figure 6A) above the shared pixel structure 614.

[0065] In some embodiments, the length L1 and width Wt of the central top layer 116tm of conductive wires of the imaging interconnect structure (110 of FIG. 6A) are each about 0.45 um, about 0.4 um to about 0.5 um, or other suitable values. The central top layer conductive wires 116tm are directly above the floating diffusion node 131. In various embodiments, the distance 622 between adjacent top conductive wires in the top layer conductive wires 166t of the imaging interconnect structure (110 of FIG. 6A) is about 0.17 um, about 0.12 um to about 0.22 um, or other suitable values.

[0066] Figure 6E shows a layout diagram 600e of some embodiments of the cross-sectional view 600a of Figure 6A taken along line 608 in Figure 6A. The layout diagram 600e in Figure 6E shows some embodiments of the layout of a plurality of pixel elements 129 of a pixel element chip (502 in Figure 6A).

[0067] The plurality of pixel elements 129 includes a plurality of source / drain regions 624 disposed in the pixel element substrate 504. Additionally, a well region 626 may be disposed in the pixel element substrate 504 and electrically coupled to a reference voltage (e.g., ground). In some embodiments, a distance 628 between the well region 626 and adjacent source / drain regions 624 of adjacent pixel elements in the plurality of pixel elements 129 is about 0.1 um, in a range of about 0.08 um to about 0.12 um, or other suitable value. In further embodiments, a distance 630 between the source / drain regions 624 of adjacent pixel elements in the plurality of pixel elements 129 is about 0.12 um, in a range of about 0.1 um to about 0.14 um, or other suitable value. In still further embodiments, a distance 632 between the source / drain region 624 of a pixel element in the plurality of pixel elements 129 and an adjacent gate electrode of the third pixel element 129c is about 0.09 um, in a range of about 0.08 um to about 0.1 um, or other suitable value.

[0068] Figure 6F shows a layout view 600f of some embodiments of the cross-sectional view 600a of Figure 6A taken along line 610 in Figure 6A. The layout view 600f of Figure 6F shows some embodiments of the layout of the first layer conductive wires 116a of the pixel element interconnect structure (506 in Figure 6A) above the plurality of pixel elements 129.

[0069] In various embodiments, the distance 634 between adjacent conductive wires in the first layer of conductive wires 116a of the pixel element interconnect structure (506 in FIG. 6A) is about 0.07 um, about 0.08 um, in the range of about 0.06 um to about 0.18 um, or other suitable value.

[0070] Figure 6G shows a layout view 600g of some embodiments of the cross-sectional view 600a of Figure 6A taken along line 612 of Figure 6A. The layout view 600g of Figure 6G shows some embodiments of the layout of the top layer conductive wires 116t of the pixel element interconnect structure (506 of Figure 6A) above the plurality of pixel elements 129.

[0071] In some embodiments, the length and width of the conductive wires 116t in the top layer of the pixel element interconnect structure (506 in FIG. 6A ) are each about 0.25 μm, about 0.2 μm to about 0.3 μm, or other suitable values. The center of the central top conductive wire 116tm in the pixel element interconnect structure (506 in FIG. 6A ) may be laterally aligned with the center of the central top conductive wire (116tm in FIG. 6D ) in the imaging interconnect structure (110 in FIG. 6A ). In various embodiments, the distance 636 between adjacent top conductive wires in the top layer of conductive wires 116t in the pixel element interconnect structure (506 in FIG. 6A ) is about 0.1 μm, about 0.08 μm to about 0.12 μm, or other suitable values.

[0072] 7A illustrates a cross-sectional view 700a of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 5A , in which the imaging junction structure 118 and the logic junction structure 120 each include at least one conductive bonding layer (e.g., the imaging junction contact 125 of FIG. 5A and the logic junction contact 127 of FIG. 5A are omitted). In some embodiments, the logic junction structure 120, the second pixel element junction structure 516, the first pixel element junction structure 510, and the imaging junction structure 118 have one or fewer conductive bonding layers, thereby reducing the number of conductive structures between elements in the logic chip 104, the imaging chip 102, and the pixel element chip 502, thereby reducing resistivity and RC delay between the stacked chips. Furthermore, having fewer conductive wiring structures facilitates reducing the size and / or spacing between conductive features in the stacked chips, which can improve the performance of the stacked CMOS image sensor while scaling down device features.

[0073] Figure 7B illustrates a cross-sectional view 700b of some embodiments of a region of the stacked CMOS image sensor of Figure 7A. In some embodiments, the cross-sectional view 700b of Figure 7B corresponds to a region (702 in Figure 7A) of the stacked CMOS image sensor, which is inverted in Figure 7B for ease of illustration.

[0074] As shown in FIG. 7B , the imaging interconnect structure 110 includes a first top wire 530 disposed between two adjacent top wires. The first top wire 530 has a width 531, which may be, for example, about 0.35 μm, in a range of about 0.3 μm to about 0.4 μm, or other suitable value. The first top wire 530 is separated from the two adjacent top wires by a first distance d1. In some embodiments, the first distance d1 is about 0.22 μm, in a range of about 0.2 μm to about 0.24 μm, or other suitable value. In further embodiments, the width 531 of the first top wire 530 is greater than the first distance d1.

[0075] The imaging junction structure 118 includes a first imaging junction pad 126a having a width 534. In some embodiments, the width 534 is approximately 0.3 um, in a range of approximately 0.25 um to approximately 0.35 um, or other suitable value. The first pixel element junction structure 510 includes a first junction contact 514a having a width 536. In various embodiments, the width 536 is approximately 0.1 um, in a range of approximately 0.075 um to approximately 1.25 um, or other suitable value. In some embodiments, the height of the first junction contact 514a is equal to the height of the first imaging junction pad 126a.

[0076] The pixel element interconnect structure 506 includes a first top wire 538 disposed between the first pair of top wires 542 and the second pair of top wires 544. The width of the first top wire 538 may be, for example, about 0.15 um, in a range of about 0.1 um to about 0.2 um, or other suitable value. Thus, in some embodiments, the width of the first top wire 538 is less than the width 531 of the first top wire 530 of the imaging interconnect structure 110. The first top wire 538 is separated from the first pair of top wires by a second distance d2, which in turn is separated from the second pair of top wires by a third distance d3. In various embodiments, the second distance d2 is about 0.15 um, in a range of about 0.1 um to about 0.2 um, or other suitable value. In further embodiments, the third distance d3 is about 0.1 um, in the range of about 0.075 um to about 1.25 um, or any other suitable value.

[0077] FIG. 7C depicts a top view 700c of some embodiments of the cross-sectional view 700b of FIG. 7B taken along line AA' of FIG. 7B, where the first imaging interface pad 126a has a circular shape in the top view.

[0078] FIG. 7D depicts a top view 700d of some embodiments of the cross-sectional view 700b of FIG. 7B taken along line AA' of FIG. 7B, where the first imaging bond pad 126a has a rectangular shape in the top view.

[0079] FIG. 8A shows a cross-sectional view 800a of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 7A, in which the imaging junction structure 118 includes a plurality of imaging junction contacts 125 and the first pixel element junction structure 510 includes a plurality of first pixel element bond pads 515.

[0080] Figure 8B illustrates a cross-sectional view 800b of some embodiments of a region of the stacked CMOS image sensor of Figure 8 A. In some embodiments, cross-sectional view 800b of Figure 8B corresponds to a region (801 in Figure 8A) of the stacked CMOS image sensor, which is inverted in Figure 8B for ease of illustration.

[0081] The imaging junction structure 118 includes a first imaging junction contact 125a having a width 532. In some embodiments, the width 532 is about 0.1 um, in a range of about 0.08 um to about 0.12 um, or other suitable value. The first pixel element junction structure 510 includes a first junction pad 515a having a width 802. In various embodiments, the width 802 is about 0.3 um, in a range of about 0.25 um to about 0.35 um, or other suitable value. In some embodiments, the height of the first imaging junction contact 125a is equal to the height of the first junction pad 515a.

[0082] FIG. 8C illustrates a top view 800c of some embodiments of the cross-sectional view 800b taken along line AA' of FIG. 8B, where the first imaging bonding contact 125a has a circular shape in the top view.

[0083] FIG. 8D illustrates a top view 800d of some embodiments of the cross-sectional view 800b taken along line AA' of FIG. 8B, where the first imaging bonding contact 125a has a rectangular shape in the top view.

[0084] 9A-9F depict various cross-sectional views 900a-900f corresponding to some embodiments of the imaging interconnect structure 110, the imaging junction structure 118, and / or the first pixel element junction structure 510 of FIGS. 5A, 6A, 7A, and / or 8A. In some embodiments, the imaging interconnect structure 110 has an interconnect dielectric structure (e.g., 113 in FIG. 5A) that includes multiple dielectric layers 906, 910, 914 and multiple etch stop layers 908, 912. In further embodiments, the imaging junction structure 118 has an imaging junction dielectric (122 in FIG. 5A) that includes the etch stop layer 912, the passivation layer 916, the dielectric layer 914, and the dielectric blocking layer 918. In yet a further embodiment, the first pixel element junction structure 510 has a first pixel element junction dielectric (e.g., 512 in FIG. 5A ) including an etch stop layer 912, a passivation layer 916, a dielectric layer 914, and a dielectric blocking layer 918. The dielectric layers 906, 910, 914 may be or include, for example, an oxide such as silicon dioxide, a low-k dielectric material, or other suitable dielectric material. The etch stop layers 908, 912 may be or include, for example, silicon nitride, silicon carbide, etc. The passivation layer 916 may be or include, for example, silicon nitride or other dielectric material. The dielectric blocking layer 918 may be or include, for example, silicon oxynitride, silicon oxycarbide, etc.

[0085] Additionally, each of the conductive vias 114 and conductive wires 116 of the imaging interconnect structure 110 includes a conductive liner 902 and a conductive body 904. The conductive liner 902 may be or include, for example, titanium nitride, tantalum nitride, etc. The conductive body 904 may be or include, for example, copper, aluminum, tungsten, ruthenium, other conductive materials, or any combination thereof.

[0086] 9A, the imaging bond structure includes an imaging bond pad 126 having a conductive liner 902 and a conductive body 904. Furthermore, the first pixel element bond structure 510 includes a first bond contact 514 and a first bond pad 515, each of which includes a conductive liner 902 and a conductive body 904.

[0087] 9B , the imaging bond structure includes an imaging bond contact 125 and an imaging bond pad 126, each including a conductive liner 902 and a conductive body 904. In a further embodiment, the first pixel element bond structure 510 includes a first bond pad 515 including a conductive liner 902 and a conductive body 904, and the first pixel element bond structure 510 includes a single conductive layer.

[0088] 9C , the imaging junction structure 118 has an imaging junction contact 125 that includes a conductive liner 902 and a conductive body 904. Additionally, the first pixel element junction structure 510 has a first bond pad 515 that includes a conductive liner 902 and a conductive body 904. Thus, in some embodiments, the imaging junction structure 118 and the first pixel element junction structure 510 each include a single conductive layer.

[0089] 9D , the imaging junction structure includes an imaging bond pad 126 having a conductive liner 902 and a conductive body 904. Additionally, the first pixel element bond structure 510 has a first bond contact 514 that includes the conductive liner 902 and the conductive body 904. Thus, in some embodiments, the imaging junction structure 118 and the first pixel element bond structure 510 each include a single conductive layer.

[0090] Referring to FIG. 9E, the first pixel element bonding structure 510 has a first bonding pad 515 including a conductive liner 902 and a conductive body 904 , and the first bonding pad 515 directly contacts the imaging interconnect structure 110 .

[0091] Referring to FIG. 9F, the first pixel element bonding structure 510 has a first bonding contact 514 including a conductive liner 902 and a conductive body 904 , and the first bonding contact 514 directly contacts the imaging interconnect structure 110 .

[0092] 9G and 9H illustrate cross-sectional views 900g-900h corresponding to some embodiments of logic interconnect structure 112, logic junction structure 120, and / or second pixel element junction structure 516 of FIGS. 5A, 6A, 7A, and / or 8A. In some embodiments, logic interconnect structure 112 has an interconnect dielectric structure (e.g., 113 in FIG. 5A) that includes multiple dielectric layers 906, 910, 914 and multiple etch stop layers 908, 912. In further embodiments, logic junction structure 120 has a logic junction dielectric (e.g., 124 in FIG. 5A) that includes etch stop layer 912, passivation layer 91, dielectric layer 914, and dielectric blocking layer 918. In yet a further embodiment, the second pixel element junction structure 516 has a second pixel element junction dielectric (e.g., 518 in FIG. 5A ) that includes an etch stop layer 912, a passivation layer 916, a dielectric layer 914, and a dielectric blocking layer 918. Furthermore, each of the conductive vias 114 and conductive wires 116 of the logic interconnect structure 112 includes a conductive liner 902 and a conductive body 904.

[0093] 9G, the logic junction structure 120 has a logic junction contact 127 that includes a conductive liner 902 and a conductive body 904. Additionally, the second pixel element junction structure 516 includes a second bond pad 521 that includes a conductive liner 902 and a conductive body 904. Thus, in some embodiments, the logic junction structure 120 and the second pixel element junction structure 516 each include a single conductive layer.

[0094] 9H, the logic junction structure 120 includes a logic junction pad 128 that includes a conductive liner 902 and a conductive body 904. Additionally, the second pixel element junction structure 516 includes a second junction contact 520 that includes a conductive liner 902 and a conductive body 904.

[0095] FIG. 10A shows a cross-sectional view 1000a of some embodiments of a stacked CMOS image sensor corresponding to some other implementations of the stacked CMOS image sensor of FIG. 5A, in which the imaging junction structure 118 includes a plurality of imaging junction pads 126, the logic junction structure 120 includes a plurality of logic junction contacts 127 and a plurality of logic junction pads 128, the first pixel element junction structure 510 includes a plurality of first pixel element junction contacts 514 and a plurality of first pixel element junction pads 515, and the second pixel element junction structure 516 includes a plurality of second pixel element junction contacts 520.

[0096] Additionally, first isolation structures 402 are provided within the logic substrate 108 and are configured to electrically isolate the logic elements 140 from one another. A plurality of top bond pads 406 extend into the backside 106b of the imaging substrate 106 toward the imaging interconnect structure 110. The plurality of top bond pads 406 are provided in a peripheral region of the imaging substrate 106. The photodetector elements 132 are provided in the device region of the imaging substrate 106, and the peripheral region of the imaging substrate 106 laterally surrounds the device region. The top bond pads 406 are configured to provide electrical connections to elements of the stacked CMOS image sensor (e.g., pixel elements 129, transfer transistors 130, logic elements 140, etc.) and other integrated circuit (IC) elements (not shown). A second isolation structure 404 may be provided within the imaging substrate 106. The second isolation structures 404 may be provided along sidewalls of the upper bond pads 406 and are configured to increase electrical isolation between the upper bond pads 406 and other elements (e.g., pixel elements 129, transfer transistors 130, photodetector elements 132) provided on and / or within the imaging substrate 106. An upper dielectric layer 408 is provided along the backside 106b of the imaging substrate 106. An upper dielectric structure 410 is provided between the upper dielectric layer 408 and the plurality of optical filters 142. Additionally, a third isolation structure 1002 is provided on the pixel element substrate 504 and is configured to electrically isolate the pixel elements 129 from each other.

[0097] 10B depicts a top view 1000b of some embodiments of the stacked CMOS image sensor of FIG. 10A taken along line 1003 of FIG. 10A. It should be understood that for ease of illustration, the interconnect dielectric structure (113 in FIG. 10A) of the imaging interconnect structure (110 in FIG. 10A) has been omitted from the top view 1000b of FIG. 10B. In some embodiments, a floating diffusion node 131 is provided at the intersection of adjacent photodetector elements 132, and a transfer transistor 130 is located directly above the corresponding photodetector element 132.

[0098] Figure 10C illustrates a top view 1000c of some embodiments of the stacked CMOS image sensor of Figure 10A taken along line 1004 of Figure 10A. It should be understood that for ease of illustration, the interconnect dielectric structure (113 of Figure 10A) and the third isolation structure (1002 of Figure 10A) of the pixel element interconnect structure (506 of Figure 10A) have been omitted from the top view 1000c of Figure 10C. In some embodiments, the first pixel element 129a is disposed laterally between the well region 202 and the second and third pixel elements 129b and 129c.

[0099] FIG. 11A shows a cross-sectional view 1100a of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the stacked CMOS image sensor of FIG. 10A, in which at least one logic element 140 is provided on a pixel element substrate 504 laterally adjacent to a plurality of pixel elements 129.

[0100] Figure 11B illustrates a top view 1100b of some embodiments of the stacked CMOS image sensor of Figure 11A taken along line 1102 of Figure 11A. It should be understood that for ease of illustration, the interconnect dielectric structure (113 in Figure 11A) of the imaging interconnect structure (110 in Figure 11A) has been omitted from the top view 1100b of Figure 11B. In some embodiments, a floating diffusion node 131 is provided at the intersection of adjacent photodetector elements 132, and a transfer transistor 130 is located directly above the corresponding photodetector element 132.

[0101] Figure 11C depicts a top view 1100b of some embodiments of the stacked CMOS image sensor of Figure 11A taken along line 1104 of Figure 11A. It should be understood that for ease of illustration, the interconnect dielectric structure (113 of Figure 11A) and the third isolation structure (1002 of Figure 11A) of the pixel element interconnect structure (506 of Figure 11A) have been omitted from top view 1100c of Figure 11C. In some embodiments, the first pixel element 129a is laterally adjacent to at least one logic element 140 provided on the pixel element substrate 504.

[0102] 12A shows a cross-sectional view 1200a of some embodiments of a stacked CMOS image sensor according to some other embodiments of the stacked CMOS image sensor of FIG. 10A, in which the imaging junction structure 118 includes a plurality of imaging junction contacts 125 and a plurality of imaging junction pads 126, the logic junction structure 120 includes a plurality of logic junction contacts 127 and a plurality of logic junction pads 128, and the second pixel element junction structure 516 includes a plurality of second pixel element junction contacts 520.

[0103] FIG. 12B shows a cross-sectional view 1200b of some embodiments of a stacked CMOS image sensor according to some other embodiments of the stacked CMOS image sensor of FIG. 12A, in which the imaging junction structure 118 includes multiple imaging junction contacts 125 and the logic junction structure 120 includes multiple logic junction contacts 127.

[0104] FIG. 12C shows a cross-sectional view 1200c of some embodiments of a stacked CMOS image sensor according to some other embodiments of the stacked CMOS image sensor of FIG. 12A, in which the imaging junction structure 118 includes a plurality of imaging junction pads 126 and the first pixel element junction structure 510 includes a plurality of first pixel element junction contacts 514.

[0105] FIG. 12D shows a cross-sectional view 1200d of some embodiments of a stacked CMOS image sensor according to some other embodiments of the stacked CMOS image sensor of FIG. 12C, in which the imaging junction structure (118 in FIG. 12C) is omitted, and the first pixel element junction structure 510 directly contacts the imaging interconnect structure 110 at a first junction interface, and the second pixel element junction structure 516 directly contacts the logic interconnect structure 112 at a second junction interface.

[0106] 12E illustrates a cross-sectional view 1200e of some embodiments of a stacked CMOS image sensor according to some other embodiments of the stacked CMOS image sensor of FIG. 12A, in which upper TSVs 1202 extend through the imaging substrate 106 in the peripheral region. Additionally, upper bond pads 1204 are directly above the upper TSVs 1202 and are electrically coupled to the imaging interconnect structure 110.

[0107] 13A illustrates a circuit diagram 1300a of some embodiments of a stacked CMOS image sensor. In various embodiments, the circuit diagram 1300a corresponds to some embodiments of the stacked CMOS image sensors of FIGS. 5A, 6A, 7A, 8A, 10A, and / or 12A-12E.

[0108] The stacked CMOS image sensor includes an imaging chip 102 electrically coupled to a pixel element chip 502 and a logic chip 104 coupled to the pixel element chip 502. In some embodiments, the imaging chip 102 includes a plurality of photodetector elements 132, at least one transfer transistor 130, and a floating diffusion node 131. In various embodiments, the pixel element chip 502 includes a first pixel element 129 a, a second pixel element 129 b, and a third pixel element 129 c. In further embodiments, the logic chip 104 includes an ASIC circuit 302. In some embodiments, the plurality of photodetector elements 132 are configured to accumulate charge in response to incident radiation, and the at least one transfer transistor 130 is configured to provide the accumulated charge to the floating diffusion node 131. The first pixel element 129a, the second pixel element 129b, and the third pixel element 129c are configured to read out the light receiving element 132, and the charge accumulated by the light receiving element 132 may be read out as a corresponding electrical signal. The electrical signal may be provided to the ASIC circuit 302 for downstream signal processing. In various embodiments, the first pixel element 129a, the second pixel element 129b, the third pixel element 129c, and the ASIC circuit 302 may be configured as shown and / or described in FIG.

[0109] 13B shows a circuit diagram 1300b of some embodiments of a stacked CMOS image sensor corresponding to some other embodiments of the cross-sectional view 1300a of FIG. 13A , where an intra-pixel circuit 1302 is provided on the pixel element chip 502 and electrically coupled between the second pixel element 129b and the ASIC circuit 302. In some embodiments, the intra-pixel circuit 1302 may include one or more additional transistors (e.g., logic transistors) and be configured to perform additional processing on the electrical signal from the second pixel element 129b before passing the electrical signal to the ASIC circuit 302. In various embodiments, the circuit diagram 1300b may correspond to some embodiments of the stacked CMOS image sensor of FIG. 11A .

[0110] 14-25 illustrate various cross-sectional views 1400-2500 of several embodiments of methods for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure. While the cross-sectional views 1400-2500 illustrated in FIGS. 14-25 are described with reference to the methods, it should be understood that the structures illustrated in FIGS. 14-25 are not limited to the methods and are independent of the methods. Furthermore, while FIGS. 14-25 are described as a series of operations, it should be understood that these operations are not limited, and the order of operations may vary in other embodiments, and the described methods may be applicable to other structures. In other embodiments, some of the operations illustrated and / or described may be omitted in part or entirely.

[0111] As shown in cross-sectional view 1400 of FIG. 1400, a plurality of photodetectors 132 are formed in an imaging substrate 106. The imaging substrate 106 may be or include, for example, silicon, single crystal silicon, epitaxial silicon, silicon germanium, other semiconductor materials, etc., and may have a first doping type (e.g., p-type). In some embodiments, a process for forming the photodetectors 132 may include selectively forming a masking layer (not shown) over the front side 106f of the imaging substrate 106, performing a selective ion implantation process on the imaging substrate 106 with the masking layer in place to implant one or more dopants into the imaging substrate 106, and performing a removal process to remove the masking layer. In various embodiments, the photodetectors 132 have a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type).

[0112] 15, a floating diffusion node 131 is formed in the imaging substrate 106. The floating diffusion node 131 may have a second doping type (e.g., n-type) and may have a higher doping concentration than the light receiving element 132. The floating diffusion node 131 may be formed by a selective ion implantation process.

[0113] 16, a plurality of transfer transistors 130 and a plurality of pixel elements 129 are formed on the front side 106f of the imaging substrate 106. In some embodiments, the process of forming the plurality of pixel elements 129 includes depositing a gate dielectric above the imaging substrate 106 (e.g., by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.), depositing a gate electrode on the gate dielectric (e.g., by PVD, CVD, sputtering, electroplating, etc.), performing a patterning process on the gate electrode, and performing a selective ion implantation process to form a plurality of source / drain regions (not shown) in the imaging substrate 106. In various embodiments, a process for forming the plurality of transfer transistors 130 includes selectively etching the imaging substrate 106 to form trenches extending into the front side 106f of the imaging substrate 106, depositing a transfer gate dielectric above the imaging substrate 106 to line the trenches (e.g., by PVD, CVD, ALD, etc.), depositing a transfer gate electrode above the transfer gate dielectric and in the trenches (e.g., by PVD, CVD, sputtering, electroplating, etc.), and performing a patterning process on the transfer gate electrode and transfer gate dielectric.

[0114] As shown in cross-sectional view 1700 of FIG. 17 , the imaging interconnect structure 110 is formed on the front side 106f of the imaging substrate 106. The imaging interconnect structure 110 includes an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The interconnect dielectric structure 113 may be formed by one or more deposition processes, such as a PVD process, a CVD process, an ALD process, other suitable growth or deposition process, or any combination thereof. In further embodiments, the plurality of conductive vias 114 and the plurality of conductive wires 116 may be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, other suitable fabrication processes, or any combination thereof. For example, the plurality of conductive vias 114 and the plurality of conductive wires 116 may be formed by a single damascene process, a dual damascene process, etc.

[0115] 18, an imaging junction structure 118 is formed on the imaging interconnect structure 110, thereby defining the imaging chip 102. In some embodiments, the imaging junction structure 118 includes an imaging junction dielectric 122, a plurality of imaging junction contacts 125, and a plurality of imaging junction pads 126. In various embodiments, the imaging junction structure 118 may be formed by depositing (e.g., by PVD, CVD, ALD, etc.) one or more dielectric layers (e.g., including silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, etc.) on the imaging interconnect structure 110, etching the one or more dielectric layers to form one or more bond contact holes and / or one or more bond pad trenches in the one or more dielectric layers, filling (e.g., by PVD, CVD, ALD, electroplating, electroless plating, etc.) the one or more bond contact holes and / or bond pad trenches with a conductive material (e.g., copper, aluminum, tungsten, etc.), and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) on the conductive material. In some embodiments, the one or more bond contact holes and / or bond pad trenches are filled with a conductive liner material followed by a conductive body material, and the imaging bond contacts 125 and imaging bond pads 126 are configured as shown and / or described in FIG. 9B . In various embodiments, after the planarization process, the top surfaces of the imaging bond dielectric 122 and the imaging bond pads 126 are flush and substantially flat, which reduces unbonded areas and promotes good bond adhesion in the subsequent bonding process.

[0116] Furthermore, although the imaging bond structure 118 of Figure 18 is formed with imaging bond contacts 125 and imaging bond pads 126, it should be understood that the imaging bond structure 118 may be formed with a conductive bonding layer as illustrated in Figures 1A-1C and / or 4, for example. For example, the imaging bond structure 118 may be formed without the imaging bond contacts 125, as depicted in Figures 1A and 1B.

[0117] 19 , a logic substrate 108 is provided, and a plurality of logic elements 140 are formed on a front side 108f of the logic substrate 108. In some embodiments, a process for forming the plurality of logic elements 140 includes depositing a logic gate dielectric (e.g., by PVD, CVD, ALD, etc.) above the logic substrate 108, depositing logic gate electrodes (e.g., by PVD, CVD, sputtering, electroplating, etc.) on the logic gate dielectric, performing a patterning process on the logic gate dielectric and the logic gate electrodes, and performing a selective ion implantation process to form source / drain regions on opposite sides of each logic gate electrode.

[0118] As shown in cross-sectional view 2000 of Figure 20, logic interconnect structure 112 is formed on front side 108f of logic substrate 108. Logic interconnect structure 112 includes interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. Interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116 may be formed as shown and / or described in Figure 17.

[0119] 21, logic junction structures 120 are formed above logic interconnect structures 112, thereby defining logic chip 104. In some embodiments, logic junction structures 120 include logic junction dielectric 124 and a plurality of logic bond pads 128. In various embodiments, logic junction structures 120 include depositing (e.g., by PVD, CVD, ALD, etc.) one or more dielectric layers (including, e.g., silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, etc.) over logic interconnect structures 112, etching the one or more dielectric layers to form one or more bond pad trenches therein, filling (e.g., by PVD, CVD, ALD, electroplating, etc.) the one or more bond pad trenches with a conductive material (e.g., copper, aluminum, tungsten, etc.), and performing a planarization process (e.g., a CMP process) on the conductive material. In some embodiments, the one or more bond pad trenches are filled with a conductive liner material followed by a conductive body material to form the logic bond pads 128 as shown / described in Figure 9H. In various embodiments, after the planarization process, the top surfaces of the logic bond pads 128 are flush and substantially flat, which reduces unbonded areas and promotes good bond adhesion during subsequent bonding processes.

[0120] 21 is formed including a plurality of logic junction pads 128, it should be understood that the logic junction structure 120 may be formed with a conductive bonding layer as depicted in, for example, Figures 1A-1C and / or 4. For example, the logic junction structure 120 may be formed without the logic junction contacts 127 as depicted in Figure 1A.

[0121] 22, the imaging chip 102 is inverted and bonded to the logic chip 104, with the imaging junction structures 118 and the logic junction structures 120 facing each other at bonding interface 119. In some embodiments, the logic chip 104 may be bonded to the imaging chip 102 by a eutectic bonding process, a fusion process, a dielectric-to-dielectric bonding process, a metal-to-metal bonding process, other suitable bonding process, or any combination thereof. In various embodiments, the logic bond pads 128 contact the imaging bond pads 126. And The imaging junction dielectric 122 is brought into contact with the logic junction dielectric 124. The temperatures of the imaging junction structure 118 and the logic junction structure 120 may be increased to form the bonded interface 119.

[0122] At least one of the imaging junction structure 118 and / or the logic junction structure 120 has one or less conductive bonding layer. For example, the logic junction structure 120 may include a single conductive bonding layer (e.g., logic bond pad 128). As a result, the number of inter-element conductive structures between the logic substrate 108 and the imaging substrate 106 is reduced, thereby reducing the resistivity and RC delay in the stacked chips. Furthermore, having fewer conductive wiring structures facilitates reducing the size and / or spacing between conductive features in the stacked chips, which can improve the performance of the stacked CMOS image sensor while scaling down device features.

[0123] 22, after bonding the imaging chip 102 to the logic chip 104, a thinning process may be performed on the imaging substrate 106 to reduce the initial thickness Ti of the imaging substrate 106 to a thickness Ts. In some embodiments, the thinning process includes performing a mechanical polishing process, a CMP process, an etching process, other suitable thinning process, or any combination thereof.

[0124] 23, a backside isolation structure 134 is formed to extend into the backside 106b of the imaging substrate 106. The backside isolation structure 134 includes a trench fill layer 138 and a liner layer 136 disposed between the imaging substrate 106 and the trench fill layer 138. In some embodiments, a process for forming the backside isolation structure 134 includes selectively etching the backside 106b of the imaging substrate 106 to form trenches between adjacent photodetectors 132, depositing a liner material (e.g., by CVD, PVD, ALD, etc.) in the trenches and above the imaging substrate 106, depositing a trench fill material (e.g., by CVD, PVD, ALD, etc.) above the liner material to fill the trenches, and performing a planarization process (e.g., a CMP process, an etching process, etc.) on the liner material and the trench fill material.

[0125] 24, a grid structure 144 and a plurality of light filters 142 are formed on the backside 106b of the imaging substrate 106. The grid structure 144 is directly above the backside isolation structure 134 and may be formed by depositing (e.g., by CVD, PVD, ALD, etc.) a grid material above the imaging substrate 106 and selectively patterning the grid material to form the grid structure 144. The plurality of light filters 142 may be formed by depositing and patterning respective color filter layers.

[0126] 25, a plurality of microlenses 146 are formed above the grid structure 144 and the light filter 142. The microlenses 146 may be formed by depositing a microlens material above the light filter 142 and patterning the microlens material to form the plurality of microlenses 146.

[0127] FIG. 26 illustrates some embodiments of a method 2600 for forming a stacked CMOS image sensor including an imaging chip with an imaging junction structure stacked on a logic chip with a logic junction structure.

[0072] While method 2600 is described as a series of acts or events, it should be understood that the method is not limited to the illustrated order or acts. Thus, in some embodiments, acts may be performed in a different order than that illustrated and / or may occur simultaneously. Furthermore, in some embodiments, an illustrated act or event may be subdivided into multiple acts or events, which may occur at different times or simultaneously with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other non-illustrated acts or events may be included.

[0128] In operation 2602, a plurality of light receiving elements are formed on an imaging substrate. Figure 14 shows a cross-sectional view 1400 corresponding to some embodiments of operation 2602.

[0129] A plurality of transfer transistors and a plurality of pixel elements are formed on the front side of the imaging substrate in operation 2604. Figure 16 shows a cross-sectional view 1600 corresponding to some embodiments of operation 2604.

[0130] An imaging interconnect structure is formed on the imaging substrate in operation 2606. Figure 17 depicts a cross-sectional view 1700 corresponding to some embodiments of operation 2606.

[0131] In operation 2608, an imaging junction structure is formed on the imaging interconnect structure, thereby defining an imaging chip. Figure 18 depicts a cross-sectional view 1800 corresponding to some embodiments of operation 2608.

[0132] A plurality of logic elements and logic interconnect structures are formed on the front side of the logic substrate in act 2610. Figures 19 and 20 depict cross-sectional views 1900 and 2000 corresponding to some embodiments of act 2610.

[0133] In operation 2612, logic junction structures are formed on the logic interconnect structures, thereby defining a logic chip. Figure 21 depicts a cross-sectional view 2100 corresponding to some embodiments of operation 2612.

[0134] In operation 2614, the imaging chip is bonded to the logic chip such that the imaging junction structure faces the logic junction structure at the bond interface. Figure 22 depicts a cross-sectional view 2200 corresponding to some embodiments of operation 2614.

[0135] In operation 2616, backside isolation structures are formed on the backside of the imaging substrate. Figure 23 depicts a cross-sectional view 2300 corresponding to some embodiments of operation 2616.

[0136] In operation 2618, a grid structure, a plurality of optical filters, and a plurality of microlenses are formed on the backside of the imaging substrate. Figures 24 and 25 show cross-sectional views 2400 and 2500 corresponding to some embodiments of operation 2618.

[0137] 27-41 illustrate cross-sectional views 2700-4100 of several embodiments of methods for forming a stacked CMOS image sensor including an imaging chip, a pixel element chip, and a logic chip stacked vertically relative to one another. While cross-sectional views 2700-4100 illustrated in FIGS. 27-41 are described with reference to the methods, it should be understood that the structures illustrated in FIGS. 27-41 are not limited to the methods and are independent of the methods. Furthermore, while FIGS. 27-41 are described as a series of operations, it should be understood that these operations are not limited, that the order of operations may vary in other embodiments, and that the described methods are applicable to other structures. In other embodiments, some of the operations illustrated and / or described may be omitted in part or entirely.

[0138] As shown in cross-sectional view 2700 of FIG. 27, a plurality of photoreceptor elements 132 are formed in an imaging substrate 106. The imaging substrate 106 may have a first doping type (e.g., p-type). In some embodiments, a method for forming the photoreceptor elements 132 may include selectively forming a masking layer (not shown) over the front side 106f of the imaging substrate 106, performing a selective ion implantation process on the imaging substrate 106 with the masking layer disposed thereon to implant one or more dopants into the imaging substrate 106, and performing a removal process to remove the masking layer. In various embodiments, the photoreceptor elements 132 have a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type).

[0139] 28, a floating diffusion node 131 and a plurality of well regions 503 are formed in the imaging substrate 106. The floating diffusion node 131 may have a second doping type (e.g., n-type) and may have a higher doping concentration than the light-receiving element 132. The well region 503 may have a first doping type (e.g., p-type) and may have a higher doping concentration than the light-receiving element 132. The floating diffusion node 131 and the plurality of well regions 503 may be formed by separate ion implantation processes.

[0140] 29, a plurality of transfer transistors 130 and an imaging interconnect structure 110 are formed on the front side 106f of the imaging substrate 106. In various embodiments, the process of forming the plurality of transfer transistors 130 includes selectively etching the imaging substrate 106 to form trenches extending into the front side 106f of the imaging substrate 106, depositing a transfer gate dielectric above the imaging substrate 106 to line the trenches (e.g., by PVD, CVD, ALD, etc.), depositing a transfer gate electrode above the transfer gate dielectric and in the trench (e.g., by PVD, CVD, sputtering, electroplating, etc.), and performing a patterning process on the transfer gate electrode and the transfer gate dielectric. The imaging interconnect structure 110 includes an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The interconnect dielectric structure 113 may be formed by one or more deposition processes, such as a PVD process, a CVD process, an ALD process, other suitable growth or deposition process, or any combination thereof. In further embodiments, the plurality of conductive vias 114 and the plurality of conductive wires 116 may be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, other suitable fabrication processes, or any combination thereof. For example, the plurality of conductive vias 114 and the plurality of conductive wires 116 may be formed by a single damascene process, a dual damascene process, etc.

[0141] As shown in cross-sectional view 3000 of Figure 30, an imaging junction structure 118 is formed on the imaging interconnect structure 110, thereby defining the imaging chip 102. In some embodiments, the imaging junction structure 118 includes an imaging junction dielectric 122, a plurality of imaging junction contacts 125, and a plurality of imaging junction pads 126. In various embodiments, the imaging junction structure 118 may be formed as shown and / or described in Figure 18. Furthermore, while the imaging junction structure 118 of Figure 30 is formed to include the imaging junction contacts 125 and the imaging junction pads 126, it should be understood that the imaging junction structure 118 may be formed with a conductive bonding layer as depicted in Figures 5A-5D, 6A, 7A-7D, 8A-8D, 9A-9F, 10A, 11A, and / or 12A-12E, for example. For example, the imaging bond structure 118 may be formed without the imaging bond pads 126 as depicted in FIG. 6A.

[0142] 31 , a pixel element substrate 504 is provided, and a plurality of pixel elements 129 are formed on a front side 504f of the pixel element substrate 504. In some embodiments, a process for forming the plurality of pixel elements 129 includes depositing a gate dielectric (e.g., by PVD, CVD, ALD, etc.) above the pixel element substrate 504, depositing a gate electrode (e.g., by PVD, CVD, sputtering, electroplating, etc.) on the gate dielectric, performing a patterning process on the transfer gate electrode and the transfer gate dielectric, and performing a selective ion implantation process to form a plurality of source / drain regions in the pixel element substrate 504.

[0143] 32, the pixel element interconnect structure 506 is formed on the front side 504f of the pixel element substrate 504. The pixel element interconnect structure 506 includes an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The interconnect dielectric structure 113, the plurality of conductive vias 114, and the plurality of conductive wires 116 may be formed as shown and / or described in FIG.

[0144] 33, a first pixel element bond structure 510 is formed above the pixel element interconnect structure 506, thereby defining the pixel element chip 502. In some embodiments, the first pixel element bond structure 510 may be formed by depositing (e.g., by PVD, CVD, ALD, etc.) one or more dielectric layers (including, e.g., silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, etc.) on the pixel element interconnect structure 506, etching the one or more dielectric layers to form one or more bond contact holes in the one or more dielectric layers, filling (e.g., by PVD, CVD, sputtering, electroplating, etc.) the one or more bond contact holes with a conductive material (e.g., copper, aluminum, tungsten, etc.), and performing a planarization process (e.g., a CMP process) on the conductive material. In some embodiments, the one or more bond contact holes are filled with a conductive liner material followed by a conductive body material, and each of the first pixel element bond contacts 514 includes a conductive liner and a conductive body. In various embodiments, after the planarization process, the top surface of the first pixel element bonding dielectric 512 and the top surface of the first pixel element bonding contact 514 are flush and substantially flat, which reduces non-bonded areas and promotes good bonding adhesion in the subsequent bonding process.

[0145] Furthermore, although the first pixel element bonding structure 510 of Figure 33 is formed with a plurality of first pixel element bonding contacts 514, it should be understood that the first pixel element bonding structure 510 may be formed with a conductive bonding layer as depicted in Figures 5A-5D, 6A, 7A-7D, 8A-8D, 9A-9F, 10A, 11A, and / or 12A-12E, for example. For example, the first pixel element bonding structure 510 may be formed with a plurality of first pixel element bonding contacts 514 and a plurality of first pixel element bonding pads 515 as depicted in Figure 6A.

[0146] As shown in cross-sectional view 3400 of FIG. 34 , a first bonding process is performed to bond the imaging chip 102 to the pixel element chip 502, thereby defining a first bonded structure 522 between the imaging chip 102 and the pixel element chip 502. Furthermore, after the first bonding process, the imaging junction structure 118 faces the first pixel element bonding structure 510 at a first bonding interface. In some embodiments, the first bonding process includes a eutectic bonding process, a fusion process, a dielectric-to-dielectric bonding process, a metal-to-metal bonding process, other suitable bonding process, or any combination thereof. In various embodiments, the imaging bond pad 126 is brought into contact with the first pixel element bonding contact 512, and the imaging junction dielectric 122 is brought into contact with the first pixel element bonding dielectric 512. The temperature of the imaging junction structure 118 may be increased to form the first bonded structure 522.

[0147] At least one of the imaging junction structure 118 and / or the first pixel element junction structure 510 has one or less conductive bonding layer. For example, the first pixel element junction structure 510 may include a single conductive bonding layer (e.g., the first pixel element bond contact 514). As a result, the number of inter-element conductive structures provided between the pixel element substrate 504 and the imaging substrate 106 is reduced, thereby reducing the resistivity and RC delay in the stacked chips. Furthermore, having fewer conductive wiring structures facilitates reducing the size and / or spacing between conductive features in the stacked chips, which can improve the performance of the stacked CMOS image sensor while scaling down device features.

[0148] 34, after performing the first bonding process, a thinning process may be performed on the pixel element substrate 504 to reduce the initial thickness Tid of the pixel element substrate 504 to a thickness Tsd. In some embodiments, the thinning process includes performing a mechanical polishing process, a CMP process, an etching process, other suitable thinning process, or any combination thereof.

[0149] As shown in cross-sectional view 3500 of Figure 35, through-substrate vias (TSVs) 508 are formed in pixel element substrate 504. In some embodiments, a process for forming TSVs 508 includes selectively patterning pixel element substrate 504 to form TSV openings that extend from pixel element substrate 504 to pixel element interconnect structure 506, filling the TSV openings with a conductive material (e.g., by PVD, CVD, sputtering, electroplating, etc.), and performing a planarization process (e.g., a CMP process, an etching process, etc.) on the conductive material.

[0150] 36, the second pixel element bonding structure 516 is formed on the backside 504b of the pixel element substrate 504. In some embodiments, the second pixel element bonding structure 516 includes a second pixel element bonding dielectric 518, a plurality of second pixel element bonding contacts 520, and a plurality of second pixel element bonding pads 521. In various embodiments, the second pixel element bond structure 516 may be formed by depositing (e.g., by PVD, CVD, ALD, etc.) one or more dielectric layers (e.g., including silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, etc.) on the backside 504b of the pixel element substrate 504, etching the one or more dielectric layers to form one or more bond contact holes and / or one or more bond pad trenches in the one or more dielectric layers, filling (e.g., by PVD, CVD, sputtering, electroplating, etc.) the one or more bond contact holes and / or bond pad trenches with a conductive material (e.g., copper, aluminum, tungsten, etc.), and performing a planarization process (e.g., a CMP process) on the conductive material. In some embodiments, the one or more bond contact holes and / or bond pad trenches are filled with a conductive liner material followed by a conductive body material, and each of the second pixel element bond contact 520 and the second pixel element bond pad 521 comprises a conductive liner and a conductive body. In various embodiments, after the planarization process, the top surface of the second pixel element bonding dielectric 518 and the top surface of the second pixel element bonding pad 521 are flush and substantially flat, which reduces non-bonded areas and promotes good bonding adhesion in the subsequent bonding process.

[0151] 36 is formed including a plurality of second pixel element bonding contacts 520 and second pixel element bonding pads 521, it should be understood that the second pixel element bonding structure 516 may be formed with a conductive bonding layer as depicted in, for example, Figures 5A, 6A, 7A, 8A, 9G-9H, 10A, 11A, and / or 12A-12E. For example, the second pixel element bonding structure 516 may be formed with only the second pixel element bonding contacts 520, and omit the second pixel element bonding pads 521 as depicted in Figure 7A.

[0152] As shown in cross-section 3700 of Figure 37, a plurality of logic elements 140 and logic interconnect structure 112 are formed on front side 108f of logic substrate 108. In various embodiments, the plurality of logic elements 140 may be formed by a process the same as or similar to the process for forming the plurality of pixel elements 129 as shown and / or described in Figure 31. 。 The logic interconnect structure 112 includes an interconnect dielectric structure 113, a plurality of conductive vias 114, and a plurality of conductive wires 116. The interconnect dielectric structure 113, the plurality of conductive vias 114, and the plurality of conductive wires 116 may be formed as shown and / or described in FIG.

[0153] As shown in cross-sectional view 3800 of FIG. 38 , logic junction structures 120 are formed on logic interconnect structures 112, thereby defining logic chip 104. In some embodiments, logic junction structures 120 include logic junction dielectric 124 and a plurality of logic junction contacts 127. In various embodiments, logic junction structures 120 may be formed by depositing (e.g., by PVD, CVD, ALD, etc.) one or more dielectric layers (including, e.g., silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, etc.) on logic interconnect structures 112, etching the one or more dielectric layers to form one or more junction contact holes in the one or more dielectric layers, filling (e.g., by PVD, CVD, ALD, electroplating, electroless plating, etc.) the one or more junction contact holes with a conductive material (e.g., copper, aluminum, tungsten, etc.), and performing a planarization process (e.g., a CMP process) on the conductive material.

[0154] Furthermore, although the logic junction structure 120 of Figure 38 is formed with a plurality of logic junction contacts 127, it should be understood that the logic junction structure 120 may be formed with conductive bonding layers as depicted in Figures 5A, 6A, 7A, 8A, 9G-9H, 10A, 11A, and / or 12A-12E, for example. For example, the logic junction structure 120 may be formed with a plurality of logic bond pads 128 as depicted in Figure 5A.

[0155] As shown in cross-sectional view 3900 of FIG. 39 , a second bonding process is performed to bond the pixel element chip 502 to the logic chip 104, thereby defining a second bonded structure 524 between the pixel element chip 502 and the logic chip 104. After the second bonding process, the logic bonding structure 120 faces the second pixel element bonding structure 516 at the second bonding interface. In some embodiments, the second bonding process includes a eutectic bonding process, a fusion process, a dielectric-to-dielectric bonding process, a metal-to-metal bonding process, other suitable bonding process, or any combination thereof. In various embodiments, the logic bonding contact 127 is brought into contact with the second pixel element bond pad 521, and the logic bonding dielectric 124 is brought into contact with the second pixel element bond dielectric 518. The temperatures of the logic bonding structure 120 and the second pixel element bonding structure 516 may be increased to form the second bonded structure 524.

[0156] At least one of the logic junction structure 120 and / or the second pixel element junction structure 516 has one or less conductive bonding layer. For example, the logic junction structure 120 may include a single conductive bonding layer (e.g., logic junction contact 127). As a result, the number of inter-element conductive structures provided between the pixel element substrate 504 and the logic substrate 108 is reduced, thereby reducing the resistivity and RC delay in the stacked chips. Furthermore, having fewer conductive wiring structures facilitates reducing the size and / or spacing between conductive features in the stacked chips, which can improve the performance of the stacked CMOS image sensor as device features are scaled down.

[0157] 39, after performing the second bonding process, a thinning process may be performed on the imaging substrate 106 to reduce the initial thickness Tii of the imaging substrate 106 to a thickness Tss. In some embodiments, the thinning process includes performing a mechanical polishing process, a CMP process, an etching process, other suitable thinning process, or any combination thereof.

[0158] As shown in cross-sectional view 4000 of Figure 40, a backside isolation structure 134 is formed to extend into the backside 106b of the imaging substrate 106. The backside isolation structure 134 includes a trench fill layer 138 and a liner layer 136. The backside isolation structure 134 may be formed as shown and / or described in Figure 23.

[0159] As shown in cross-sectional view 4100 of Figure 41, a grid structure 144, a plurality of optical filters 142, and a plurality of microlenses 146 are formed on the backside 106b of the imaging substrate 106. The grid structure 144 and the plurality of optical filters 142 may be formed as shown and / or described in Figure 24. The plurality of microlenses 146 may be formed as shown and / or described in Figure 25.

[0160] FIG. 42 illustrates some embodiments of a method 4200 for forming a stacked CMOS image sensor, including an imaging chip, a pixel element chip, and a logic chip stacked vertically on top of one another. While method 4200 is illustrated and / or described as a series of acts or events, it should be understood that the method is not limited to the illustrated order or acts. Thus, in some embodiments, acts may be performed in a different order than that illustrated and / or may occur simultaneously. Furthermore, in some embodiments, an illustrated act or event may be subdivided into multiple acts or events, which may occur at different times or simultaneously with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other acts or events not illustrated may be included.

[0161] In operation 4202, a plurality of light receiving elements are formed on an imaging substrate. Figure 27 depicts a cross-sectional view 2700 corresponding to some embodiments of operation 4202.

[0162] In operation 4204, a plurality of transfer transistors are formed on the front side of the imaging substrate. Figure 29 shows a cross-sectional view 2900 corresponding to some embodiments of operation 4204.

[0163] An imaging interconnect structure is formed on the front side of the imaging substrate in operation 4206. Figure 29 depicts a cross-sectional view 2900 corresponding to some embodiments of operation 4206.

[0164] In operation 4208, an imaging junction structure is formed on the imaging interconnect structure, thereby defining an imaging chip. Figure 30 depicts a cross-sectional view 3000 corresponding to some embodiments of operation 4208.

[0165] In operation 4210, a plurality of pixel elements and pixel element interconnect structures are formed on the front side of the pixel element substrate. Figures 31 and 32 show cross-sectional views 3100 and 3200 corresponding to some embodiments of operation 4210.

[0166] In operation 4212, a first pixel element bonding structure is formed on the pixel element interconnect structure, thereby defining a pixel element chip. Figure 33 shows a cross-sectional view 3300 corresponding to some embodiments of operation 4212.

[0167] In operation 4214, a first bonding process is performed to bond the pixel element chip to the imaging chip such that the imaging bonding structure faces the first pixel element bonding structure at a first bonding interface. Figure 34 depicts a cross-sectional view 3400 corresponding to some embodiments of operation 4214.

[0168] In operation 4216, TSVs are formed to extend through the pixel element substrate to the pixel element interconnect structure. Figure 35 shows a cross-sectional view 3500 corresponding to some embodiments of operation 4216.

[0169] A second pixel element junction structure is formed on the backside of the pixel element substrate in operation 4218. Figure 36 shows a cross-sectional view 3600 corresponding to some embodiments of operation 4218.

[0170] In operation 4220, a plurality of logic elements and logic interconnect structures are formed on the front side of the logic substrate. Figure 37 depicts a cross-sectional view 3700 corresponding to some embodiments of operation 4220.

[0171] In operation 4222, logic junction structures are formed on the logic interconnect structures, thereby defining a logic chip. Figure 38 depicts a cross-sectional view 3800 corresponding to some embodiments of operation 4222.

[0172] In operation 4224, a second bonding process is performed to bond the logic chip to the pixel element chip such that the logic junction structure faces the second pixel element junction structure at a second bonding interface. Figure 39 depicts a cross-sectional view 3900 corresponding to some embodiments of operation 4224.

[0173] In operation 4226, backside isolation structures are formed on the backside of the imaging substrate. Figure 40 depicts a cross-sectional view 4000 corresponding to some embodiments of operation 4226.

[0174] In operation 4228, a grid structure, a plurality of optical filters, and a plurality of microlenses are formed on the backside of the imaging substrate. Figure 41 depicts a cross-sectional view 4100 corresponding to some embodiments of operation 4228.

[0175] Thus, in some embodiments, the present invention relates to an image sensor that includes an imaging chip with an imaging junction structure overlying a logic chip with a logic junction structure, wherein at least one of the imaging junction structure and the logic junction structure includes a single conductive junction layer.

[0176] In some embodiments, the present application provides an image sensor, the image sensor including: a first chip including a first substrate, a plurality of light receiving elements provided on the first substrate, a first interconnect structure provided on a front side of the first substrate, and a first bonding structure provided on the first interconnect structure; and a second chip below the first chip, the second chip including a second substrate, a plurality of semiconductor elements provided on the second substrate, a second interconnect structure provided on a front side of the second substrate, and a second bonding structure provided on the second interconnect structure, a first bonding interface provided between the second bonding structure and the first bonding structure, the second interconnect structure being electrically coupled to the first interconnect structure by the first bonding structure and the second bonding structure, and at least one of the first bonding structure and the second bonding structure including one or less conductive bonding structures. In one embodiment, the first bonding structure includes a single conductive bonding layer, and the second bonding structure includes a plurality of second bonding pads overlying a plurality of second bonding contacts. In one embodiment, the single conductive bonding layer includes a plurality of first bonding pads or a plurality of first bonding contacts. In one embodiment, the first bonding structure directly contacts a top conductive wire in the first interconnect structure, and the second junction structure directly contacts a top conductive wire in the second interconnect structure. In one embodiment, a plurality of transfer transistors and a plurality of pixel elements are provided on the front side of the first substrate, and the plurality of pixel elements include a reset transistor, a source follower transistor, and a select transistor. In one embodiment, the image sensor further includes a third chip disposed between the first chip and the second chip, the third chip including a third substrate, a plurality of pixel elements disposed on a front side of the third substrate, a third interconnect structure disposed on the front side of the third substrate, a third junction structure disposed on the third interconnect structure, and a fourth junction structure disposed on a back side of the third substrate, the third junction structure facing the first junction structure at the first junction interface, and the fourth junction structure facing the second junction structure at a second junction interface.In one embodiment, the image sensor further includes a plurality of through-substrate vias (TSVs) disposed in the third substrate, the TSVs electrically coupling the fourth junction structure to the third interconnect structure. In one embodiment, at least one of the third junction structure and the fourth junction structure includes one or less conductive bonding layers. In one embodiment, the fourth junction structure includes a single conductive bonding layer.

[0177] In some embodiments, the present application provides an image sensor, the image sensor including: a first chip including a first interconnect structure provided on a first substrate, a plurality of light receiving elements provided on the first substrate, and a first bonding structure on the first interconnect structure; a second chip including a second interconnect structure provided on a front side of a second substrate, a plurality of pixel elements provided on the front side of the second substrate, a second bonding structure provided on the second interconnect structure, and a third bonding structure provided on a back side of the second substrate, the second chip being bonded to the first chip; a third chip including a third interconnect structure provided on a third substrate, a plurality of semiconductor elements on the third substrate, and a fourth bonding structure provided on the third interconnect structure, the third chip being bonded to the second chip, wherein at least one of the second bonding structure, the third bonding structure, and the fourth bonding structure includes a single conductive bonding layer. In one embodiment, the first bonding structure includes a plurality of first bonding pads in physical contact with the second bonding structure. In one embodiment, the second bonding structure includes a plurality of second bonding pads disposed on a plurality of second bonding contacts, and the first bonding pads are in direct contact with the second bonding pads. In one embodiment, the second bonding structure includes the single conductive bonding layer in direct contact with the first bonding pads. In one embodiment, the first interconnect structure includes a top-layer conductive wire in direct contact with a first conductive bonding feature of the second bonding structure. In one embodiment, the image sensor further includes a plurality of through-substrate vias (TSVs) disposed in the second substrate and extending continuously from the third bonding structure to the second interconnect structure, and a plurality of upper bonding pads disposed in the first substrate, the upper bonding pads being electrically coupled to the first interconnect structure and laterally aligned with the TSVs. In one embodiment, the third bonding structure includes a plurality of bond pads directly electrically coupled to the TSVs.

[0178] In various embodiments, the present application provides a method for forming an image sensor, the method including: forming a plurality of light receiving elements in a first substrate; forming a first interconnect structure on the first substrate; forming a first bonding structure on the first interconnect structure; forming a plurality of semiconductor elements on a second substrate; forming a second interconnect structure on the second substrate; forming a second bonding structure on the second interconnect structure, wherein at least one of the first bonding structure and the second bonding structure includes a single conductive bonding layer; and performing a first bonding process to bond the first bonding structure to the second bonding structure such that a bonding interface is formed between the first bonding structure and the second bonding structure. In one embodiment, the method further includes forming a third chip including a third interconnect structure on the third substrate and a third bonding structure on the third interconnect structure; and bonding the third chip to the first substrate before performing the first bonding process, wherein the third bonding structure directly contacts the first bonding structure. In one embodiment, the method further includes performing a first thinning process on a backside of the third substrate, forming through-substrate vias (TSVs) in the third substrate, and forming a fourth bonding structure on the backside of the third substrate, where the first bonding process is performed after the fourth bonding structure is formed, and the second bonding structure is in direct contact with the fourth bonding structure. In one embodiment, the method further includes performing a second thinning process on the backside of the first substrate, forming a backside isolation structure in the first substrate, where the backside isolation structure is disposed between adjacent photodetectors, forming a plurality of optical filters above the backside of the first substrate, and forming a plurality of microlenses on the plurality of optical filters.

[0179] The foregoing outlines features of several embodiments to enable those skilled in the art to more easily understand aspects of the present invention. Those skilled in the art should readily appreciate that this disclosure may be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and alterations can be made thereto without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0180] The image sensor and method for forming the image sensor of the present invention can be used in applications requiring high performance in image sensing. [Explanation of symbols]

[0181] 100a, 100b, 100c, 400, 500a, 500b, 500c, 500d, 600a, 700a, 700b, 800a, 800b, 900a-900h, 1000a, 1100a, 1200a, 1200b, 1200d, 1200e, 1400-2500, 2700-4100: Cross section 102: Imaging chip 104: Logic chip 106: Imaging board 106f: Front side of 106 106b: The other side of 106 108: Logic board 108f: Front side of 108 110: Imaging interconnect structure 112: Logic interconnect structure 113: Interconnect dielectric structure 114: Conductive via 116: Conductive wire 116a: First layer of conductive wire 116 116t: Top layer of conductive wire 116 116tm: Central top layer of conductive wire 118: Imaging joint structure 119: Bonding interface 120: Logical Junction Structure 122: Imaging junction dielectric 124:Logic Junction Dielectric 125: Imaging bonding contact 125a: First imaging contact 126: Imaging bonding pad 126a: First imaging bonding pad 127:Logical junction contact 128:Logic bonding pad 129: Pixel element 129a: first pixel element 129b: second pixel element 129c: third pixel element 130: Transfer transistor 131: Floating diffusion node 132: Light receiving element 134: Back isolation structure 136: Liner layer 138: Trench filling layer 140: Logic element 142: Optical filter 144: Grid structure 146: Microlens 200, 700c, 500d, 800c, 800d, 1000b, 1000c, 1100b, 1100c: Top view 202, 503, 626: Well area 204: Source / drain region 204a: first source / drain region 300, 1300a, 1300b: Circuit diagram 302:ASIC circuit 402: 1st isolation structure 404:Second isolation structure 406, 1204: Upper bonding pad 408: Upper dielectric layer 410: Upper dielectric structure 502: Pixel element chip 504: Pixel element substrate 504b: The other side of 504 504f: Front side of 504 506: Pixel element interconnect structure 508, 1202: Through-substrate vias (TSVs) 510: First pixel element junction structure 512: First pixel element junction dielectric 514: First pixel element junction contact 514a: First mating contact 515: First pixel element bonding pad 515a: First bonding pad 516: Second pixel element junction structure 518: Second pixel element junction dielectric 520: Second pixel element junction contact 521: Second pixel element bonding pad 522: First bonded structure 524: Second bonded structure 526, 702, 801: Stacked CMOS image sensor area 530: First top wire Width 531:530 Width of 532:125a Width of 534:126a Width of 536:514a 538: First top wire Width 540:538 542: First pair of top wires 544: Top wire of second pair 600b, 600c, 600d, 600e, 600f, 600g: Layout diagram 602, 604, 606, 608, 610, 612, 1003, 1004, 1102, 1104: Line 614: Shared pixel structure 616: Width of each conductive via 114 618: Width of each conductive wire in the first layer 116a of conductive wires 620, 622, 628, 630, 632, 634, 636: Distance 624: Source / drain region Width of 802:515a 902: Conductive liner 904: Conductive body 906, 910, 914: Dielectric layers 908, 912: Etch stop layer 916: Passivation layer 918: Dielectric blocking layer 1002:Third isolation structure 1302: Pixel circuit 2600, 4200: Method 2602, 2604, 2606, 2608, 2610, 2612, 2614, 2616, 2618, 4202, 4204, 4206, 4208, 4210, 4212, 4214, 4216, 4218, 4220, 4222, 4224, 4226, 4228: Operation A-A': Line d1: First distance d2: Second distance d3: The third distance Lt: 116tm length RST: Reset signal Tid, Tii: initial thickness Tsd, Tss: thickness TX: Transmit signal Vdd: supply voltage Vrst: Reset voltage Wt: 116tm width

Claims

1. a first substrate, a plurality of light receiving elements provided on the first substrate, and a light receiving element provided on the front side of the first substrate; a first interconnect structure disposed on the first interconnect structure; and a first joining structure disposed on the first interconnect structure. Hmm, the first chip and a second substrate under the first chip and a plurality of semiconductors provided on the second substrate; a device; a second interconnect structure provided on the front side of the second substrate; and a second chip including a second bonding structure disposed thereon; and Including, a first bonding interface is provided between the second bonding structure and the first bonding structure; The second interconnection structure is configured to connect the first interconnection structure to the first joint structure and the second joint structure. electrically coupled to the connecting structure; At least one of the first and second junction structures has one or less conductive joints. including synthetic structures, Image sensor.

2. The first bonding structure includes a single conductive bonding layer, and the second bonding structure includes a plurality of second bonding layers. The image sensor of claim 1 , further comprising a plurality of second bond pads overlying the contacts.

3. The single conductive bonding layer includes a plurality of first bonding pads or a plurality of first bonding contacts. The image sensor of claim 2 .

4. The first bonding structure is in direct contact with the top layer of conductive wires in the first interconnect structure, the second bonding structure is in direct contact with a top layer of conductive wires in the second interconnect structure. Item 2. The image sensor according to item 1.

5. a plurality of transfer transistors and a plurality of pixel elements are provided on a front side of the first substrate; The plurality of pixel elements include a reset transistor, a source follower transistor, and a select transistor. a select transistor, The image sensor of claim 1 .

6. a third chip provided between the first chip and the second chip; Further comprising: The third chip includes a third substrate and a plurality of pixel elements provided on a front side of the third substrate. a third interconnect structure provided on the front side of the third substrate; and a third bonding structure provided on the back side of the third substrate; and a fourth bonding structure provided on the back side of the third substrate. 、 The third bonding structure faces the first bonding structure at the first bonding interface, and the fourth bonding structure faces the second bonding structure at a second bonding interface; The image sensor of claim 1 .

7. a plurality of through-substrate vias (TSVs) provided in the third substrate; Further comprising: the TSV electrically couples the fourth junction structure to the third interconnect structure; 7. The image sensor according to claim 6.

8. At least one of the third junction structure and the fourth junction structure has one or less conductive joints. The image sensor of claim 6 including a composite layer.

9. 9. The image sensor of claim 8, wherein the fourth junction structure comprises a single conductive junction layer.

10. a first interconnect structure provided on a first substrate; and a plurality of light receiving elements provided on the first substrate. a first chip including a first bonding structure on the first interconnect structure; a second interconnect structure disposed on the front side of the second substrate; a second junction structure provided on the second interconnect structure; and a third bonding structure provided on the backside of the second substrate, the second bonding structure being bonded to the first chip; Chips and a third interconnect structure provided on a third substrate; and a plurality of semiconductor devices on the third substrate; a fourth bonding structure provided on the third interconnection structure, and bonded to the second chip. The third chip Including, At least one of the second joint structure, the third joint structure, and the fourth joint structure is a single conductive bonding layer; Image sensor.

11. The first bonding structure includes a plurality of first bonding pads in physical contact with the second bonding structure. The image sensor of claim 10 .

12. The second bonding structure includes a plurality of second bonding pads disposed on a plurality of second bonding contacts. Including, the first bond pad directly contacts the second bond pad; The image sensor of claim 11.

13. The second bonding structure includes the single conductive bonding layer in direct contact with the first bonding pad. The image sensor of claim 11 .

14. The first interconnect structure is in direct contact with the first conductive bonding feature of the second bonding structure.

11. The image sensor of claim 10, further comprising a top layer of conductive wires.

15. a second interconnect structure provided on the second substrate and extending continuously from the third bonding structure to the second interconnect structure; a plurality of through-substrate vias (TSVs); a plurality of upper bonding pads provided on the first substrate; Further comprising: The upper bond pad is electrically connected to the first interconnect structure and is laterally connected to the TSV. are aligned in the direction 11. An image sensor according to claim 10.

16. the third bonding structure includes a plurality of bonding pads directly electrically coupled to the TSVs; 16. The image sensor of claim 15.

17. 1. A method for forming an image sensor, comprising: forming a plurality of light receiving elements in a first substrate; forming a first interconnect structure on the first substrate; forming a first bonding structure on the first interconnect structure; forming a plurality of semiconductor devices on a second substrate; forming a second interconnect structure on the second substrate; forming a second bonding structure on the second interconnect structure, the second bonding structure being connected to the first bonding structure; at least one of the second bonding structures includes a single conductive bonding layer; The first bonding structure is bonded to the second bonding structure so that a bonding interface is provided between the first bonding structure and the second bonding structure. performing a first bonding process to bond a structure to the second bonding structure; A method comprising:

18. a third interconnect structure on the third substrate; and a third bonding structure on the third interconnect structure. forming a third chip including the first and second chips; bonding the third chip to the first substrate before performing the first bonding process. wherein the third joining structure is in direct contact with the first joining structure.

20. The method of claim 17, further comprising:

19. performing a first thinning process on a backside of the third substrate; forming a through substrate via (TSV) in the third substrate; forming a fourth bonding structure on the backside of the third substrate; Further comprising: the first bonding process is performed after the fourth bonding structure is formed; the second joining structure is in direct contact with the fourth joining structure; 20. The method of claim 18.

20. performing a second thinning process on the backside of the first substrate; forming a backside isolation structure on the first substrate, the backside isolation structure being adjacent to an adjacent receiving being provided between the optical elements; forming a plurality of optical filters over the backside of the first substrate; forming a plurality of microlenses on the plurality of optical filters; 20. The method of claim 18, further comprising:

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