Contact pad for three-dimensional memory device and manufacturing method for the same

Abstract

To suppress plasma-induced damage in a complementary metal-oxide-semiconductor circuit.SOLUTION: Three-dimensional (3D) NAND memory device and method are provided. In one aspect, the manufacturing method includes the steps of: preparing a substrate, forming a memory cell on the substrate, depositing a first dielectric layer in order to cover the memory cell, forming at least one contact pad on the substrate, depositing a second dielectric layer on the at least one contact pad, forming a first connection pad on the second dielectric layer, bonding the first connection pad to a second connection pad in a peripheral structure, and exposing the at least one contact pad from a back surface of the substrate.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and more particularly to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] NAND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. The growing demand for consumer electronics, cloud computing, and big data has created a constant need for high-capacity, high-performance NAND memory. As traditional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory plays an important role. 3D NAND memory uses multiple stack layers on a single die to achieve high density, large capacity, fast performance, low power consumption, and excellent cost efficiency.

[0003] When fabricating contact pads for 3D NAND structures, metal layers are deposited and plasma processing is often used during the process. Plasma processing can cause plasma-induced damage (PID) to complementary metal-oxide-semiconductor (CMOS) circuits. For example, unintentional high electric fields can cause stress that can degrade the gate oxide of metal-oxide-semiconductor (MOS) transistors during plasma processing. Furthermore, the insulators of metal-insulator-metal (MIM) capacitors can also be degraded or damaged. The disclosed device and method are intended to solve one or more of the above problems and other issues. Summary of the Invention [Means for solving the problem]

[0004] In one aspect of the present disclosure, a method for manufacturing a 3D memory device includes: preparing a substrate for the 3D memory device; forming memory cells of the 3D memory device on a first portion of a surface of the substrate; depositing a first dielectric layer covering the memory cells and the substrate; forming at least one contact pad on a second portion of the surface of the substrate; depositing a second dielectric layer on the at least one contact pad and the first dielectric layer; forming a first connection pad on the second dielectric layer and connected to the at least one contact pad and the memory cell; coupling the first connection pad to a second connection pad of a peripheral structure; and exposing the at least one contact pad from a back surface of the substrate.

[0005] In another aspect of the present disclosure, a 3D memory device includes an array device, a peripheral device, and an opening. The array device and the peripheral device are coupled face-to-face. The array device includes an insulating layer, one or more contact pads, and memory cells between a first portion of the insulating layer and the peripheral device. An opening is formed through a second portion of the insulating layer to expose one or more contact pads located at the bottom of the opening from the back surface of the array device. The bottom of the opening is located at a level between the insulating layer and the peripheral device.

[0006] Other aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure. [Brief explanation of the drawings]

[0007] [Figure 1] 1A-1D are cross-sectional views of an exemplary three-dimensional (3D) array device at particular stages during a manufacturing process according to various embodiments of the present disclosure. [Figure 2] 1A-1D are cross-sectional views of an exemplary three-dimensional (3D) array device at particular stages during a manufacturing process according to various embodiments of the present disclosure. [Figure 3]3A-3C are top and cross-sectional views of the 3D array device shown in FIG. 2 after channel holes have been formed according to various embodiments of the present disclosure. [Figure 4] 3A-3C are top and cross-sectional views of the 3D array device shown in FIG. 2 after channel holes have been formed according to various embodiments of the present disclosure. [Figure 5] 5A and 5B are top and cross-sectional views of the 3D array device shown in FIGS. 3 and 4 after gate line slits have been formed according to various embodiments of the present disclosure. [Figure 6] 5A and 5B are top and cross-sectional views of the 3D array device shown in FIGS. 3 and 4 after gate line slits have been formed according to various embodiments of the present disclosure. [Figure 7] 7A-7C are cross-sectional views of the 3D array device shown in FIGS. 5 and 6 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 8] 7A-7C are cross-sectional views of the 3D array device shown in FIGS. 5 and 6 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 9] 7A-7C are cross-sectional views of the 3D array device shown in FIGS. 5 and 6 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 10] 10A-C are cross-sectional views of the 3D array device shown in FIG. 9 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 11] 10A-C are cross-sectional views of the 3D array device shown in FIG. 9 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 12] 10A-C are cross-sectional views of the 3D array device shown in FIG. 9 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 13] 10A-C are cross-sectional views of the 3D array device shown in FIG. 9 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 14] 1 is a cross-sectional view of an exemplary peripheral device according to various embodiments of the present disclosure. [Figure 15]15 is a cross-sectional view of an exemplary 3D memory device after the 3D array device shown in FIG. 13 is combined with the peripheral device shown in FIG. 14 in accordance with various embodiments of the present disclosure. [Figure 16] 16A-16D are cross-sectional views of the 3D memory device shown in FIG. 15 at various stages according to various embodiments of the present disclosure. [Figure 17] 16A-16D are cross-sectional views of the 3D memory device shown in FIG. 15 at various stages according to various embodiments of the present disclosure. [Figure 18] 1 is a schematic flow chart of fabricating a 3D memory device according to various embodiments of the present disclosure. [Figure 19] 1A-1D are cross-sectional views of an exemplary 3D array device at various stages during a manufacturing process according to various embodiments of the present disclosure. [Figure 20] 1A-1D are cross-sectional views of an exemplary 3D array device at various stages during a manufacturing process according to various embodiments of the present disclosure. [Figure 21] 21A-21C are cross-sectional views of the 3D array device shown in FIG. 20 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 22] 21A-21C are cross-sectional views of the 3D array device shown in FIG. 20 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 23] 21A-21C are cross-sectional views of the 3D array device shown in FIG. 20 at various stages in the manufacturing process according to various embodiments of the present disclosure. [Figure 24] 1 is a cross-sectional view of an exemplary peripheral device according to various embodiments of the present disclosure. [Figure 25] 25 is a cross-sectional view of an exemplary 3D memory device after the 3D array device shown in FIG. 23 is combined with the peripheral device shown in FIG. 24 in accordance with various embodiments of the present disclosure. [Figure 26] 26A-26D are cross-sectional views of the 3D memory device shown in FIG. 25 at various stages according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, technical solutions in embodiments of the present disclosure will be described with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Obviously, the described embodiments are only a part, not all, of the embodiments of the present disclosure. Functions of various embodiments can be exchanged and / or combined. Other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative effort shall fall within the scope of the present disclosure.

[0009] 1-13 schematically illustrate a manufacturing process for an exemplary 3D array device 100 according to an embodiment of the present disclosure. The 3D array device 100 is part of a memory device, sometimes referred to as a 3D memory structure, with the top view in the XY plane and the cross-sectional view in the YZ plane.

[0010] As shown in the cross-sectional view of FIG. 1, the 3D array device 100 may include a substrate 110. In some embodiments, the substrate 110 may include a monocrystalline silicon layer. The substrate 110 may also include a semiconductor material such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), polycrystalline silicon (polysilicon), or a III-V compound such as gallium arsenide (GaAs) or indium phosphide (InP). The substrate 110 may also include a non-conductive material such as glass, a plastic material, or a ceramic material. If the substrate 110 includes a glass, plastic, or ceramic material, the substrate 110 may further include a thin layer of polysilicon deposited on the glass, plastic, or ceramic material. In this case, the substrate 110 can be processed like a polysilicon substrate. By way of example, substrate 110 in the following description comprises an undoped or lightly doped monocrystalline silicon layer.

[0011] In some embodiments, the upper portion of the substrate 110 may be doped with an n-type dopant by ion implantation and / or diffusion to form a doped region 111. The dopant in the doped region 111 may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). As shown in FIG. 1 , a cover layer 120 may be deposited on the doped region 111. The cover layer 120 is a sacrificial layer and may include a single layer or multiple layers. For example, the cover layer 120 may include one or more of a silicon oxide layer and a silicon nitride layer. The cover layer 120 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some other embodiments, the cover layer 120 may include another material, such as aluminum oxide.

[0012] Additionally, a sacrificial layer 130 may be deposited over the cover layer 120. The sacrificial layer 130 may include a dielectric material, a semiconductor material, or a conductive material. An exemplary material for the sacrificial layer 130 is polysilicon.

[0013] After the polysilicon sacrificial layer 130 is deposited, a layer stack 140 may be formed. The layer stack 140 may include multiple pairs of stack layers, including, for example, a first dielectric layer 141 and a second dielectric layer 142 alternately stacked on top of each other. The layer stack may include 64 pairs, 128 pairs, or more than 128 pairs of the first and second dielectric layers 141 and 142.

[0014] In some embodiments, the first dielectric layer 141 and the second dielectric layer 142 may be made of different materials. For example, the different materials may include silicon oxide and silicon nitride. In the following description, the first dielectric layer 141 may illustratively include a silicon oxide layer that may be used as an isolation stack layer, and the second dielectric layer 142 may illustratively include a silicon nitride layer that may be used as a sacrificial stack layer. The sacrificial stack layer may then be etched and replaced with a conductor layer. The first dielectric layer 141 and the second dielectric layer 142 may be deposited by CVD, PVD, ALD, or a combination thereof.

[0015] FIG. 2 shows a schematic cross-sectional view of a 3D array device 100 according to an embodiment of the present disclosure. As shown in FIG. 2, after the layer stack 140 is formed, a stair-forming process may be performed to trim a portion of the layer stack 140 into a stair-shaped structure. Any suitable etching process, including dry etching and / or wet etching, may be used in the stair-forming process. For example, the height of the stair-shaped structure may increase stepwise along the Y direction. A dielectric layer 121 may be deposited to cover the stair-shaped structure. As shown in FIG. 2, the layer stack 140, the sacrificial layer 130, and the cover layer 120 may be removed from the side of the stair-shaped structure, for example, in the region to the left of the stair-shaped structure. This region may be considered a contact region where a contact pad may be configured. The contact region is covered by the dielectric layer 121 during the stair-forming process. In some embodiments, the cover layer 120 may not be etched away in the stair-shaped process, and a portion of the cover layer 120 may be buried by the dielectric layer 121 in the contact region.

[0016] 3 and 4 show schematic top and cross-sectional views of the 3D array device 100 after the channel holes 150 have been formed and then filled with a layer structure according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 4 is taken along line A-A' in FIG. 3. The quantity, dimensions, and arrangement of the channel holes 150 shown in FIGS. 3 and 4 and other figures of the present disclosure are exemplary and for purposes of explanation, although any suitable quantity, dimensions, and arrangement can be used in the disclosed 3D array device 100 according to various embodiments of the present disclosure.

[0017] As shown in FIGS. 3 and 4 , the channel holes 150 extend in the Z direction or a direction substantially perpendicular to the substrate 110 and are arranged to form an array of a predetermined pattern (not shown) in the XY plane. The channel holes 150 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes. Other fabrication processes, such as patterning processes including lithography, cleaning, and / or chemical mechanical polishing (CMP), can also be performed. The channel holes 150 can have a cylindrical or pillar shape that penetrates the layer stack 140, the sacrificial layer 130, the cover layer 120, and partially penetrates the doped region 111. After the channel holes 150 are formed, a functional layer 151 can be deposited on the sidewalls and bottom of the channel holes. The functional layer 151 may include a blocking layer 152 on the sidewalls and bottom of the channel hole to block charge outflow, a charge trapping layer 153 on the surface of the blocking layer 152 to store charge during operation of the 3D array device 100, and a tunnel insulating layer 154 on the surface of the charge trapping layer 153. The blocking layer 152 may include one or more layers that can include one or more materials. The material of the blocking layer 152 may include a high-k dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide, or another wide bandgap material. The charge trapping layer 153 may include one or more layers that can include one or more materials. The material of the charge trapping layer 153 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or another wide bandgap material. The tunnel insulating layer 154 may include one or more layers that can include one or more materials. The material of the tunnel insulating layer 154 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, or another wide bandgap material.

[0018] In some embodiments, the functional layer 151 may include an oxide-nitride-oxide (ONO) structure. If necessary, the functional layer 151 may have a structure different from the ONO structure. When the ONO structure is exemplified in the following description, the functional layer 151 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. That is, the blocking layer 152 may be a silicon oxide layer deposited on the sidewall of the channel hole 150, the charge trapping layer 153 may be a silicon nitride layer deposited on the blocking layer 152, and the tunnel insulating layer 154 may be another silicon oxide layer deposited on the charge trapping layer 153.

[0019] Furthermore, a channel layer 155 may be deposited on the tunnel insulating layer 154. The channel layer 155, also referred to as a "semiconductor channel," may comprise polysilicon in some embodiments. Alternatively, the channel layer 155 may comprise amorphous silicon. Similar to the channel hole, the channel layer 155 also extends through the layer stack 140 into the doped region 111. The blocking layer 152, the charge trapping layer 153, the tunnel insulating layer 154, and the channel layer 155 may be deposited by, for example, CVD, PVD, ALD, or a combination of two or more of these processes. After the channel layer 155 is formed, the channel hole 150 may be filled with an oxide material 156. The functional layer 151 and the channel layer 155 formed in the channel hole 150 may be considered a channel hole structure.

[0020] In the above process, the channel hole 150 is etched after the stair structure is formed. The channel hole 150 may also be formed before the stair formation process. For example, after the layer stack 140 is fabricated as shown in FIG. 1, the channel hole 150 may be formed, and then the functional layer 151 and the channel layer 155 may be deposited. After the channel hole 150 is filled with the oxide material 156, the stair formation process may be performed to form the stair structure.

[0021] 5 and 6 show a schematic top view and a schematic cross-sectional view of the 3D array device 100 after gate line slits 160 have been formed according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 6 is taken along line B-B' in FIG. 5. The gate line slits are also referred to as a gate line slit structure. The 3D array device 100 may have a large number of channel holes 150 arranged in memory planes (not shown). Each memory plane may be divided into memory blocks (not shown) and memory fingers by the gate line slits. For example, the configuration of the channel holes 150 shown in FIG. 5 may reflect the memory fingers between the gate line slits 160.

[0022] The gate line slits 160 can be formed by a dry etching process or a combination of dry and wet etching processes. As shown in FIGS. 5 and 6 , the gate line slits 160 can extend horizontally, for example, in the X direction, through the layer stack 140, and reach or partially penetrate the sacrificial layer 130 in the Z direction, or a direction generally perpendicular to the substrate 110. In this manner, the sacrificial layer 130 is exposed at the bottom of the gate line slits 160. A spacer layer (not shown) can then be deposited on the sidewalls and bottom of the gate line slits 160 by CVD, PVD, ALD, or a combination of two or more of these processes. The spacer layer is configured to protect the first and second dielectric layers 141 and 142 and can include, for example, silicon oxide and silicon nitride.

[0023] After the spacer layer is deposited, selective etching may be performed to remove a portion of the spacer layer at the bottom of the gate line slit 160 by dry etching or a combination of dry etching and wet etching. The sacrificial layer 130 is then exposed again. Subsequently, a selective etching process, for example, a selective wet etching process, may be performed to remove the sacrificial layer 130. Removing the sacrificial layer 130 forms a cavity, exposing the bottom of the cover layer 120 and the blocking layer 152 formed in the channel hole 150. Furthermore, multiple selective etching processes, for example, multiple selective wet etching processes, may be performed to successively remove the exposed portions of the blocking layer 152, the charge trapping layer 153, and the tunnel insulating layer 154, thereby exposing the bottom portion of the channel layer 155.

[0024] If cover layer 120 is silicon oxide and / or silicon nitride, cover layer 120 may be removed when the bottom of functional layer 151 is etched away. In certain embodiments, cover layer 120 may comprise a material other than silicon oxide or silicon nitride, and cover layer 120 may be removed by one or more additional selective etching steps. Removing cover layer 120 exposes the top surface of doped region 111.

[0025] After the etching step, the doped region 111 and the sides of the channel layer 155 near the bottom of the channel hole 150 may be exposed in a cavity left by etching away the sacrificial layer 130 and the cover layer 120. The cavity may be filled with a semiconductor material, such as polysilicon, to form a semiconductor layer 131, for example, by a CVD and / or PVD deposition step. The semiconductor layer 131 may be n-doped and formed on the exposed surfaces of the doped region 111 and on the sidewalls or sides of the channel layer 155, and electrically connected to the doped region 111 and the channel layer 155.

[0026] If desired, selective epitaxial growth may be performed such that a layer of monocrystalline silicon is grown on the exposed surfaces of doped region 111 and a layer of polysilicon is grown on the exposed surfaces of channel layer 155. Thus, semiconductor layer 131 may include adjacent layers of monocrystalline silicon and polysilicon.

[0027] When the functional layer 151 and the bottom of the cover layer 120 are etched, a portion of the spacer layer may be etched away, with the remaining spacer layer remaining on the sidewalls of the gate line slits 160 to protect the first and second dielectric layers 141 and 142. After the semiconductor layer 131 is formed, the remaining spacer layer may be removed by a selective etching process, such as a selective wet etching process, to expose the side surfaces of the second dielectric layer 142 around the gate line slits 160. In some embodiments, the innermost spacer layer in contact with the sidewalls is silicon nitride. Because the second dielectric layer 142 is also a silicon nitride layer, the innermost spacer layer and the second dielectric layer 142 are removed together during the etching process, leaving a cavity 143 between the first dielectric layer 141, as shown in FIG. 7 . Thus, the layer stack 140 is transformed into the layer stack 144.

[0028] Additionally, a conductive material, such as tungsten (W), may be grown to fill the cavity 143 left by the removal of the second dielectric layer 142 and form a conductive layer 145 between the first dielectric layers 141. After the conductive layer 145 is fabricated, the layer stack 144 is converted into a layer stack 146, as shown in FIG. 8. The layer stack 146 includes the first dielectric layer 141 and the conductive layer 145 alternately stacked on top of each other. The functional layer 151 and the channel layer 155 in the channel hole 150 can be considered a channel structure. Each channel structure extends through the layer stack 146 and the conductive layer 145 into the doped region 111, as shown in FIG. 8.

[0029] In some embodiments, before the metal W is deposited in the cavity 143, a dielectric layer (not shown) of a high-k dielectric material such as aluminum oxide may be deposited, followed by a layer of a conductive material such as titanium nitride (TiN) (not shown). The metal W may then be deposited to form the conductor layer 145. CVD, PVD, ALD, or a combination of two or more of these processes may be used in the deposition process. Alternatively, another conductive material such as cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), doped silicon, or any combination thereof may be used to form the conductor layer 145.

[0030] 8 , a portion of each functional layer 151 within the channel hole 150 is located between a portion of one of the conductor layers 145 and a portion of the channel layer 155 within the channel hole 150. Each conductor layer 145 is configured to electrically connect rows of NAND memory cells in the XY plane and is configured as a word line of the 3D array device 100. The channel layer 155 formed within the channel hole 150 is configured to electrically connect columns or strings of NAND memory cells along the Z direction and is configured as a bit line of the 3D array device 100. Therefore, as part of a NAND memory cell, a portion of the functional layer 151 within the channel hole 150 in the XY plane is located between the conductor layer 145 and the channel layer 155, i.e., between the word line and the bit line. The functional layer 151 can also be considered to be located between the channel layer 155 and the layer stack 146. A portion of the conductor layer 145 surrounding a portion of the channel hole 150 functions as a control gate or gate electrode of the NAND memory cell. The 3D array device 100 can be thought of as including a 2D array of strings of NAND cells (such strings are also referred to as "NAND strings"). Each NAND string includes multiple NAND memory cells and extends vertically toward the substrate 110. The NAND strings form a 3D array of NAND memory cells.

[0031] For substrate 110, the bottom surface is also referred to as the backside, and the top surface, i.e., the surface having doped regions 111, is sometimes referred to as the front or front side. As shown in Figure 8, NAND memory cells are formed on a portion of the surface of substrate 110.

[0032] After growing the conductor layer 145 in the cavity 143, a dielectric layer (e.g., a silicon oxide layer) can be deposited on the sidewalls and bottom of the gate line slits 160 by CVD, PVD, ALD, or a combination thereof. A dry etching process, or a combination of dry and wet etching processes, can be performed to remove the dielectric layer at the bottom of the gate line slits and expose a portion of the semiconductor layer 131. The gate line slits can be filled with a conductive material 161 (e.g., doped polysilicon) and a conductive plug 162 (e.g., metal W). As shown in FIG. 9 , the conductive material 161 in the gate line slits can extend through the layer stack 146 and make electrical contact with the semiconductor layer 131. The filled gate line slit can become an array common source of the 3D array device 100. In some embodiments, forming the array common source in the gate line slit can include depositing an insulating layer, a conductive layer (such as TiN, W, Co, Cu, or Al), and then a conductive material such as doped polysilicon. If desired, some gate line slits may be filled with a dielectric, in which case some other gate line slits may be filled with a conductive material to serve as a common source for the array.

[0033] 10-13 show schematic cross-sectional views of the 3D array device 100 at various stages after contacts and vias have been formed according to embodiments of the present disclosure. After the gate line slits 160 are filled and the array common source is formed, openings for word line contacts 171 can be formed, for example, by a dry etching process or a combination of dry and wet etching processes, to form interconnects for the 3D array device 100. The openings for the contacts 171 are then filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material for the contacts 171 can include W, Co, Cu, Al, or combinations thereof. Optionally, when the contacts 171 are fabricated, a layer of a conductive material (e.g., TiN) can be deposited as a contact layer before another conductive material is deposited.

[0034] Furthermore, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) to form a dielectric layer covering the substrate 110, the contact 171, and the NAND memory cell. The newly deposited dielectric layer adds to the dielectric layer 121, thus making the dielectric layer 121 thicker. An opening for the via 172 may be formed by a dry etching process or a combination of dry and wet etching processes. The opening may then be filled with a conductive material, such as W, Co, Cu, Al, or a combination thereof, to form the via 172, as shown in FIG. 10 . CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof may be performed. The via 172 may be electrically connected to the word line contact 171, the top end of the corresponding NAND string, and the array common source plug 162. If necessary, a layer of a conductive material (e.g., TiN) may be first deposited before filling the opening to form the via 172.

[0035] Furthermore, metal layers 173 and 174 for interconnection can be grown by CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. Metal layer 173 is deposited on via 172 and electrically contacts it. Metal layer 174 is an interconnect for a contact pad and is located in a contact region on the side of the staircase structure. Metal layers 173 and 174 may include conductive materials such as W, Co, Cu, Al, or a combination thereof.

[0036] Similar to the formation of via 172, vias 175 and 176 can be formed on metal layers 173 and 174. For example, as shown in FIG. 11 , a dielectric material can be deposited to cover metal layers 173 and 174 and make dielectric layer 121 thicker, and openings for vias 175 and 176 can be formed, which can then be filled with a conductive material to form vias 175 and 176.

[0037] Referring now to FIG. 12 , CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof can be performed to grow metal layers 177 and 178 on vias 175 and 176, respectively. If desired, a single metal layer 178 (not shown) can be formed on via 176 instead of multiple metal layers 178. In the following description, multiple metal layers 178 are used illustratively. As shown in FIG. 12 , the NAND memory cell is formed on one portion of the surface of substrate 110, while metal layer 178 is formed on another portion of the surface of substrate 110. Metal layers 177 and 178 are formed simultaneously from the same material and at approximately the same level relative to doping region 111 and substrate 110. As used herein, a level refers to an XY plane along the Z axis. The level of metal layer 178 refers to an XY plane passing through metal layer 178. The height of a level, i.e., the height of the XY plane of the level, is measured relative to the Z axis. Metal layers 177 and 178 may include a conductive material such as W, Co, Cu, Al, or any combination thereof. Metal layer 177 is electrically connected to layer stack 146 or a NAND memory cell through metal layer 173 and via 175. Metal layer 178 is configured as a contact pad and is connected to metal layer 174 through via 176.

[0038] Further, a CVD or PVD process may be performed again to deposit a dielectric material (e.g., silicon oxide or silicon nitride) to form a dielectric layer that covers metal layers 177 and 178 and further thickens dielectric layer 121. Similar to the formation of vias 172 and 175, an opening may be formed and then filled with a conductive material to form via 179. Via 179 is deposited on and electrically connected to metal layer 177. Further, a dielectric material may be deposited to fill via 179 and further thicken dielectric layer 121. Openings may be formed and then filled to form connection contacts 170 that serve as interconnects with peripheral devices. As shown in FIG. 13, connection pads 170 are each electrically connected to metal layer 177 through vias 179. Connection pads 170 may include W, Co, Cu, Al, or a combination of two or more of these materials. If necessary, a contact layer of a conductive material (e.g., TiN) may be first deposited before filling the openings to form connection pads 170.

[0039] FIG. 14 shows a schematic cross-sectional view of a peripheral device 180 according to an embodiment of the present disclosure. The peripheral device 180 is a portion of a memory device and may also be referred to as a peripheral structure. The peripheral device 180 may include a substrate 181, which may include single-crystal silicon, Ge, SiGe, SiC, SOI, GOI, polysilicon, or a III-V compound such as GaAs or InP. Peripheral CMOS circuitry (e.g., control circuitry) (not shown) may be fabricated on the substrate 181 and used to facilitate operation of the memory device. For example, the peripheral CMOS circuitry may include metal-oxide-semiconductor field-effect transistors (MOSFETs) and provide functional devices such as a page buffer, sense amplifiers, column decoders, and row decoders. A dielectric layer 182 may be deposited on the substrate 181 and the CMOS circuitry. Connection pads and vias, such as connection pad 183, may be formed in the dielectric layer 182. The dielectric layer 182 may include one or more dielectric materials, such as silicon oxide and silicon nitride. The connection pads 183 are configured as interconnects with the 3D array device 100 and may include conductive materials such as W, Co, Cu, Al, or combinations thereof.

[0040] 15-17 schematically illustrate a manufacturing process for an exemplary 3D memory device 190 according to an embodiment of the present disclosure. The cross-sectional views of FIGS. 15-17 are in the YZ plane. The 3D memory device 190 may include the 3D array device 100 shown in FIG. 13 and the peripheral device 180 shown in FIG. 14. The peripheral device 180 is configured to control the array device 100.

[0041] As shown in FIG. 15 , the 3D array device 100 and the peripheral device 180 are bonded by flip-chip bonding to form a 3D memory device 190. In some embodiments, the 3D array device 100 may be flipped vertically, upside down, with the top surfaces of the connection pads 170 facing downward in the Z direction. The two devices may be placed together such that the 3D array device 100 is above the peripheral device 180. After alignment, for example, such that the connection pads 170 are aligned with the connection pads 183, the 3D array device 100 and the peripheral device 180 may be bonded and bonded together. The layer stack 146 and the peripheral CMOS circuitry become sandwiched between the substrates 110 and 181, or between the doped region 111 and the substrate 181. In some embodiments, the connection pads 170 may be bonded to the connection pads 183, respectively, using solder or a conductive adhesive. Thus, the connection pads 170 are electrically connected to the connection pads 183, respectively. The 3D array device 100 and the peripheral device 180 are in electrical communication after the flip-chip bonding process is completed. For example, the contact pads 178 can be electrically connected to the peripheral device 180 via the connection pads 170 and 183.

[0042] For the 3D array device 100 and the peripheral device 180, the bottom side of the substrate 110 or 181 can be referred to as the backside, and the side having the connection pads 170 or 183 can be referred to as the front side or top side. As shown in Figure 15, after the flip-chip bonding process, the 3D array device 100 and the peripheral device 180 are bonded face to face.

[0043] Then, from the backside (after flip-chip bonding), the substrate 110 of the 3D array device 100 can be thinned by a thinning process such as wafer grinding, dry etching, wet etching, CMP, or a combination thereof. In some embodiments, the substrate 110 can be removed by the thinning process, exposing the doped region 111. The dielectric layer 112 can be grown on the doped region 111 by a deposition process (e.g., a CVD or PVD process). The opening 113 can be formed by a dry etching process or a combination of dry and wet etching processes. As shown in FIG. 16 , the opening 113 can penetrate the dielectric layer 112, the doped region 111, and the dielectric layer 121, exposing the metal layer 178. The exposed metal layer 178, vertically adjacent to the peripheral device 180 and beside the staircase structure and layer stack 146, can be used as a contact pad for the 3D memory device 190. For example, bonding wires that can connect the 3D memory device 190 with other devices may be bonded onto the metal layer 178. As shown in FIG. 16 , a staircase structure may illustratively be present between the metal layer 178 and the layer stack 146. As previously mentioned, the metal layers 177 and 178 may be formed simultaneously from the same conductive material at the same level. Thus, after the bonding process, the metal layers 177 and 178 are at approximately the same level relative to the doped regions 111, the connection pads 183, or the peripheral devices 180. In the vertical direction, the metal layer 177 is present between the layer stack 146 and the connection pads 183, the peripheral CMOS circuitry, or the peripheral devices 180.

[0044] Further, a dielectric material may be deposited to form a dielectric layer 114 on top of the dielectric layer 112 and on the sidewalls and bottom of the opening 113. The dielectric layer 114 may function as a passivation layer, which may include materials such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), or a combination thereof. The dielectric layer 114 may be formed by a deposition process such as CVD or PVD. Next, as shown in FIG. 17 , a dry etching process or a dry and wet etching process may be performed to remove a portion of the dielectric layer 114 at the bottom of the opening 113. The metal layer 178 is again exposed to become a contact pad or part of a contact pad of the 3D memory device 190.

[0045] The dielectric layers 112 and 114 can be considered together as an upper insulating layer. As shown in FIG. 17 , the layer stack 146 and the NAND memory cell may be disposed between a portion (e.g., a first portion) of the upper insulating layer and the peripheral device 180, and the metal layer 178 may be disposed between another portion (e.g., a second portion) of the upper insulating layer and the peripheral device 180. An opening 113 is formed through the second portion of the upper insulating layer to expose the metal layer 178 disposed at the bottom of the opening 113 from the backside of the array device 100. The metal layer 178 and the bottom of the opening 113 can be disposed at a level between the upper insulating layer and the peripheral device 180. Furthermore, the metal layer 178 can be disposed at a level between the NAND memory cell and the peripheral device 180.

[0046] Other manufacturing steps or processes may then be performed to complete the fabrication of the 3D memory device 190. For simplicity, details of other manufacturing steps or processes have been omitted.

[0047] If the contact pads of the 3D memory device 190 are formed after bonding the 3D array device 100 and the peripheral device 180, plasma treatments are used several times during the formation of the contact pads, which may cause PID in the peripheral CMOS circuitry of the peripheral device 180 and lead to yield and reliability issues. As shown in FIGS. 15 to 17 , the metal layer 178 becomes the contact pads of the 3D memory device 190 after the flip-chip bonding process. That is, several plasma treatment steps are performed during the fabrication of the 3D array device 100, rather than after the 3D array device 100 and the peripheral device 180 are bonded. Because the formation of the contact pads is performed before the flip-chip bonding process, the peripheral device 180 may undergo fewer plasma treatment steps after bonding with the 3D array device 100, and therefore, less PID may occur in the peripheral CMOS circuitry. Therefore, the fabrication of the metal layer 178 can reduce the effects of PID and improve the yield and reliability of the 3D memory device 190.

[0048] FIG. 18 shows a schematic flowchart 200 for fabricating a 3D memory device according to an embodiment of the present disclosure. At 211, a sacrificial layer may be deposited on a top surface of a substrate for a 3D array device. The substrate may include a semiconductor substrate, such as a single crystal silicon substrate. In some embodiments, a cover layer may be grown on the substrate before depositing the sacrificial layer. The cover layer may include a single layer or multiple layers grown sequentially on the substrate. For example, the cover layer may include silicon oxide, silicon nitride, and / or aluminum oxide. In some other embodiments, the sacrificial layer may be deposited without first depositing a cover layer on the substrate. The sacrificial layer may include single crystal silicon, polysilicon, silicon oxide, or silicon nitride.

[0049] A layer stack of the 3D array device can be formed on the sacrificial layer. The layer stack can include alternating first and second stack layers. The first stack layer can include a first dielectric layer, and the second stack layer can include a second dielectric layer different from the first dielectric layer. In some embodiments, one of the first and second dielectric layers is used as the sacrificial stack layer.

[0050] At 212, a stair formation process may be performed to convert a portion of the layer stack into a stair structure. The stair formation process may include multiple etches used to trim the portion of the layer stack into the stair structure. A deposition process may be performed to deposit a dielectric layer that covers the stair structure. Portions of the dielectric layer on the sides of the stair structure may be used as contact areas where contact pads may be configured.

[0051] At 213, channel holes extending through the layer stack and the sacrificial layer may be formed to expose portions of the substrate. A functional layer and a channel layer may be deposited on the sidewalls and bottom surface of each channel hole. Forming the functional layer may include depositing a blocking layer on the sidewalls of the channel hole, depositing a charge trapping layer on the blocking layer, and depositing a tunnel insulating layer on the charge trapping layer. The channel layer deposited on the tunnel insulating layer functions as a semiconductor channel and may include a polysilicon layer.

[0052] Gate line slits for the 3D array device may be formed at 214. Along the vertical direction, the gate line slits may penetrate through the layer stack. After the gate line slits are etched, a portion of the sacrificial layer is exposed.

[0053] At 215, the sacrificial layer may be etched away to create a cavity on the substrate. The cavity exposes the bottom of the blocking layer of the functional layer in the cavity. If a cover layer is deposited on the substrate, the cover layer is also exposed in the cavity. The layers of the functional layer sequentially exposed in the cavity, including the blocking layer, charge trapping layer, and tunnel insulating layer, are each etched away, for example, by one or more selective etching processes. As a result, a portion of the functional layer close to the substrate may be removed in the cavity. If deposited, the cover layer may also be etched away during the process, and portions of the functional layer may be etched away by etching or another selective etching process. Thus, a portion of the substrate and a portion of the channel layer are exposed in the cavity.

[0054] A deposition step can then be performed to grow a semiconductor layer, such as a polysilicon layer, in the cavity, which is in electrical contact with the channel layer and the substrate.

[0055] In some embodiments, the layer stack can include two dielectric stack layers, one of which is sacrificial. The sacrificial stack layer can be etched away at 216 to leave a cavity, which can then be filled with a conductive material to form the conductor layer. The conductive material can include a metal such as W, Co, Cu, Al, Ti, or Ta.

[0056] At 217, a dielectric layer such as an oxide layer may be deposited on the sidewalls and bottom surface of the gate line slits. Portions of the bottom dielectric layer may be selectively etched to expose the semiconductor layer. A conductive material such as TiN, W, Cu, Al, and / or doped polysilicon may be deposited in the gate line slits to form an array common source in electrical contact with the semiconductor layer. Further etching and deposition steps may be performed to form word line contacts, a first metal layer for interconnection, and vias.

[0057] At 218, a conductive material such as W, Co, Cu, Al, or a combination thereof may be deposited to form a second metal layer. Some of the second metal layer may be used as contact pads, and some of the second metal layer may be used for interconnections. The second metal layer may be covered by a dielectric layer. Further, etching and deposition processes may be performed to form vias and connection pads. The connection pads are configured for connection between the 3D array device and peripheral devices.

[0058] At 219, a flip-chip bonding process may be performed to bond the 3D array device to a peripheral device or secure the 3D array device to a peripheral device to create a 3D memory device. In some embodiments, the 3D array device may be placed upside down on top of the peripheral device. The connection pads of the 3D array device and the peripheral device may be aligned and then bonded. The substrate of the 3D array device may be thinned. An etching process may be performed to expose a second metal layer configured as contact pads in the contact area. The contact pads may be used to connect the 3D memory device to another device.

[0059] 19-23 schematically illustrate a manufacturing process for an exemplary 3D array device 300 according to an embodiment of the present disclosure. In Figures 19-23, the cross-sectional views are in the YZ plane.

[0060] 19, the 3D array device 300 may include a substrate 310. The substrate 310 may include a single crystal silicon layer, or may include another semiconductor material such as Ge, SiGe, SiC, SOI, GOI, polysilicon, GaAs, or InP. In the following description, as an example, the substrate 310 includes an undoped or lightly doped single crystal silicon layer.

[0061] In some embodiments, the upper portion of the substrate 310 may be doped with an n-type dopant to form a doped region 311. As shown in FIG. 19, a cover layer 320 may be deposited on the doped region 311. The cover layer 320 is a sacrificial layer and may include a single layer or multiple layers. For example, the cover layer 320 may include one or more of a silicon oxide layer and a silicon nitride layer. The cover layer 320 may be deposited by CVD, PVD, ALD, or a combination thereof. Alternatively, the cover layer 320 may include another material, such as aluminum oxide.

[0062] A sacrificial layer 330 may be deposited on the cover layer 320. The sacrificial layer 330 may include a semiconductor material or a dielectric material. In the following description, as an example, the sacrificial layer 330 is a polysilicon layer. After the sacrificial layer 330 is formed, a layer stack 340 may be formed. The layer stack 340 includes multiple pairs of stack layers 341 and 342. That is, the stack layers 341 and 342 are alternately stacked.

[0063] In some embodiments, the stack layers 341 and 342 may include a first dielectric layer and a second dielectric layer different from the first dielectric layer. The alternating stack layers 341 and 342 may be deposited by CVD, PVD, ALD, or any combination thereof. In the description, the materials of the stack layers 341 and 342 (i.e., the first and second dielectric layers) are silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, and the silicon nitride layer may be used as a sacrificial stack layer.

[0064] Furthermore, a stair-forming process may be performed to trim a portion of the layer stack 340 into a stair-step structure within the channel hole region 332. The stair-step structure may be covered with a dielectric material, such as silicon oxide, to form the dielectric layer 321. During the stair-step forming process, the stack layers 341 and 342 of the contact region 333, the cover layer 320, and the sacrificial layer 330 may remain unchanged. The contact region 333 may be configured for a contact pad. As shown in FIG. 20 , the stack layers 341 and 342 of the contact region 333 may form a layer stack 347 on the remaining sacrificial layer 330 and the remaining cover layer 320. The layer stack 347 includes the stack layers 341 and 342, i.e., alternating first and second dielectric layers. In the horizontal direction, the layer stack 347 may be located on the side of the stair-step structure, for example, on the left side of the stair-step structure, or the stair-step structure may be located between the layer stacks 340 and 347. The staircase structure and the layer stack 347 may be separated by a portion of a dielectric layer 321 that is deposited on the doped region 311 .

[0065] 21, 22, and 23 show schematic cross-sectional views of a 3D array device 300 at certain stages in accordance with an embodiment of the present disclosure. After the layer stack 340 is formed, channel holes 350 may be formed. The quantity, dimensions, and placement of the channel holes 350 shown in FIGS. 21-23 are illustrative examples of the structure and manufacturing method.

[0066] The channel hole 350 may have the shape of a cylinder or a pillar extending through the layer stack 340, the sacrificial layer 330, and the cover layer 320, and may partially penetrate into the doped region 311. After the channel hole 350 is formed, a functional layer 351 may be deposited on the sidewalls and bottom of the channel hole. The functional layer 351 may include a blocking layer on the sidewalls and bottom of the channel hole, a charge trapping layer on the surface of the blocking layer, and a tunnel insulating layer on the surface of the charge trapping layer.

[0067] In some embodiments, the functional layer 351 may include an ONO structure, which will be used in the following description. For example, a silicon oxide layer may be deposited on the sidewall of the channel hole 350 as a blocking layer. A silicon nitride layer may be deposited on the blocking layer as a charge trapping layer. Another silicon oxide layer may be deposited on the charge trapping layer as a tunnel insulating layer. A polysilicon layer may be deposited on the tunnel insulating layer as a channel layer 355. Similar to the channel hole, the channel layer 355 may also extend through the layer stack 340 into the doped region 311. After the channel layer 355 is formed, the channel hole 350 may be filled with an oxide material. The channel hole 350 may be sealed by a plug that includes a conductive material (e.g., metal W) and can be in electrical contact with the channel layer 355.

[0068] Furthermore, the gate line slits 360 may be formed by a dry etching process or a combination of dry and wet etching processes. The gate line slits 360 may extend through the layer stack 340 to reach or partially penetrate the sacrificial layer 330 in the Z direction. In this manner, a portion of the sacrificial layer 330 is exposed at the bottom of the gate line slits 360. A spacer layer (not shown) may be deposited on the sidewalls and bottom of the gate line slits 360, and a portion of the spacer layer at the bottom of the slits 360 may be etched away to re-expose the sacrificial layer 330. The sacrificial layer 330 may be etched away. Removing the sacrificial layer 330 forms a cavity, exposing the cover layer 320 and the bottom of the blocking layer formed in the channel hole 350. Portions of the blocking layer, charge trapping layer, and tunnel insulating layer may be etched away, exposing the bottom of the channel layer 355. The cover layer 320 may be removed once the bottom of the functional layer 351 is etched away or removed in an additional selective etching step to expose the top surface of the doped region 311 .

[0069] The cavity may be filled with a semiconductor material, such as polysilicon, to form semiconductor layer 331. Semiconductor layer 331 may be deposited on the surfaces of doped region 311 and the exposed portions of channel layer 355. Furthermore, sacrificial stack layer 342 may be removed by etching and replaced with conductor layer 345 including a conductive material, such as W. As shown in FIG. 21 , after conductor layer 345 is formed, layer stack 340 becomes layer stack 346.

[0070] Each conductor layer 345 is configured to electrically connect one or more rows of NAND memory cells along the Y direction or XY plane and is configured as a word line of the 3D array device 300. The channel layers 355 formed in the channel holes 350 are configured to electrically connect the NAND strings along the Z direction and are configured as bit lines of the 3D array device 300.

[0071] 22, the gate line slits 360 may be filled with a conductive material 361 (e.g., doped polysilicon) and a conductive plug 362 (e.g., a conductive material W). In some embodiments, the filled gate line slits may become an array-common source of the 3D array device 300.

[0072] Thereafter, openings for word line contacts 371 may be formed. The openings are filled with a conductive material (W, Co, Cu, Al, or a combination thereof) to form the contacts 371. Further, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) on the 3D array device 300. The dielectric layer 321 becomes thicker. Further, openings for vias 372 may be formed and subsequently filled with a conductive material such as W, Co, Cu, or Al. Some of the vias 372 are electrically connected to the word line contacts 371. Some of the vias 372 are electrically connected to the plugs 362 and the top ends of the corresponding NAND strings.

[0073] Further, metal layers 373 and 374 for interconnection may be deposited. Metal layer 373 electrically contacts each of vias 372. Metal layer 374 is in contact region 333 and configured to interconnect with the contact pad. Metal layers 373 and 374 may include a conductive material such as W, Co, Cu, Al, or a combination thereof.

[0074] Additionally, metal layers 373 and 374 may be covered by a dielectric material that thickens dielectric layer 321. Similar to the formation of via 372, vias 375 and 376 may be formed on and in contact with metal layers 373 and 374, respectively, as shown in FIG.

[0075] Additionally, CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof may be performed to grow metal layers 377 and 378 over vias 375 and 376, respectively. Metal layers 377 and 378 may be formed simultaneously from the same material and disposed at approximately the same level relative to layer stacks 346 and 347, doped region 311, or substrate 310. Metal layers 377 and 378 may include a conductive material such as W, Co, Cu, Al, or any combination thereof. Metal layer 377 may be electrically connected to the NAND memory cell via layer stack 346 or metal layer 373 and vias 372 and 375. Metal layer 378 may be configured as a contact pad and connected to metal layer 374 through via 376. Metal layer 378 may be disposed over a dielectric region including a portion of dielectric layer 321 and layer stack 347.

[0076] Further, a CVD or PVD process may be performed again to deposit a dielectric material to cover metal layers 377 and 378 and thicken dielectric layer 321. Similar to the formation of vias 372 and 375, an opening may be formed and then filled with a conductive material to form via 379 that contacts and overlies metal layer 377. Further, a dielectric material may be deposited to cover via 379 and further thicken dielectric layer 321. Openings are made and filled to form connection pads 370 that serve to connect to peripheral devices. Connection pads 370 are in electrical contact with each of vias 379, as shown in FIG. 23 . Connection pads 370 may include W, Co, Cu, Al, or a combination thereof.

[0077] 24 schematically illustrates, in cross-section, a peripheral device 380 according to an embodiment of the present disclosure. The peripheral device 380 may include a semiconductor substrate 381 (e.g., a substrate of single crystal silicon). Peripheral CMOS circuitry (e.g., control circuitry) (not shown) may be fabricated on the substrate 381 and used to facilitate operation of the 3D array device 300. A dielectric layer 382 including one or more dielectric materials is deposited on the substrate 381. Connection pads and vias, such as connection pad 383, may be formed in the dielectric layer 382. The connection pad 383 is configured to connect with the 3D array device 300 and may include a conductive material (e.g., W, Co, Cu, Al, or any combination thereof).

[0078] 25 and 26 illustrate a schematic manufacturing process for an exemplary 3D memory device 390 according to an embodiment of the present disclosure. The cross-sectional views in FIGS. 25-26 are in the YZ plane. The 3D memory device 390 is formed by bonding the 3D array device 300 and the peripheral device 380 together using a flip-chip bonding process. In some embodiments, the 3D array device 300 can be flipped vertically and inverted so that the top surfaces of the connection pads 370 face downward in the Z direction. The 3D array device 300 can be placed and aligned on top of the peripheral device 380. For example, the connection pads 370 can be aligned with the connection pads 383, respectively. The 3D array device 300 and the peripheral device 380 can then be bonded together and face-to-face, as shown in FIG. 25. The connection pads 370 are electrically connected to the connection pads 383, respectively. Thus, the metal layer 378 can be electrically connected to the peripheral device 380 via the connection pads 370 and 383.

[0079] The substrate 310 of the 3D array device 300 can then be thinned, and a dielectric layer 312 can be grown on the doped region 311 by a deposition process. The opening 313 can be formed by a dry etching process or a combination of dry and wet etching processes. The opening 313 penetrates the dielectric layer 312, the doped region 311, the remaining cover layer 320, the remaining sacrificial layer 330, the layer stack 347, and the dielectric layer 321 to expose the metal layer 378. After the opening 313 is formed, a portion of the layer stack 347 is etched away. The remaining portion of the layer stack 347 can be considered a layer stack including alternating first and second dielectric layers (i.e., stack layers 341 and 342). In some embodiments, the opening 313 can be completely surrounded by the remaining layer stack 347 in the XY plane. Optionally, the opening 313 can be partially surrounded by the remaining layer stack 347 in the XY plane. For example, in the latter scenario, a portion of opening 313 may pass through layer stack 347 and another portion of opening 313 may pass through dielectric region 321 in the XY plane. In the vertical direction (e.g., in the Z direction), metal layer 378 may be below the remaining layer stack 347 or between the remaining layer stack 347 and peripheral device 380. Additionally, dielectric layer 314 may be formed on the dielectric layer 312 and the sidewalls of opening 313 as a passivation layer.

[0080] The exposed metal layer 378 beside the staircase structure and layer stack 346 can be used as a contact pad for the 3D memory device 390. For example, a bonding wire can be bonded onto the metal layer 378 for connection to another device. As described above, the metal layer 377 and the metal layer 378 (i.e., the contact pad) are simultaneously formed of the same material. After the flip-chip bonding process, the metal layer 377 is between the layer stack 346 and the peripheral device 380, or between the layer stack 346 and the connection pad 383. The metal layers 377 and 378 are disposed at approximately the same level with respect to the layer stacks 346 and 347, the doped region 311, the connection pad 383, or the peripheral device 380.

[0081] Other manufacturing steps or processes may then be performed to complete the fabrication of the 3D memory device 390. Details of other manufacturing procedures or processes have been omitted for simplicity.

[0082] Because the contact pads (i.e., metal layer 378) are formed before the flip-chip bonding process, the peripheral device 380 can undergo fewer plasma processing steps after being bonded to the 3D array device 300. Therefore, less PID may occur in the peripheral CMOS circuitry. The effects of PID can be reduced, and the yield and reliability of the 3D memory device 390 can be improved.

[0083] Although the principles and implementations of the present disclosure have been described herein using specific embodiments, the foregoing description of the embodiments is intended only to aid in the understanding of the present disclosure. Furthermore, features of different embodiments described above can be combined to form additional embodiments. Those skilled in the art can make changes to specific implementations and application scopes in accordance with the spirit of the present disclosure. Therefore, the contents of the specification should not be interpreted as limitations on the present disclosure.

[0084] [Additional note 1] 1. A method for manufacturing a three-dimensional (3D) memory device, comprising: providing a substrate for the 3D memory device; forming a plurality of memory cells of the 3D memory device over a first portion of a surface of the substrate; depositing a first dielectric layer covering the plurality of memory cells and the substrate; forming at least one contact pad on a second portion of the surface of the substrate; depositing a second dielectric layer over the at least one contact pad and the first dielectric layer; forming a plurality of first connection pads over the second dielectric layer, the first connection pads being connected to the at least one contact pad and the plurality of memory cells; coupling the plurality of first connection pads to a plurality of second connection pads of a peripheral structure; exposing the at least one contact pad from a backside of the substrate; A method comprising: [Additional note 2] forming the plurality of memory cells of the 3D memory device, forming a first layer stack including a plurality of first dielectric stack layers and a plurality of conductive stack layers alternately stacked on top of one another; forming the plurality of memory cells through the first layer stack; The method according to claim 1, comprising: [Additional note 3] forming the plurality of memory cells through the first layer stack, The method described in Appendix 2, further comprising a step of forming a plurality of channel structures extending through the first layer stack, each of the channel structures including a functional layer and a channel layer, the functional layer being between the channel layer and the first layer stack. [Additional note 4] forming the plurality of memory cells through the first layer stack, The method of claim 3, further comprising forming a semiconductor layer disposed between the first layer stack and the substrate, wherein each of the plurality of channel structures extends within the semiconductor layer. [Additional note 5] 5. The method of claim 4, wherein the semiconductor layer comprises one or more doped layers. [Additional note 6] The method of claim 1, further comprising forming a plurality of conductive layers for interconnection on the first dielectric layer. [Additional note 7] 7. The method of claim 6, wherein the at least one contact pad and the plurality of conductive layers comprise the same material and are disposed at the same level relative to the substrate. [Additional note 8] forming a plurality of memory cells of the 3D memory device, The method of claim 2, further comprising trimming a portion of the first layer stack to form a staircase structure. [Additional note 9] the step of exposing the at least one contact pad comprises: 10. The method of claim 1, further comprising forming an opening through the substrate and the first dielectric layer to expose the at least one contact pad. [Additional Note 10] the step of exposing the at least one contact pad comprises: 10. The method of claim 9, further comprising thinning or removing the substrate before forming the opening to expose the at least one contact pad. [Additional Note 11] The method of claim 2, further comprising a step of forming a second layer stack, the second layer stack being disposed between the second portion of the surface of the substrate and the at least one contact pad and including a plurality of second dielectric stack layers and a plurality of third dielectric stack layers alternately stacked on top of each other. [Additional Note 12] An array device and a peripheral device coupled face-to-face, an array device and a peripheral device, wherein the array device includes an insulating layer, one or more contact pads, and a plurality of memory cells between a first portion of the insulating layer and the peripheral device; an opening formed through a second portion of the insulating layer, the opening exposing the one or more contact pads located at a bottom of the opening from a backside of the array device, the bottom of the opening being located at a level between the insulating layer and the peripheral device; A three-dimensional (3D) memory device comprising: [Additional Note 13] 13. The 3D memory device of claim 12, further comprising a first layer stack including a plurality of first dielectric stack layers and a plurality of conductive stack layers alternately stacked on top of each other, wherein the plurality of memory cells include a plurality of channel structures and the plurality of conductive stack layers, each of the channel structures extending through the plurality of conductive stack layers. [Additional Note 14] 13. The 3D memory device of claim 12, further comprising a plurality of conductive layers located between the insulating layer and the plurality of memory cells and connected to the plurality of memory cells. [Additional Note 15] 15. The 3D memory device of claim 14, wherein the one or more contact pads and the plurality of conductive layers comprise the same material and are positioned at the same level relative to the peripheral devices. [Additional Note 16] 14. The 3D memory device of claim 13, further comprising a second layer stack disposed between the second portion of the insulating layer and the one or more contact pads. [Additional Note 17] 17. The 3D memory device of claim 16, wherein the second layer stack includes a plurality of second dielectric stack layers and a plurality of third dielectric stack layers alternately stacked on top of each other. [Additional Note 18] 14. The 3D memory device of claim 13, wherein each of the channel structures includes a functional layer and a channel layer, the functional layer being between the channel layer and the first layer stack. [Additional Note 19] 14. The 3D memory device of claim 13, further comprising a semiconductor layer disposed between the insulating layer and the first layer stack, wherein each of the plurality of channel structures extends into the semiconductor layer. [Additional Note 20] 20. The 3D memory device of claim 19, wherein the semiconductor layer comprises one or more doped layers. [Additional Note 21] 13. The 3D memory device of claim 12, wherein the one or more contact pads are located at a level between the insulating layer and the peripheral device. [Additional note 22] 22. The 3D memory device of claim 21, wherein the one or more contact pads are located at a level between the plurality of memory cells and the peripheral device. [Additional Note 23] 15. The 3D memory device of claim 14, further comprising a first dielectric layer disposed between the plurality of conductive layers and the plurality of memory cells. [Additional note 24] 15. The 3D memory device of claim 14, further comprising a second dielectric layer disposed between the one or more contact pads and the peripheral device. [Explanation of symbols]

[0085] 100, 300 Three-dimensional (3D) array device 110, 181, 310 board 111, 311 doped region 112, 114, 121, 182, 312, 321, 382 Dielectric layers 170, 183, 188, 193, 194, 195 Connection pads 120, 320 cover layer 113, 171, 313 openings 130, 330 sacrificial layer 131, 331 Semiconductor layer 140, 144, 146, 340, 346, 347 layer stacks 141 first dielectric layer 142 second dielectric layer 143 Cavity 145 Conductor Layer 150, 350 channel holes 151, 351 Functional layer 152 Blocking Layer 153 Charge trap layer 154 Tunnel Insulator 155, 355 channel layer 156 Oxide Materials 160, 360 gate line slit 161, 361 Conductive materials 162, 362 Conductive plug 171, 371 word line contacts 172, 175, 176, 179, 372, 375, 376, 379 via 173, 174, 177, 178, 373, 374, 377, 378 metal layer 180, 380 peripheral devices 190, 390 3D memory devices 333 Contact Area 341, 342 Alternating stack layers

Claims

1. A memory device comprising an array device, the array device comprises: an insulating layer and a semiconductor layer overlying the insulating layer in a first direction; a first stack above the semiconductor layer spaced apart from the insulating layer in the first direction, the first stack including a plurality of first dielectric stack layers and a plurality of conductor stack layers alternately stacked on top of each other in the first direction; a first dielectric layer spaced apart from and overlying the insulating layer in the first direction; a plurality of contact pads on the first dielectric layer; Equipped with the insulating layer, the semiconductor layer, and the first dielectric layer have a recessed structure; A memory device, wherein a plurality of the contact pads are disposed on sides of the recessed structure in the first direction.

2. The memory device of claim 1 , further comprising a channel structure extending through the first stack into the semiconductor layer along the first direction.

3. the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is between the first semiconductor layer and the first stack; The memory device of claim 2 , wherein the channel structure further extends along the first direction through the second semiconductor layer and into the first semiconductor layer.

4. the channel structure comprises a channel layer and a functional layer; The memory device of claim 3 , wherein the functional layer is between the channel layer and the first stack in a second direction perpendicular to the first direction.

5. the second semiconductor layer extends through the functional layer of the channel structure; The memory device of claim 4 , wherein the second semiconductor layer contacts the channel layer of the channel structure.

6. The memory device of claim 1 , wherein the recessed structure contacts two or more of the contact pads.

7. further comprising a plurality of conductive layers in the first stack on a side away from the semiconductor layer in the first direction; The memory device of claim 2 , wherein a plurality of said conductive layers are connected to said channel structure.

8. The memory device of claim 7 , wherein the contact pads and the conductive layers comprise the same material and are disposed at the same level with respect to the insulating layer.

9. a first connection pad on one of the plurality of conductive layers that is located away from the first stack in the first direction; The memory device of claim 7 , wherein the first connection pad is connected to multiple conductive layers.

10. a peripheral device spaced apart from the insulating layer and overlying the first dielectric layer; the peripheral device comprises a second dielectric layer and a second connection pad on the second dielectric layer; The memory device of claim 9 , wherein the second connection pad is coupled to the first connection pad.

11. The memory device of claim 10 , wherein a plurality of the contact pads are between the semiconductor layer and the peripheral device.

12. The memory device of claim 10 , wherein a plurality of the conductive layers are between the first stack and the peripheral device.

13. The memory device of claim 1 , wherein the semiconductor layer comprises a doped region comprising an n-type dopant.

14. A memory device comprising an array device, the array device comprises: an insulating layer and a semiconductor layer overlying the insulating layer in a first direction, the semiconductor layer having a first portion and a second portion in a second direction different from the first direction; a first stack spaced apart from the insulating layer in the first direction and overlying the first portion of the semiconductor layer, the first stack including a plurality of first dielectric stack layers and a plurality of conductor stack layers alternately stacked on top of each other in the first direction; a channel structure extending through the first stack along the first direction; a second stack spaced apart from the insulating layer in the first direction and overlying a second portion of the semiconductor layer, the second stack including a plurality of second dielectric stack layers and a plurality of third dielectric stack layers alternately stacked on top of each other in the first direction, the insulating layer, the semiconductor layer, and the second stack comprising a recessed structure; a plurality of contact pads in the first dielectric layer, the plurality of contact pads being disposed on sides of the recessed structure in the first direction; A memory device comprising:

15. a first dielectric layer spaced apart from the insulating layer and overlying the first semiconductor layer; the first dielectric layer overlies the second stack; The memory device of claim 14 , wherein a plurality of said contact pads are formed in said first dielectric layer.

16. a peripheral device spaced apart from the insulating layer and overlying the first dielectric layer; The memory device of claim 15 , wherein a plurality of the contact pads are between the second stack and the peripheral device.

17. The semiconductor layer is a first semiconductor layer; a second semiconductor layer between the first semiconductor layer and the first stack; Equipped with The memory device of claim 14 , wherein the channel structure extends along the first direction through the second semiconductor layer and into the first semiconductor layer.

18. the channel structure comprises a channel layer and a functional layer; the functional layer is between the channel layer and the first stack in a second direction perpendicular to the first direction; the second semiconductor layer extends through the functional layer of the channel structure; The memory device of claim 17 , wherein the second semiconductor layer contacts the channel layer of the channel structure.

19. further comprising a plurality of conductive layers between the first stack and the peripheral device; 17. The memory device of claim 16, wherein the contact pads and the conductive layers comprise the same material and are disposed at the same level relative to the peripheral device.

20. The memory device of claim 16 , wherein the array device and the peripheral device are coupled face-to-face.

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