Semiconductor device

Abstract

To provide a semiconductor device that can conduct electricity from a voltage below a threshold value of a Schottky diode even when a semiconductor material and an ohmic metal are in direct contact with each other, and can reduce forward loss during rated operation.SOLUTION: A semiconductor device includes a first conductivity type semiconductor substrate 30, a first conductivity type region 12 provided inside the semiconductor substrate 30 and exposed at a first main surface of the semiconductor substrate, a second conductivity type region 13 selectively provided in a surface region of the first conductivity type region 12 in contact with the first conductivity type region 12, a silicide film 33 forming an ohmic junction with the second conductivity type region, and an electrode 14 in contact with the silicide film 33 and forming a Schottky junction with the first conductivity type region 12. The silicide film 33 has a contact region 37 in contact with the first conductivity type region 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, a semiconductor device has been proposed in which an anode electrode is Schottky junctioned to the surface of a SiC epitaxial layer to reduce reverse leakage current and threshold voltage (see, for example, Patent Document 1 below). It has also been proposed to realize ohmic contact between the electrode and silicon carbide by ion-implanting phosphorus (P) to turn the area into an amorphous layer and then heat-treating the amorphous layer to recrystallize it into n-type cubic single-crystal silicon carbide (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-30618 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-49198 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when manufacturing diode chips using ohmic metal, particles and other factors can cause the p-type semiconductor region directly below the ohmic metal to not form properly, resulting in direct contact between the semiconductor material and the ohmic metal, resulting in the formation of defective chips that allow large leakage currents to flow when a reverse voltage is applied.

[0005] In order to solve the problems of the conventional technology described above, the present disclosure aims to provide a semiconductor device that can conduct electricity from a voltage below the threshold value of the Schottky diode even when the semiconductor material and the ohmic metal are in direct contact with each other, and that can reduce forward loss during rated operation. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: The semiconductor device includes a first conductivity type semiconductor substrate, a first conductivity type region provided within the semiconductor substrate and exposed at a first main surface of the semiconductor substrate, a second conductivity type region selectively provided in a surface region of the first conductivity type region so as to be in contact with the first conductivity type region, a silicide film forming an ohmic junction with the second conductivity type region, and an electrode in contact with the silicide film and forming a Schottky junction with the first conductivity type region. The silicide film has a contact region in contact with the first conductivity type region.

[0007] According to the above disclosure, the second conductivity type region (p + The first conductivity type region (n - Since there is no Schottky barrier in the contact area between the first conductivity type region (n-type drift region) and the silicide film (ohmic metal), there is no threshold for the forward applied voltage VF, and operation is possible from the low VF region. - This blocks leakage current from the contact area between the silicon nitride film and the silicon dioxide film, preventing defective chips. [Effects of the Invention]

[0008] According to the semiconductor device of the present disclosure, even if the semiconductor material and the ohmic metal are in direct contact with each other, conduction is possible at a voltage below the threshold value of the Schottky diode, thereby achieving the effect of reducing forward loss during rated operation. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment; [Figure 2] 2 is a perspective view showing the structure of a region S of FIG. 1 of the semiconductor device according to the embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing the defect width in the p+ type region of the active region and the operation when a reverse voltage is applied (part 1). [Figure 4] FIG. 2 is a cross-sectional view showing the defect width in the p+ type region of the active region and the operation when a reverse voltage is applied (part 2). [Figure 5] 10 is a graph showing the relationship between the defect width in the p+ type region of the active region and the yield rate. [Figure 6A] 1 is a plan view showing a structure of a semiconductor device according to an embodiment; [Figure 6B] FIG. 10 is a plan view showing another structure of the semiconductor device according to the embodiment; [Figure 7] FIG. 10 is a plan view showing another structure of the semiconductor device according to the embodiment; [Figure 8] FIG. 10 is a plan view showing another structure of the semiconductor device according to the embodiment; [Figure 9] FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device. [Figure 10] FIG. 10 is a perspective view showing the structure of a region S in FIG. 9 having an ohmic metal of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Summary of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: The semiconductor device includes a first conductivity type semiconductor substrate, a first conductivity type region provided within the semiconductor substrate and exposed at a first main surface of the semiconductor substrate, a second conductivity type region selectively provided in a surface region of the first conductivity type region so as to be in contact with the first conductivity type region, a silicide film forming an ohmic junction with the second conductivity type region, and an electrode in contact with the silicide film and forming a Schottky junction with the first conductivity type region. The silicide film has a contact region in contact with the first conductivity type region.

[0011] According to the above disclosure, the second conductivity type region (p + The first conductivity type region (n -Since there is no Schottky barrier in the contact area between the first conductivity type region (n-type drift region) and the silicide film (ohmic metal), there is no threshold for the forward applied voltage VF, and operation is possible from the low VF region. - This blocks leakage current from the contact area between the silicon nitride film and the silicon dioxide film, preventing defective chips.

[0012] Moreover, in the semiconductor device according to the present disclosure, the contact region is within 0.5 μm from the second conductivity type region in a plan view.

[0013] Moreover, in the semiconductor device according to the present disclosure, the contact region is sandwiched between the second conductivity type regions.

[0014] Furthermore, in the semiconductor device according to the present disclosure, the spacing between the second conductivity type regions sandwiching the contact region is 1 μm or less.

[0015] Moreover, in the semiconductor device according to the present disclosure, the silicide film contains any one of Ni, Ti, and Al.

[0016] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second conductivity type regions and the contact regions are alternately provided to form a striped pattern as a whole.

[0017] In addition, in the semiconductor device according to the present disclosure, the distance between the second conductivity type regions between the stripes is 1.0 μm or more and 5.0 μm or less.

[0018] Moreover, in the semiconductor device according to the present disclosure, the contact region includes a 3C—SiC structure.

[0019] The semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the semiconductor substrate has a back surface electrode on a back surface thereof.

[0020] Moreover, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the semiconductor substrate is SiC or GaN.

[0021] <Findings underlying this disclosure> First, the problems with conventional semiconductor devices will be described. Silicon carbide (SiC) semiconductors have recently been attracting attention as a semiconductor material that can be used to fabricate (manufacture) semiconductor devices (hereinafter referred to as silicon carbide semiconductor devices) that exceed the limitations of semiconductor devices using silicon (Si) semiconductors. In particular, silicon carbide semiconductors are expected to be applied to high-voltage (e.g., 1200 V or higher) semiconductor devices, taking advantage of their characteristics of higher breakdown field strength and higher thermal conductivity compared to silicon semiconductors.

[0022] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), n - n-type drift region - Since the design specifications for the epitaxial layer can be set to a thin thickness and a high impurity concentration, silicon carbide diodes with a breakdown voltage of up to about 3300V generally have a Schottky barrier diode (SBD) structure.

[0023] Typically, SBD structures have problems such as high electric field strength at the junction between the semiconductor substrate and the front electrode, which increases reverse leakage current due to electron tunneling through the Schottky barrier when a reverse voltage is applied, or increases reverse leakage current due to surface defects inherent to silicon carbide. For this reason, silicon carbide diodes have been proposed that employ a Junction Barrier Schottky (JBS) structure, which combines a Schottky junction and a pn junction on the front side of the semiconductor substrate.

[0024] As for the structure of a conventional silicon carbide diode, the structure of a silicon carbide diode employing a JBS structure will be described below. Fig. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0025] In a conventional silicon carbide semiconductor device 140 shown in FIG. 9, an n - The SBD structure is formed by a Schottky junction between the titanium film 131 that forms the front electrode 114 and the drift region 112. + Type region 113 and n - The diode is a vertical silicon carbide diode with a JBS structure in which a pn junction with a type drift region 112 is mixed.

[0026] The Schottky junction of the conventional silicon carbide semiconductor device 140 is formed by an n-type junction exposed on the front surface of the semiconductor substrate 130. - The semiconductor substrate 130 is formed of an n-type drift region 112 and a front electrode 114 made of a titanium film 131 and an aluminum alloy film 132 provided on the front surface of the semiconductor substrate 130. The semiconductor substrate 130 is formed of an n-type silicon carbide + On the front surface of the starting mold substrate 111, n - n type drift region 112 - It is an epitaxial substrate with a layer of n-type epitaxial layers. + The starting substrate 111 is n + A back electrode 119 is provided on the entire back surface of the semiconductor substrate 130, and an n-type cathode region is formed. + The starting substrate 111 is electrically connected to the field oxide film. Reference numerals 115, 120, 120a, 124, 121, 122, and 123 respectively denote a field oxide film, an edge termination region, a connection region for the edge termination region, a field limiting ring (FLR), and p regions constituting the JTE structure. - Type domain and p -- type region, and n + This is the mold channel stopper region.

[0027] p + The p-type region 113 is selectively provided in the surface region of the front surface of the semiconductor substrate 130 in the active region 110. + Between the n-type regions 113, the front surface of the semiconductor substrate 130 is - The drift region 112 is exposed. +Type region 113 and n - A pn junction is formed on the front surface of the semiconductor substrate 130 by the adjacent p + n between type regions 113 - The type drift region 112 forms a Schottky junction with the titanium film 131 that is the bottom layer of the front surface electrode 114 provided on the front surface of the semiconductor substrate 130 .

[0028] Also, p + In order to reduce the contact resistance between the titanium film 131 and the Schottky metal region 113, + There are also diodes in which ohmic metal is disposed on the type region 113. FIG. 10 is a perspective view showing the structure of the region S in FIG. 9 which has ohmic metal in a conventional semiconductor device. In FIG. 10, a nickel silicide film 133 is disposed as the ohmic metal. The nickel silicide film 133 is disposed as the bottom layer of the front surface electrode 114. + As shown in FIG. 10, the p + The mold region 113 and the nickel silicide film 133 are provided in a stripe shape. + The mold region 113 is connected to the FLR 124 at its edge, and the nickel silicide film 133 in the active region 110 is connected to the nickel silicide film 133 on the FLR 124 at its edge.

[0029] With this structure, when the rated current flows in the forward direction, p + n outside type region 113 - Current flows in the Schottky region of the p-type drift region 112. Furthermore, when a surge current flows due to a lightning strike or the like, the current cannot flow only in the Schottky region. + The p-type region 113 performs bipolar operation, allowing current to flow. + By providing a nickel silicide film 133 as an ohmic region on the type region 113, p + The stripe structure of only the mold region 113 facilitates bipolar operation.

[0030] However, when manufacturing a diode chip using ohmic metal in the active region 110, particles or the like can cause damage to the p + In some cases, the formation of the mold region 113 is not successful. + Since the mold region 113 and the ohmic metal (nickel silicide film 133) are in direct contact with each other, there is a problem that a defective chip is formed in which a large leakage current flows when a reverse voltage is applied.

[0031] Preferred embodiments of the semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions without the prefix. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0032] (Embodiment) A semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. The semiconductor device according to the present disclosure is configured using a wide bandgap semiconductor. As the semiconductor device according to the embodiment, the structure of a silicon carbide semiconductor device will be described. The semiconductor device according to the embodiment can also be made of other wide bandgap semiconductors, such as GaN (gallium nitride). FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the embodiment.

[0033] The silicon carbide semiconductor device 40 according to the embodiment shown in FIG. 1 has a front surface electrode (first electrode) 14 and an n-type semiconductor layer 15 on the front surface (first main surface) side of a semiconductor substrate 30 in an active region 10. - an SBD structure formed by a Schottky junction with a p-type drift region (first conductivity type region) 12; + type region (second conductivity type region) 13 and n -The silicon carbide diode has a JBS structure in which a pn diode formed by a pn junction with the silicon carbide drift region 12 and a pn diode are mixed.

[0034] n - type drift region 12 and p + The mold regions 13 are arranged in a substantially uniform pattern on the front surface of the active region 10. - type drift region 12 and p + The mold regions 13 are arranged in stripes extending in the same direction parallel to the front surface of the semiconductor substrate 30, and are alternately and repeatedly arranged in contact with each other in the short direction perpendicular to the longitudinal direction of the stripes. - The drift region 12 is formed by adjacent p + The front surface of the semiconductor substrate 30 is exposed between the mold regions 13 .

[0035] Active region 10 is a region through which current flows when the silicon carbide diode is in an on-state. Active region 10 has, for example, a substantially rectangular planar shape and is located approximately in the center of semiconductor substrate 30. Edge termination region 20 is a region between active region 10 and the edge of semiconductor substrate 30, and surrounds the periphery of active region 10. Edge termination region 20 is an n - This region of the type drift region 12 relaxes the electric field on the front surface side of the semiconductor substrate 30 and maintains a breakdown voltage. The breakdown voltage is the limit voltage at which the element does not malfunction or break down.

[0036] A breakdown voltage structure such as a junction termination extension (JTE) structure is disposed in edge termination region 20. The JTE structure is formed by disposing a plurality of p-type regions (in FIG. 1, p - Type region 21 and p -- The active region 10 is surrounded by a substantially rectangular planar voltage-resistant structure (shown as a gate region 22).

[0037] A field limiting ring (FLR) 24 is disposed in the edge termination region 20. The FLR 24 is a p + The edge termination region 20 is a p-type region that extends outward from the connecting region 20a. - The FLR24 is adjacent to the mold region 21. + In the longitudinal direction in which the type region 13 extends in a stripe shape, + It may be in contact with the mold region 13 .

[0038] The connecting region 20a of the edge termination region 20 is a region between the active region 10 and the field oxide film 15 described below, and surrounds the periphery of the active region 10 and connects the active region 10 to the breakdown voltage structure of the edge termination region 20. The breakdown voltage structure of the edge termination region 20 is the portion of the edge termination region 20 from the inner edge of the field oxide film 15 to the edge (chip edge) of the semiconductor substrate 30, and p - type area 21,p -- JTE structures such as type 22 and n + A predetermined pressure-resistant structure such as a mold channel stopper region 23 is disposed.

[0039] The front surface electrode 14 is provided on the front surface of the semiconductor substrate 30 in the active region 10. The front surface electrode 14 is - type drift region 12 and p + In contact with the mold region 13, n - type drift region 12 and p + The semiconductor substrate 30 is electrically connected to the mold region 13. A passivation film (not shown) is provided on the front surface of the semiconductor substrate 30. The passivation film functions as a protective film that protects the element structure and front surface electrodes 14 on the front surface side of the semiconductor substrate 30.

[0040] The passivation film has an opening that exposes a portion of the front surface electrode 14. The portion of the front surface electrode 14 exposed in the opening of the passivation film functions as a bonding pad. The bonding pad is disposed, for example, in the center of the semiconductor substrate 30. An aluminum (Al) wire (not shown) is bonded (joined) to the bonding pad, which is the most common wiring connection when supplying current to the bonding pad.

[0041] Next, a description will be given of a cross-sectional structure of silicon carbide semiconductor device 40 according to the embodiment. As described above, silicon carbide semiconductor device 40 according to the embodiment includes an SBD structure of a silicon carbide diode and a JBS structure having a pn diode in active region 10 of semiconductor substrate 30 made of silicon carbide, and includes a JTE structure as a breakdown voltage structure in edge termination region 20.

[0042] The semiconductor substrate 30 is made of silicon carbide. + On the front surface of the starting mold substrate 11, n - n type drift region 12 - It is an epitaxial substrate with a layer of n-type epitaxial layers. + The starting substrate 11 is n + The semiconductor substrate 30 is an n-type cathode region. - The main surface (n - n type drift region 12 - The surface of the n-type epitaxial layer) is the front surface, + The main surface (n + The back surface of the mold starting substrate 11 is referred to as the back surface.

[0043] In the active region 10, the surface region on the front side of the semiconductor substrate 30 is provided with one or more p-type semiconductor layers that constitute a pn diode. + A mold area 13 is selectively provided. + The n-type region 13 is connected to the front surface of the semiconductor substrate 30. - The p + The n-type region 13 is exposed on the front surface of the semiconductor substrate 30. -It contacts the mold drift region 12 .

[0044] In the edge termination region 20, the surface region on the front surface side of the semiconductor substrate 30 includes the FLR 24, one or more p-type regions (here, two: p - Type region 21 and p -- type region 22) and n + The FLRs 24 are provided in the entire area of ​​the connecting region 20a of the edge termination region 20 and extend outward from the connecting region 20a. - It contacts the mold region 21. The active region 10 is located inside the inner end of the FLR 24.

[0045] p - The mold region 21 is provided outside the FLR 24, away from the connecting region 20a of the edge termination region 20, and adjacent to the FLR 24. -- The type region 22 is p - The mold region 21 is provided outside the mold region 21. - Adjacent to the mold region 21. + The type channel stopper region 23 is p -- Outside the mold region 22, p -- It is provided away from the mold area 22. + The mold channel stopper region 23 is exposed at the edge (chip edge) of the semiconductor substrate 30.

[0046] FLR24, p - type region 21, p -- Type regions 22 and n + The n-type channel stopper region 23 is - The FLR24, p - type region 21, p -- Type regions 22 and n + The n-type channel stopper region 23 is exposed on the front surface of the semiconductor substrate 30. - The FLR24 contacts the drift region 12. - type region 21, p -- Type regions 22 and n +The depth of the type channel stopper region 23 is, for example, p + It may be the same as the depth of the mold region 13 .

[0047] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15. The field oxide film 15 may be a laminated film formed by sequentially stacking, for example, a thermal oxide film and a deposited oxide film. The thermal oxide film can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15. When the field oxide film 15 includes a deposited oxide film, the field oxide film 15 can be formed in a shorter time than when the entire field oxide film 15 is a thermal oxide film.

[0048] Field oxide film 15 has contact holes 15a that expose almost the entire front surface of semiconductor substrate 30 in active region 10. The sidewalls of contact holes 15a in field oxide film 15 (inner side surfaces of field oxide film 15) are, for example, approximately perpendicular to the front surface of semiconductor substrate 30. Contact holes 15a in field oxide film 15 are provided throughout the entire area from active region 10 to connecting region 20a of edge termination region 20.

[0049] The contact hole 15a of the field oxide film 15 is formed with the n - type drift region 12 and p + Form region 13 is exposed. Also, FLR 24 in connecting region 20a of edge termination region 20 is exposed. Inside contact hole 15a of field oxide film 15, on the front surface of semiconductor substrate 30, front surface electrode 14 functioning as an anode electrode is provided along the front surface of semiconductor substrate 30.

[0050] The front electrode 14 has a layered structure formed by sequentially stacking a titanium film 31 and an aluminum alloy film (metal electrode film containing aluminum) 32. In addition, the front electrode 14 has a lowermost nickel silicide (NiSi) film 33 selectively provided between the front surface of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may also contain carbon (C). The front electrode 14 may extend outward on the field oxide film 15. The ohmic metal may be a titanium silicide (TiSi) film, an aluminum silicide (AlSi) film, or a mixture thereof, in addition to the nickel silicide (NiSi) film 33.

[0051] The titanium film 31 is provided on the entire front surface of the semiconductor substrate 30 inside the contact hole 15a. - The titanium film 31 contacts the n-type drift region 12. - The junction with the n-type drift region 12 - This is a Schottky electrode that forms a Schottky junction with the type drift region 12. The titanium film 31 may extend outward on the field oxide film 15 and terminate at a position facing the FLR 24 in the depth direction, for example.

[0052] The aluminum alloy film 32 covers the entire surface of the titanium film 31, is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 via the titanium film 31. The aluminum alloy film 32 extends on the field oxide film 15 to the outside of the titanium film 31, and has a p - It may terminate at a position facing the mold region 22. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. Instead of the aluminum alloy film 32, an aluminum film or an aluminum silicon copper (AlSiCu) film may be provided.

[0053] The nickel silicide film 33 is in contact with the titanium film 31 and p + The nickel silicide film 33 is selectively provided between the titanium film 31 and the p-type region 13.+ The p-type region 13 is an ohmic electrode that makes an ohmic contact with the p-type region 13. + By disposing a nickel silicide film 33 (ohmic metal) on the type region 13, the titanium film 31 (Schottky metal) and p + Since the contact resistance of the mold region 13 is reduced, the amount of heat generated when a large current flows through the active region 10 is reduced, and the chip's resistance to heat generated when a large current flows (IFSM resistance) is increased.

[0054] The nickel silicide film 33 is provided in the surface region of the front surface of the semiconductor substrate 30 and has a p + It may be in contact with the mold region 13 and protrude from the front surface of the semiconductor substrate 30 in a direction away from the front surface of the semiconductor substrate 30 .

[0055] 2 is a perspective view showing the structure of the region S of FIG. 1 of the semiconductor device according to the embodiment. As shown in FIG. 2, in the embodiment, striped p + The mold region 13 is cut to a cut width D, for example, a width of 1.0 μm or less. - A contact region 37 (see FIGS. 3 and 4) is formed where the type drift region 12 and the nickel silicide film 33 (ohmic metal) are in contact with each other, and p + The type regions 13 and the contact regions 37 are provided alternately. Since the contact regions do not have a Schottky barrier, there is no threshold value for the forward applied voltage VF, and operation is possible from a low VF region.

[0056] 3 and 4 show the p + 3 and 4 are cross-sectional views showing the width of the defect in the mold region and the behavior when a reverse voltage is applied. - The contact region 37 between the type drift region 12 and the nickel silicide film 33 is p + The p + In the case where the defect width D of the type region 13 is greater than 2 μm, the p +If there is a defect in the mold region 13, a leakage current 35 flows from the contact region 37, resulting in a defective chip that does not function as a diode. + In this case, the depletion layer 36 extending from the pn junctions on both sides completely covers the contact region 37, and therefore the leakage current from the contact region 37 is blocked by the depletion layer 36. - The contact region 37 where the type drift region 12 and the nickel silicide film 33 contact each other is formed by two adjacent p + It is preferable that the width D of the gap between the mold regions 13 is 1 μm or less. + It is preferable that the distance is within 0.5 μm from the mold region 13 .

[0057] Figure 5 shows the p + 5 is a graph showing the relationship between the defect width in the mold region and the yield rate. In FIG. 5, the horizontal axis indicates the defect width D in μm, and the vertical axis indicates the yield rate. In FIG. 5, + The results are shown in Table 1. The defect width D was varied by creating a defect in the type region 13, and the electrical characteristics were obtained by measuring the WAT (Wafer Acceptance Test). - The dopant of the drift region 12 is N (nitrogen), and the impurity concentration is 8.80×10 15 ±30%cm -3 , the thickness is set to 10±10%μm, and the Schottky metal is a titanium film, p + The SBD was carried out under the condition that the impurity of the type region 13 was Al (aluminum).

[0058] As shown in FIG. 5, when the defect width D is larger than 1.0 μm, the leakage current increases and the yield rate decreases. For this reason, in the embodiment, the defect width D is preferably 0.2 μm or more and 1.0 μm or less. In addition, the plurality of p + The spacing A of the mold region 13 is p + The thickness is preferably 1.0 μm or more and 5.0 μm or less so that the depletion layer 36 does not close between the n-type regions 13. - If the impurity concentration of the n-type drift region 12 is low, the depletion layer 36 tends to expand.- The impurity concentration of the drift region 12 is 1.0×10 15 / cm 3 Over 1.0 x 10 17 / cm 3 It is preferable that the value is equal to or less than the value shown in FIG. + The width B of the mold region 13 is preferably 1.0 μm or more and 3.0 μm. The width C of the nickel silicide film 33 in FIG.

[0059] Also, instead of the nickel silicide film 33, the contact region 37 can be made of a semiconductor having a 3C-SiC structure. Since an ohmic contact is formed between the semiconductor having a 3C-SiC structure and the titanium film 31 or the aluminum alloy film 32, there is no need to arrange an ohmic metal. In this case, the semiconductor having a 3C-SiC structure has the same structure as the nickel silicide film 33, that is, p + It is in the form of stripes provided on the mold region 13. The 3C-SiC structure can be formed by, for example, implanting ions such as argon ions and then performing a heat treatment.

[0060] 6A is a plan view showing the structure of the semiconductor device according to the embodiment. The structure of the semiconductor device according to the embodiment can be a structure other than that shown in FIG. 6A. For example, in FIG. 6A, adjacent p + The missing portion of the mold region 13 is p + The p + The missing portion of the mold region 13 is + In the structure of FIG. 6A, the p-type regions 13 of the Schottky portion can be staggered in the direction in which they extend. + The depletion layer is difficult to close between the vacant portions of the p-type region 13 (the positions of the x in FIG. 6A), and the reverse current IR may increase when a reverse voltage is applied. + When the recessed portions of the type region 13 are alternately inserted (FIG. 6B), the depletion layer of the Schottky portion is easily closed, and an increase in the reverse current IR can be prevented.

[0061] Furthermore, p +It is also possible to arrange the p-type regions 13 and the nickel silicide films 33 in a dot-like arrangement so as to form a planar close-packed structure. + By providing alternately dot-shaped voids, which are voids in the mold region 13, it becomes easier to close the depletion layer in the Schottky region, and an increase in the reverse current IR can be prevented.

[0062] 7 and 8 are plan views showing other structures of the semiconductor device according to the embodiment. As shown in Fig. 7, by providing a nickel silicide film 33 on the entire surface of the active region 10 and making the Schottky junctions all boundary regions, it is possible to create a diode with no VF threshold.

[0063] As shown in FIG. 8, only a few p + It is also possible to have a structure in which the mold region 13 has a wide portion T. When IFSM or surge current flows into a circuit in which multiple chips are mounted in parallel, the current may concentrate in some chips where a large current is likely to flow due to variations in the quality of the product. + By providing a wide portion T) of the mold region 13, variations between chips during high current operation can be reduced.

[0064] The silicon carbide semiconductor device 40 according to the embodiment is manufactured in the same manner as in the conventional manufacturing method. For example, it is formed as follows. First, n + The starting substrate (semiconductor wafer) 11 is, for example, 5×10 18 / cm 3 A silicon carbide four-layer periodic hexagonal crystal (4H-SiC) substrate doped with about 1000 nm of nitrogen (N) is prepared. + On the front surface of the starting substrate 11, - 1.0 × 10 15 / cm 3 Over 1.0 x 10 17 / cm 3 The following nitrogen doped n - A type epitaxial layer is grown to form a semiconductor substrate 30 .

[0065] Next, by photolithography and ion implantation of p-type impurities such as aluminum, one or more p-type impurities constituting a pn diode are formed in the surface region of the front surface of the semiconductor substrate 30 in the active region 10. + The p-type region 13 and the FLR 24 are selectively formed. + The p-type region 13 is formed in a stripe shape. + The mold region 13 is voided by a void width D. Next, the entire front surface of the semiconductor substrate 30 is protected by covering it with, for example, a carbon (C) protective film, and then the ion-implanted impurities are activated by heat treatment.

[0066] Next, an oxide film is formed over the entire front surface of the semiconductor substrate 30. Next, openings are formed by selectively removing the oxide film using photolithography and etching. Next, a metal material film is formed on the surface of the oxide film, extending from the surface of the oxide film to the front surface (surface) of the semiconductor substrate 30 within the openings in the oxide film, using a method such as sputtering.

[0067] After this, the metal material film is subjected to a first sintering process using heat treatment to generate an aluminum-nickel-silicon (Al-Ni-Si) compound in the openings of the oxide film, and then the excess metal (excess portion) on the oxide film and in the openings of the oxide film is removed.

[0068] Next, the Al—Ni—Si compound is subjected to a second sintering by heat treatment, which generates nickel silicide in the Al—Ni—Si compound, turning the Al—Ni—Si compound into a nickel silicide film 33 that forms an ohmic junction with the semiconductor substrate 30.

[0069] Next, etching is performed using a resist film as a mask to form contact holes 15a that penetrate the field oxide film 15 in the depth direction. Next, a titanium film 31 is formed by physical vapor deposition (PVD) such as sputtering, covering the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 within the contact holes 15a. Next, photolithography and etching are performed to leave the titanium film 31 only within the contact holes 15a.

[0070] Next, the titanium film 31 is sintered by heat treatment at a temperature of about 500°C for about 10 minutes. Next, an aluminum alloy film having a thickness of about 5 μm is formed on the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by physical vapor deposition such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching, leaving behind on the surface of the titanium film 31 as an aluminum alloy film 32 that will become the front electrode 14.

[0071] Next, the back surface (n + After nickel or titanium is formed on the entire back surface of mold starting substrate 11, a heat treatment is performed to form back electrode 19. Rapid thermal processing (RTA) or laser annealing is used for the heat treatment. Thereafter, the protective film on the front surface of semiconductor substrate 30 is removed, and then semiconductor substrate 30 is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 40 of the embodiment.

[0072] As described above, according to the embodiment, p + The mold region is depleted to a width of 1.0 μm or less. - Since there is no Schottky barrier in the contact area between the type drift region and the nickel silicide film (ohmic metal), there is no threshold for the forward applied voltage VF, and operation is possible from the low VF region. -This blocks leakage current from the contact area between the die drift region and the nickel silicide film, preventing defective chips.

[0073] As described above, the present disclosure is not limited to the above-described embodiments, but can be modified in various ways without departing from the spirit of the present disclosure, and can be applied to semiconductor devices having ohmic electrodes that form ohmic contacts with p-type regions arranged in a predetermined pattern.

[0074] Specifically, for example, the present disclosure relates to a p-type region (or a p-type region disposed between the p-type region and the main surface of the semiconductor substrate). + The present invention is useful for a silicon carbide semiconductor device configured to reduce the contact resistance between a p-type contact region and an ohmic electrode, and a semiconductor device configured such that an ohmic electrode making an ohmic contact with a p-type region is in contact with an oxide film. [Industrial Applicability]

[0075] As described above, the semiconductor device according to the present disclosure is useful as a power semiconductor device used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0076] 10, 110 active area 11, 111n + Starting substrate 12, 112 n - Type Drift Region 13, 113 p that constitutes a pn diode + type area 14, 114 Front electrode 15, 115 Field oxide 15a Contact hole 19, 119 Back electrode 20, 120 Edge termination area 20a, 120a connecting area 21, 121 JTE structure - type area 22, 122 JTE structure -- type area 23, 123 n + Mold channel stopper region 24, 124 Field Limiting Ring (FLR) 30, 130 Semiconductor substrate 31, 131 Titanium film 32, 132 Aluminum alloy film 33, 133 Nickel silicide film 35 Leakage current 36 Depletion layer 37 Contact area 40, 140 Silicon carbide semiconductor device

Claims

1. a semiconductor substrate of a first conductivity type; a first conductivity type region provided inside the semiconductor substrate and exposed to a first main surface of the semiconductor substrate; a second conductivity type region selectively provided in a surface region of the first conductivity type region in contact with the first conductivity type region; a silicide film in ohmic contact with the second conductivity type region; an electrode in contact with the silicide film and forming a Schottky junction with the first conductivity type region; Equipped with The semiconductor device is characterized in that the silicide film has a contact region in contact with the first conductivity type region.

2. 2. The semiconductor device according to claim 1, wherein the contact region is located within 0.5 [mu]m from the second conductivity type region in a plan view.

3. 2. The semiconductor device according to claim 1, wherein the contact region is sandwiched between the second conductivity type regions.

4. 4. The semiconductor device according to claim 3, wherein the distance between the plurality of second conductivity type regions sandwiching the contact region is 1 [mu]m or less.

5. 2. The semiconductor device according to claim 1, wherein the silicide film contains any one of Ni, Ti, and Al.

6. 2. The semiconductor device according to claim 1, wherein the second conductivity type regions and the contact regions are alternately provided to form a stripe pattern as a whole.

7. 7. The semiconductor device according to claim 6, wherein the distance between the second conductivity type regions between the stripes is 1.0 [mu]m or more and 5.0 [mu]m or less.

8. 2. The semiconductor device of claim 1, wherein the contact region comprises a 3C-SiC structure.

9. 2. The semiconductor device according to claim 1, further comprising a back electrode on a back surface of the semiconductor substrate.

10. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of SiC or GaN.

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