Matrix arithmetic circuit

Abstract

To reduce a circuit area of an arithmetic circuit capable of supporting operations with a plurality of precisions.SOLUTION: A plurality of second computing units 2 are arranged in a matrix, each of the second computing units 2 having a plurality of first computing units 3 and auxiliary computing units 4 connected to the plurality of first computing units 3, respectively. In each of the plurality of second computing units 2, each of the first computing units 3 performs multiplication between a partial matrix generated by dividing multipliers of a matrix product and a partial matrix generated by dividing multiplicands to calculate a partial matrix product. The auxiliary computing unit 4 performs digit alignment and addition for the partial matrix products calculated by the plurality of first computing units 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a matrix calculation circuit. [Background technology]

[0002] In recent years, floating-point arithmetic has been widely used in applications executed in HPC (High Performance Computing) (HPC applications) and applications implementing ML (Machine Learning) (ML applications).

[0003] Furthermore, many of these HPC and ML applications use matrix multiplication, but since matrix multiplication, which operates on floating-point data, takes a long time to calculate, there is a demand for accelerators to speed up this process.In addition, in general multiplication circuits that realize floating-point operations, the longest calculation time is spent on processing by the integer multiplier of the mantissa (or significand).

[0004] Furthermore, in floating-point arithmetic, multiple precision (bit width) numbers such as FP (Floating Point) 64, FP32, and FP16 are used depending on the application. FP32 multiplication requires 24 x 24-bit integer multiplication, and FP64 multiplication requires 53 x 53-bit integer multiplication. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-33813 Summary of the Invention [Problem to be solved by the invention]

[0006] To support multi-precision floating-point operations, the accelerator must implement multiple arithmetic circuits for each precision, which increases the circuit area. In addition, the arithmetic circuits for unused precisions are not operational, which reduces the utilization rate of the arithmetic units.

[0007] In one aspect, the present invention aims to reduce the circuit area of ​​an arithmetic circuit that can handle multi-precision arithmetic. [Means for solving the problem]

[0008] For this reason, this matrix operation circuit is a matrix operation circuit that performs a matrix multiplication operation, and includes a plurality of second operation units arranged in a lattice pattern, each second operation unit having a plurality of first operation units and auxiliary operation units connected to each of the plurality of first operation units. In each of the plurality of second operation units, each of the plurality of first operation units calculates a partial matrix product by multiplying a submatrix generated by dividing a multiplier of the matrix multiplication by a submatrix generated by dividing a multiplicand, and the auxiliary operation unit aligns and adds the partial matrix products calculated by each of the plurality of first operation units. [Effects of the Invention]

[0009] According to one embodiment, it is possible to reduce the circuit area of ​​an arithmetic circuit that can handle multi-precision arithmetic. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram illustrating a schematic configuration of an arithmetic circuit according to an embodiment. [Figure 2] FIG. 1 is a diagram for explaining a Wallace tree. [Figure 3] FIG. 1 is a diagram illustrating the structure of a Wallace tree. [Figure 4] FIG. 1 is a diagram illustrating the structure of a Wallace tree. [Figure 5] FIG. 1 is a diagram illustrating the structure of a Wallace tree. [Figure 6]FIG. 1 illustrates a Wallace tree for a 53×53-bit integer multiplier that includes four Wallace trees for 24×24-bit integer multipliers. [Figure 7] FIG. 7 is a layout diagram of the Wallace tree illustrated in FIG. 6. [Figure 8] 8 is a diagram showing the configuration of each Wallace tree of four low-precision multipliers and auxiliary arithmetic units that constitute the Wallace tree for the 53×53-bit integer multiplier illustrated in FIGS. 6 and 7. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the matrix calculation circuit will be described with reference to the drawings. However, the embodiments shown below are merely examples, and are not intended to exclude the application of various modifications and techniques not explicitly stated in the embodiments. In other words, the present embodiment can be implemented with various modifications within the scope of its purpose. Furthermore, each figure does not intend to include only the components shown in the figure, but can also include other functions, etc.

[0012] (A) Basic configuration FIG. 1 is a diagram schematically illustrating the configuration of an arithmetic circuit according to an embodiment.

[0013] The arithmetic circuit 1 shown in Fig. 1 is a multiplication circuit configured as a two-dimensional systolic array, and performs matrix multiplication (X = A * B). In Fig. 1, the left-right direction corresponds to the row direction, and the up-down direction corresponds to the column direction.

[0014] The present arithmetic circuit 1 is capable of performing operations with multiple precisions (bit widths). In this embodiment, the arithmetic circuit 1 is capable of operating by switching between two types of arithmetic modes: a low-precision calculation mode in which data with a first precision is processed, and a high-precision calculation mode in which data with a second precision higher than the first precision is processed. The low-precision calculation mode is an example of the first calculation mode, and the high-precision calculation mode is an example of the second calculation mode.

[0015] The arithmetic circuit 1 has a plurality of (four in the example shown in FIG. 1) high-precision multipliers 2. Hereinafter, the high-precision multipliers 2 may be represented by the symbol bMUL. The high-precision multipliers 2 may be identified by combining the symbol bMUL with a unique identification value. In FIG. 1, the four high-precision multipliers 2 are represented by the symbols bMUL00, bMUL01, bMUL10, and bMUL11. In the symbols representing these high-precision multipliers 2, the numerical values ​​00, 01, 10, and 11 are examples of identification values.

[0016] In the arithmetic circuit 1, the multiple high precision multipliers 2 are arranged in a two-dimensional lattice, and are aligned in both the row and column directions.

[0017] 1, bMUL10 is placed below bMUL00, and bMUL01 is placed to the right of bMUL00. Also, bMUL11 is placed to the right of bMUL10 and below bMUL01.

[0018] The high-precision multipliers 2 function in high-precision calculation mode. Each high-precision multiplier 2 has a plurality of low-precision multipliers 3 (four in the example shown in FIG. 1). In the low-precision calculation mode, the plurality of low-precision multipliers 3 included in the calculation circuit 1 function as a two-dimensional systolic array as a whole. The processing performed by the low-precision multipliers 3 as a two-dimensional systolic array in this low-precision calculation mode is known, and a description thereof will be omitted.

[0019] Hereinafter, the low-precision multiplier 3 may be represented by the symbol sMUL. Furthermore, by combining this symbol sMUL with a unique identification value, multiple low-precision multipliers 3 may be identified.

[0020] In the example shown in Figure 1, bMUL00 has sMUL0L0L, sMUL0H0L, sMUL0L0H, and sMUL0H0H. Also, bMUL10 has sMUL1L0L, sMUL1H0L, sMUL1L0H, and sMUL1H0H. Furthermore, bMUL01 has sMUL0L1L, sMUL0H1L, sMUL0L1H, and sMUL0H1H. Also, bMUL11 has sMUL1L1L, sMUL1H1L, sMUL1L1H, and sMUL1H1H.

[0021] In the codes representing these low-precision multipliers 3, a character string such as 0L0H formed by combining 0L, 1L, 0H, and 1H is an example of an identification value.

[0022] In each high precision multiplier 2, the multiple low precision multipliers 3 are arranged in the row and column directions, forming a two-dimensional lattice configuration. As a result, in the arithmetic circuit 1, the multiple low precision multipliers 3 are arranged in the row and column directions. In the arithmetic circuit 1 illustrated in FIG. 1, 16 low precision multipliers 3 are arranged in a 4 row by 4 column lattice configuration. In the arithmetic circuit 1, the high precision multipliers 2 and the low precision multipliers 3 can be said to share a circuit. The high precision multiplier 2, which is configured by integrating multiple (four in the example shown in FIG. 1) low precision multipliers 3, operates as a high precision two-dimensional systolic array circuit.

[0023] 1, in bMUL00, sMUL0H0L is placed below sMUL0L0L and sMUL0L0H is placed to the right of sMUL0L0L. Also, sMUL0H0H is placed to the right of sMUL0H0L and below sMUL0L0H.

[0024] Similarly, in bMUL10, sMUL1H0L is placed below sMUL1L0L, and sMUL1L0H is placed to the right of sMUL1L0L. Also, sMUL1H0H is placed to the right of sMUL1H0L and below sMUL1L0H.

[0025] In bMUL01, sMUL0H1L is placed below sMUL0L1L, and sMUL0L1H is placed to the right of sMUL0L1L. Also, sMUL0H1H is placed to the right of sMUL0H1L, below sMUL0L1H. Furthermore, in bMUL11, sMUL1H1L is placed below sMUL1L1L, and sMUL1L1H is placed to the right of sMUL1L1L. Also, sMUL1H1H is placed to the right of sMUL1H1L, below sMUL1L1H.

[0026] In the arithmetic circuit 1, each low-precision multiplier 3 arranged in the row direction is connected by a signal line arranged along the row direction, and each low-precision multiplier 3 arranged in the column direction is connected by a signal line arranged along the column direction.

[0027] Each high-precision multiplier 2 is also provided with an auxiliary arithmetic unit 4. The auxiliary arithmetic unit 4 is connected via a communication line to all of the low-precision multipliers 3 included in the high-precision multiplier 2 in which it is mounted (hereinafter, sometimes referred to as its own high-precision multiplier 2). The auxiliary arithmetic unit 4 may be represented by the symbol exADD.

[0028] In the arithmetic circuit 1 configured as described above, for example, the multiplier (A) of the matrix product is input from the left end of the two-dimensional lattice, and the multiplicand (B) of the matrix product is input from the top end of the two-dimensional lattice, each divided into multiple submatrices.

[0029] 1, the multiplier A is divided into two submatrices A0 and A1 (A=A0, A1). In addition, the submatrix A0 is divided into two submatrices A0L and A0H (A0=A0L, A0H), and the submatrix A1 is divided into two submatrices A1L and A1H (A1=A1L, A1H).

[0030] Submatrix A0L is the lower bits of submatrix A0, and submatrix A0H is the upper bits of submatrix A0. Furthermore, submatrix A1L is the lower bits of submatrix A1, and submatrix A1H is the upper bits of submatrix A1. Hereinafter, when there is no particular distinction between submatrix A0L and A1L, they will be referred to as submatrix A#L, and when there is no particular distinction between submatrix A0H and A1H, they will be referred to as submatrix A#H. Hereinafter, when there is no particular distinction between submatrix A0 and A1, they will be referred to as submatrix A#. However, # is 0 or 1.

[0031] Then, the submatrix A0L is input to each of the low-precision multipliers 3 that make up the row starting from sMUL0L0L. Also, the submatrix A0H is input to each of the low-precision multipliers 3 that make up the row starting from sMUL0H0L. Furthermore, the submatrix A1L is input to each of the low-precision multipliers 3 that make up the row starting from sMUL1L0L. Also, the submatrix A1H is input to each of the low-precision multipliers 3 that make up the row starting from sMUL1H0L.

[0032] Meanwhile, the multiplicand B is divided into two submatrices B0 and B1 (B = B0, B1). In addition, the submatrix B0 is divided into two submatrices B0L and B0H (B0 = B0L, B0H), and the submatrix B1 is divided into two submatrices B1L and B1H (B1 = B1L, B1H).

[0033] Submatrix B0L is the lower bits of submatrix B0, and submatrix B0H is the upper bits of submatrix B0. Submatrix B1L is the lower bits of submatrix B1, and submatrix B1H is the upper bits of submatrix B1. Hereinafter, when submatrix B0L and B1L are not particularly distinguished, they will be referred to as submatrix B#L, and when submatrix B0H and B1H are not particularly distinguished, they will be referred to as submatrix B#H. Hereinafter, when submatrix B0 and B1 are not particularly distinguished, they will be referred to as submatrix B#. Submatrix A#H, A#L, B#H, and B#L may be referred to as low-precision values. Submatrix A# and B# may be referred to as high-precision values.

[0034] Then, the submatrix B0L is input to each of the low-precision multipliers 3 that make up the column starting with sMUL0L0L. Also, the submatrix B0H is input to each of the low-precision multipliers 3 that make up the column starting with sMUL0L0H. Furthermore, the submatrix B1L is input to each of the low-precision multipliers 3 that make up the column starting with sMUL0L1L. Also, the submatrix B1H is input to each of the low-precision multipliers 3 that make up the column starting with sMUL0L1H.

[0035] The input submatrix may be propagated sequentially between the plurality of low-precision multipliers 3 that make up each row and each column.

[0036] Each low-precision multiplier 3 multiplies the input submatrix of the multiplier by the input submatrix of the multiplicand to calculate a submatrix product.

[0037] The low-precision multiplier 3 receives the low-precision value A#L or A#H and the low-precision value B#L or B#H as input, and performs low-precision multiplication of the partial matrix products (A#L*B#L, A#L*B#H, A#H*B#L or A#H*B#H).

[0038] For example, in bMUL00, sMUL0L0L calculates the partial matrix product (A0L*B0L) using the input submatrices A0L and B0L, and sMUL0H0L calculates the partial matrix product (A0H*B0L) using the input submatrices A0H and B0L. Also, sMUL0L0H calculates the partial matrix product (A0L*B0H) using the input submatrices A0L and B0H, and sMUL0H0H calculates the partial matrix product (A0H*B0H) using the input submatrices A0H and B0H.

[0039] In FIG. 1, the partial matrix products calculated by each low-precision multiplier 3 are shown in parentheses.

[0040] In the arithmetic circuit 1, in the low-precision calculation mode, input is made in accordance with the operation of a two-dimensional systolic array, and the original matrix product (X=A*B) is obtained by adding up the partial matrix products calculated in all the low-precision multipliers 3.

[0041] On the other hand, in the high precision calculation mode, in each high precision multiplier 2, each low precision multiplier 3 inputs the calculated value of the partial matrix product to the auxiliary calculator 4 of that high precision multiplier 2.

[0042] The auxiliary arithmetic unit 4, for example, adds bits of the high-precision input that are not input to the low-precision multiplier 3 to the result of digit alignment of the partial matrix products calculated in each low-precision multiplier 3 mounted in its own high-precision multiplier 2, and calculates the result as the high-precision multiplication result. The input is made in accordance with the operation of the two-dimensional systolic array, and the partial matrix products calculated in all the high-precision multipliers 2 included in the arithmetic circuit 1 are added together to obtain the original matrix product (X=A*B).

[0043] (B) Explanation of application examples Below is an example in which this arithmetic circuit 1 is applied to multi-precision arithmetic (integer multiplication). In the following, an example is shown in which each of the low-precision multipliers 3 is a partial sum addition circuit formed using a Wallace tree.

[0044] A Wallace tree can be constructed from a set of full adders (FA). A full adder is a circuit that takes three bit values ​​as input, has one carry, and one output. A full adder can be expressed as (x, y, z) → (s, c).

[0045] FIG. 2 is a diagram for explaining a Wallace tree, where (a) shows a 4×4-bit integer multiplication, and (b) shows a Wallace tree that realizes the 4×4-bit integer multiplication shown in (a).

[0046] The integer multiplier computes 4x4 bit integer multiplication as binary long division. A Wallace tree is used to add the partial products digit by digit.

[0047] In the diagram shown by symbol (a) in Figure 2, if the input of the partial product of each digit is represented by a black circle and the carry from the lower digit is represented by a white circle, the Wallace tree can be represented by a diamond-shaped arrangement as shown by symbol (b).

[0048] 3 to 5 are diagrams showing the configuration of a Wallace tree. In these figures, (a) shows numerical information representing the configuration of a Wallace tree, and (b) shows the size of the Wallace tree.

[0049] In Figure 3(a), for each digit (i-th digit) of the Wallace tree used in 4x4-bit integer multiplication, the number of inputs for each digit, the number of carries from the lower digit, the number of terms to be summed, and the number of full adders are shown.

[0050] When expressing the area, height, and width of a Wallace tree in terms of the number of full adders, they can be calculated using the following formulas (1), (2), and (3), respectively. Note that N is the number of bits. In the following formulas, the units are the number of full adders (FAs).

[0051] Area=N*(N-1) ···(1) Height = N*2-2 (2) Width=N*2=8 ···(3) In the case of 4×4-bit integer multiplication, N=4, so the area, height, and width can be calculated as follows using equations (1) to (3).

[0052] Area=12(FAs) Height = 6 (FAs) Width = 8 (FAs) The Wallace tree thus obtained has a size as shown by reference symbol (b) in FIG.

[0053] Figure 4(a) shows the number of inputs to each digit (i-th digit) of the Wallace tree used in 24 × 24 bit integer multiplication in FP32, the number of carries from the lower digit, the number of terms to be summed, and the number of full adders.

[0054] Based on the above formulas (1), (2), and (3), the area, height, and width of the Wallace tree used in the 24×24-bit integer multiplication used in FP32 are calculated.

[0055] In the case of 24×24 bit integer multiplication, N=24, so the area, height, and width can be calculated as follows using equations (1) to (3).

[0056] Area=552(FAs) Height = 46 (FAs) Width = 48 (FAs) The Wallace tree thus obtained has a size as shown by reference symbol (b) in FIG.

[0057] Figure 5(a) shows the number of inputs for each digit (i-th digit) of the Wallace tree used in 53 × 53-bit integer multiplication in FP64, the number of carries from the lower digit, the number of terms to be summed, and the number of full adders.

[0058] Based on the above formulas (1), (2), and (3), the area, height, and width of the Wallace tree used in the 53×53-bit integer multiplication used in FP64 are calculated.

[0059] In the case of 53×53 bit integer multiplication, N=53, so the area, height, and width can be calculated as follows using equations (1) to (3).

[0060] Area=2756(FAs) Height = 104 (FAs) Width = 106 (FAs) The Wallace tree thus obtained has a size as shown by reference symbol (b) in FIG.

[0061] As described above, in this arithmetic circuit 1, a high-precision multiplier 2 is formed by combining a plurality of low-precision multipliers 3 and auxiliary arithmetic units 4.

[0062] Here, by combining a Wallace tree for a low-precision integer multiplier with the auxiliary arithmetic unit 4 connected thereto, it is possible to configure a Wallace tree for an integer multiplier that is compatible with both low and high precision.

[0063] For example, a Wallace tree for a 53×53-bit integer multiplier can be configured by combining, as the low-precision multiplier 3, four Wallace trees for a 24×24-bit integer multiplier and the auxiliary arithmetic unit 4 connected thereto. The Wallace tree for a 53×53-bit integer multiplier configured in this way functions as the high-precision multiplier 2.

[0064] That is, by using a circuit that operates on FP32 data as the low-precision multiplier 3 and combining it with an auxiliary calculator 4 connected to it, a high-precision multiplier 2 that operates on FP64 data can be configured.

[0065] FIG. 6 is a diagram illustrating a Wallace tree for a 53×53-bit integer multiplier including four Wallace trees for 24×24-bit integer multipliers, and FIG. 7 is a layout diagram of the Wallace tree illustrated in FIG.

[0066] 6 and 7 show an example in which a Wallace tree for a 53×53 bit integer multiplier is used as bMUL00 in FIG.

[0067] In FIG. 6, four Wallace trees for 24×24-bit integer multipliers are arranged at the four corners of a rectangular (diamond) Wallace tree for a 53×53-bit integer multiplier.

[0068] These four Wallace trees for 24×24-bit integer multipliers correspond to the low-precision multipliers 3 (sMUL0L0L, sMUL0H0L, sMUL0L0H, sMUL0H0H) in the arithmetic circuit 1 illustrated in FIG.

[0069] In addition, auxiliary arithmetic units 4 (exADD) are formed between the four Wallace trees for 24×24-bit integer multipliers so as to fill the gaps between adjacent Wallace trees for 24×24-bit integer multipliers. As a result, each of the four Wallace trees for 24×24-bit integer multipliers is connected to an auxiliary arithmetic unit 4.

[0070] 6 and 7, the auxiliary arithmetic unit 4 is composed of 624 full adders. Also, each of the four low-precision multipliers 3 is composed of 552 full adders. Therefore, the high-precision multiplier 2 illustrated in FIGS. 6 and 7 is composed of 2832 full adders.

[0071] Fig. 8 is a diagram showing the configuration of each Wallace tree of the four low-precision multipliers 3 and auxiliary arithmetic unit 4 that constitute the Wallace tree for the 53 × 53-bit integer multiplier illustrated in Fig. 6 and Fig. 7. Fig. 8 shows numerical information representing the configuration of each Wallace tree for the four 24 × 24-bit integer multipliers that constitute the Wallace tree for the 53 × 53-bit integer multiplier, as well as numerical information representing the configuration of the Wallace tree of the auxiliary arithmetic unit 4 (exADD).

[0072] In the high-precision multiplier 2 illustrated in FIG. 8, sMUL0L0H is placed in the upper bit positions 76 to 29, and sMUL0H0H is placed in the lower left bit positions 100 to 53, adjacent to a portion of sMUL0L0H (bit positions 76 to 53). Also, sMUL0L0L is placed to the right of sMUL0H0H and to the lower right of sMUL0L0H, in bit positions 47 to 0, adjacent to a portion of sMUL0L0H (bit positions 47 to 29). Also, sMUL0H0L is placed to the lower right of sMUL0H0H and to the lower left of sMUL0L0L, in bit positions 76 to 29. This sMUL0H0L is placed adjacent to a portion of sMUL0H0H (bit positions 76 to 53) and also adjacent to a portion of sMUL0L0L (bit positions 47 to 29). In this way, in the bit addition configuration of the high precision multiplier 2 illustrated in FIG. 8, each low precision multiplier 3 is arranged with a 24×24 bit full adder configuration shifted in bit digit.

[0073] Also, below sMUL0H0L, an auxiliary arithmetic unit 4 (exADD) is placed adjacent to sMUL0H0L at bit digits 105 to 24. The auxiliary arithmetic unit 4 has inputs from each digit.

[0074] The high-precision multiplier 2 (bMUL) has an input of 2809 (=53 × 53) bits, but the four inputs of the Wallace tree for the 24 × 24-bit integer multiplier only have 2304 (=24 × 24 × 4) bits, leaving a shortage of 505 input bits. These missing input bits become the input of the auxiliary arithmetic unit 4 (exADD). The auxiliary arithmetic unit 4 aligns and adds these input bits and the output bits of the four low-precision multipliers 3 using a Wallace tree, and outputs a 53 × 53-bit multiplication result.

[0075] Arranging the Wallace trees for low-precision integer multipliers two-dimensionally on the top, bottom, left, and right of the diamond shape of the Wallace tree for high-precision integer multipliers matches the arrangement of the low-precision multipliers 3 in a two-dimensional systolic array configuration, and also achieves area reduction from the viewpoint of circuit layout.

[0076] As shown in the layout diagram of Figure 7, by arranging the Wallace trees (low-precision multipliers 3) that calculate A0{L,H}*B0{L,H} close together in two dimensions, the length of the wiring to the auxiliary arithmetic unit 4 and the wiring related to the carry can be shortened, thereby reducing the circuit area and improving the circuit speed.

[0077] (C) Effects In the arithmetic circuit 1 configured as described above, a plurality of high-precision multipliers 2 (second arithmetic units) are arranged in a lattice pattern, each of which has a plurality of low-precision multipliers 3 (first arithmetic units) arranged in a lattice pattern and auxiliary arithmetic units 4 connected to each of the plurality of low-precision multipliers 3. In each high-precision multiplier 2, each low-precision multiplier 3 calculates a partial matrix product by multiplying a submatrix generated by dividing a multiplier (A) of the matrix product by a submatrix generated by dividing a multiplicand (B) (A#L*B#L, A#L*B#H, A#H*B#L, or A#H*B#H). The auxiliary arithmetic unit 4 then aligns and adds the partial matrix products calculated by each low-precision multiplier 3.

[0078] This allows one arithmetic circuit 1 to handle both multi-precision (high-precision and low-precision) multiplications, thereby reducing the circuit area.

[0079] For example, a Wallace tree for a 53 × 53-bit integer multiplier shared with four 24 × 24-bit integer multipliers requires only 5% more full adders than a Wallace tree for a 53 × 53-bit integer multiplier without sharing. Furthermore, the circuit delay increases by only one full adder, so the operating speed of the circuit is the same.

[0080] Generally, in a multiplier using a Wallace tree, most of the circuit area is taken up by the Wallace tree. Therefore, in this arithmetic circuit 1, the effect of reducing the circuit area is particularly large, since it can handle both high- and low-precision multiplication with roughly the same circuit area and circuit delay as an arithmetic circuit that only performs high-precision arithmetic.

[0081] The arithmetic circuit 1 can operate by switching between two calculation modes: a low-precision calculation mode (first calculation mode) for processing low-precision (first precision) data, and a high-precision calculation mode (second calculation mode). In the low-precision calculation mode, low-precision matrix multiplication can be performed by adding up the partial matrix products calculated by all of the low-precision multipliers 3 provided in the arithmetic circuit 1. In the high-precision calculation mode, high-precision matrix multiplication can be performed by adding up the calculation results of the auxiliary calculation units 4 provided in the multiple high-precision multipliers 2.

[0082] Furthermore, since each of the low-precision multipliers 3 is a circuit that operates on FP32 data and each of the high-precision multipliers 2 is a circuit that operates on FP64 data, it is possible to perform matrix multiplication in FP32 and matrix multiplication in FP64 in the arithmetic circuit 1.

[0083] Furthermore, since each of the low-precision multipliers 3 is a partial product addition circuit formed using a Wallace tree, it is possible to reliably realize an arithmetic circuit 1 that supports both low-precision and high-precision matrix multiplication operations.

[0084] (D) Other Regardless of the above-described embodiment, various modifications can be made without departing from the spirit of the present embodiment.

[0085] For example, in the above-described embodiment, the high-precision multiplier 2 has four low-precision multipliers 3, so that the four low-precision multipliers 3 and one high-precision multiplier 2 share a circuit, but this is not limiting. For example, in a two-dimensional systolic array configuration in which the low-precision multiplier 3 is a circuit that operates on FP32 data and the high-precision multiplier 2 is a circuit that operates on FP64 data, the low-precision multiplier 3 may be further divided into four half-precision (i.e., FP16) multipliers to configure 16 (=4×4) half-precision multipliers.

[0086] In the above-described embodiment, a circuit that operates on FP32 data is used as the low-precision multiplier 3, and by combining this with the auxiliary calculation unit 4 connected thereto, the high-precision multiplier 2 that operates on FP64 data is configured. That is, an example is shown in which the low-precision multiplier 3 is a circuit that operates on FP32 data, and the high-precision multiplier 2 is a circuit that operates on FP64 data, but the present invention is not limited to this.

[0087] For example, the low-precision multiplier 3 may be a circuit that operates on FP16 data, and the high-precision multiplier 2 may be a circuit that operates on FP32 data. This allows the arithmetic circuit 1 to perform matrix multiplication in FP16 and matrix multiplication in FP32.

[0088] Alternatively, the low-precision multiplier 3 may be a circuit that operates on 8-bit floating-point data, and the high-precision multiplier 2 may be a circuit that operates on FP16 data. This allows the arithmetic circuit 1 to perform both 8-bit floating-point matrix multiplication and FP16 matrix multiplication.

[0089] Furthermore, the above disclosure will enable those skilled in the art to implement and manufacture the present embodiment. [Explanation of symbols]

[0090] 1 Arithmetic circuit 2 High-precision multiplier 3 Low-Precision Multiplier 4 Auxiliary computing unit

Claims

1. A matrix calculation circuit for performing a matrix multiplication operation, a plurality of second computing units each having a plurality of first computing units and auxiliary computing units connected to each of the plurality of first computing units are arranged in a lattice pattern; In each of the plurality of second computing units, each of the plurality of first computing units calculates a partial matrix product by multiplying a submatrix generated by dividing a multiplier of a matrix product by a submatrix generated by dividing a multiplicand; The auxiliary computing unit performs digit alignment and addition of the partial matrix products calculated by each of the plurality of first computing units. A matrix operation circuit comprising:

2. the matrix operation circuit is operable by switching between two calculation modes: a first calculation mode for processing data with a first precision, and a second calculation mode for processing data with a second precision higher than the first precision; In the first calculation mode, the partial matrix products calculated by each of the plurality of first calculators included in the matrix calculation circuit are added together; In the second calculation mode, the calculation results of the auxiliary calculation units of the plurality of second calculation units are added together.

2. The matrix operation circuit according to claim 1.

3. each of the plurality of first computing units is a circuit that performs a computation on data of a floating point (FP) 32; Each of the plurality of second computing units is a circuit that performs an operation on FP64 data.

2. The matrix operation circuit according to claim 1.

4. each of the plurality of first computing units is a circuit that performs an operation on data of FP16; Each of the plurality of second computing units is a circuit that performs a computation on data of FP32.

2. The matrix operation circuit according to claim 1.

5. each of the plurality of first arithmetic units is a circuit that performs an operation on 8-bit floating-point data; Each of the plurality of second computing units is a circuit that performs a computation on data of FP32.

2. The matrix operation circuit according to claim 1.

6. Each of the plurality of first computing units is a partial product addition circuit formed using a Wallace tree.

2. The matrix operation circuit according to claim 1.

7. The plurality of first computing units are arranged in a lattice pattern.

7. The matrix operation circuit according to claim 1, wherein:

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