Oxide semiconductor memory device having dual channel structure and method for manufacturing the same

Abstract

To provide an oxide semiconductor memory device having a dual channel structure that achieves excellent program and erase operations, and a method for manufacturing the same.SOLUTION: An oxide semiconductor memory device comprises a tunnel layer 200, a charge trap layer 300, a barrier layer 400, and a gate electrode 500 disposed on a dual channel structure 100 that uses both the oxide semiconductor channel 100 and a polysilicon channel 120, and achieves high mobility characteristics in the oxide semiconductor channel while also enabling erase operations.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an oxide semiconductor memory device having a dual channel structure and a manufacturing method thereof, and more particularly to an oxide semiconductor memory device having a dual channel structure including both an oxide semiconductor channel and a polysilicon channel and a manufacturing method thereof. [Background technology]

[0002] Currently, demand for memory semiconductors is exploding due to the Fourth Industrial Revolution. The explosive growth of IoT (Internet-on-Things) devices has led to an increase in memory demand for edge devices such as smartphones, and the use of deep learning has led to an explosive increase in the amount of data that must be handled.

[0003] To keep up with this technological trend, non-volatile memory semiconductors are required to have high integration density and excellent memory performance, and 3D NAND flash memory is dominating the non-volatile memory market because it is significantly superior to other methods in terms of element integration density.

[0004] 3D NAND flash memory not only functions as a non-volatile memory, but is also attracting attention as a CIM (Computing-In-Memory) element for the coming AI era. CIM elements perform MAC (Multiply and Accumulation) operations, which are the core operations of deep learning, at the memory stage, and can operate more efficiently by reducing frequent data transfers between logic and memory.

[0005] With the latest trend in memory-based devices, it is more essential than ever to perform read, write, and erase operations as quickly as possible and to store large amounts of information (e.g., 3 bits per cell) in a single device.

[0006] Meanwhile, to improve the performance of 3D NAND flash memory, research is being conducted extensively on oxide semiconductors as an alternative to silicon-based semiconductor elements. In terms of materials, research results have been reported on single-, binary-, and ternary-component compounds based on indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO). Oxide semiconductors have the advantage of exhibiting superior mobility compared to hydrogenated amorphous silicon.

[0007] However, oxide semiconductors have a wider energy bandgap than polysilicon channels and a Fermi level pinning phenomenon due to certain defects, which can limit the generation of hole current for the erase operation. In other words, oxide semiconductors have limitations in the erase operation despite their excellent program operation. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention is intended to solve the above problems, and an object of the present invention is to achieve an erase operation while maintaining the high mobility characteristics of the oxide semiconductor channel by using both an oxide semiconductor channel and a polysilicon channel. [Means for solving the problem]

[0009] According to one aspect of the present invention, there is disclosed an oxide semiconductor memory element having a dual channel structure, including: a dual channel including a plurality of channels; a tunnel layer located on the dual channel; a charge trapping layer located on the tunnel layer and trapping injected charges; a blocking layer located on the charge trapping layer; and a gate electrode located on the blocking layer and to which an on voltage and an off voltage are applied from a gate bias circuit.

[0010] According to an embodiment, an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the dual channel includes an oxide semiconductor channel and a polysilicon channel.

[0011] According to an embodiment, an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the polysilicon channel of the dual channel is formed between the oxide semiconductor channel and the tunnel layer.

[0012] According to an embodiment, an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the polysilicon channel has a thickness of 1 nm or more and 2 nm or less.

[0013] According to an embodiment, an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the oxide semiconductor channel includes at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO).

[0014] According to another aspect of the present invention, a method for manufacturing an oxide semiconductor memory device having a dual channel structure is disclosed, comprising: (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word lines and insulating films and forming a blocking layer on an inner surface of the hole; (c) forming a charge trapping layer on the inner surface of the blocking layer; (d) forming a tunnel layer on the inner surface of the charge trapping layer; (e) forming a polysilicon channel on the inner surface of the tunnel layer; (f) forming an oxide semiconductor channel on the inner surface of the polysilicon channel; and (g) removing the insulating film and depositing a metal along the word line to form a gate electrode.

[0015] According to an embodiment, a method for manufacturing an oxide semiconductor memory device having a dual channel structure is disclosed, wherein step (e) deposits the polysilicon channel using an oxidation process and a selective wet etch process.

[0016] According to an embodiment, a method for manufacturing an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the polysilicon channel has a thickness of 1 nm or more and 2 nm or less.

[0017] According to an embodiment, a method for manufacturing an oxide semiconductor memory device having a dual channel structure is disclosed, wherein the oxide semiconductor channel includes at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO). [Effects of the Invention]

[0018] According to the present invention, the mobility characteristics can be improved by using an oxide semiconductor channel. Furthermore, according to the present invention, an erase operation can be realized by including a polysilicon channel along with an oxide semiconductor channel.

[0019] Furthermore, according to the present invention, by forming a polysilicon channel of 2 nm or less, electrons can be distributed in the oxide semiconductor channel when the memory element is in an on-state where it operates.

[0020] Furthermore, according to the present invention, the polysilicon channel is deposited using an oxidation process and a selective wet etching process, so that the surface roughness of the polysilicon channel can be improved. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a diagram illustrating a configuration of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention; [Figure 2] 1 is a graph illustrating program operation characteristics of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention; [Figure 3] 1 is a graph illustrating erase operation characteristics of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention. [Figure 4] 1 is a graph showing program and erase operation characteristics of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention; [Figure 5] 1 is a graph illustrating quantum mechanical effects in an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention; [Figure 6] 1 is a flowchart illustrating a method for manufacturing an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The above-mentioned objects, features, and advantages of the present invention will become more apparent through the following embodiments in conjunction with the accompanying drawings. The following specific structural and functional descriptions are provided merely for the purpose of describing embodiments according to the inventive concept, and the embodiments according to the inventive concept may be implemented in various forms and should not be construed as being limited to the embodiments described in this specification or application. Since the embodiments according to the inventive concept may be modified in various ways and may have various forms, specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, it should be understood that this is not intended to limit the embodiments according to the inventive concept to the specific disclosed form, but includes all modifications, equivalents, or alternatives falling within the spirit and technical scope of the present invention. Terms such as "first" and "second" may be used to describe various components, but the components are not limited to these terms. The terms may be used solely to distinguish one component from another. For example, a first component may be designated a "second component," and similarly, a second component may be designated a "first component," without departing from the scope of the inventive concept. When a component is referred to as being coupled or connected to another component, it should be understood that the component may be directly coupled or connected to the other component, but that other components may also exist between the components. On the other hand, when a component is referred to as being directly coupled or connected to another component, it should be understood that there are no other components between them. Other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly. The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. It should be understood that in this specification, terms such as "comprise" or "have" specify the presence of performed features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. The present invention will now be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numerals in each drawing indicate the same elements.

[0023] FIG. 1 is a diagram showing the configuration of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention. Referring to FIG. 1, an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention may include a dual channel 100 including a polysilicon channel 120 and an oxide semiconductor channel 110, a tunnel layer 200 located on the dual channel 100, a charge trapping layer 300 located on the tunnel layer 200 and trapping injected charges, a blocking layer 400 located on the charge trapping layer 300, and a gate electrode 500 located on the blocking layer 400 and to which an on voltage and an off voltage are applied from a gate bias circuit.

[0024] The dual channel 100 can include a polysilicon channel 120 and an oxide semiconductor channel 110. The oxide semiconductor channel 110 can include at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO). The oxide semiconductor channel 110 has a characteristic of high electron mobility. The dual channel 100 may include a polysilicon channel 120 between the oxide semiconductor channel 110 and the tunnel layer 200. In this case, the thickness (T) of the polysilicon channel 120 may be 1 nm or more and 2 nm or less. The thickness (T) of the polysilicon channel 120 is required for a conduction path, i.e., for electrons to be formed in the oxide semiconductor channel 110. If the thickness (T) of the polysilicon channel 120 is 2 nm or less, a conduction path is formed in the oxide semiconductor channel 110 due to a quantum mechanical effect, and the improvement in electron mobility of the oxide semiconductor channel 110 can be utilized as is.

[0025] 2 to 4 are graphs showing the program operation and erase operation characteristics of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention.

[0026] First, referring to FIG. 2, it can be seen that the oxide semiconductor memory device having a dual channel structure according to the present invention has an improved threshold voltage of a positive value during a program operation in which a positive voltage is applied, similar to a conventional oxide semiconductor memory device.

[0027] 3, it can be seen that the oxide semiconductor memory device having a dual channel structure according to the present invention has a threshold voltage shifted to the negative direction during an erase operation in which a negative voltage is applied, unlike a conventional oxide semiconductor memory device. Conventional oxide semiconductor memory devices have a problem in that they have a wider energy bandgap than polysilicon channels and a Fermi level pinning phenomenon due to certain defects, which may restrict hole current generation for an erase operation. The oxide semiconductor memory device having a dual channel structure according to the present invention can overcome the drawbacks of conventional oxide semiconductor memory devices by adding a polysilicon channel 120 to an oxide semiconductor channel 110 .

[0028] 4 shows the threshold voltages of the program and erase operations of an oxide semiconductor memory device having a dual channel structure according to the present invention as a function of time. Referring to FIG. 4, it can be seen that the oxide semiconductor memory device having a dual channel structure according to the present invention operates normally, with the threshold voltage rising in a positive direction during a program operation and the threshold voltage falling in a negative direction during an erase operation.

[0029] FIG. 5 is a graph showing the quantum mechanical effect of an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention. 5, the number of electrons (# of electrons) is at its maximum in the oxide semiconductor channel 110, and the thickness (T) of the polysilicon channel 120 may be 2 nm or less. That is, the thickness (T) of the polysilicon channel 120 is necessary because a conduction path is formed in the oxide semiconductor channel 110. If the thickness (T) of the polysilicon channel 120 is set to 2 nm or less, a conduction path is formed in the oxide semiconductor channel 110 due to a quantum mechanical effect, and the improvement in electron mobility of the oxide semiconductor channel 110 can be utilized as is.

[0030] FIG. 6 is a flowchart illustrating a method for manufacturing an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention. 6, a method for manufacturing an oxide semiconductor memory device having a dual channel structure according to an embodiment of the present invention may include the steps of alternately stacking word lines (WL) and interlayer dielectrics (ILDs) (S100), forming cylindrical holes in the stacked word lines (WL) and interlayer dielectrics (ILDs) and forming blocking layers 400 on inner surfaces of the holes (S200), forming charge trapping layers 300 on inner surfaces of the blocking layers 400 (S300), forming tunnel layers 200 on inner surfaces of the charge trapping layers 300 (S400), forming polysilicon channels 120 on inner surfaces of the tunnel layers 200 (S500), forming oxide semiconductor channels on inner surfaces of the polysilicon channels 120 (S600), and removing the insulating layers (ILDs) and depositing metal along the word lines (WLs) to form gate electrodes 500 (S700).

[0031] Here, steps S100 to S400 and step S700 may follow a general three-dimensional flash memory device process. In step S500, the method for fabricating an oxide semiconductor memory device having a dual channel structure according to the present invention deposits the polysilicon channel 120 using an oxidation process and a selective wet etch process. Low-pressure chemical vapor deposition (LPCVD), a typical method for depositing polysilicon channels, is unable to deposit a polysilicon channel 120 with a thickness of 2 nm or less. Reducing the thickness of a thick polysilicon channel by a dry etch process after depositing it deteriorates the surface roughness of the polysilicon channel 120 and the oxide semiconductor channel 110, making it impossible to improve the string current. Therefore, the present invention deposits a thin polysilicon channel 120 with a thickness of 2 nm or less using an oxidation process and a selective wet etch process, thereby maintaining the surface roughness of the polysilicon channel 120 and the oxide semiconductor channel 110 at a predetermined level.

[0032] In step S600, the oxide semiconductor channel 110 may be deposited including at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO).

[0033] Although the preferred embodiments of the present invention have been described above, the embodiments disclosed in the present invention are for the purpose of explanation and not for the purpose of limiting the technical idea of ​​the present invention. Therefore, the technical idea of ​​the present invention includes not only each of the disclosed embodiments but also combinations of the disclosed embodiments, and the scope of the technical idea of ​​the present invention is not limited to such embodiments. Furthermore, a person having ordinary skill in the art to which the present invention pertains may make various changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered to fall within the scope of the present invention as equivalents. [Explanation of symbols]

[0034] 100: Dual channel 110: Oxide semiconductor channel 120: Polysilicon channel 200: Tunnel layer 300: Charge trapping layer 400:Isolation layer 500: Gate electrode

Claims

1. Dual channels include multiple channels; a tunnel layer located on the dual channel; a charge trapping layer located on the tunnel layer and trapping the injected charges; a blocking layer overlying the charge trapping layer; a gate electrode located on the blocking layer, to which an on-voltage and an off-voltage are applied from a gate bias circuit; 1. An oxide semiconductor memory element having a dual channel structure, comprising:

2. The dual channel The oxide semiconductor memory device having a dual channel structure according to claim 1 , comprising an oxide semiconductor channel and a polysilicon channel.

3. The polysilicon channel of the dual channel is The oxide semiconductor memory device having a dual channel structure according to claim 2 , wherein the oxide semiconductor is formed between the oxide semiconductor channel and the tunnel layer.

4. The polysilicon channel is The oxide semiconductor memory device having a dual channel structure according to claim 3 , wherein the thickness is 1 nm or more and 2 nm or less.

5. The oxide semiconductor channel is Indium oxide (In ２ O ３ ), zinc oxide (ZnO), gallium oxide (Ga ２ O ３ 3. The oxide semiconductor memory device having a dual channel structure according to claim 2, comprising at least one of indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO).

6. (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word line and insulating film, and forming a blocking layer on an inner circumferential surface of the hole; (c) forming a charge trapping layer on the inner circumferential surface of the blocking layer; (d) forming a tunnel layer on an inner circumferential surface of the charge trapping layer; (e) forming a polysilicon channel on an inner surface of the tunnel layer; (f) forming an oxide semiconductor channel on an inner circumferential surface of the polysilicon channel; (g) removing the insulating film and depositing metal along the word line to form a gate electrode; 1. A method for manufacturing an oxide semiconductor memory device having a dual channel structure, comprising:

7. The step (e) comprises:

7. The method of claim 6, wherein the polysilicon channel is deposited using an oxidation process and a selective wet etching process.

8. The polysilicon channel is 8. The method for manufacturing an oxide semiconductor memory device having a dual channel structure according to claim 7, wherein the thickness is 1 nm or more and 2 nm or less.

9. The oxide semiconductor channel is Indium oxide (In ２ O ３ ), zinc oxide (ZnO), gallium oxide (Ga ２ O ３ 7. The method for manufacturing an oxide semiconductor memory device having a dual channel structure according to claim 6, wherein the oxide semiconductor memory device comprises at least one of indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO).

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