Semiconductor memory device including ferroelectric capacitor and manufacturing method thereof

Abstract

To provide: a semiconductor memory device capable of securing a memory window and changing a threshold voltage by forming a ferroelectric capacitor on a rear face of a channel structure; and a manufacturing method thereof.SOLUTION: The present invention relates to a semiconductor memory device capable of preventing electrons from being captured in an interface layer (IL) by adding a ferroelectric capacitor 400 to a location where an oxide filler is formed inside a channel structure 300 and forming the ferroelectric capacitor between a channel structure and a lower electrode 500. Electrons are prevented from being captured in the IL of the semiconductor memory device, thereby prolonging a lifetime of the semiconductor memory device, securing a high memory window and enhancing data storage characteristics.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device including a ferroelectric capacitor and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same, in which a ferroelectric capacitor is added at a position where an oxide filler is formed inside a channel structure, and the ferroelectric capacitor is formed between the channel structure and a lower electrode, thereby preventing electrons from being trapped in an interface layer (IL). [Background technology]

[0002] Currently, demand for memory semiconductors is exploding due to the Fourth Industrial Revolution. The explosive growth of IoT (Internet-on-Things) devices has led to an increase in memory demand for edge devices such as smartphones, and the use of deep learning has led to an explosive increase in the amount of data that must be handled.

[0003] To keep up with this technological trend, non-volatile memory semiconductors are required to have high integration density and excellent memory performance, and 3D NAND flash memory is dominating the non-volatile memory market because it is significantly superior to other methods in terms of element integration density.

[0004] 3D NAND flash memory not only functions as a non-volatile memory, but is also attracting attention as a CIM (Computing-In-Memory) element for the coming AI era. CIM elements perform MAC (Multiply and Accumulation) operations, which are the core operations of deep learning, at the memory stage, and can operate more efficiently by reducing frequent data transfers between logic and memory.

[0005] With the latest trend in memory-based devices, it is more essential than ever to perform read, write, and erase operations as quickly as possible and to store large amounts of information (e.g., 3 bits per cell) in a single device.

[0006] For this type of 3D NAND flash memory, process technology has been developed in the direction of Z-scaling, which stacks cells along the z-axis while reducing the spacing between word lines and the given height. Integration through Z-scaling helps to secure more layers by reducing the spacing between cells, but XY-scaling, which reduces the diameter of the cell, must be accompanied to increase gate control strength to suppress the short channel effect.

[0007] However, there is a limit to how much the cell diameter can be reduced, and reducing the cell diameter can cause problems such as a deterioration in memory window and data storage performance.

[0008] Meanwhile, in dual mechanism memory devices, the remanent polarization of the ferroelectric and the charges trapped in the charge trapping layer cause the threshold voltage to change in the same direction, resulting in a memory window that is more than twice as large as that of conventional charge trapping type flash memory devices, thereby solving the problem of reliability degradation that occurs when applying QLC (Quad Level Cell).

[0009] However, conventional FeFET memory devices containing such ferroelectrics have the drawback of having a short lifespan due to electrons being gradually trapped in the interface layer (IL) formed between the ferroelectric and the channel, and a low memory window of less than 3V. Summary of the Invention [Problem to be solved by the invention]

[0010] The present invention is intended to solve the above problems, and an object of the present invention is to add a ferroelectric capacitor to a memory cell, lower the threshold voltage regardless of XYZ-scaling, secure a wide memory window, configure a bottom electrode in a semiconductor memory, and form a ferroelectric between the channel structure and the bottom electrode to prevent electrons from being trapped in the IL (Interface Layer). [Means for solving the problem]

[0011] According to one aspect of the present invention, there is disclosed a semiconductor memory device including: a stacked structure including word lines and insulators alternately stacked on a substrate; a channel structure connected to the substrate through the stacked structure; a vertical insulator interposed between the stacked structure and the channel structure, the vertical insulator including a tunnel layer in contact with the channel structure, a blocking layer in contact with the stacked structure, and a charge trapping layer interposed between the tunnel layer and the blocking layer; and a ferroelectric capacitor connected to an inner surface of the channel structure and forming an electrode, the ferroelectric capacitor including a ferroelectric thin film and a metal coating.

[0012] According to an embodiment, a semiconductor memory device is disclosed, wherein the ferroelectric capacitor is configured such that one side of the ferroelectric thin film is connected to the channel structure and the metal coating is connected to the other side of the ferroelectric thin film.

[0013] According to an embodiment, a semiconductor memory element is disclosed, characterized in that the ferroelectric thin film includes at least one of HfO2 (Hafnium Oxide), an insulating thin film of HfO2 containing at least one element of Al, Zr, La, Si, Gd, Sc, Y, Ge, and N, ZrO2 (Zirconium Oxide), Al2O3 (Aluminum Oxide), and BST (Barium Strontium Titanate).

[0014] According to an embodiment, a semiconductor memory device is disclosed, wherein the metal coating includes at least one of TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), and MoN (Molybdenum Nitride).

[0015] According to an embodiment, a semiconductor memory device is disclosed in which a bias voltage of −5V or more and +5V or less is applied to the ferroelectric capacitor. According to an embodiment, a semiconductor memory device is disclosed, wherein the ferroelectric thin film has a thickness of 10 nm or less.

[0016] According to another aspect of the present invention, there is disclosed a semiconductor memory device connected to a positive terminal and a negative terminal of a power supply, the semiconductor memory device comprising: a stacked structure connected to the positive terminal of the power supply and to which a voltage is applied; a vertical insulator formed on a lower surface of the stacked structure; a channel structure formed on the lower surface of the vertical insulator and connected to a substrate; a ferroelectric capacitor formed on the lower surface of the channel structure; and a lower electrode formed on the lower surface of the ferroelectric capacitor and connected to the negative terminal of the power supply.

[0017] According to an embodiment, a semiconductor memory device is disclosed, wherein the ferroelectric capacitor includes a ferroelectric material based on HfO2 (Hafnium Oxide).

[0018] According to an embodiment, a semiconductor memory device is disclosed, wherein the HfO2 (Hafnium Oxide)-based ferroelectric material has a thickness greater than 0 nm and less than or equal to 30 nm.

[0019] According to an embodiment, a semiconductor memory device is disclosed, wherein the ferroelectric capacitor includes a perovskite-based ferroelectric material including at least one of PbTiO3, SrTiO3, and CaTiO3.

[0020] According to an embodiment, a semiconductor memory device is disclosed, wherein the perovskite-based ferroelectric material containing at least one of PbTiO3, SrTiO3, and CaTiO3 has a thickness greater than 0 nm and less than or equal to 100 nm.

[0021] According to an embodiment, a semiconductor memory device is disclosed, wherein the ferroelectric capacitor includes a two-dimensional material including at least one of α-In2Se3 and SnS. According to an embodiment, a semiconductor memory device is disclosed, wherein the channel structure has a thickness greater than 0 nm and less than or equal to 100 nm.

[0022] According to an embodiment, a semiconductor memory device is disclosed, further comprising: a first thin film formed between the channel structure and the ferroelectric capacitor; and a second thin film formed between the ferroelectric capacitor and the lower electrode.

[0023] According to another aspect of the present invention, a method for manufacturing a semiconductor memory device is disclosed, comprising: (a) alternately stacking word lines and insulators to form a stacked structure; (b) forming a cylindrical hole in the stacked structure and forming a blocking layer on an inner surface of the hole; (c) forming a charge trapping layer on an inner surface of the blocking layer; (d) forming a tunnel layer on an inner surface of the charge trapping layer; (e) forming a channel structure on an inner surface of the tunnel layer; (f) forming a ferroelectric capacitor on an inner surface of the channel structure; and (g) removing a thin film layer included in the insulator and depositing a metal along the word line to form a gate electrode.

[0024] According to an embodiment, a method for manufacturing a semiconductor memory device is disclosed, wherein the step (f) further includes: (f-1) forming a ferroelectric thin film on an inner surface of the channel structure; and (f-2) forming a metal coating on an inner surface of the ferroelectric thin film.

[0025] According to an embodiment, a method for manufacturing a semiconductor memory device is disclosed, wherein in step (f-1), the ferroelectric thin film includes at least one of HfO2 (Hafnium Oxide), an insulating thin film containing at least one element of Al, Zr, La, Si, Gd, Sc, Y, Ge, and N in HfO2, Zirconium Oxide (ZrO2), Aluminum Oxide (Al2O3), and Barium Strontium Titanate (BST).

[0026] According to an embodiment, a method for manufacturing a semiconductor memory device is disclosed, wherein in step (f-2), the metal coating includes at least one of TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), and MoN (Molybdenum Nitride). [Effects of the Invention]

[0027] According to the present invention, a memory window of a semiconductor memory device can be secured. Furthermore, according to the present invention, a ferroelectric capacitor can be formed on the back surface of the channel structure to change the threshold voltage.

[0028] Furthermore, according to the present invention, electrons are not trapped in the IL (Interface Layer) of the semiconductor memory device, so that the life of the semiconductor memory device can be extended. Furthermore, according to the present invention, a higher memory window can be ensured. Furthermore, according to the present invention, data storage characteristics can be improved. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a perspective cross-sectional view illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2] 1 is a plan view illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 3] 2 is a flowchart illustrating a manufacturing sequence of a semiconductor memory device according to an embodiment of the present invention. [Figure 4] 1 is a plan view illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 5] 10 is a plan view illustrating a configuration of a semiconductor memory device according to another embodiment of the present invention; [Figure 6] 1 is a graph illustrating threshold voltage as a function of thickness of a channel structure of a semiconductor memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0030] The above-mentioned objects, features, and advantages of the present invention will become more apparent through the following embodiments in conjunction with the accompanying drawings. The following specific structural and functional descriptions are provided merely for the purpose of describing embodiments according to the inventive concept, and the embodiments according to the inventive concept may be implemented in various forms and should not be construed as being limited to the embodiments described in this specification or application. Since the embodiments according to the inventive concept may be modified in various ways and may have various forms, specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, it should be understood that this is not intended to limit the embodiments according to the inventive concept to the specific disclosed form, but includes all modifications, equivalents, or alternatives falling within the spirit and technical scope of the present invention. Terms such as "first" and "second" may be used to describe various components, but the components are not limited to these terms. The terms may be used solely to distinguish one component from another. For example, a first component may be designated a "second component," and similarly, a second component may be designated a "first component," without departing from the scope of the inventive concept. When a component is referred to as being coupled or connected to another component, it should be understood that the component may be directly coupled or connected to the other component, but that other components may also exist between the components. On the other hand, when a component is referred to as being directly connected or directly attached to another component, it should be understood that there are no other components between them. Other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly. The terms used in this specification are merely used to describe particular embodiments and are not intended to limit the present invention. The singular forms include the plural forms unless the context clearly dictates otherwise. It should be understood that, in this specification, terms such as "comprise" or "have" specify the presence of implemented features, numbers, steps, operations, components, parts, or combinations thereof, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. The present invention will now be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numerals in each drawing indicate the same elements.

[0031] FIG. 1 is a perspective cross-sectional view showing the configuration of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a plan view showing the configuration of a semiconductor memory device according to an embodiment of the present invention.

[0032] 1 and 2, a semiconductor memory device according to an embodiment of the present invention may include a stacked structure 100 including a word line 110 and an insulator 120, a channel structure 300 that penetrates the stacked structure 100 and is connected to a substrate, a vertical insulator 200 that is interposed between the stacked structure 100 and the channel structure 300 and includes a tunnel layer 210 in contact with the channel structure 300, a blocking layer 230 in contact with the stacked structure 100, and a charge trapping layer 220 interposed between the tunnel layer 210 and the blocking layer 230, and a ferroelectric capacitor 400 that is connected to an inner surface of the channel structure 300 and forms an electrode.

[0033] The stacked structure 100 may have word lines 110 and insulators 120 alternately stacked on a substrate. The word lines 110 of the 3D semiconductor memory are repeatedly arranged across multiple layers in the stacked structure 100, allowing individual access to memory cells in each layer. That is, the word lines 110 may enable access to specific cells in the stacked structure 100 in the vertical direction. The insulators 120 may be located between the word lines 110 to prevent electrical interference between metal wirings. The insulators 120 may be made of a material such as SiO2 or SiCOH.

[0034] The channel structure 300 may include a polysilicon channel or an oxide semiconductor channel. The oxide semiconductor channel may include at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO). The oxide semiconductor channel has the property of high electron mobility.

[0035] The vertical insulator 200 may include a blocking layer 230, a charge trapping layer 220, and a tunneling layer 210. The blocking layer 230 corresponds to a blocking layer portion of the charge trapping memory device.

[0036] The charge trapping layer 220 is located on the blocking layer 230 and is configured to capture charges injected from the stacked structure 100. This means that when a negative gate voltage is applied to the stacked structure 100, charges that have passed through the tunnel layer 210 cannot move to the channel structure 300 due to the blocking layer 230, and are instead trapped on the charge trapping layer 220.

[0037] The charge trapping layer 220 is preferably made of silicon nitride (Si3N4), but may also be made of any one or a combination of aluminum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, and niobium oxide.

[0038] As described above, the tunnel layer 210 is provided so that when a negative gate voltage is applied to the stacked structure 100 , charges in the stacked structure 100 move to the charge trapping layer 220 via the tunnel layer 210 .

[0039] Such a tunnel layer 210 serves as an energy barrier layer for preventing tunneling of charges, and is preferably made of an oxide film such as silicon oxide (SiO2).

[0040] Furthermore, the process of forming the tunnel layer 210 is preferably performed by a thermal oxidation process or a radical oxidation process, and the thickness of the tunnel layer 210 is preferably formed to be smaller than the thickness of the blocking layer and equal to or smaller than the thickness of the charge trapping layer 220, as described above, and the thickness of the tunnel layer 210 is preferably 5 nm to 10 nm, for example.

[0041] Meanwhile, the stacked structure 100 is located on top of the blocking layer 230, and an on voltage and an off voltage are applied from the gate bias circuit. As described above, in the present invention, a negative gate voltage corresponds to the on voltage, and when a negative gate voltage is applied, charges in the stacked structure 100 move to the charge trapping layer 220 via the blocking layer 230.

[0042] Such a layered structure 100 preferably includes conductive nitrides such as TiN, TaN, and WN. In addition, the material may include conductive oxynitrides (for example, TiON, etc.) or combinations thereof (for example, TiSiN, TiAlON, etc.), or may include polysilicon doped with a high concentration of impurities.

[0043] Of course, instead of the nitride form as described above, conductive metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), molybdenum (Mo), or alloys thereof may be included, but these materials are merely examples and the present invention is not limited thereto.

[0044] Meanwhile, an oxide filler is generally formed in the center of the channel structure 300, and the semiconductor memory device according to the present invention may include a ferroelectric capacitor 400 where the oxide filler is located. The ferroelectric capacitor 400 may be connected to the inner surface of the channel structure 300 to form an electrode. The ferroelectric capacitor 400 may include a ferroelectric thin film 410 and a metal coating 420. The ferroelectric thin film 410 may include at least one of hafnium oxide (HfO2), a ferroelectric material; an insulating thin film containing at least one element of Al, Zr, La, Si, Gd, Sc, Y, Ge, and N in HfO2; zirconium oxide (ZrO2); aluminum oxide (Al2O3); and barium strontium titanate (BST).

[0045] The metal coating 420 may include at least one of TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), and MoN (Molybdenum Nitride). The ferroelectric thin film 410 is characterized in that electric polarization occurs within it when an electric field is applied, and the polarization remains even when the electric field is removed.

[0046] At this time, a bias voltage of -5V or more and +5V or less may be applied to the ferroelectric capacitor 400. The ferroelectric capacitor 400 is formed on the back surface of the channel structure 300, and the threshold voltage may be changed by the body effect. That is, the threshold voltage may be changed by the ferroelectric capacitor 400, thereby ensuring a memory window of the semiconductor memory device. At this time, the body effect coefficient, which indicates the degree to which the threshold voltage changes due to the body effect, may be proportional to the thickness of the gate dielectric film.

[0047] Furthermore, the ferroelectric capacitor 400 can operate as a typical flash memory when the electrodes are maintained at a grounded state (=0V). In this case, while an inversion layer is not formed in the channel structure 200, an electric field can be instantaneously formed on the ferroelectric capacitor 400 side due to a potential increase on the channel structure 200 side. In other words, both polarization switching within the ferroelectric and the charge trapping mechanism used in typical flash memories can be used.

[0048] FIG. 3 is a flowchart illustrating a manufacturing sequence of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 3, a method for manufacturing a semiconductor memory device according to an embodiment of the present invention may include the steps of: forming a stacked structure 100 by alternately stacking word lines 110 and insulators 120 (S100); forming a blocking layer 400 (S200); forming a charge trapping layer 500 (S300); forming a tunnel layer 300 (S400); forming a channel structure 200 (S500); forming a ferroelectric capacitor (S600); and forming a gate electrode (S700).

[0049] In step S100, word lines 110 and insulators 120 may be alternately stacked to form a stacked structure 100. The word lines 110 of the semiconductor memory are repeatedly arranged across multiple layers in the stacked structure 100, allowing individual access to memory cells in each layer. That is, the word lines 110 may vertically enable access to specific cells in the stacked structure 100. The insulators 120 may be positioned between the word lines 110 to prevent electrical interference between metal wirings. The insulators 120 may be made of a material such as SiO2 or SiCOH.

[0050] Steps S200 to S500 may follow a general semiconductor memory device process. In step S500, the channel structure 200 may include either a polysilicon channel or an oxide semiconductor channel.

[0051] In step S600, a ferroelectric capacitor 400 may be formed on the inner circumferential surface of the channel structure 300. This may include a step (S610) of forming a ferroelectric thin film 410 on the inner circumferential surface of the channel structure 300, and a step (S620) of forming a metal coating 420 on the inner circumferential surface of the ferroelectric thin film 410. The ferroelectric thin film 410 may include at least one of hafnium oxide (HfO2), an insulating thin film containing at least one element of Al, Zr, La, Si, Gd, Sc, Y, Ge, and N in HfO2, zirconium oxide (ZrO2), aluminum oxide (Al2O3), and barium strontium titanate (BST).

[0052] The metal coating 420 may include at least one of TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), and MoN (Molybdenum Nitride).

[0053] In step S700, the thin film layer such as SiN included in the insulator 120 is removed, and metal is deposited along the word line 110 to form a gate electrode.

[0054] 4 and 5 are plan views showing a partly cut away semiconductor memory element according to an embodiment of the present invention. 4, a semiconductor memory device according to an embodiment of the present invention may include a stacked structure 100, a vertical insulator 200, a channel structure 300, a ferroelectric capacitor 400, and a bottom electrode 500. The semiconductor memory device may be connected to the positive and negative terminals of a power source.

[0055] The stacked structure 100 is connected to the positive terminal of a power supply, and a voltage can be applied to the stacked structure 100. A program voltage (V PGM ) and erase voltage (V ERS ) can be applied.

[0056] The vertical insulator 200 may be formed on the lower surface of the stacked structure 100. The vertical insulator 200 may include a blocking layer 230, a charge trapping layer 220, and a tunneling layer 210. The vertical insulator 200 may be formed by sequentially stacking the blocking layer 230, the charge trapping layer 220, and the tunneling layer 210. The blocking layer 230, the charge trapping layer 220, and the tunneling layer 210 included in the vertical insulator 200 may be similar to the blocking layer, the charge trapping layer, and the tunneling layer used in a general semiconductor memory device.

[0057] The channel structure 300 may be formed on the lower surface of the vertical insulator 200 and connected to the substrate. The channel structure 300 may be made of any semiconductor material, including single-crystal silicon, polysilicon, or an oxide semiconductor. The oxide semiconductor channel may include at least one of indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZnO), and indium gallium zinc oxide (InGaZnO). In this case, the channel structure 300 may have a thickness greater than 0 nm and less than or equal to 100 nm to increase the threshold voltage.

[0058] Unlike conventional semiconductor memory devices, the ferroelectric capacitor 400 may be formed on the underside of the channel structure 300. The ferroelectric capacitor 400 may include a ferroelectric material based on HfO2 (Hafnium Oxide), a perovskite-based ferroelectric material including at least one of PbTiO3, SrTiO3, and CaTiO3, or a two-dimensional material including at least one of α-In2Se3 and SnS. In this case, to ensure ferroelectricity, the ferroelectric capacitor 400 may have a thickness of more than 0 nm and not more than 30 nm if it is made of a HfO2 (Hafnium Oxide)-based ferroelectric material. Also, if the ferroelectric capacitor 400 is made of a perovskite-based ferroelectric material including at least one of PbTiO3, SrTiO3, and CaTiO3, it may have a thickness of more than 0 nm and not more than 100 nm. In the semiconductor memory device according to the present invention, the ferroelectric capacitor 400 is formed on the lower surface of the channel structure 300, thereby preventing electrons from being trapped in the interface layer (IL).

[0059] The lower electrode 500 may be formed on the lower surface of the ferroelectric capacitor 400 and connected to the negative terminal of a power supply. When a conventional ferroelectric capacitor is formed between a channel structure and a stack structure, electrons in an inversion layer are trapped by an interface layer (IL) during programming, shortening the capacitor's lifespan. In the semiconductor memory device structure of the present invention, the interface layer (IL) is located between the channel structure 300 and the ferroelectric capacitor 400, so the problem of electron trapping during programming does not occur. In addition, during an erase operation, holes in the channel structure 300 move in the opposite direction to the interface layer (IL), so hole trapping does not occur.

[0060] FIG. 5 is a plan view showing a configuration of a semiconductor memory device according to another embodiment of the present invention. 5, a semiconductor memory device according to another embodiment of the present invention may include a stacked structure 100, a vertical insulator 200, a channel structure 300, a ferroelectric capacitor 400, and a bottom electrode 500. The semiconductor memory device may be connected to a positive terminal and a negative terminal of a power source. The semiconductor memory device according to another embodiment of the present invention may also include a first thin film 600_1 and a second thin film 600_2.

[0061] The first thin film 600_1 may be formed between the channel structure 300 and the ferroelectric capacitor 400, and the second thin film 600_2 may be formed between the ferroelectric capacitor 400 and the lower electrode 500. The semiconductor memory device according to the present invention can capture electrons and secure more memory windows by forming the first thin film 600_1 and the second thin film 600_2.

[0062] FIG. 6 is a graph illustrating threshold voltage as a function of thickness of a channel structure of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 6, it can be seen that the thinner the thickness of the channel structure 300 of the semiconductor memory device according to the embodiment of the present invention, the higher the efficiency of the threshold voltage.

[0063] In particular, it can be seen that the change in threshold voltage gradually increases when the thickness of the channel structure 300 is 100 nm or less. As the thickness of the channel structure 300 becomes sufficiently thin, a fully depleted state is reached, resulting in an increase in threshold voltage.

[0064] Although preferred embodiments of the present invention have been described above, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present invention. Therefore, the technical concept of the present invention includes not only each of the disclosed embodiments but also combinations of the disclosed embodiments, and the scope of the technical concept of the present invention is not limited by such embodiments. Furthermore, a person skilled in the art to which the present invention pertains may make various changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered equivalents within the scope of the present invention. [Explanation of symbols]

[0065] 100: Laminated structure 110: Word Line 120: Insulator 200: Vertical insulator 210: Tunnel layer 220: Charge trapping layer 230:Isolation layer 300: Channel structure 400: Ferroelectric capacitor 410: Ferroelectric thin film 420: Metal coating 500: Lower electrode 600_1: First thin film 600_2: Second thin film

Claims

1. a stacked structure including word lines and insulators alternately stacked on a substrate; a channel structure that penetrates the laminated structure and is connected to the substrate; a vertical insulator interposed between the stacked structure and the channel structure, the vertical insulator including a tunnel layer in contact with the channel structure, a blocking layer in contact with the stacked structure, and a charge trapping layer interposed between the tunnel layer and the blocking layer; a ferroelectric capacitor connected to an inner surface of the channel structure and forming an electrode thereon; Including, The ferroelectric capacitor is A semiconductor memory element comprising a ferroelectric thin film and a metal coating.

2. The ferroelectric capacitor is 2. The semiconductor memory device of claim 1, wherein one side of the ferroelectric thin film is connected to the channel structure, and the metal coating is connected to the other side of the ferroelectric thin film.

3. The ferroelectric thin film is HfO ２ (Hafnium Oxide), HfO ２ an insulating thin film containing at least one element selected from Al, Zr, La, Si, Gd, Sc, Y, Ge, and N; ZrO ２ (Zirconium Oxide), Al ２ O ３ 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises at least one of aluminum oxide (AuOxide) and barium strontium titanate (BST).

4. The metal coating is TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), Mo ２ 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device comprises at least one of N (Molybdenum Nitride).

5. The ferroelectric capacitor is 2. The semiconductor memory device according to claim 1, wherein a bias voltage of −5V or more and +5V or less is applied.

6. The ferroelectric thin film is 2. The semiconductor memory device according to claim 1, wherein the thickness is 10 nm or less.

7. A semiconductor memory device connected to a positive terminal and a negative terminal of a power supply, a laminated structure connected to the positive terminal of the power supply and to which a voltage is applied; a vertical insulator formed on the lower surface of the laminated structure; a channel structure formed on a lower surface of the vertical insulator and connected to a substrate; a ferroelectric capacitor formed on a lower surface of the channel structure; a lower electrode formed on a lower surface of the ferroelectric capacitor and connected to a negative terminal of the power supply; A semiconductor memory device comprising:

8. The ferroelectric capacitor is HfO ２ 8. The semiconductor memory device of claim 7, comprising a hafnium oxide-based ferroelectric material.

9. The HfO ２ (Hafnium Oxide)-based ferroelectric materials are 9. The semiconductor memory device according to claim 8, wherein the thickness is greater than 0 nm and less than or equal to 30 nm.

10. The ferroelectric capacitor is PbTiO ３ , SrTiO ３ , CaTiO ３ 8. The semiconductor memory device according to claim 7, comprising a perovskite-based ferroelectric material including at least one of:

11. The PbTiO ３ , SrTiO ３ , CaTiO ３ The perovskite-based ferroelectric material includes at least one of 11. The semiconductor memory device according to claim 10, wherein the thickness is greater than 0 nm and less than or equal to 100 nm.

12. The ferroelectric capacitor is α-In ２ Se ３ 8. The semiconductor memory device according to claim 7, comprising a two-dimensional material containing at least one of SnS.

13. The channel structure comprises:

8. The semiconductor memory device according to claim 7, wherein the thickness is greater than 0 nm and less than or equal to 100 nm.

14. a first thin film formed between the channel structure and the ferroelectric capacitor; 8. The semiconductor memory device of claim 7, further comprising: a second thin film formed between the ferroelectric capacitor and the lower electrode.

15. (a) forming a stacked structure by alternating word lines and insulators; (b) forming a cylindrical hole in the laminated structure and forming a blocking layer on the inner circumferential surface of the hole; (c) forming a charge trapping layer on the inner circumferential surface of the blocking layer; (d) forming a tunnel layer on an inner circumferential surface of the charge trapping layer; (e) forming a channel structure on an inner circumferential surface of the tunnel layer; (f) forming a ferroelectric capacitor on an inner circumferential surface of the channel structure; (g) removing the thin film layer included in the insulator and depositing metal along the word line to form a gate electrode; 2. A method for manufacturing a semiconductor memory device, comprising:

16. The step (f) includes: (f-1) forming a ferroelectric thin film on the inner circumferential surface of the channel structure; 16. The method of claim 15, further comprising: (f-2) forming a metal coating on an inner circumferential surface of the ferroelectric thin film.

17. In the step (f-1), the ferroelectric thin film is HfO ２ (Hafnium Oxide), HfO ２ an insulating thin film containing at least one element selected from Al, Zr, La, Si, Gd, Sc, Y, Ge, and N; ZrO ２ (Zirconium Oxide), Al ２ O ３ 17. The method of claim 16, wherein the material includes at least one of aluminum oxide (Aluminum Oxide) and barium strontium titanate (BST).

18. In the step (f-2), the metal coating is TiN (Titanium Nitride), TaN (Tantalum Nitride), CrN (Chromium Nitride), ZrN (Zirconium Nitride), AlN (Aluminum Nitride), W (Tungsten), WN (Tungsten Nitride), Mo (Molybdenum), Mo ２ 17. The method of claim 16, wherein the semiconductor memory device further comprises at least one of N (Molybdenum Nitride).

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