Dual switching memory device and method of manufacturing the same
Aluminum-doped hafnium oxide (Al-doped HfO2) in the blocking layer of dual switching memory devices addresses thermal instability issues, enhancing memory window and ferroelectricity, thus improving the reliability and speed of memory operations.
Patent Information
- Application Number
- JP2025037023
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-09-25
- Filing Date
- 2025-03-10
- Publication Date
- 2025-09-29
AI Technical Summary
3D NAND flash memory processes involving high-temperature steps degrade the leakage current characteristics and ferroelectricity of commonly used ferroelectric materials like HfZrO2, leading to reliability issues and reduced memory window in dual switching memory devices.
Employing aluminum-doped hafnium oxide (Al-doped HfO2) as the ferroelectric material in the blocking layer, which maintains ferroelectricity and improves thermal stability during high-temperature processes, combined with a specific composition ratio of hafnium to aluminum (23(Hf):1(Al) for optimal performance.
The use of Al-doped HfO2 enhances the memory window and maintains ferroelectricity without deterioration, even in high-temperature treatments, ensuring improved thermal stability and operating speed in dual switching memory devices.
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a dual switching memory device and a method for manufacturing the same, and more particularly to a dual switching memory device and a method for manufacturing the same, which can improve thermal stability during the manufacturing process and improve the operating speed and memory window of the memory device. [Background technology]
[0002] Currently, demand for memory semiconductors is exploding due to the Fourth Industrial Revolution. The explosive growth of IoT (Internet-on-Things) devices has led to an increase in memory demand for edge devices such as smartphones, and the use of deep learning has led to an explosive increase in the amount of data that must be handled.
[0003] To keep up with this technological trend, non-volatile memory semiconductors are required to have high integration density and excellent memory performance, and 3D NAND flash memory is dominating the non-volatile memory market because it is significantly superior to other methods in terms of element integration density.
[0004] 3D NAND flash memory not only functions as a non-volatile memory, but is also attracting attention as a CIM (Computing-In-Memory) element for the coming AI era. CIM elements perform MAC (Multiply and Accumulation) operations, which are the core operations of deep learning, at the memory stage, and can operate more efficiently by reducing frequent data transfers between logic and memory.
[0005] With the latest trend in memory-to-calculator devices, it is more essential than ever to perform memory read, write, and erase operations as quickly as possible and to store large amounts of information (e.g., 4 bits / cell) in a single device.
[0006] Meanwhile, in dual mechanism memory devices, the remanent polarization of the ferroelectric and the charges trapped in the charge trapping layer cause a shift in threshold voltage in the same direction, resulting in a memory window more than twice as large as that of conventional charge trapping flash memory devices. This solves the problem of reliability degradation that occurs when applying QLC (Quad Level Cell). However, HfZrO2, a commonly used ferroelectric material, has a drawback in that it is susceptible to high-temperature processes. 3D NAND flash memory processes involve high-temperature processes such as depositing a channel structure after depositing a gate insulating film and then source / drain activation. However, subsequent processes at temperatures exceeding 900°C can cause degradation of HfZrO2's leakage current characteristics and ferroelectricity. Summary of the Invention [Problem to be solved by the invention]
[0007] The present invention has been made to solve the above problems, and an object of the present invention is to improve the thermal stability during the process of a dual switching memory device, and to improve the operating speed and memory window of the memory device. [Means for solving the problem]
[0008] According to one aspect of the present invention, a dual switching memory element is disclosed, comprising: a blocking layer located on a channel structure; a charge trapping layer located on the blocking layer and trapping injected charges; a tunneling layer located on the charge trapping layer; and a gate electrode located on the tunneling layer and to which an on voltage and an off voltage from a gate bias circuit are applied, wherein the blocking layer contains a ferroelectric material so that both charge trapping and ferroelectric polarization switching are performed.
[0009] According to an embodiment, a dual switching memory element is disclosed, wherein the ferroelectric material is aluminum-doped hafnium oxide (Al-doped HfO2).
[0010] According to an embodiment, the aluminum-doped hafnium oxide (Al doped HfO2) has a composition ratio of hafnium and aluminum of T Hf :1(Al), and the T Hf is a natural number between 20 and 26.
[0011] According to an embodiment, a dual switching memory element is disclosed, wherein the composition ratio of hafnium to aluminum is 23(Hf):1(Al).
[0012] According to an embodiment, a dual switching memory element is disclosed, wherein the hafnium has an atomic concentration of 35% in the aluminum-doped hafnium oxide (Al doped HfO2), and the aluminum has an atomic concentration of 1.6% in the aluminum-doped hafnium oxide (Al doped HfO2).
[0013] According to another aspect of the present invention, a method for manufacturing a dual switching memory device is disclosed, including the steps of: (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word lines and insulating films and forming a tunnel layer on an inner peripheral surface of the hole; (c) forming a charge trapping layer on an inner peripheral surface of the tunneling layer; (d) forming a blocking layer on an inner peripheral surface of the charge trapping layer; (e) forming a channel structure on an inner peripheral surface of the blocking layer; and (f) removing the insulating film and depositing a metal along the word lines to form a gate electrode, wherein the blocking layer includes a ferroelectric material so that both charge trapping and ferroelectric polarization switching are performed.
[0014] According to an embodiment, a method for manufacturing a dual switching memory device is disclosed, wherein the ferroelectric material is aluminum-doped hafnium oxide (Al-doped HfO2).
[0015] According to an embodiment, the aluminum-doped hafnium oxide (Al doped HfO2) has a composition ratio of hafnium and aluminum of T Hf :1(Al), and the T Hf is a natural number between 20 and 26, inclusive.
[0016] According to an embodiment, a method for manufacturing a dual switching memory element is disclosed, wherein the composition ratio of hafnium to aluminum is 23(Hf):1(Al).
[0017] According to an embodiment, a method for manufacturing a dual switching memory device is disclosed, wherein the hafnium has an atomic concentration of 35% in the aluminum-doped hafnium oxide (Al doped HfO2), and the aluminum has an atomic concentration of 1.6% in the aluminum-doped hafnium oxide (Al doped HfO2). [Effects of the Invention]
[0018] According to the present invention, it is possible to obtain a blocking layer having excellent leakage current characteristics even in a high-temperature heat treatment process. Furthermore, according to the present invention, a larger memory window of the dual switching memory device can be secured. Furthermore, according to the present invention, the ferroelectricity can be maintained without deterioration even during a high-temperature heat treatment process. [Brief explanation of the drawings]
[0019] [Figure 1] 1 is a diagram illustrating a configuration of a dual switching memory device according to an embodiment of the present invention; [Figure 2] 10 is a graph illustrating ferroelectric characteristics as a function of aluminum concentration of a dual switching memory device according to an embodiment of the present invention. [Figure 3] 10 is a graph showing the relationship between electric polarization and voltage depending on the composition ratio of hafnium and aluminum in a dual switching memory element according to an embodiment of the present invention. FIG. [Figure 4] 1 is a flowchart illustrating a method for manufacturing a dual switching memory device according to an embodiment of the present invention. [Figure 5] 1 is a perspective cross-sectional view of a dual switching memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION
[0020] The above-mentioned objects, features, and advantages of the present invention will become more apparent through the following embodiments in conjunction with the accompanying drawings. The following specific structural and functional descriptions are provided merely for the purpose of illustrating embodiments according to the inventive concept. The embodiments according to the inventive concept may be embodied in various forms and should not be construed as being limited to the embodiments described in this specification or application. Because the embodiments according to the inventive concept may be variously modified and have various forms, specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, this is not intended to limit the embodiments according to the inventive concept to the specific disclosed form, but should be understood to include all modifications, equivalents, or alternatives falling within the spirit and technical scope of the present invention. Terms such as "first" and / or "second" may be used to describe various components, but the components are not limited to these terms. The terms are used solely to distinguish one component from another, for example, a first component may be called a second component, and similarly, a second component may be called a first component, without departing from the scope of the inventive concept. When a component is referred to as being coupled or connected to another component, it may be directly coupled or connected to the other component, but it should be understood that there may be other components between them. On the other hand, when a component is referred to as being directly coupled or connected to another component, it should be understood that there are no other components between them. Other expressions describing the relationship between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted similarly. The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.As used herein, terms such as "comprise" or "have" specify the presence of implemented features, numbers, steps, operations, components, parts, or combinations thereof, and should be understood not to preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with the contextual meaning of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. The present invention will now be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numerals in the various drawings refer to the same elements.
[0021] FIG. 1 is a diagram showing the configuration of a dual switching memory element according to an embodiment of the present invention. 1, a dual switching memory device 1000 according to an embodiment of the present invention includes a blocking layer 100 positioned on a channel structure, a charge trapping layer 200 positioned on the blocking layer 100, a tunneling layer 300 positioned on the charge trapping layer 200, and a gate electrode 400 positioned on the tunneling layer 300. Here, the channel structure may be made of any semiconductor material, including single-crystal silicon, polysilicon, or an oxide semiconductor.
[0022] Here, the dual switching memory device 1000 is configured to inject electrons through the gate electrode 400, rather than through the channel as in conventional charge trapping memory devices.
[0023] In the case of a conventional charge trap memory device, a positive gate voltage is applied to the gate electrode 400, and electrons are injected from the channel structure side, and V FB rises. Here, the V FB is the gate voltage required for the band of the channel structure to become flat.
[0024] However, in the case of conventional ferroelectric memory devices, when a positive gate voltage is applied, V FB is decreasing. Therefore, by configuring the structure in which electrons are injected by a negative gate voltage, V due to the gate voltage of the ferroelectric memory element and the charge trap memory can be reduced. FB The change direction of the can be aligned.
[0025] In addition, the blocking layer 100 corresponds to the blocking layer portion of a charge trapping memory device, and the present invention configures the blocking layer of such a conventional charge trapping memory device with a ferroelectric material. In particular, the dual switching memory device 1000 according to the present invention can use aluminum-doped hafnium oxide (Al-doped HfO2) for thermal stability during processing.
[0026] Furthermore, the thickness of the blocking layer 100 is preferably greater than the thickness of the charge trapping layer 200 and the thickness of the tunnel layer 300, which will be described later. For example, the thickness of the blocking layer 100 is preferably about 10 nm.
[0027] Meanwhile, the charge trapping layer 200 is located on the blocking layer 100 and is provided to capture charges injected from the gate electrode 400. When a negative gate voltage is applied to the gate electrode 400, charges that have passed through the tunneling layer 300 are prevented from moving to the channel structure (Si) by the blocking layer 100 and are instead trapped on the charge trapping layer 200.
[0028] Such a charge trap layer 200 is preferably typically silicon nitride (Si3N4). In addition to this, it can also be composed of any one of aluminum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, and niobium oxide, or a combination of these.
[0029] Furthermore, when the charge trap layer 200 is made of silicon nitride (Si3N4), it is preferably formed by a Chemical Vapor Deposition (CVD) method at 400°C to 800°C using SiH4 gas or SiCl2H2 gas and NH3 gas.
[0030] Also, silicon nitride (Si3N4) is preferably formed to have a composition ratio of nitrogen to silicon of 0.6 to 1.45 (0.6 < N / Si < 1.45).
[0031] The thickness of such a charge trap layer 200 is preferably formed to be the same as or greater than the tunnel layer 300 described later. As an example, the thickness of the charge trap layer 200 is preferably 5 nm to 8 nm.
[0032] On the other hand, the tunnel layer 300 is located above the charge trap layer 200 and below the gate electrode 400. As described above, when a negative gate voltage is applied to the gate electrode 400, the charge of the gate electrode 400 is provided to move to the charge trap layer 200 via the tunnel layer 300.
[0033] Such a tunnel layer 300 is provided as an energy barrier layer by charge tunneling and is preferably made of an oxide film such as silicon oxide (SiO2).
[0034] Furthermore, the process of forming the tunnel layer 300 is preferably carried out by a thermal oxidation process or a radical oxidation process, and the thickness of the tunnel layer 300 is preferably formed to be smaller than the thickness of the blocking layer and the same as or smaller than the thickness of the charge trapping layer 200, as described above, and the thickness of the tunnel layer 300 is preferably 4 nm to 6 nm, for example.
[0035] Meanwhile, the gate electrode 400 is located above the tunnel layer 300, and an on voltage and an off voltage are applied from a gate bias circuit. As described above, in the present invention, a negative gate voltage corresponds to an on voltage, and when a negative gate voltage is applied, charges in the gate electrode 400 move to the charge trapping layer 200 via the tunnel layer 300.
[0036] Such gate electrode 400 preferably comprises a conductive nitride such as TiN, TaN, and WN. In addition, the material may include conductive oxynitrides (for example, TiON, etc.) or combinations thereof (for example, TiSiN, TiAlON, etc.), or may include polysilicon doped with a high concentration of impurities.
[0037] Of course, instead of the nitride form as described above, conductive metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), molybdenum (Mo), or alloys thereof may be included, but these materials are merely examples and the present invention is not limited thereto.
[0038] FIG. 2 is a graph showing ferroelectric characteristics as a function of aluminum concentration of a dual switching memory device according to an embodiment of the present invention. Referring to FIG. 2, the dual switching memory device 1000 according to an embodiment of the present invention has ferroelectric characteristics that change depending on the aluminum concentration of the ferroelectric material of the blocking layer 100, which is aluminum-doped hafnium oxide (Al-doped HfO).
[0039] Here, O-Phase (Orthorhombic phase) is a crystal structure in which three mutually different axes form right angles, and exhibits ferroelectric properties, while T-Phase (Tetragonal phase) is a crystal structure in which three axes form right angles, two of which are identical, and exhibits electrical properties similar to antiferroelectricity. In other words, the larger the O-Phase and the smaller the T-Phase, the stronger the ferroelectric properties.
[0040] It has been confirmed that the dual switching memory device 1000 according to the present invention exhibits the most efficient ferroelectricity when the aluminum concentration of aluminum-doped hafnium oxide (Al-doped HfO2) is 1.3% to 1.9%. In particular, it has been confirmed that the ferroelectricity is highest when the aluminum concentration is in the range of 1.6% where the composition ratio of hafnium to aluminum is 23(Hf):1(Al).
[0041] FIG. 3 is a graph showing the relationship between electric polarization (P) and voltage (V) according to the composition ratio of hafnium and aluminum in a dual switching memory element according to an embodiment of the present invention.
[0042] Referring to FIG. 3, in the dual switching memory device 1000 according to an embodiment of the present invention, the PV characteristics change depending on the composition ratio of hafnium and aluminum in the aluminum-doped hafnium oxide (Al-doped HfO), which is the ferroelectric material of the blocking layer 100, and therefore the memory window also changes.
[0043] As described above with reference to FIG. 2, the blocking layer 100 of the dual switching memory device 1000 according to the present invention exhibits the most efficient ferroelectric characteristics when the aluminum concentration is in the range of 1.3% to 1.9%, which corresponds to a hafnium to aluminum composition ratio of 20(Hf):1(Al) to 26(Hf):1(Al). That is, when the composition ratio of hafnium to aluminum is 20(Hf):1(Al), the material constituting aluminum-doped hafnium oxide (Al doped HfO2) is 34% hafnium and 1.9% aluminum; when the composition ratio of hafnium to aluminum is 23(Hf):1(Al), the material constituting aluminum-doped hafnium oxide (Al doped HfO2) is 35% hafnium and 1.6% aluminum; and when the composition ratio of hafnium to aluminum is 26(Hf):1(Al), the material constituting aluminum-doped hafnium oxide (Al doped HfO2) is 35% hafnium and 1.3% aluminum.
[0044] As shown in FIG. 3, the dual switching memory device 1000 according to the present invention exhibits the largest memory window when the composition ratio of hafnium to aluminum is 23(Hf):1(Al), i.e., when the materials constituting aluminum-doped hafnium oxide (Al-doped HfO2) contain 35% hafnium and 1.6% aluminum.
[0045] FIG. 4 is a flowchart illustrating a method for manufacturing a dual switching memory device according to an embodiment of the present invention, and FIG. 5 is a perspective cross-sectional view of a dual switching memory device according to an embodiment of the present invention.
[0046] 4A and 4B are cross-sectional views sequentially illustrating a method for manufacturing a dual switching memory device according to an embodiment of the present invention. Referring to FIGS. 4A and 4B and 5A and 5B, the method may include the steps of: (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word lines and insulating films and forming a tunnel layer 300 on the inner surface of the hole; (c) forming a charge trapping layer 200 on the inner surface of the tunnel layer 300; (d) forming a blocking layer 100 on the inner surface of the charge trapping layer 200; (e) forming a channel structure (Si) on the inner surface of the blocking layer 100; and (f) removing the insulating film and depositing a metal along the word line to form a gate electrode 400.
[0047] The blocking layer 100 corresponds to the blocking layer portion of a charge trapping memory device, and the present invention configures the blocking layer of such a conventional charge trapping memory device with a ferroelectric material. In particular, the dual switching memory device 1000 according to the present invention can use aluminum-doped hafnium oxide (Al-doped HfO2) for thermal stability during processing.
[0048] Furthermore, the thickness of the blocking layer 100 is preferably greater than the thickness of the charge trapping layer 200 and the thickness of the tunnel layer 300, which will be described later. For example, the thickness of the blocking layer 100 is preferably about 10 nm.
[0049] Meanwhile, the charge trapping layer 200 is located on the blocking layer 100 and is provided to capture charges injected from the gate electrode 400. When a negative gate voltage is applied to the gate electrode 400, charges that have passed through the tunneling layer 300 are prevented from moving to the channel structure (Si) by the blocking layer 100 and are instead trapped on the charge trapping layer 200.
[0050] Such a charge trap layer 200 is preferably typically silicon nitride (Si3N4). In addition to this, it can also be composed of any one of aluminum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, and niobium oxide, or a combination thereof.
[0051] Furthermore, when the charge trap layer 200 is made of silicon nitride (Si3N4), it is preferably formed by a chemical vapor deposition (CVD) method at 400°C to 800°C using SiH4 gas or SiCl2H2 gas and NH3 gas.
[0052] Also, silicon nitride (Si3N4) is preferably formed to have a composition ratio of nitrogen to silicon of 0.6 to 1.45 (0.6 < N / Si < 1.45).
[0053] The thickness of such a charge trap layer 200 is preferably formed to be the same as or larger than the tunnel layer 300 described later. As an example, the thickness of the charge trap layer 200 is preferably 5 nm to 8 nm.
[0054] On the other hand, the tunnel layer 300 is located above the charge trap layer 200 and below the gate electrode 400. As described above, when a negative gate voltage is applied to the gate electrode 400, the charge of the gate electrode 400 is provided to move to the charge trap layer 200 via the tunnel layer 300.
[0055] Such a tunnel layer 300 is provided as an energy barrier layer by charge tunneling and is preferably made of an oxide film such as silicon dioxide (SiO2).
[0056] Furthermore, the process of forming the tunnel layer 300 is preferably carried out by a thermal oxidation process or a radical oxidation process, and the thickness of the tunnel layer 300 is preferably formed to be smaller than the thickness of the blocking layer and the same as or smaller than the thickness of the charge trapping layer 200, as described above, and the thickness of the tunnel layer 300 is preferably 4 nm to 6 nm, for example.
[0057] Meanwhile, the gate electrode 400 is located above the tunnel layer 300, and an on voltage and an off voltage are applied from a gate bias circuit. As described above, in the present invention, a negative gate voltage corresponds to an on voltage, and when a negative gate voltage is applied, charges in the gate electrode 400 move to the charge trapping layer 200 via the tunnel layer 300.
[0058] Such gate electrode 400 preferably comprises a conductive nitride such as TiN, TaN, and WN. In addition, the material may include conductive oxynitrides (for example, TiON, etc.) or combinations thereof (for example, TiSiN, TiAlON, etc.), or may include polysilicon doped with a high concentration of impurities.
[0059] Of course, instead of the nitride form as described above, conductive metals such as platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), silicon (Si), copper (Cu), nickel (Ni), cobalt (Co), molybdenum (Mo), or alloys thereof may be included, but these materials are merely examples and the present invention is not limited thereto.
[0060] Although preferred embodiments of the present invention have been described above, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present invention. Therefore, the technical concept of the present invention includes not only each of the disclosed embodiments but also combinations of the disclosed embodiments, and the scope of the technical concept of the present invention is not limited by such embodiments. Furthermore, a person skilled in the art to which the present invention pertains may make various changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered equivalents within the scope of the present invention. [Explanation of symbols]
[0061] 100: Blocking layer 200: Charge trapping layer 300: Tunnel layer 400: Gate electrode 1000: Dual switching memory element
Claims
1. a blocking layer positioned over the channel structure; a charge trapping layer located on the blocking layer for trapping injected charges; a tunnel layer located on the charge trapping layer; a gate electrode located on the tunnel layer, to which an on-voltage and an off-voltage are applied from a gate bias circuit; Including, The blocking layer is A dual switching memory element characterized by including a ferroelectric material such that both charge trapping and ferroelectric polarization switching occur.
2. The ferroelectric material is Aluminum doped hafnium oxide (Al doped HfO ２ 2. The dual switching memory element according to claim 1, wherein:
3. The aluminum-doped hafnium oxide (Al doped HfO ２ )teeth, The composition ratio of hafnium and aluminum is T Ｈｆ :1(Al), Said T Ｈｆ 3. The dual switching memory element according to claim 2, wherein is a natural number between 20 and 26.
4. The composition ratio of hafnium and aluminum is 4. The dual switching memory element of claim 3, wherein the Hf layer is 23(Hf):1(Al).
5. The hafnium is The aluminum-doped hafnium oxide (Al doped HfO ２ ) has an atomic concentration of 35%; The aluminum is The aluminum-doped hafnium oxide (Al doped HfO ２ 5. The dual switching memory element according to claim 4, wherein the atomic concentration in the silicon dioxide is 1.6%.
6. (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word line and insulating film, and forming a tunnel layer on an inner circumferential surface of the hole; (c) forming a charge trapping layer on an inner circumferential surface of the tunnel layer; (d) forming a blocking layer on the inner circumferential surface of the charge trapping layer; (e) forming a channel structure on an inner circumferential surface of the barrier layer; (f) removing the insulating film and depositing metal along the word line to form a gate electrode; Including, The blocking layer is A method for fabricating a dual switching memory element, comprising a ferroelectric material such that both charge trapping and ferroelectric polarization switching occur.
7. The ferroelectric material is Aluminum doped hafnium oxide (Al doped HfO ２ 7. The method for manufacturing a dual switching memory device according to claim 6, wherein
8. The aluminum-doped hafnium oxide (Al doped HfO ２ )teeth, The composition ratio of hafnium and aluminum is T Ｈｆ :1(Al), Said T Ｈｆ 8. The method of claim 7, wherein is a natural number between 20 and 26.
9. The composition ratio of hafnium and aluminum is 9. The method of claim 8, wherein the Hf layer is 23(Hf):1(Al).
10. The hafnium is The aluminum-doped hafnium oxide (Al doped HfO ２ ) has an atomic concentration of 35%; The aluminum is The aluminum-doped hafnium oxide (Al doped HfO ２ 10. The method of claim 9, wherein the atomic concentration in the silicon dioxide is 1.6%.