Power semiconductor device

Abstract

To provide a power semiconductor device which includes multiple doping regions, in which at least a part of the multiple doping regions includes a convex boundary surface, thereby alleviating electric field concentration and improving stability.SOLUTION: A power semiconductor device includes: a trench that recesses from a surface of a semiconductor substrate 400 into an interior of the semiconductor substrate along a Z direction; a body region including a first body region 421 that is in contact with a side surface and a bottom surface of the trench and extends along a Y direction inside the semiconductor substrate, and a second body region 422 that extends further along the Z direction from the first body region below the trench; and an electric field junction region 440 that is in contact with a lower surface of the first body region and also in contact with a side surface of the second body region. The electric field junction region contains an impurity of a first conductivity type. The first body region and the second body region contain an impurity of a second conductivity type. A boundary surface between the second body region and the electric field junction region is convex downward.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices that include multiple doped regions. [Background technology]

[0002] Power semiconductor devices are semiconductor elements that operate in high-voltage and high-current environments. Such power semiconductor devices can be used in fields requiring high-power switching, such as inverter elements. Examples of transistors that can be used as power semiconductor devices include insulated gate bipolar transistors (IGBTs) and power metal-oxide semiconductor field-effect transistors (MOSFETs).

[0003] The power semiconductor device may include a gate, and the gate may include an insulating layer. To maintain stability of the gate of the power semiconductor device including the trench-type gate, a predetermined doping region may be formed in the semiconductor substrate. Summary of the Invention [Problem to be solved by the invention]

[0004] The power semiconductor device according to the embodiment of the present invention can provide a power semiconductor device that protects the lower part of the gate trench and reduces the concentration of the electric field, but these problems are merely examples and are not intended to limit the scope of the present invention. [Means for solving the problem]

[0005] A power semiconductor device according to one embodiment of the present invention may include a trench recessed along a first direction from a surface of a semiconductor substrate into the semiconductor substrate, a body region including a first body region contacting a side and a bottom surface of the trench and extending along a second direction into the semiconductor substrate, and a second body region below the trench and further extending from the first body region along the first direction, and a field junction region contacting a bottom surface of the first body region and a side surface of the second body region, wherein the field junction region contains impurities of a first conductivity type, and the first and second body regions contain impurities of a second conductivity type, and an interface between the second body region and the field junction region may be downwardly convex.

[0006] The power semiconductor device according to an embodiment of the present invention may further include a drift region disposed below the second body region and the field junction region and containing impurities of a first conductivity type, and a drain electrode layer disposed below the drift region.

[0007] The power semiconductor device according to an embodiment of the present invention may further include a current spreading layer in contact with a lower surface of the second body region and disposed on the drift region, the current spreading layer having a higher concentration of the first conductivity type impurities than the drift region.

[0008] The power semiconductor device according to an embodiment of the present invention may further include a trench gate electrode layer disposed within the trench, and a planar gate electrode layer in contact with the trench gate electrode layer and extending in one direction on the surface of the semiconductor substrate.

[0009] The power semiconductor device according to an embodiment of the present invention may further include a lower insulating layer disposed along an inner wall of the trench and in contact with the trench gate electrode layer, and an upper insulating layer in contact with an upper surface and side surfaces of the planar gate electrode layer.

[0010] The power semiconductor device according to an embodiment of the present invention may further include a source electrode layer in contact with an upper surface and a side surface of the upper insulating layer and in contact with the surface of the semiconductor substrate.

[0011] The power semiconductor device according to an embodiment of the present invention may further include a source region in the first body region, contacting the source electrode layer at the surface of the semiconductor substrate and containing impurities of the first conductivity type.

[0012] According to another embodiment of the present invention, a power semiconductor device includes first and second trench gate electrode layers recessed into a semiconductor substrate, extending in a first direction and spaced apart from each other in a second direction; a planar gate electrode layer contacting upper surfaces of the first and second trench gate electrode layers, respectively, and extending in the second direction on a surface of the semiconductor substrate; a lower insulating layer surrounding a lower surface and side surfaces of the trench gate electrode layers; a body region including a first body region and a second body region contacting the side surfaces and lower surface of the lower insulating layer and extending in the second direction, the second body region being further recessed in a portion of a lower surface of the first body region; and a source region within the first body region and contacting the surface of the semiconductor substrate, wherein the source region contains impurities of a first conductivity type and the body region contains impurities of a second conductivity type, and the second body region overlaps the source region and the lower insulating layer and includes a boundary surface that is convex outward from a portion overlapping with the source region.

[0013] The power semiconductor device according to an embodiment of the present invention may further include a field junction region contacting a lower surface of the first body region and the convex boundary surface of the second body region and containing impurities of the first conductivity type.

[0014] The power semiconductor device according to an embodiment of the present invention may further include a current spreading layer contacting a lower surface of the second body region and containing impurities of the first conductivity type.

[0015] The power semiconductor device according to an embodiment of the present invention may further include a drift region disposed below the current spreading layer and the field junction region and containing impurities of the first conductivity type.

[0016] In the power semiconductor device according to an embodiment of the present invention, the concentration of the first conductivity type impurity may be higher in the source region than in the current spreading layer, and higher in the current spreading layer than in the drift region.

[0017] The power semiconductor device according to an embodiment of the present invention may further include an upper insulating layer in contact with an upper surface and a side surface of the planar gate electrode layer, and a source electrode layer disposed on the upper insulating layer.

[0018] In the power semiconductor device according to one embodiment of the present invention, the upper insulating layer may contact the lower insulating layer on the surface of the semiconductor substrate, and the source electrode layer may contact the source region on the surface of the semiconductor substrate. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a perspective view exemplarily illustrating a portion of a power semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view exemplarily illustrating the surface of the power semiconductor device of FIG. 1 cut along line AA'. [Figure 3] 3 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross section of FIG. 2 along line BB'. [Figure 4] 3 is a cross-sectional view exemplarily illustrating a surface cut along line CC' of the first cross-section of FIG. 2. FIG. [Figure 5] 3 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross-section of FIG. 2 along line DD'. FIG. [Figure 6] 3 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross-section of FIG. 2 along line EE'. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0020] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. When referring to components in each drawing, it should be noted that the same components are assigned the same reference numerals as much as possible even if they appear in different drawings. Furthermore, when describing the embodiments of the present invention, if it is determined that a detailed description of related known structures or functions would hinder understanding of the embodiments of the present invention, such a detailed description will be omitted.

[0021] When describing components of embodiments of the present invention, terms such as "first," "second," etc. may be used. These terms are intended to distinguish the component from other components, and do not limit the nature, order, or sequence of the components unless otherwise specified. Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains. Terms defined in commonly used dictionaries may be interpreted as meanings consistent with the meanings they have in the context of the relevant art, and unless explicitly defined in this application, they should not be interpreted in an idealized or overly formal sense.

[0022] FIG. 1 is a perspective view exemplarily illustrating a portion of a power semiconductor device 1 according to one embodiment of the present invention.

[0023] Referring to FIG. 1, a power semiconductor device 1 may include a source electrode layer 100 , an upper insulating layer 210 , a gate structure 300 , a semiconductor substrate 400 and a drain electrode layer 500 .

[0024] The source electrode layer 100 may be disposed on the upper insulating layer 210. The source electrode layer 100 may be in contact with the top and side surfaces of the upper insulating layer 210. The source electrode layer 100 may be a region to which a source voltage is applied. The source electrode layer 100 may include at least one of a conductive material, for example, polysilicon, polysilicon containing impurities, metal, metal nitride, metal silicide, or a combination thereof. The source voltage applied to the source electrode layer 100 may be applied to the source region 410.

[0025] The upper insulating layer 210 may be disposed on the gate electrode layer 300. The upper insulating layer 210 may be in contact with the top and side surfaces of the gate electrode layer 300. The upper insulating layer 210 may include an insulating material, for example, at least one of silicon oxide, silicon nitride, germanium oxide, germanium nitride, hafnium oxide, zirconium oxide, aluminum oxide, and combinations thereof. The upper insulating layer 210 may electrically isolate the source electrode layer 100 and the gate electrode layer 300.

[0026] The gate electrode layer 300 may be disposed below the upper insulating layer 210. The gate electrode layer 300 may be disposed between the upper insulating layer 210 and the lower insulating layer 230. The gate electrode layer 300 may include at least one of a conductive material, for example, polysilicon, impurity-doped polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The gate electrode layer 300 may include a planar gate electrode layer (310 in FIG. 3) and a trench gate electrode layer (320 in FIG. 3). The planar gate electrode layer 310 and the trench gate electrode layer 320 will be described in more detail with reference to FIG. 3 and subsequent figures.

[0027] The semiconductor substrate 400 may include a source region 410, a first body region 421, a second body region (422 in FIG. 3), a drift region 430, a field junction region 440, and a current spreading layer (450 in FIG. 3). The semiconductor substrate 400 may include a material having a band gap larger than that of silicon (e.g., silicon carbide (SiC), gallium nitride (GaN), etc.).

[0028] The source region 410 may be a region containing impurities of a first conductivity type (e.g., N-type). The source region 410 may be a region in contact with the source electrode layer 100 and to which a source voltage is applied by the source electrode layer 100. The source region 410 may be disposed on the upper part of the semiconductor substrate 400. The source region 410 may be in contact with the source electrode layer 100 on the surface of the semiconductor substrate 400 in the first body region 421.

[0029] The first body region 421 may be a region containing impurities of a second conductivity type (e.g., P-type) opposite to the first conductivity type. The first body region 421 may be in contact with the side and bottom surfaces of the source region 410. The first body region 421 may be in contact with, for example, the side surfaces of the lower insulating layer 230. The first body region 421 may form a channel through which current flows between the drift region 430 and the source region 410 when the power semiconductor device 1 is in an on-state. The channel may be formed, for example, in the vertical direction Z.

[0030] The drift region 430 may be a region containing impurities of the first conductivity type. The concentration of the impurities of the first conductivity type in the drift region 430 may be lower than the concentration of the impurities of the first conductivity type in the source region 410.

[0031] The field junction region 440 may be in contact with the drift region 430. For example, the field junction region 440 may be in contact with an upper surface of the drift region 430. The field junction region 440 may be in contact with a lower surface of the first body region 421. The field junction region 440 may include impurities of the first conductivity type. The concentration of the impurities of the first conductivity type in the field junction region 440 may be lower than that in the source region 410 and higher than that in the drift region 430.

[0032] The second body region (422 in FIG. 3) and the current spreading layer (450 in FIG. 3) will be described with reference to FIG. 3 and subsequent figures.

[0033] The drain electrode layer 500 may be disposed under the semiconductor substrate 400. The drain electrode layer 500 may be a region to which a drain voltage (e.g., a ground voltage) is applied. The drain electrode layer 500 may include at least one of a conductive material, for example, polysilicon, doped polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.

[0034] FIG. 2 is a cross-sectional view exemplarily illustrating the surface of the power semiconductor device 1 of FIG. 1 cut along line AA'.

[0035] 1 and 2, the first cross section 2 may be an embodiment of a cross section of the power semiconductor device 1 taken along line A-A'. The first cross section 2 may include the source electrode layer 100, the upper insulating layer 210, and the gate electrode layer 300.

[0036] The source electrode layer 100 may contact the side surface of the upper insulating layer 210. For example, the source electrode layer 100 may be disposed between the upper insulating layers 210.

[0037] The upper insulating layer 210 may contact the side of the gate electrode layer 300 .

[0038] The gate electrode layer 300 may be in contact with the upper insulating layer 210. For example, the gate electrode layer 300 may be disposed between the upper insulating layers 210. The gate electrode layer 300 of the first cross section 2 may be a portion corresponding to the planar gate electrode layer 310 of the second cross section 3 in FIG.

[0039] In the following FIGS. 3 to 6, the contents that overlap with the contents explained in FIGS. 1 and 2 will be omitted.

[0040] FIG. 3 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross section 2 of FIG. 2 along line BB'.

[0041] 1 to 3, the second cross section 3 may be an embodiment of a cross section obtained by cutting the first cross section 2 along line B-B'. The second cross section 3 may include a source electrode layer 100, an upper insulating layer 210, a lower insulating layer 230, a gate electrode layer 300, a semiconductor substrate 400, and a drain electrode layer 500.

[0042] The source electrode layer 100 may be disposed on the upper insulating layer 210. For example, the source electrode layer 100 may contact an upper surface (surface) of the upper insulating layer 210. The source electrode layer 100 may extend in the Y direction. The source electrode layer 100 may further extend along the Z direction into a space between two adjacent upper insulating layers 210. For example, the source electrode layer 100 may contact a side surface of the upper insulating layer 210. The source electrode layer 100 may contact an upper surface of the semiconductor substrate 400. For example, at least one end of the source electrode layer 100 may contact the upper surface of the semiconductor substrate 400. The source electrode layer 100 may contact a source region 410.

[0043] The upper insulating layer 210 may be disposed on the gate electrode layer 300. For example, the upper insulating layer 210 may contact an upper surface of the planar gate electrode layer 310. The upper insulating layer 210 may contact a side surface of the planar gate electrode layer 310. At least one end of the upper insulating layer 210 may contact an upper surface of the semiconductor substrate 400. The plurality of upper insulating layers 210 may be spaced apart from each other along the X direction.

[0044] The lower insulating layer 230 may be disposed along the inner wall of the gate trench. The gate trench may be recessed from the upper surface (surface) of the semiconductor substrate 400 into the semiconductor substrate 400 along the vertical direction Z.

[0045] The lower insulating layer 230 may enclose a trench structure (e.g., trench gate electrode layer 320) of the gate electrode layer 300 recessed into the semiconductor substrate 400. For example, the lower insulating layer 230 may contact the bottom and side surfaces of the trench gate electrode layer 320 inside the semiconductor substrate 400. The lower insulating layer 230 may contact the upper insulating layer 210 on the top surface of the semiconductor substrate 400. The lower insulating layer 230 may electrically isolate the trench gate electrode layer 320 and the semiconductor substrate 400.

[0046] The upper insulating layer 210 and the lower insulating layer 230 may have a region where they contact each other on the upper surface of the semiconductor substrate 400. The upper insulating layer 210 and the lower insulating layer 230 may surround the gate electrode layer 300. For example, the upper insulating layer 210 and the lower insulating layer 230 may function as a gate insulating layer.

[0047] The gate electrode layer 300 may be a region to which a gate voltage is applied. When the difference between the gate voltage and the source voltage is equal to or greater than the threshold voltage of the power semiconductor device 1, the power semiconductor device 1 can be in an on-state. When the difference between the gate voltage and the source voltage is smaller than the threshold voltage of the power semiconductor device 1, the power semiconductor device 1 can be in an off-state. When the power semiconductor device 1 is in the on-state, unlike the off-state, a current flows inside the semiconductor substrate 400, and the power semiconductor device 1 can operate. The gate electrode layer 300 may include a planar gate electrode layer 310 and a trench gate electrode layer 320.

[0048] The gate electrode layer 300 may include at least one of a conductive material, for example, polysilicon, polysilicon containing impurities, metal, metal nitride, metal silicide, or a combination thereof.

[0049] The planar gate electrode layer 310 may contact the top surface of the trench gate electrode layer 320 and extend in the Y direction above the top surface of the semiconductor substrate 400 .

[0050] The trench gate electrode layer 320 may be disposed inside the gate trench and may extend in the X direction.

[0051] The semiconductor substrate 400 may include a source region 410, a body region 420, a drift region 430, a field junction region 440, and a current spreading layer 450. The upper surface of the semiconductor substrate 400 may be the surface of the semiconductor substrate 400 where the source region 410 is located. The lower surface of the semiconductor substrate 400 may be the surface where the drain electrode layer 500 and the drift region 430 contact each other.

[0052] The source region 410 may contact the source electrode layer 100 on the upper surface of the semiconductor substrate 400. The source region 410 may contact the upper insulating layer 210 on the upper surface of the semiconductor substrate 400. For example, the source region 410 may be disposed on both sides of the gate electrode layer 310. The side of the source region 410 may contact the lower insulating film 230. The source region 410 may be disposed in the first body region 421.

[0053] The first body region 421 may extend to a first depth d1 from the upper surface of the semiconductor substrate 400. The first body region 421 may be disposed between two adjacent lower insulating layers 230. The first body region 421 may contact side and lower surfaces of the gate trench and extend along the X direction within the semiconductor substrate 400. The first body region 421 may contact side and lower surfaces of the lower insulating layer 230 and extend in the X direction.

[0054] The second body region 422 may further extend in the Z direction from the first body region 421 under the gate trench. For example, the second body region 422 may extend to a second depth d2 from the upper surface of the semiconductor substrate 400. The second depth d2 may be greater than the first depth d1. For example, the second body region 422 may be a region recessed further in the Z direction from a portion of the lower surface of the first body region 421.

[0055] The second body region 422 may overlap the source region 410 and the lower insulating layer 230 when viewed in the Z direction. The second body region 422 may contact the field junction region 440. The interface between the second body region 422 and the field junction region 440 may have a downwardly convex shape. The downwardly convex shape may refer to a shape that protrudes toward the field junction region 440. The interface between the second body region 422 and the field junction region 440 may overlap the source region 410 when viewed in the Z direction. The interface may have a convex shape that protrudes toward the outside of the second body region 422.

[0056] When the second body region 422 has the convex shape, the electric field concentrated at the boundary surface of the second body region 422 is alleviated, and the stability of the power semiconductor device 1 can be improved.

[0057] The field junction region 440 may contact the bottom surface of the first body region 421 and the side surface of the second body region 422 (eg, the interface).

[0058] The current spreading layer 450 may be disposed below the second body region 422. As an example, the current spreading layer 450 may be disposed on a lower surface of the second body region 422. The current spreading layer 450 may include impurities of a first conductivity type. The concentration of the impurities of the first conductivity type in the current spreading layer 450 may be greater than the concentration of the impurities of the first conductivity type in the drift region 430. The current spreading layer 450 may be disposed on the drift region 430.

[0059] The current spreading layer 450 can prevent a tailing phenomenon, in which impurities penetrate to a location much deeper than the second depth d2, when the body region 420 is formed by implanting second conductivity type impurities into the semiconductor substrate 400 during the manufacturing process of the power semiconductor device 1.

[0060] The drift region 430 may be disposed below the second body region 422 and the field junction region 440. The drift region 430 may be disposed below the current spreading layer 450.

[0061] The drain electrode layer 500 may be disposed below the drift region 430. As an example, the drain electrode layer 500 may contact the lower surface of the drift region 430.

[0062] FIG. 4 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross section 2 of FIG. 2 along line CC'.

[0063] In Fig. 4, differences from Fig. 3 will be mainly described. Referring to Figs. 1, 2 and 4, the third cross section 4 may be an embodiment of a cross section of the first cross section 2 taken along line CC'.

[0064] The third cross section 4 may include the source electrode layer 100 , the upper insulating layer 210 , the lower insulating layer 230 , the gate electrode layer 300 , the source region 410 , the first body region 421 , the drift region 430 , the field junction region 440 and the drain electrode layer 500 .

[0065] In the third cross section 4, the gate electrode layer 300 may refer to the planar gate electrode layer 310 portion of FIG.

[0066] A lower insulating layer 230 may be disposed below the planar gate electrode layer 310. The lower insulating layer 230 may be disposed on an upper surface of the semiconductor substrate 400.

[0067] The source region 410 may be disposed below a region where the upper insulating layer 210 and the upper surface of the semiconductor substrate 400 meet. The source region 410 may partially overlap both end portions of the lower insulating layer 230 when viewed in the Z direction.

[0068] The first body regions 421 may include the source regions 410 and may be spaced apart along the X direction. The first body regions 421 may penetrate a portion of the source region 410 and contact the source electrode layer 100 on the top surface of the semiconductor substrate 400. Regions between the plurality of first body regions 421 may be filled with field junction regions 440.

[0069] The field junction region 440 may contact the side and bottom surfaces of the first body region 421. A portion of the field junction region 440 may extend in the opposite direction to the Z direction up to the top surface of the semiconductor substrate 400. For example, the field junction region 440 may contact the lower insulating layer 230.

[0070] The drift region 430 can be disposed below the field junction region 440 .

[0071] FIG. 5 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross section 2 of FIG. 2 along line DD'.

[0072] 5 will be described focusing on differences from FIGS. 3 and 4. Referring to FIGS. 1, 2, and 5, the fourth cross section 5 may be an embodiment of a cross section obtained by cutting the first cross section 2 along line DD'. The fourth cross section 5 may include the source electrode layer 100, the semiconductor substrate 400, and the drain electrode layer 500.

[0073] The semiconductor substrate 400 may include a source region 410 , a first body region 421 , a drift region 430 and a field junction region 440 .

[0074] The source electrode layer 100 may be in contact with the source region 410 and the first body region 421, respectively, on the upper surface of the semiconductor substrate 400. The contact area between the source electrode layer 100 and the source region 410 and the contact area between the source electrode layer 100 and the first body region 421 may be alternately arranged along the Y direction.

[0075] FIG. 6 is a cross-sectional view exemplarily illustrating a surface obtained by cutting the first cross section 2 of FIG. 2 along line EE'.

[0076] 6 will be described focusing on differences from FIG 5. Referring to FIGS. 1, 2, 5 and 6, the fifth cross section 6 may include a source electrode layer 100, an upper insulating layer 210, a lower insulating layer 230, a gate electrode layer 300, a semiconductor substrate 400 and a drain electrode layer 500.

[0077] The gate electrode layer 300 may include a planar gate electrode layer 310 and a trench gate electrode layer 320 .

[0078] The trench gate electrode layers 320 may be recessed into the semiconductor substrate 400, extend in the X direction, and be spaced apart from each other in the Y direction.

[0079] The planar gate electrode layer 310 may be in contact with the upper surfaces of the plurality of trench gate electrode layers 320, respectively, and may extend from above the surface of the semiconductor substrate 400 in the Y direction.

[0080] The lower insulating layer 230 may contact the lower surface of the planar gate electrode layer 310 and be disposed on the surface of the semiconductor substrate 400. The lower insulating layer 230 may surround the lower surface and side surfaces of the trench gate electrode layer 320.

[0081] The semiconductor substrate 400 may include a first body region 421 , a second body region 422 , a drift region 430 , a field junction region 440 and a current spreading layer 450 .

[0082] First body region 421 and second body region 422 may have, for example, the same concentration of impurities of the first conductivity type, but may vary depending on process variables or limitations.

[0083] The first body region 421 and the second body region 422 can be disposed below the trench gate electrode layer 320. The first body region 421 and the second body region 422 can alleviate electric field concentration in portions of the lower insulating layer 230 that surround the side and bottom surfaces of the trench gate electrode layer 320, thereby preventing dielectric breakdown of the lower insulating layer 230 and increasing the stability of the power semiconductor device 1.

[0084] The second body region 422 may be disposed below the first body region 421, and the current spreading layer 450 may be disposed below the second body region 422.

[0085] The field junction region 440 may contact the surface of the semiconductor substrate 400 and, by way of example, may extend to a second depth d2.

[0086] The drift region 430 may contact the bottom surface of the field junction region 440 and may contact, for example, the side and bottom surfaces of the current spreading layer 450 .

[0087] The above description merely exemplifies the technical concept of the present invention, and various modifications and variations are possible by those skilled in the art without departing from the essential characteristics of the present invention. The embodiments disclosed in the present invention are for illustrative purposes only, and are not intended to limit the technical concept of the present invention. The scope of the present invention should be interpreted by the scope of the claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims

1. a trench recessed along a first direction from a surface of a semiconductor substrate into the semiconductor substrate; a body region including a first body region contacting a side surface and a bottom surface of the trench and extending along a second direction within the semiconductor substrate, and a second body region further extending along the first direction from the first body region below the trench; a field junction region in contact with a bottom surface of the first body region and a side surface of the second body region; the field junction region includes impurities of a first conductivity type, and the first and second body regions include impurities of a second conductivity type; The power semiconductor device, wherein an interface between the second body region and the field junction region is downwardly convex.

2. a drift region disposed below the second body region and the field junction region and containing impurities of a first conductivity type; The power semiconductor device of claim 1 , further comprising: a drain electrode layer disposed below said drift region.

3. 3. The power semiconductor device according to claim 2, further comprising: a current spreading layer in contact with a lower surface of said second body region, disposed above said drift region, and having a higher concentration of said first conductivity type impurity than said drift region.

4. a trench gate electrode layer disposed within the trench; 2. The power semiconductor device according to claim 1, further comprising: a planar gate electrode layer in contact with said trench gate electrode layer and extending in one direction above said surface of said semiconductor substrate.

5. a lower insulating layer disposed along an inner wall of the trench and in contact with the trench gate electrode layer; 5. The power semiconductor device according to claim 4, further comprising an upper insulating layer in contact with an upper surface and side surfaces of said planar gate electrode layer.

6. The power semiconductor device according to claim 5 , further comprising a source electrode layer in contact with the top and side surfaces of said upper insulating layer and in contact with said surface of said semiconductor substrate.

7. The power semiconductor device according to claim 6 , further comprising: a source region in said first body region, said source region being in contact with said source electrode layer at said surface of said semiconductor substrate and containing said impurity of said first conductivity type.

8. first and second trench gate electrode layers recessed into the semiconductor substrate, extending in a first direction and spaced apart from each other in a second direction; a planar gate electrode layer in contact with upper surfaces of the first and second trench gate electrode layers, respectively, and extending in the second direction on the surface of the semiconductor substrate; a lower insulating layer surrounding a lower surface and a side surface of the trench gate electrode layer; a body region including a first body region contacting a side surface and a bottom surface of the lower insulating layer and extending in the second direction and a second body region recessed further in a portion of a bottom surface of the first body region; a source region in the first body region and in contact with the surface of the semiconductor substrate; the source region contains impurities of a first conductivity type, and the body region contains impurities of a second conductivity type; The second body region overlaps the source region and the lower insulating layer and includes a boundary surface that is convex outward from a portion that overlaps the source region.

9. The power semiconductor device according to claim 8 , further comprising a field junction region contacting a lower surface of said first body region and said convex boundary surface of said second body region, said field junction region containing said first conductivity type impurity.

10. The power semiconductor device according to claim 9 , further comprising: a current spreading layer contacting a lower surface of said second body region and containing said first conductivity type impurity.

11. The power semiconductor device according to claim 10 , further comprising a drift region disposed below said current spreading layer and said field junction region and containing impurities of said first conductivity type.

12. 12. The power semiconductor device according to claim 11, wherein the concentration of the first conductivity type impurity is higher in the source region than in the current spreading layer, and higher in the current spreading layer than in the drift region.

13. an upper insulating layer in contact with the top and side surfaces of the planar gate electrode layer; The power semiconductor device according to claim 8 , further comprising: a source electrode layer disposed on the upper insulating layer.

14. The power semiconductor device according to claim 13 , wherein the upper insulating layer contacts the lower insulating layer on the surface of the semiconductor substrate, and the source electrode layer contacts the source region on the surface of the semiconductor substrate.

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