Oxide semiconductor memory element and method for manufacturing the same

Abstract

To provide an oxide semiconductor memory element and a method for manufacturing the same.SOLUTION: The present invention relates to an oxide semiconductor memory element forming an amorphous indium-gallium-zinc-oxide (a-IGZO) thin film and a method for manufacturing the same. The present invention aims to solve the problem that the oxide semiconductor forming the a-IGZO thin film has a negative threshold voltage and to improve the mobility characteristics.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an oxide semiconductor memory device and a manufacturing method thereof, and more particularly to an oxide semiconductor memory device in which an amorphous indium-gallium-zinc-oxide (a-IGZO) thin film is formed, and a manufacturing method thereof. [Background technology]

[0002] Currently, demand for memory semiconductors is exploding due to the Fourth Industrial Revolution. As the number of Internet-on-Things (IoT) devices increases explosively, the demand for memory is increasing in edge devices such as smartphones, and the amount of data that must be handled is exploding with the use of deep learning.

[0003] To keep pace with this technological trend, non-volatile memory semiconductors require high integration and excellent memory performance, and 3D NAND flash memory dominates the non-volatile memory market because it is far superior to other methods in terms of element integration.

[0004] 3D NAND flash memory is not only a non-volatile memory but is also attracting attention as a CIM (Computing-In-Memory) element in the coming AI era. CIM elements perform MAC (Multiply and Accumulation) operations, which are the core operations of deep learning, at the memory stage, and can operate more efficiently by reducing frequent data transfers between logic and memory.

[0005] With the latest trend in memory-to-processor devices, it is more essential than ever to perform memory read, write, and undo operations as quickly as possible, and to store large amounts of information in a single device (e.g., 3 bits per cell).

[0006] Meanwhile, to improve the performance of 3D NAND flash memory, oxide semiconductors have been widely studied instead of silicon-based semiconductor elements. In terms of materials, research results have been reported on single-, binary-, and ternary-component compounds based on indium oxide (In2O3), zinc oxide (ZnO), gallium oxide (Ga2O3), indium zinc oxide (InZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (InGaZnO). Oxide semiconductors have the advantage of exhibiting superior mobility compared to hydrogenated amorphous silicon.

[0007] However, in the case of oxide semiconductors, since they have a negative threshold voltage, they have the problem of operating in a normally-on state and low stability against external stress. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention is intended to solve the above-mentioned problems, and aims to solve the problem of an oxide semiconductor forming an a-IGZO thin film having a negative threshold voltage, and to improve mobility characteristics. [Means for solving the problem]

[0009] According to one aspect of the present invention, a method for manufacturing an oxide semiconductor memory device is disclosed, comprising: (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at a center of the stacked word lines and insulating films and forming a tunnel layer on an inner peripheral surface of the hole; (c) forming a charge trapping layer on an inner peripheral surface of the tunnel layer; (d) forming a blocking layer on an inner peripheral surface of the charge trapping layer; (e) forming an oxide channel on an inner peripheral surface of the blocking layer; and (f) removing the insulating film and depositing a metal along the word line to form a gate electrode, wherein in step (e), the oxide channel is formed of fluorine-doped a-IGZO (amorphous indum-gallium-zinc-oxide).

[0010] According to an embodiment, the method for manufacturing an oxide semiconductor memory device is disclosed, wherein step (e) includes: (e-1) depositing an a-IGZO layer; (e-2) depositing a polymer layer containing a perfluorodecanoic acid (PFDA) on the a-IGZO layer; (e-3) depositing an aluminum oxide (Al2O3) layer on the polymer layer; and (e-4) performing a drive-in process of applying heat to the oxide channel.

[0011] According to an embodiment, a method for manufacturing an oxide semiconductor memory device is disclosed, wherein step (e-2) comprises depositing the polymer layer containing the perfluorinated compound by an initiated chemical vapor deposition (iCVD) process.

[0012] According to an embodiment, a method for manufacturing an oxide semiconductor memory device is disclosed, wherein the step (e-3) deposits the aluminum oxide layer by an atomic layer deposition (ALD) process.

[0013] According to an embodiment, a method for manufacturing an oxide semiconductor memory device is disclosed, wherein the step (e-4) comprises applying heat at 400°C.

[0014] According to another aspect of the present invention, there is disclosed an oxide semiconductor memory device including: a blocking layer located on an oxide channel; a charge trapping layer located on the blocking layer and trapping injected charges; a tunnel layer located on the charge trapping layer; and a gate electrode located on the tunnel layer and to which an on voltage and an off voltage from a gate bias circuit are applied, wherein the oxide channel is formed of fluorine-doped a-IGZO (amorphous indum-gallium-zinc-oxide).

[0015] According to an embodiment, an oxide semiconductor memory device is disclosed, wherein the oxide channel is formed by depositing a polymer layer containing a perfluorodecanoic acid (PFDA) by an initiated chemical vapor deposition (iCVD) process.

[0016] According to an embodiment, an oxide semiconductor memory device is disclosed, wherein the oxide channel is formed by depositing an aluminum oxide (Al2O3) layer by an atomic layer deposition (ALD) process. [Effects of the Invention]

[0017] According to the present invention, the threshold voltage and mobility performance can be improved by doping an oxide channel made of a-IGZO with fluorine.

[0018] Furthermore, according to the present invention, fluorine can be uniformly doped into the inside of the a-IGZO oxide channel using the iCVD process.

[0019] Furthermore, according to the present invention, the number of oxygen vacancies is reduced, and bulk traps can be efficiently passivated. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a flowchart illustrating a method for manufacturing an oxide semiconductor memory device according to an embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a method of manufacturing an oxide semiconductor memory device according to an embodiment of the present invention. [Figure 3] 1 is a flowchart illustrating a method for doping fluorine into an oxide channel of an oxide semiconductor memory device according to an embodiment of the present invention. [Figure 4] 10 is a graph illustrating an effect of an oxide semiconductor memory device according to an embodiment of the present invention. [Figure 5] 1 is a perspective cross-sectional view illustrating a configuration of an oxide semiconductor memory device according to an embodiment of the present invention; [Figure 6] 1 is a diagram illustrating a configuration of an oxide semiconductor memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0021] The above-mentioned objects, features, and advantages of the present invention will become more apparent from the following embodiments in conjunction with the accompanying drawings. The following specific structural or functional descriptions are merely illustrative for describing other embodiments of the inventive concept. The embodiments of the inventive concept may be implemented in various forms and should not be construed as being limited to the embodiments described in this specification or application. Because the embodiments of the inventive concept may be modified in various ways and have various forms, specific embodiments are illustrated in the drawings and described in detail in this specification or application. However, this does not limit the embodiments of the inventive concept to the specific disclosed form, but should be understood to include all modifications, equivalents, or alternatives within the spirit and technical scope of the present invention. Terms such as "first" and "second" may be used to describe various components, but the components are not limited to these terms. These terms are used solely to distinguish one component from another; for example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the inventive concept. When a component is referred to as being connected to or coupled to another component, it should be understood that it may be directly connected to or coupled to the other component, but that there may be other components in between. On the other hand, when a component is referred to as being directly connected to or coupled to another component, it should be understood that there are no other components in between. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to," should be interpreted similarly. The terms used herein are merely used to describe specific embodiments and are not intended to limit the present invention. The singular term "a" includes the plural term unless the context clearly dictates otherwise.As used herein, terms such as "comprise" or "have" specify the presence of a stated feature, numeral, step, operation, component, part, or combination thereof, but should be understood not to preclude the presence or addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. The present invention will now be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numerals in the various drawings refer to the same elements.

[0022] 1 and 2 are flowcharts illustrating a method for manufacturing an oxide semiconductor memory device according to an embodiment of the present invention.

[0023] 1 and 2, a method for manufacturing an oxide semiconductor memory device according to an embodiment of the present invention may include the steps of alternately stacking word lines (WL) and insulating films (ILD) (S100), forming cylindrical holes in the stacked word lines WL and insulating films ILD and forming tunnel layers 300 on inner surfaces of the holes (S200), forming charge trapping layers 200 on inner surfaces of the tunnel layers 300 (S300), forming blocking layers 100 on inner surfaces of the charge trapping layers 200 (S400), forming oxide channels 50 on inner surfaces of the blocking layers 100 (S500), and removing the insulating films ILD and depositing metal along the word lines WL to form gate electrodes 400 (S600).

[0024] Here, steps S100 to S400 and step S600 may follow a general three-dimensional flash memory device process.

[0025] Meanwhile, step S500 forms an amorphous indium-gallium-zinc-oxide (a-IGZO) oxide channel, and a step of doping fluorine into the a-IGZO may be added. Hereinafter, a method of doping fluorine into the a-IGZO oxide channel will be described in detail with reference to FIG. 3.

[0026] FIG. 3 is a flowchart illustrating a method for doping fluorine into an oxide channel of an oxide semiconductor memory device according to an embodiment of the present invention.

[0027] Referring to FIG. 3, a method for doping fluorine into an a-IGZO oxide channel of an oxide semiconductor memory device according to an embodiment of the present invention may include the steps of depositing an a-IGZO layer (S510), depositing a polymer layer containing a perfluorodecanoic acid (PFDA) on the a-IGZO layer (S520), depositing an aluminum oxide (Al2O3) layer on the polymer layer (S530), and performing a drive-in process of applying heat to the oxide channel (S540).

[0028] In step S510, the method for doping fluorine into the a-IGZO oxide channel of the oxide semiconductor memory device can deposit an a-IGZO layer to form an oxide channel 50 based on the a-IGZO.

[0029] In step S520, a method for doping fluorine into the a-IGZO oxide channel of an oxide semiconductor memory device can involve depositing a polymer layer containing a perfluorinated compound (PFDA) on the a-IGZO layer. Conventional methods of doping fluorine into a-IGZO can cause ion bombardment, which can degrade the morphology of the oxide channel and break ionic bonds. To solve these problems, a polymer layer containing a perfluorinated compound (PFDA), a fluorine-based polymer containing fluorine, can be deposited on the a-IGZO layer using an initiated chemical vapor deposition (iCVD) process.

[0030] In step S530, the method for doping fluorine into the a-IGZO oxide channel of the oxide semiconductor memory device can deposit an aluminum oxide (Al2O3) layer on the polymer layer. Here, the aluminum oxide (Al2O3) layer can serve as a capping layer to prevent fluorine from being lost to the atmosphere during a subsequent heat treatment process. The aluminum oxide (Al2O3) layer can be deposited on the polymer layer using a thin film process (Atomic Layer Deposition (ALD)).

[0031] In step S540, the method of doping fluorine into the a-IGZO oxide channel of the oxide semiconductor memory device may include a drive-in process to dope fluorine contained in a perfluorinated compound (PFDA) into the a-IGZO layer, where heat of 400°C may be applied to dope fluorine into the a-IGZO layer.

[0032] FIG. 4 is a graph showing the effect of an oxide semiconductor memory device according to an embodiment of the present invention.

[0033] FIG. 4 is a graph comparing the threshold voltage of the gate voltage according to the drain current value of an oxide semiconductor memory device according to an embodiment of the present invention and a conventional oxide semiconductor memory device.

[0034] A conventional oxide semiconductor memory device is an oxide channel semiconductor memory device formed only of a-IGZO, and the gate voltage depending on the drain current can be expressed as A. On the other hand, an oxide semiconductor memory device according to an embodiment of the present invention is an oxide channel semiconductor memory device formed by doping a-IGZO with fluorine, and the gate voltage depending on the drain current can be expressed as B.

[0035] It can be seen that the semiconductor memory device (A) with an oxide channel made only of a-IGZO has a negative threshold voltage (-1.3 V), whereas the semiconductor memory device (B) with a fluorine-doped a-IGZO oxide channel of the present invention has a positive threshold voltage (0.9 V). A negative threshold voltage can lead to the problem of normally-on characteristics, but the use of fluorine-doped a-IGZO oxide allows for normally-off characteristics.

[0036] It can also be seen that the semiconductor memory device (B) including the fluorine-doped a-IGZO oxide channel according to the present invention has improved on-current performance.

[0037] FIG. 5 is a perspective cross-sectional view illustrating a configuration of an oxide semiconductor memory device according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating a configuration of an oxide semiconductor memory device according to an embodiment of the present invention.

[0038] 5 and 6, an oxide semiconductor memory device according to an embodiment of the present invention may include a blocking layer 100 located on an oxide channel 50, a charge trapping layer 200 located on the blocking layer 100 and trapping injected charges, a tunnel layer 300 located on the charge trapping layer 200, a gate electrode 400 located on the tunnel layer 300 and to which an on voltage and an off voltage from a gate bias circuit are applied, and the oxide channel 50.

[0039] Here, the oxide channel 50 may be formed of fluorine-doped a-IGZO. Also, to dope fluorine into the a-IGZO, a polymer layer containing a perfluorodecanoic acid (PFDA) may be deposited by an initiated chemical vapor deposition (iCVD) process. Also, to dope fluorine into the a-IGZO, an aluminum oxide (Al2O3) layer may be deposited by an atomic layer deposition (ALD) process to prevent fluorine from being lost to the atmosphere during a heat treatment process.

[0040] Although the preferred embodiments of the present invention have been described above, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present invention. Therefore, the technical concept of the present invention includes not only each of the disclosed embodiments but also combinations of the disclosed embodiments, and the scope of the technical concept of the present invention is not limited by such embodiments. Furthermore, a person skilled in the art to which the present invention pertains can make numerous changes and modifications to the present invention without departing from the spirit and scope of the appended claims, and all such appropriate changes and modifications should be considered as equivalents within the scope of the present invention. [Explanation of symbols]

[0041] 50 oxide channels 100 blocking layers 200 Charge trap layer 300 Tunnel Layer 400 gate electrode

Claims

1. (a) alternately stacking word lines and insulating films; (b) forming a cylindrical hole at the center of the stacked word line and insulating film, and forming a tunnel layer on the inner circumferential surface of the hole; (c) forming a charge trapping layer on an inner peripheral surface of the tunnel layer; (d) forming a blocking layer on an inner peripheral surface of the charge trapping layer; (e) forming an oxide channel on an inner circumferential surface of the insulating layer; (f) removing the insulating film and depositing metal along the word line to form a gate electrode; In the step (e), the oxide channel is A method for manufacturing an oxide semiconductor memory device, which is formed of fluorine-doped a-IGZO (amorphous indum-gallium-zinc-oxide).

2. The step (e) comprises: (e-1) depositing an a-IGZO layer; (e-2) depositing a polymer layer containing a perfluorinated compound (perfluorodecanoic acid, PFDA) on the a-IGZO layer; (e-3) Aluminium oxide (Al) is deposited on the polymer layer. ２ O ３ ) layer; and (e-4) performing a drive-in process of applying heat to the oxide channel.

3. The step (e-2) 3. The method of claim 2, wherein the polymer layer containing the perfluorinated compound is deposited by an initiated chemical vapor deposition (iCVD) process.

4. The step (e-3) is 3. The method of claim 2, wherein the aluminum oxide layer is deposited by atomic layer deposition (ALD).

5. The step (e-4) is The method for manufacturing an oxide semiconductor memory device according to claim 2 , wherein heat is applied at 400° C.

6. a blocking layer located on the oxide channel; a charge trapping layer located on the blocking layer for trapping injected charges; a tunnel layer located on the charge trapping layer; a gate electrode located on the tunnel layer, to which an on-voltage and an off-voltage from a gate bias circuit are applied; The oxide channel is An oxide semiconductor memory device formed of fluorine-doped a-IGZO (amorphous indium-gallium-zinc-oxide).

7. The oxide channel is 7. The oxide semiconductor memory device according to claim 6, wherein the polymer layer containing perfluorodecanoic acid (PFDA) is deposited by an initiated chemical vapor deposition (iCVD) process.

8. The oxide channel is Aluminum oxide (Al) is deposited by a thin film process (Atomic Layer Deposition, ALD). ２ O ３ 7. The oxide semiconductor memory device according to claim 6, wherein a SiO.sub.2 layer is deposited.

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