Semiconductor device

Abstract

To provide a semiconductor device capable of improving voltage-withstanding.SOLUTION: A semiconductor device comprises an insulation layer 2, which is formed on a semiconductor substrate 1, and a resistor which is embedded in the insulation layer 2. The resistor includes: a first resistive layer (resistor R(1)); a first embedded electrode (second connection region BE(2)) electrically connected to one end of the first resistive layer; a first dummy wire (DW(1)) capacity-coupled to the first embedded electrode; a second resistive layer (resistor R(2)) disposed adjacently to the first resistive layer (resistor R(1)); and a second embedded electrode (BE(N)) electrically connected to one end of the second resistive layer (resistor R(2)) and electrically connected to the first dummy wire (DW(1)).SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistor elements within a chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview] The present disclosure provides a semiconductor device capable of improving the breakdown voltage.

[0005] The semiconductor device of the present disclosure comprises an insulating layer formed on a semiconductor substrate and a resistor embedded in the insulating layer, the resistor comprising a first resistive layer, a first buried electrode electrically connected to one end of the first resistive layer, a first dummy wiring capacitively coupled to the first buried electrode, a second resistive layer arranged adjacent to the first resistive layer, and a second buried electrode electrically connected to one end of the second resistive layer and electrically connected to the first dummy wiring. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor package equipped with a high-voltage detection device. [Figure 2] FIG. 2 is a circuit diagram of the high voltage detection device. [Figure 3] FIG. 3 is a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)). [Figure 4] FIG. 4 is a circuit diagram of a resistor including a high resistance portion. [Figure 5] FIG. 5 is a plan view of a resistor including a high resistance portion. [Figure 6] 6A and 6B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 5 along the arrow AA (FIG. 6A), a diagram showing the longitudinal cross-sectional configuration along the arrow BB (FIG. 6B), and a diagram showing the longitudinal cross-sectional configuration along the arrow CC (FIG. 6C). [Figure 7] FIG. 7 is a circuit diagram of a resistor including a high resistance portion. [Figure 8] FIG. 8 is a plan view of a resistor including a high resistance portion. [Figure 9] 9A and 9B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 8 taken along the arrow AA (FIG. 9A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 9B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 9C). [Figure 10] FIG. 10 is a perspective view of the vicinity of the end of the resistance layer. [Figure 11] FIG. 11 is a plan view of a resistor in which a dummy wiring is placed near the high-voltage input electrode. [Figure 12] FIG. 12 is a plan view of an example resistor chip. [Figure 13] FIG. 13 is a plan view of the area near the high resistance portion of the resistor chip. [Figure 14] FIG. 14 is a plan view of a resistor including a high resistance portion in which the spacing between resistive layers is changed. [Figure 15] 15A, 15B, and 15C are plan views of the low resistance portion for voltage detection. [Figure 16] FIG. 16 is a perspective view of the vicinity of the end of the resistance layer.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0008] 1 is a plan view of a semiconductor package 100 equipped with a high-voltage detection device, with the top cover removed.

[0009] The semiconductor package 100 includes a case 30 having a recess D1. The case 30 is made of an insulating material such as resin or ceramic. The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 within the recess D1 and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 within the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an enclosed space within the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. An appropriate potential, such as ground potential, is applied to the first die pad 110 and the second die pad 120 via a lead frame. If necessary, the potential of the first die pad 110 may be set to a high potential, for example.

[0010] The output voltage of the resistor chip 10 is input to the amplifier chip 20. The amplifier chip 20 outputs an output voltage corresponding to the detected voltage.

[0011] The positive terminal of the battery 200 is electrically connected to the first inner lead 10a and is connected via a bonding wire to the first electrode E1 (see FIG. 2) of the resistor chip 10. The negative terminal of the battery 200 is electrically connected to the second inner lead 10b and is connected via a bonding wire to the second electrode E2 (see FIG. 2) of the resistor chip 10.

[0012] Each terminal of the amplifier chip 20 can be connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, and the ninth inner lead 10i via bonding wires.

[0013] For example, the third inner lead 10c is supplied with a power supply voltage Vcc and input to the amplifier chip 20. The ninth inner lead 10i is supplied with a ground potential GND and input to the amplifier chip 20. The sixth inner lead 10f can output an output voltage Vout. The fourth inner lead 10d can output a monitor signal corresponding to the potential of the first output electrode EP (see Figure 2). The eighth inner lead 10h can output a monitor signal corresponding to the potential of the second output electrode EN (see Figure 2). The fifth inner lead 10e and the seventh inner lead 10g can be used for other purposes as needed.

[0014] 2 is a circuit diagram of a high-voltage detection device. The high-voltage detection device includes a resistor circuit C10 (voltage divider circuit) and a voltage detection circuit C20. The resistor chip 10 described above includes the resistor circuit C10. The amplifier chip 20 includes the voltage detection circuit C20. A first input terminal HV(+) of the resistor circuit C10 is electrically connected to the positive electrode of the battery 200. A second input terminal HV(-) of the resistor circuit C10 is electrically connected to the negative electrode of the battery 200. The first input terminal HV(+) is electrically connected to a first electrode E1 (electrode pad). The second input terminal HV(-) is electrically connected to a second electrode E2 (electrode pad).

[0015] The resistance circuit C10 includes a first high resistance section RP (first resistor), a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN (second resistor). The first high resistance section RP, the first low resistance section RPS, the second low resistance section RNS, and the second high resistance section RN are connected in series in this order between the first electrode E1 and the second electrode E2. The first high resistance section RP and the second high resistance section RN have a function of reducing a high voltage and each have a high resistance value. The first low resistance section RPS and the second low resistance section RNS have a function of detecting a voltage and each have a relatively low resistance value compared to the high resistance sections.

[0016] An exemplary resistance value of one high resistance section is 500 MΩ, but it can also be 1 MΩ or more and 1000 MΩ or less. The resistance value of the high resistance section can also be 100 MΩ or more and 800 MΩ or less. The resistance value of the high resistance section can also be 300 MΩ or more and 600 MΩ or less. This resistance value should be a resistance value that can withstand high voltages and allows voltage detection.

[0017] The resistance of one low resistance section (RPS or RNS) is equal to or less than K% of the resistance of the high resistance section. Exemplary values ​​of K are 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, 0.05%, or 0.01%, and the resistance of the low resistance section can be, for example, 0.01 MΩ to 10 MΩ.

[0018] A first output electrode EP (electrode pad) is electrically connected to the connection point between the first high resistance section RP and the first low resistance section RPS. A second output electrode EN (electrode pad) is electrically connected to the connection point between the second high resistance section RN and the second low resistance section RNS. A reference electrode EG (electrode pad) is electrically connected between the first low resistance section RPS and the second low resistance section RNS.

[0019] The resistor circuit C10 is a voltage divider circuit, which can obtain a voltage corresponding to the resistance value between two selected points within the resistor circuit C10. The first output electrode EP is electrically connected to the first input terminal INP of the voltage detection circuit C20. The second output electrode EN is electrically connected to the second input terminal INN of the voltage detection circuit C20. The reference electrode EG is electrically connected to the reference terminal VC of the voltage detection circuit C20. The potential of the reference terminal VC can be set to, for example, ground potential. The voltage detection circuit C20 can output an output voltage Vout. The output voltage Vout can be the sum of a first potential difference between the first input terminal INP and the reference terminal VC and a second potential difference between the second input terminal INN and the reference terminal VC. The voltage detection circuit C20 can include a source follower (amplifier) ​​that amplifies the voltage input from the input terminals and a differential amplifier circuit that obtains the sum of the input voltages. The voltage detection circuit C20 has an input terminal for a power supply voltage Vcc for operating the internal circuit and an input terminal for setting the ground potential GND.

[0020] Resistor circuit C10 may include a dummy resistor.

[0021] FIG. 3 shows a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)).

[0022] In the resistor circuit C10 of FIG. 3A, one end of a dummy resistor R (Dmy) is electrically connected to the input side of the first high resistance section RP. The dummy resistor R (Dmy) is electrically connected to the input side of the second high resistance section RN. The dummy resistor does not need to be electrically connected to a resistor. For example, resistors at both ends of a resistor chip may have different resistance characteristics compared to resistors near the center. Treating such resistors as dummy resistors may improve detection accuracy.

[0023] The resistor circuit C10 in FIG. 3B has a configuration that is a modification of the circuit of the first example. In this example, the first high resistance section RP is composed of a high resistance section RP1 and a high resistance section RP2 connected in series, and the second high resistance section RN is composed of a high resistance section RN1 and a high resistance section RN2 connected in series. In addition, the reference electrode EG is separated into a first reference electrode EG1 and a second reference electrode EG2, and these electrodes are electrically connectable on the voltage detection circuit side. Furthermore, compared to the circuit of the first example, one or more dummy resistors R (Dmy) are provided between each resistor section.

[0024] The dummy resistor is a resistor through which no current flows, and is provided to maintain electrical equivalence in the resistor circuit C10, maintain electrical stability, or reduce error factors that may occur during resistor manufacturing in the manufacturing process. The circuit configuration of the high voltage detection device is not limited to these, and the shape and arrangement of the resistor may be changed as long as the basic voltage detection function is achieved.

[0025] As described above, the high-voltage detection device can be housed in a single semiconductor package. Alternatively, the functions of each circuit can be separated into a resistor chip and an amplifier chip and mounted in the package. Modifications are also possible in which some of the circuit elements are moved to either chip or integrated into a single chip.

[0026] FIG. 4 is a circuit diagram of a resistor including a high resistance portion.

[0027] The high voltage (HV) input terminal is connected to the first electrode E1 (or the second electrode E2). The first electrode E1 is electrically connected to the first high resistance section RP. The second electrode E2 is electrically connected to the second high resistance section RN. The first high resistance section RP (or the second high resistance section RN) includes a plurality of resistors R connected in series. The node to which the high voltage (high potential) is first input in the first high resistance section RP (or the second high resistance section RN) is defined as the first node N1. Within the first high resistance section RP (or the second high resistance section RN), the second node N2 of the resistor R adjacent to the resistor R connected to the first node N1 is adjacent to the first node N1.

[0028] A dummy resistor R (Dmy) (extension region) is electrically connected to an end of the first high resistance portion RP (or the second high resistance portion RN). The dummy resistor R (Dmy) includes one or more resistors R. Each resistor R is a resistive layer, and a specific example of its planar shape is a linear shape extending linearly, so this resistor R can be called a linear resistor or a linear-shaped resistor. In the dummy resistor R (Dmy) of this example, both ends of each resistor R are short-circuited, and the multiple resistors R are connected in parallel. In this example, a buried electrode BE (buried wiring) including the third node N3 short-circuits both ends of the resistor R in the dummy resistor R (Dmy), but the short-circuiting may be performed by other wiring.

[0029] This buried short-circuiting electrode BE (buried wiring) can be arranged directly below the dummy resistor R (Dmy). The buried short-circuiting electrode BE is capacitively coupled to a dummy wiring DW arranged nearby, forming a parasitic third capacitor C3. The dummy wiring DW is a wiring through which no current normally flows, but is a bypass wiring through which AC current can flow when a surge voltage or the like is input. The dummy wiring DW can also be extended to the vicinity of the high-voltage input electrode (first electrode E1 or second electrode E2).

[0030] When a voltage large relative to the ground potential is input to the first electrode E1 (or the second electrode E2), that voltage is transmitted to the first node N1. In a steady state, the potential of the first node N1 drops via one or more resistors R connected in series to it, and the potential after the voltage drop appears at the second node N2. If the potential of the first node N1 increases instantaneously, the potential of the second node N2 cannot immediately follow this change, and a large potential difference occurs between the first node N1 and the second node N2.

[0031] For example, if the gap between a first resistor R (R(1)) having a first node N1 at one end and a second resistor R (R(2)) having a second node N2 is 1 μm, breakdown may occur if a voltage (e.g., 4000 V) exceeding the voltage (e.g., 500 V) that provides an electric field that can be withstood by this gap is applied between the first node N1 and the second node N2.

[0032] In this example, a dummy wiring DW is connected to the second node N2. The dummy wiring DW forms a parasitic first capacitor C1 between itself and the buried electrode including the first node N1. Therefore, the dummy wiring DW is capacitively coupled to the first node N1 via the first capacitor C1, and is also capacitively coupled to the third node N3 via the third capacitor C3.

[0033] The potential of the first node N1 is equal to the potential of the third node N3. When the magnitude of the potential of the third node N3 (and the first node N1) suddenly increases, a current flows from the buried electrode BE to the dummy wiring DW via the third capacitor C3, and also to the dummy wiring DW via the first capacitor C1, increasing the magnitude of the potential of the second node N2. In other words, the potential difference between the first node N1 and the second node N2 is reduced, and damage near the nodes due to a sudden voltage change can be suppressed.

[0034] The combined capacitance of the exemplary capacitors (C1, C3) is preferably at least 1 fF or more, and preferably 10 fF or more, in which case it is believed that sudden voltage changes can be sufficiently suppressed.

[0035] If the potential of the second node N2 suddenly increases, a potential difference may occur between the node of the adjacent resistor R on the lower potential side, which may result in breakdown. Therefore, it is preferable to electrically connect multiple dummy wires to one end of each resistor R.

[0036] Fig. 5 is a plan view of a resistor including the high resistance portion shown in Fig. 4. Note that the resistor, embedded electrodes, and dummy wiring are actually embedded in an insulating layer, but for clarity of explanation, the insulating layer is not shown.

[0037] Each resistor R extends along the X-axis direction, and multiple resistors R are aligned along the Y-axis direction. The depth direction of the chip is the Z-axis, which is perpendicular to the X-axis and Y-axis. Via electrodes VE are physically and electrically connected to the undersides of both ends of each resistor R, and the via electrodes VE are physically and electrically connected to buried electrodes BE. Note that, because the physical connection of conductive elements involves electrical connection, in the explanation, the term "connection" may be used simply when the connection state is clear.

[0038] In the dummy resistor R (Dmy), the embedded electrode BE has a first connection region BE(1) that connects all of the ends on one side of the multiple resistors R, a second connection region BE(2) that connects all of the ends on the other side, and a third connection region BE(3) that connects these connection regions. The third connection region BE(3) forms one electrode of the third capacitor C3.

[0039] In the first high resistance section RP (or the second high resistance section RN), the embedded electrode BE connects one end of the nth and n+1th resistors R counting from the high voltage (HV) side along the Y-axis direction, and connects the other end of the n+1th and n+2th resistors R (n is a natural number).

[0040] It is also possible to consider a structure in which the vertical positional relationship between the via electrodes VE and buried electrodes BE and the resistor R is reversed. In this case, the resistor R is positioned in a lower layer than the via electrodes VE and buried electrodes BE.

[0041] The buried electrode BE connected to the input side electrode that provides a high voltage (HV) is connected to one end of the input side of the first resistor R through a buried electrode BE (second connection region BE(2)) located below one end of the dummy resistor R (Dmy) and via a via electrode VE. One end of the second resistor R next to the first is connected to the buried electrode BE(N) through a via electrode VE. The buried electrode BE(N), like the other buried electrodes BE, connects one end of the adjacent resistor R through a via electrode VE. The buried electrode BE(N) is connected to the dummy wiring DW located above it through a second via electrode VE2.

[0042] A plurality of resistors R in the high resistance section are connected in series between an electrode that applies a high voltage (HV) and an output electrode that becomes a low voltage (LV).

[0043] In a plan view, the region where the dummy resistor R(Dmy) is arranged is an extended region extending in the longitudinal direction (Y-axis direction) of the resistor when viewed from the high resistance portion. The shortest distance X1 between the first buried electrode (second connection region BE(2)) included in this extended region and the second buried electrode (buried electrode BE(N) directly below the resistor R(2)) and the shortest distance X2 between the first buried electrode (third connection region BE(3)) included in the extended region and the dummy wiring DW satisfy the relationship X1≦X2. In the third capacitor C3 that provides X2, the electric field strength tends to be reduced and the voltage resistance tends to be increased.

[0044] As described above, the resistor chip includes an insulating layer formed on a semiconductor substrate and a resistor embedded in the insulating layer. The resistor includes a first resistance layer (the first resistor R(1) from the high potential side in the high resistance section), a first buried electrode (second connection region BE(2)) electrically connected to one end of the first resistance layer, a first dummy wiring (DW) capacitively coupled to the first buried electrode via a third capacitor C3 (and the first capacitor C1), a second resistance layer (the second resistor R(2) from the high potential side in the high resistance section) disposed adjacent to the first resistance layer (resistor R(1)), and a second buried electrode (BE(N)) electrically connected to one end of the second resistance layer (resistor R(2)) and electrically connected to the first dummy wiring (DW).

[0045] 6A and 6B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 5 along the arrow AA (FIG. 6A), a diagram showing the longitudinal cross-sectional configuration along the arrow BB (FIG. 6B), and a diagram showing the longitudinal cross-sectional configuration along the arrow CC (FIG. 6C).

[0046] As shown in FIGS. 6(A) to 6(C), the resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0047] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0048] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top.L and the lower dielectric layer 2A L Upper dielectric layer 2A formed on H The lower dielectric layer 2A L and upper dielectric layer 2A H The exemplary material is the same as the material of the first dielectric layer 2A.

[0049] The protective film 4 includes a first protective film 4A, a second protective film 4B, and a third protective film 4C, which are sequentially stacked on the insulating layer 2. The first protective film 4A may be made of an inorganic insulator such as silicon oxide or silicon nitride, for example, SiO2. The second protective film 4B is formed on the first protective film 4A. The second protective film 4B is made of an inorganic insulator such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, for example, silicon nitride. The third protective film 4C is made of a resin (insulator) such as polyimide.

[0050] The buried electrodes BE (including BE(1) to BE(3) and BE(N)) are formed on the lower dielectric layer 2A. L An upper dielectric layer 2A is formed on the H The upper dielectric layer 2A is located within the H can have multiple dielectric layers (insulating layers), and the upper dielectric layer 2A H A resistor R (resistance layer) is formed on a specific dielectric layer in the upper dielectric layer 2A, and the buried electrode BE and the resistor R are connected by a via electrode VE. Also, as shown in FIG. 6(C), the lower surface of the dummy wiring DW is H It is connected to the buried electrode BE(N) at the bottom through a second via electrode VE2 passing through it.

[0051] Next, an example in which a plurality of dummy wirings are electrically connected to one end of each resistor R will be described.

[0052] FIG. 7 is a circuit diagram of a resistor including a high resistance portion.

[0053] The high voltage (HV) input terminal is connected to the first electrode E1 (or the second electrode E2). The first electrode E1 is electrically connected to the first high resistance section RP. The second electrode E2 is electrically connected to the second high resistance section RN. The first high resistance section RP (or the second high resistance section RN) includes a plurality of resistors R connected in series. The node to which the high voltage (high potential) is first input in the first high resistance section RP (or the second high resistance section RN) is defined as the first node N1. Within the first high resistance section RP (or the second high resistance section RN), the second node N2 of the resistor R adjacent to the resistor R connected to the first node N1 is adjacent to the first node N1.

[0054] A dummy resistor R (Dmy) is electrically connected to an end of the first high resistance portion RP (or the second high resistance portion RN). The dummy resistor R (Dmy) includes one or more resistors R. Each resistor R is a resistive layer, and an example of a specific planar shape is a linear shape extending linearly. In the dummy resistor R (Dmy) of this example, both ends of each resistor R are short-circuited, and the multiple resistors R are connected in parallel. In this example, the embedded wiring BE including the third node N3 short-circuits both ends of the resistor R in the dummy resistor R (Dmy), but the short-circuiting may be performed by other wiring.

[0055] This buried short-circuit wiring BE can be placed directly below the dummy resistor R (Dmy). The buried short-circuit wiring BE is capacitively coupled to two dummy wirings DW placed nearby, each of which forms a parasitic third capacitor (C311, C312). The dummy wiring DW is a wiring through which no current normally flows, but is a bypass wiring through which AC current can flow when a surge voltage or the like is input. The dummy wiring DW can also be extended to the vicinity of the high-voltage input electrode (first electrode E1 or second electrode E2).

[0056] When a voltage large relative to the ground potential is input to the first electrode E1 (or the second electrode E2), that voltage is transmitted to the first node N1. In a steady state, the potential of the first node N1 drops via one or more resistors R connected in series to it, and the potential after the voltage drop appears at the second node N2. If the potential of the first node N1 increases instantaneously, the potential of the second node N2 cannot immediately follow this change, and as explained in the above example, a large potential difference occurs between the first node N1 and the second node N2, which may result in breakdown.

[0057] A dummy wiring DW is connected to the second node N2. The dummy wiring DW forms a parasitic first capacitor (C11) between itself and the buried electrode including the first node N1. Therefore, the dummy wiring DW is capacitively coupled to the first node N1 via the first capacitor (C11) and also capacitively coupled to the third node N3 via the third capacitor (C311).

[0058] The potential of the first node N1 is equal to the potential of the third node N3. When the magnitude of the potential of the third node N3 (and the first node N1) suddenly increases, a current flows from the buried electrode BE to the dummy wiring DW via the third capacitor (C311), and also to the dummy wiring DW via the first capacitor (C11), increasing the magnitude of the potential of the second node N2. In other words, the potential difference between the first node N1 and the second node N2 is reduced, and damage near the nodes due to a sudden voltage change can be suppressed.

[0059] When the magnitude of the potential at the second node N2 increases suddenly, a potential difference tends to occur between the node of the resistor R adjacent thereto.

[0060] Therefore, in this example, a dummy wiring DW is also connected to the node Na adjacent to the second node N2, and this dummy wiring DW forms a parasitic capacitor (C12) together with the dummy wiring DW adjacent to it on the inside, forming a capacitor (C321). These capacitors (C12, C321) are connected to the first capacitor (C11) and the third capacitor (C311), and as a result, are coupled to the buried electrode BE of the dummy resistor.

[0061] Similarly, a dummy wiring DW is connected to a node Nb adjacent to the node Na, and this dummy wiring DW forms a parasitic capacitor C13 together with the adjacent dummy wiring DW on the inside, forming a capacitor C331. These capacitors C13, C331 are connected to the capacitors C12, C11 and the capacitors C321, C311, and are consequently coupled to the buried electrodes BE of the dummy resistors.

[0062] On the opposite side of the capacitors (C11 to C13, C311 to C331), a plurality of dummy wirings DW are arranged so as to form parasitic capacitors (C21 to C23, C312 to C332). This circuit arrangement improves equivalence and also alleviates a sudden rise in potential at the end of each resistor R on the opposite side from the first node N1.

[0063] More specifically, on the opposite side of the first node N1 of the first resistor R(1) in the high resistance section is a node Nd, and a parasitic capacitor (C21) formed by a dummy wiring DW is capacitively coupled to the node Nd. This dummy wiring DW is connected to a node Ne on the opposite side of the second node N2 of the third resistor R(3) in the high resistance section. The dummy wiring DW connected to the node Ne, together with the buried electrode BE of the dummy resistor, forms a parasitic capacitor (C21) and a capacitor (C312).

[0064] On the opposite side of the node Na of the fifth resistor R(5) in the high resistance section is the node Nf, and the dummy wiring DW connected to the node Nf, together with the adjacent dummy wiring DW on the inside, forms a parasitic capacitor (C22) and a capacitor (C322).

[0065] On the opposite side of node Nb of the seventh resistor R(7) in the high resistance section is node Ng, and the dummy wiring DW connected to node Ng, together with the adjacent dummy wiring DW on the inside, forms parasitic capacitors (C23) and (C332).

[0066] Dummy wirings DW are also connected to the other nodes Nc and Nh located at both ends of the resistor R, and are capacitively coupled to the adjacent dummy wirings DW. Note that the number of dummy wirings is an example, and for example, the number of dummy wirings on one side connected to one end of the resistor R can be four or more, six or more, eight or more, or ten or more.

[0067] The range of the combined capacitance of the exemplary capacitors (C11, C311) can be set to the same range as the combined capacitance of the capacitors (C1, C3) described above. It is believed that within such a range, sudden voltage changes can be sufficiently suppressed. Similarly, the combined capacitance of the capacitors (C12, C321), the combined capacitance of the capacitors (C13, C331), the combined capacitance of the capacitors (C21, C312), the combined capacitance of the capacitors (C22, C322), and the combined capacitance of the capacitors (C23, C332) can be set to the same range as described above, but may also be set to other ranges.

[0068] Fig. 8 is a plan view of a resistor including the high resistance portion shown in Fig. 7. Note that the resistor, embedded electrodes, and dummy wiring are actually embedded in an insulating layer, but for clarity of explanation, the insulating layer is not shown.

[0069] Each resistor R extends along the X-axis direction, and the resistors R are aligned along the Y-axis direction. Via electrodes VE are physically and electrically connected to the lower surfaces of both ends of each resistor R, and the via electrodes VE are physically and electrically connected to buried electrodes BE.

[0070] In the dummy resistor R (Dmy), the embedded electrode BE has a first connection region BE(1) that connects all of the ends on one side of the multiple resistors R, a second connection region BE(2) that connects all of the ends on the other side, and a third connection region BE(3) that connects these connection regions. The third connection region BE(3) forms one electrode of the third capacitor (C311, C312).

[0071] In the first high resistance section RP (or the second high resistance section RN), the embedded electrode BE connects one end of the nth and n+1th resistors R and connects the other end of the n+1th and n+2th resistors R along the Y-axis direction (n is a natural number).

[0072] It is also possible to consider a structure in which the vertical positional relationship between the via electrodes VE and buried electrodes BE and the resistor R is reversed. In this case, the resistor R is positioned in a lower layer than the via electrodes VE and buried electrodes BE.

[0073] The buried electrode BE connected to the electrode that supplies the high voltage (HV) is connected to one end of the input side of the first resistor R(1) of the high resistance section through a via electrode VE via a buried electrode BE (second connection region BE(2)) located below one end of the dummy resistor R(Dmy).

[0074] One end of the next second resistor R(2) is connected to the buried electrode BE(N) through a via electrode VE. Like the other buried electrodes BE, the buried electrode BE(N) connects one end of the adjacent resistor R through the via electrode VE. The buried electrode BE(N) is connected to the dummy wiring DW located above it through a second via electrode VE2 (located in the region S).

[0075] The buried electrodes BE are located directly below the resistor-side ends of the plurality of dummy wirings DW, and each dummy wiring DW is connected to the buried wiring BE directly below it via a second via electrode VE2.

[0076] The multiple resistors R in the high resistance section are connected in series between an input electrode that applies a high voltage (HV) and an output electrode that becomes a low voltage (LV).

[0077] As described above, the resistor chip includes an insulating layer formed on a semiconductor substrate and a resistor embedded in the insulating layer. The resistor includes a first resistance layer (the first resistor R(1) from the high potential side in the high resistance section), a first buried electrode (second connection region BE(2)) electrically connected to one end of the first resistance layer, a first dummy wiring (DW(1)) capacitively coupled to the first buried electrode via capacitors (C311, C11), a second resistance layer (the second resistor R(2) from the high potential side in the high resistance section) disposed adjacent to the first resistance layer (resistor R(1)), and a second buried electrode (BE(N)) electrically connected to one end of the second resistance layer (resistor R(2)) and electrically connected to the first dummy wiring (DW(1)).

[0078] The resistor also includes a resistive layer (resistor R(3)), a buried electrode BE(N) electrically connected to one end of the resistive layer (resistor R(3)), a first dummy wiring (DW(1)) electrically connected to the buried electrode BE(N), a second dummy wiring (DW(2)) capacitively coupled to the first dummy wiring (DW(1)) via capacitors (C321, C12), a (second) buried electrode BE electrically connected to the second dummy wiring (DW(2)), and a resistive layer (resistor R(4)) electrically connected to the (second) buried electrode BE and arranged adjacent to the resistive layer (resistor R(3)).

[0079] 9A and 9B are a diagram showing the longitudinal cross-sectional configuration of the resistor shown in FIG. 8 taken along the arrow AA (FIG. 9A), a diagram showing the longitudinal cross-sectional configuration taken along the arrow BB (FIG. 9B), and a diagram showing the longitudinal cross-sectional configuration taken along the arrow CC (FIG. 9C).

[0080] As shown in FIGS. 9(A) to 9(C), the resistor chip includes a semiconductor substrate 1, an insulating layer 2 provided on the semiconductor substrate 1, and a protective film 4 provided on the insulating layer 2.

[0081] The structures of the insulating layer 2 and the protective film 4 are the same as those shown in FIG.

[0082] The buried electrodes BE (including BE(1) to BE(3) and BE(N)) are formed on the lower dielectric layer 2A. L An upper dielectric layer 2A is formed on the H The upper dielectric layer 2A is located within the H can have multiple dielectric layers (insulating layers), and the upper dielectric layer 2A H A resistor R (resistance layer) is formed on a specific dielectric layer in the upper dielectric layer 2A, and the buried electrode BE and the resistor R are connected by a via electrode VE. Also, as shown in FIG. 6(C), the lower surface of the dummy wiring DW is H The dummy wirings DW are connected to the underlying buried electrode BE(N) through a second via electrode VE2 passing through the dummy wirings DW. The dummy wirings DW are adjacent to each other along the X-axis direction, with a first protective film 4A interposed between them. The capacitance between the dummy wirings can also be changed by changing the dielectric constant of the first protective film 4A.

[0083] The capacitance of the capacitor between the dummy wirings depends on the size of the gap, the area of ​​the side of the dummy wiring DW, and the dielectric constant of the dielectric between them. The range of the gap between the dummy wirings DW can be set to satisfy the exemplary range of the combined capacitance of the capacitor described above.

[0084] FIG. 10 is a perspective view of the vicinity of the end of the resistance layer.

[0085] The connection structure between the second via electrode VE2 and the buried wiring BE is the same everywhere, but as an example, the structure of the second via electrode VE2 and the buried wiring BE(N) inside the region S in FIG. 8 is shown.

[0086] A pair of resistors R are arranged adjacent to each other. The bottom surface of each resistor R is connected to the top surface of the buried wiring BE(N) through a via electrode VE. The top surface of the buried wiring BE(N) is connected to the bottom surface of the dummy wiring DW through a second via electrode VE2.

[0087] FIG. 11 is a plan view of a resistor in which a dummy wiring is arranged near the high-voltage input electrode.

[0088] When multiple dummy wirings DW extend from the first high resistance portion RP (or the second high resistance portion RN) as described above, the multiple dummy wirings DW may be extended to the periphery of the first electrode E1 (or the second electrode E2) and arranged to surround the first electrode E1 (or the second electrode E2). The number of dummy wirings is not limited to the above number.

[0089] In the first dummy wiring region DMY1 including a group of dummy wirings connected to one end of each resistor, multiple dummy wirings may be arranged further outside the dummy wirings DW located on the outside in the drawing along the direction of the first arrow A1. The dummy wirings in the first dummy wiring region DMY1 extend to a position on the opposite side of the first high resistance portion RP (or second high resistance portion RN) of the first electrode E1 (or second electrode E2).

[0090] In the second dummy wiring region DMY2 including the dummy wiring group connected to the other side of each resistor, multiple dummy wirings may be arranged further outside the dummy wiring DW located on the outside in the figure along the direction of the second arrow A2. The dummy wirings in the second dummy wiring region DMY2 extend to a position on the opposite side of the first electrode E1 (or the second electrode E2) from the first high resistance portion RP (or the second high resistance portion RN).

[0091] The dummy wiring groups in the first dummy wiring region DMY1 and the second dummy wiring region DMY2 face each other with a gap between them at a position opposite to the first high resistance portion RP (or second high resistance portion RN) of the first electrode E1 (or second electrode E2).

[0092] In a third dummy wiring region DMY3 including a dummy wiring group located on the low-voltage side among the dummy wiring groups connected to one end of each resistor, a plurality of dummy wirings may be arranged along the direction of a third arrow A3. The third dummy wiring region DMY3 is a region adjacent to the first dummy wiring region DMY1, but the dummy wirings in this region do not reach the position of the first electrode E1 (or the second electrode E2).

[0093] In the fourth dummy wiring region DMY4, which includes a dummy wiring group located on the low-voltage side among the dummy wiring groups connected to one end of each resistor, a plurality of dummy wirings may be arranged along the direction of the fourth arrow A4. The fourth dummy wiring region DMY4 is a region adjacent to the second dummy wiring region DMY2, but the dummy wirings in this region do not reach the position of the first electrode E1 (or the second electrode E2).

[0094] Since the first electrode E1 (or the second electrode E2) is given a potential with a large absolute value, a gradual change in the electric field strength distribution around it increases the voltage tolerance. In this structure, part of the dummy wiring extends to a position surrounding the first electrode E1 (or the second electrode E2), and has the function of gradually lowering the electric potential around the electrode from the high-voltage side to the low-voltage side. This improves the voltage tolerance of the resistor chip. The third dummy wiring region DMY3 and the fourth dummy wiring region DMY4 arranged on the low-voltage side can preliminarily mitigate changes in electric field strength.

[0095] FIG. 12 is a plan view of an example resistor chip.

[0096] This resistor chip corresponds to the circuit diagram in FIG. 3(A). The resistor chip 10 is constructed by forming an insulating layer on a semiconductor substrate and embedding a resistor in the insulating layer. The resistor chip 10 has a rectangular planar shape and includes a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. A ring-shaped conductor 1R can be embedded in the insulating layer along these sides. The ring-shaped conductor 1R can be constructed of a metal material (e.g., copper). However, if necessary, a ring-shaped conductor made of another material (e.g., a resistive material CrSi) can be provided above or below the metal material and electrically connected by a via electrode (e.g., tungsten). The ring-shaped conductor can contribute to improving waterproofness and electrical stability.

[0097] In this example, in a plan view, the first electrode E1, dummy resistor R (Dmy), first high resistance section RP, first low resistance section RPS, second low resistance section RNS, second high resistance section RN, dummy resistor R (Dmy), and second electrode E2 are aligned in one direction. The first output electrode EP is electrically connected to the buried electrode between the first high resistance section RP and the first low resistance section RPS. The second output electrode EN is electrically connected to the buried electrode between the second high resistance section RN and the second low resistance section RNS. The reference electrode EG is electrically connected to the buried electrode between the first low resistance section RPS and the second low resistance section RNS.

[0098] Another example of a resistor chip is also conceivable.

[0099] For example, several structures are possible for a resistor chip corresponding to the circuit diagram in FIG. 3(B). The structure of another example of a resistor chip will be described with reference to the circuit diagram in FIG. 3(B) and the resistor chip structure described above. This resistor chip, like the resistor chip 10 shown in FIG. 12, is configured by forming an insulating layer on a semiconductor substrate and embedding a resistor in the insulating layer. The resistor chip 10 has a rectangular planar shape and includes a first side surface 10A, a second side surface 10B, a third side surface 10C, and a fourth side surface 10D. It is also possible to embed an annular conductor 1R in the insulating layer along these sides. The structure of the annular conductor 1R is as described above.

[0100] In another example of a resistor chip, in a plan view, the elements shown in FIG. 3B, i.e., the first electrode E1, dummy resistor R(Dmy), high resistance section RP2, dummy resistor R(Dmy), dummy resistor R(Dmy), high resistance section RN2, dummy resistor R(Dmy), and second electrode E2, are aligned along one direction. Also, in a plan view, the high resistance section RP1 and dummy resistor R(Dmy) are aligned next to the first electrode E1 in a direction perpendicular to the above-mentioned one direction. The dummy resistor R(Dmy), high resistance section RP1, dummy resistor R(Dmy), first low resistance section RPS, second low resistance section RNS, dummy resistor R(Dmy), high resistance section RN1, and dummy resistor R(Dmy) are aligned along one direction. One end of the low-voltage side of the high resistance section RP2 is connected to the first output electrode EP. One end on the low voltage side of the high resistance section RN2 is connected to the second output electrode EN.

[0101] One end on the low-voltage side of the first low-resistance unit RPS is electrically connected to the first reference electrode EG1, via an intermediate electrode if necessary. One end on the low-voltage side of the second low-resistance unit RNS is electrically connected to the second reference electrode EG2. The first reference electrode EG1 and the second reference electrode EG2 can also be shorted within the resistor chip or an external amplifier chip and used as the reference electrode EG.

[0102] The electrical connection of the circuit elements of another example of a resistor chip is as shown in Figure 3(B), but the arrangement of the circuit elements is not limited to the above arrangement example and various modifications are possible.

[0103] FIG. 13 is a plan view of the area near the high resistance portion of the resistor chip.

[0104] A dummy resistor R (Dmy) is arranged on the side of the first electrode E1 (or the second electrode E2). The first electrode E1 (or the second electrode E2) is arranged at the same depth as the dummy wiring DW. The buried wiring BE is continuous with the high voltage (HV) side of the third connection region BE (3) and is electrically connected to the first electrode E1 (or the second electrode E2) through a via electrode VE.

[0105] FIG. 14 is a plan view of a resistor including a high resistance portion in which the arrangement intervals of resistors R (resistance layers) are changed.

[0106] In the dummy resistor R (Dmy), the gap between adjacent resistors R in the Y-axis direction is ΔYD. In a plan view, in the first high resistance section RP (or the second high resistance section RN), the gap between adjacent resistors R in the Y-axis direction has a first gap ΔYRA (shortest distance between resistors R(W)) and a second gap ΔYRB (shortest distance between resistors R). The group of resistors R(W) providing the first gap ΔYRA (first region) is positioned closer to the dummy resistor R (Dmy) than the group of resistors R providing the second gap ΔYRB (second region). The first gap ΔYRA in the Y-axis direction is larger than the second gap ΔYRB, satisfying the relationship ΔYRB<ΔYRA. The gap ΔYD between the dummy resistors can be set equal to the second gap ΔYRB.

[0107] By satisfying the relationship ΔYRB<ΔYRA, even if the same potential difference as above occurs between resistors R(W) spaced widely apart, the electric field strength between the resistors can be reduced and the breakdown voltage can be increased.

[0108] Each buried electrode BE can be electrically connected to a dummy wiring via the second via electrode as described above. Even if such a dummy wiring is not connected, the effect of increasing the breakdown voltage can be obtained. However, when the dummy wiring is connected, the breakdown voltage increases synergistically, and it is possible to further suppress the breakdown of the resistor chip.

[0109] There are various possible configurations for the low resistance portion, and examples are given below.

[0110] 15A, 15B, and 15C are plan views of the low resistance portion for voltage detection.

[0111] The first low resistance section RPS (or the second low resistance section RNS) is made up of a plurality of linear resistors R EEach resistor R E A via electrode VE is provided below the end of the resistor, and is physically and electrically connected to the buried electrode BE located below the via electrode VE. The number of linear resistors may be three or more, or may be less than three.

[0112] In the example shown in FIG. 15(A), three linear resistors R E The linear resistor R E and one end of the second row of linear resistors R E The first end of the linear resistor R in the second row is connected to the first end of the linear resistor R in the second row through a via electrode VE and a buried electrode BE. E and the other end of the third row linear resistor R E The other end of the via electrode VE is connected to the other end of the buried electrode BE through a via electrode VE and a buried electrode BE.

[0113] In the example shown in FIG. 15(B), the linear resistor in FIG. 15(A) is divided into two in each row, and a plurality of linear resistors R E Therefore, there are a total of six linear resistors R E In each row, a pair of adjacent linear resistors R E The opposing ends of the electrodes are connected via a via electrode VE and a buried electrode BE.

[0114] In the example shown in FIG. 15(C), all the linear resistors R E One end of each of the linear resistors R is connected to the other end of each of the linear resistors R through a via electrode VE and a common buried electrode BE. E The other ends of the resistors are connected through a via electrode VE and a common buried electrode BE. In this example, the combined resistance value can be reduced more than that of the resistor shown in FIG.

[0115] The cross-sectional structure of the low resistance section (RPS, RNS) for detection can be the same as that of the high resistance section (RP, RN) except for the planar shape. EThe via electrodes VE and the buried electrodes BE (buried wiring) are buried in an insulating layer formed on a semiconductor substrate.

[0116] FIG. 16 is a perspective view of the vicinity of the end of the resistance layer.

[0117] A pair of resistors R are arranged adjacent to each other. The bottom surface of each resistor R is connected to the top surface of the buried wiring BE via a via electrode VE. On the other hand, the top surface of the buried wiring BE is not connected to the bottom surface of the dummy wiring DW, and a parasitic capacitor is formed between them. This resistor R (resistance layer) can be located far from the high-potential location of the high-resistance section. For example, such a capacitor connection structure can be adopted in the third dummy wiring region DMY3 and the fourth dummy wiring region DMY4 in FIG. 11. As shown in FIG. 10, the type in which the connection is made using the second via electrode VE2 is considered to be a direct connection structure.

[0118] Note that the connection structures between the resistance layer constituting the high resistance portion and the dummy wiring may all be direct connection structures. In particular, when an insulating layer is formed on a semiconductor substrate and the high resistance portion is formed within this insulating layer, the capacitance between the dummy wiring or high resistance portion and the semiconductor substrate can be made very small, so it is possible to use direct connection structures for all without worrying about interactions with the capacitor connection structure. In other cases, for example, it is also possible to apply a mixture of direct connection structures and capacitor connection structures.

[0119] In the first high resistance section RP (or the second high resistance section RN), the ratio of the number of capacitor-connected structures to the number of direct-connected structures can be set as follows.

[0120] The direct connection structure is defined as the first type, and the capacitor connection structure is defined as the second type. The number of resistor layers (resistors R) belonging to the first type of resistor layer group is N1, and the number of resistor layers (resistors R) belonging to the second type of resistor layer group is N2. N1 and N2 are natural numbers, and the relationship N1 < N2 is satisfied. If the direct connection structure is provided in a part on the high voltage side, a breakdown suppression effect can be obtained, so the rest may be the capacitor connection structure.

[0121] When the dummy wiring DW used in the capacitor connection structure is defined as the third dummy wiring, the device includes a third buried electrode BE capacitively coupled to the third dummy wiring and a third resistor layer (resistor R) electrically connected to the third buried electrode BE.

[0122] Resistors including the first type of resistor layer group and the second type of resistor layer group are embedded in the insulating layer of the resistor chip. The first type of resistor layer group (direct connection structure) is arranged closer to the end in the longitudinal direction (Y-axis) of the resistor (high resistance part) than the second type of resistor layer group (capacitor connection structure). The first type of resistor layer group (direct connection structure) includes a plurality of first resistor units (direct connection structures in FIG. 10) arranged in an aligned manner. Each first resistor unit includes a first dummy wiring (dummy wiring DW in FIG. 10), a first buried electrode (buried electrode BE(N) or BE in FIG. 10) electrically connected to the first dummy wiring, and a first resistor layer (resistor R) electrically connected to the first buried electrode. The second type of resistor layer group (capacitor connection structure) includes a plurality of second resistor units (capacitor connection structures in FIG. 16) arranged in an aligned manner. Each second resistor unit includes a second dummy wiring (dummy wiring DW in FIG. 16), a second buried electrode (buried electrode BE in FIG. 16) capacitively coupled to the second dummy wiring, and a second resistor layer (resistor R in FIG. 16) electrically connected to the second buried electrode.

[0123] In this case, the multiple first dummy wirings (dummy wirings DW in Figure 10) are arranged to surround the first electrode E1 (or the second electrode E2) located at the end of the resistor (dummy wirings DW in the first dummy wiring region DMY1 and the second dummy wiring region DMY2 in Figure 11), and the second dummy wirings (dummy wirings DW in Figure 16) extend so as not to surround the first electrode E1 (or the second electrode E2) (dummy wirings DW in the third dummy wiring region DMY3 and the fourth dummy wiring region DMY4 in Figure 11).

[0124] The materials of each element will be explained.

[0125] The semiconductor substrate 1 (FIGS. 6 and 9) may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 × 10 14 (cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0126] The material of the resistive layer (wire resistor) constituting the resistor R is a resistive material with a higher resistivity than polysilicon. Specifically, the material of the resistor (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The material of the resistor R may be composed of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently high, and when the thickness Rd is equal to or greater than the lower limit, the durability and strength of the resistive layer can be maintained.

[0127] The first electrode E1, the second electrode E2, and the buried electrodes (buried wiring) can be made of metal materials such as Al (aluminum) or Cu (copper).The various via electrodes can be made of high-melting-point metals such as tungsten (W), but other electrode materials can also be used.

[0128] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0129] [A1] A semiconductor device comprising: an insulating layer 2 formed on a semiconductor substrate 1; and resistors (first high resistance portion RP, second high resistance portion RN, first low resistance portion RPS, second low resistance portion RNS) embedded in the insulating layer 2, the resistors comprising: a first resistance layer (resistor R(1) in FIG. 5); a first buried electrode (second connection region BE(2) in FIG. 5) electrically connected to one end of the first resistance layer; a first dummy wiring (DW) capacitively coupled to the first buried electrode; a second resistance layer (resistor R(2)) arranged adjacent to the first resistance layer (resistor R(1)); and a second buried electrode (BE(N)) electrically connected to one end of the second resistance layer and electrically connected to the first dummy wiring (DW).

[0130] When one end of the first resistive layer (resistor R(1)) is at a high potential, the potential difference between it and the adjacent second resistive layer (resistor R(2)) can cause breakdown. Therefore, the first resistive layer (resistor R(1)) is coupled to the second resistive layer (resistor R(2)) via the first buried electrode (second connection region BE(2)), parasitic capacitors (C1, C3, C11, C311), first dummy wiring (DW, DW(1)), second via electrode VE2, and second buried electrode (BE(N)). The AC voltage (surge voltage) applied to the first resistive layer (resistor R(1)) is transmitted to the second resistive layer (resistor R(2)) via the parasitic capacitor, quickly reducing the potential difference between the first and second resistive layers and preventing breakdown. When the frequency of the input signal is high, the impedance of the parasitic capacitor decreases.

[0131] [A2] A semiconductor device includes an insulating layer 2 formed on a semiconductor substrate 1, and resistors (first high resistance portion RP, second high resistance portion RN, first low resistance portion RPS, second low resistance portion RNS) embedded in the insulating layer 2, the resistors including a first resistance layer (resistor R(3) in FIG. 8), a first buried electrode (buried electrode BE(N)) electrically connected to one end of the first resistance layer (resistor R(3)), and a first buried electrode (buried electrode BE(N)) electrically connected to the first buried electrode (buried electrode BE(N)). A semiconductor device comprising: a dummy wiring (DW(1) in FIG. 8); a second dummy wiring (DW(2) in FIG. 8) capacitively coupled to the first dummy wiring (DW(1)); a second buried electrode (buried electrode BE) electrically connected to the second dummy wiring (DW(2)); and a second resistance layer (resistor R(4) in FIG. 8) electrically connected to the second buried electrode (buried electrode BE) and arranged adjacent to the first resistance layer (resistor R(3) in FIG. 8).

[0132] If one end of resistor R(3) is at a high potential, the potential difference between it and the adjacent resistor R(4) may cause breakdown. Therefore, resistor R(3) is coupled to resistor R(4) via a parasitic capacitor between the dummy wiring. The AC voltage (surge voltage) applied to resistor R(3) is transmitted to resistor R(4) via the parasitic capacitor, quickly alleviating the potential difference between resistors R(3) and R(4), preventing breakdown.

[0133] [A3] The semiconductor device described in [A2], wherein the resistor comprises a third dummy wiring (dummy wiring DW in Figure 16), a third buried electrode (buried electrode BE in Figure 16) capacitively coupled to the third dummy wiring, and a third resistance layer (resistor R(4) in Figure 8) electrically connected to the second resistance layer and the third buried electrode (resistor R in Figure 16).

[0134] The third resistive layer, located away from the longitudinal end (high voltage) of the resistor, is electrically connected to the second resistive layer on the high voltage side, but since it is located in a low voltage area, there is little risk of damage due to potential differences, and a capacitively coupled (capacitor connection structure) connection may be used.

[0135] [A4] An insulating layer 2 formed on a semiconductor substrate 1, and a resistor embedded in the insulating layer 2 and including a first type of resistor layer group (direct connection structure in FIG. 10) and a second type of resistor layer group (capacitor connection structure in FIG. 16), wherein the first type of resistor layer group is arranged at a position closer to an end in the longitudinal direction (Y-axis) of the resistor (high resistance portions (RP, RN)) than the second type of resistor layer group. The first type of resistor layer group includes a plurality of first resistor units (direct connection structure in FIG. 10) arranged in alignment. Each first resistor unit includes a first dummy wiring (dummy wiring DW in FIG. 10), a first embedded electrode (embedded electrode BE(N) in FIG. 10) electrically connected to the first dummy wiring, and a first resistor layer (resistor R in FIG. 10) electrically connected to the first embedded electrode. The second type of resistor layer group includes a plurality of second resistor units (capacitor connection structure in FIG. 16) arranged in alignment. Each second resistor unit includes a second dummy wiring (dummy wiring DW in FIG. 16), a second embedded electrode (embedded electrode BE in FIG. 1) capacitively coupled to the second dummy wiring, and a second resistor layer (resistor R in FIG. 16) electrically connected to the second embedded electrode. A semiconductor device.

[0136] [A5] The plurality of first dummy wirings (dummy wiring DW in FIG. 10) are arranged to surround a first electrode E1 (or a second electrode E2) located at an end of the resistor (high resistance portions (RP, RN)), and the second dummy wiring (dummy wiring DW in FIG. 16) extends so as not to surround the first electrode E1 (or the second electrode E2). The semiconductor device according to [A4].

[0137] [A6] The number of resistor layers belonging to the first type of resistor layer group is N1, the number of resistor layers belonging to the second type of resistor layer group is N2, N1 and N2 are natural numbers, and the semiconductor device according to [A4] satisfies the relationship N1 < N2.

[0138] [A7] The semiconductor device according to [A1], which includes, in a planar view, an extension region (dummy resistor R(Dmy)) located at an end of the resistor (first high resistance portion RP, second high resistance portion RN, first low resistance portion RPS, second low resistance portion RNS) in the longitudinal direction (Y-axis direction), and the extension region includes one or more dummy resistance layers (resistors R in the dummy resistor R(Dmy)) embedded in an insulating layer 2, one end of which is connected to a first embedded electrode (second connection region BE(2)).

[0139] [A8] A semiconductor device according to [A2], which includes, in a plan view, an extension region (dummy resistor R(Dmy)) located at an end of the resistor (first high resistance portion RP, second high resistance portion RN, first low resistance portion RPS, second low resistance portion RNS) in the longitudinal direction (Y-axis direction), and the extension region includes one or more dummy resistance layers (resistors R in the dummy resistor R(Dmy)) embedded in an insulating layer 2, one end of which is connected to a buried electrode (second connection region BE(2)).

[0140] [A9] The semiconductor device according to [A7], wherein, in a planar view, the shortest distance X1 between the first buried electrode (second connection region BE(2)) included in the extension region (dummy resistor R(Dmy)) and the second buried electrode (BE(N)) and the shortest distance X2 between the first buried electrode (third connection region BE(3)) included in the extension region and the first dummy wiring (high-voltage side dummy wiring DW) satisfy the relationship X1≦X2.

[0141] [A10] The semiconductor device described in [A8], wherein, in a planar view, the buried electrode (second connection region BE(2)) included in the extension region (dummy resistor R(Dmy)) is adjacent to the first buried electrode (buried electrode BE(N)), and a shortest distance X1 between the buried electrode included in the extension region and the first buried electrode and a shortest distance X2 between the buried electrode included in the extension region and the first dummy wiring satisfy the relationship X1≦X2.

[0142] [A11] A resistor (first high resistance portion RP, second high resistance portion RN, first low resistance portion RPS, second low resistance portion RNS) is provided on a semiconductor substrate 1, and the resistor comprises a first region having a first resistance layer group including a plurality of resistance layers (resistor R(W) in the high resistance portion (RP, RN) of FIG. 14), and a second region having a second resistance layer group including a plurality of resistance layers (resistor R in the high resistance portion (RP, RN) of FIG. 14), and the first region (resistor R(W) formation region a first region (resistor R formation region in the high resistance portion) is located closer to the longitudinal end (Y-axis direction) of the resistor (high resistance portion) than the second region (resistor R formation region in the high resistance portion), and the shortest distance (first gap ΔYRA) between the resistance layers (resistors R(W)) belonging to the first resistance layer group in the longitudinal direction of the resistor and the shortest distance (second gap ΔYRB) between the resistance layers (resistors R in the high resistance portion) belonging to the second resistance layer group satisfy the relationship ΔYRB<ΔYRA.

[0143] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0144] 1...Semiconductor substrate 2...Insulating layer 10...Resistor chip 20...Amplifier chip C10…Resistance circuit C20: Voltage detection circuit BE, BE(N)...buried electrode (buried wiring) BE(1)...First connection region BE(2)...Second connection region BE(3)...3rd connection region 1R...Ring conductor 2A...First dielectric layer 2B: Second dielectric layer 2A H …top dielectric layer 2A L ...lower dielectric layer 4...Protective film 4A…First protective film 4B…Second protective film 4C…Third protective film 10a…1st inner lead 10b…Second inner lead 10c…3rd inner lead 10d…4th inner lead 10e…5th Inner Lead 10f...6th inner lead 10g...7th inner lead 10h…8th inner lead 10i…9th inner lead 10A...First side 10B…Second side 10C…Third side 10D…4th side 30…cases 100...Semiconductor package 110...First die pad 120...Second die pad 200...battery A1...First arrow A2...Second arrow A3...Third arrow A4...Fourth arrow C1: First capacitor C3: Third capacitor D1...Concave DMY1: First dummy wiring area DMY2: Second dummy wiring area DMY3: Third dummy wiring area DMY4: Fourth dummy wiring area DW...Dummy wiring E1…1st electrode E2…Second electrode EG…Reference electrode EG1...1st reference electrode EG2…Second reference electrode EP…1st output electrode EN: Second output electrode GND: Ground potential HV(+)...First input terminal HV(-)...Second input terminal INP...First input terminal INN: Second input terminal N1: First node N2: Second node N3: Third node Na, Nb, Nc, Nd, Ne, Nf, Ng, Nh...nodes R,R(W)…Resistor R...Dummy resistor (Dmy) R E …Linear resistor RP…1st high resistance part RPS...1st low resistance section RN…Second high resistance section RNS…Second low resistance section RN1,RN2,RP1,RP2…High resistance part S...area VC…Reference terminal Vcc: power supply voltage VE: Via electrode VE2: Second via electrode Vout: Output voltage X1,X2…Shortest distance YD...gap ΔYRA…First gap ΔYRB…Second gap

Claims

1. an insulating layer formed on a semiconductor substrate; a resistor embedded within the insulating layer; The resistor is a first resistive layer; a first buried electrode electrically connected to one end of the first resistive layer; a first dummy wiring capacitively coupled to the first buried electrode; a second resistive layer disposed adjacent to the first resistive layer; a second buried electrode electrically connected to one end of the second resistance layer and to the first dummy wiring; A semiconductor device comprising:

2. an insulating layer formed on a semiconductor substrate; a resistor embedded within the insulating layer; The resistor is a first resistive layer; a first buried electrode electrically connected to one end of the first resistive layer; a first dummy wiring electrically connected to the first buried electrode; a second dummy wiring that is capacitively coupled to the first dummy wiring; a second buried electrode electrically connected to the second dummy wiring; a second resistive layer electrically connected to the second buried electrode and disposed adjacent to the first resistive layer; A semiconductor device comprising:

3. The resistor includes a third dummy wiring, a third buried electrode capacitively coupled to the third dummy wiring; a third resistive layer electrically connected to the second resistive layer and the third buried electrode; The semiconductor device according to claim 2 , comprising:

4. an insulating layer formed on a semiconductor substrate; a resistor embedded in the insulating layer, the resistor including a first type of resistive layer group and a second type of resistive layer group; Equipped with the first type resistive layer group is disposed closer to an end of the resistor in the longitudinal direction than the second type resistive layer group; The first-type resistor layer group includes a plurality of aligned first resistor units, each of which includes: a first dummy wiring; a first buried electrode electrically connected to the first dummy wiring; a first resistive layer electrically connected to the first buried electrode; Equipped with The second-type resistor layer group includes a plurality of aligned second resistor units, each of which includes: A second dummy wiring; a second buried electrode capacitively coupled to the second dummy wiring; a second resistive layer electrically connected to the second buried electrode; Equipped with Semiconductor device.

5. the plurality of first dummy wirings are arranged so as to surround a first electrode located at an end of the resistor, The second dummy wiring extends so as not to surround the first electrode. The semiconductor device according to claim 4 .

6. The number of resistive layers belonging to the first type resistive layer group is N １ Individuals, The number of resistive layers belonging to the second type resistive layer group is N ２ Individuals, N １ and N ２ is a natural number, and N １ <N ２ Satisfy the relationship of The semiconductor device according to claim 4 .

7. an extension region located at an end of the resistor in a longitudinal direction in a plan view; the extension region includes one or more dummy resistance layers embedded in the insulating layer, and one end of each dummy resistance layer is connected to the first buried electrode; The semiconductor device according to claim 1 .

8. an extension region located at an end of the resistor in a longitudinal direction in a plan view; the extension region includes one or more dummy resistance layers embedded in the insulating layer, and one end of each dummy resistance layer is connected to a buried electrode; The semiconductor device according to claim 2 .

9. In plan view, a shortest distance X1 between the first buried electrode and the second buried electrode included in the extension region; The shortest distance X2 between the first buried electrode included in the extension region and the first dummy wiring is The relationship X1≦X2 is satisfied. The semiconductor device according to claim 7 .

10. In plan view, the buried electrode included in the extension region is adjacent to the first buried electrode, a shortest distance X1 between the buried electrode included in the extension region and the first buried electrode; The shortest distance X2 between the buried electrode included in the extension region and the first dummy wiring is The relationship X1≦X2 is satisfied. The semiconductor device according to claim 8 .

11. a resistor provided on a semiconductor substrate; The resistor is a first region including a first resistive layer group including a plurality of resistive layers; a second region including a second resistive layer group including a plurality of resistive layers; Equipped with the first region is located closer to an end of the resistor in the longitudinal direction than the second region; The shortest distance ΔYRA between the resistor layers belonging to the first resistor layer group and the shortest distance ΔYRB between the resistor layers belonging to the second resistor layer group in the longitudinal direction of the resistor are The relationship ΔYRB<ΔYRA is satisfied. Semiconductor device.

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