Semiconductor device including capacitor structure and data storage system including the same

Abstract

To provide a semiconductor device including a capacitor structure improved in integration degree and reliability, and a data storage system including the same.SOLUTION: A semiconductor device includes a peripheral circuit structure including a substrate 201, a circuit element on the substrate, a lower wiring structure, which is electrically connected with the circuit element, and a capacitor structure 200 separated from the lower wiring structure; and a memory cell structure including a plate layer disposed on the peripheral circuit structure, gate electrodes which are laminated on a top face of the plate layer while being separated from each other in a vertical direction Z on the plate layer and are successively laminated, and a channel structure penetrating the gate electrodes and extending in the vertical direction. The capacitor structure including an insulation layer IL1 includes: a first electrode structure 210 including first electrodes MC1a and ML1a which are mutually separated in a first direction X in parallel with a top face of the substrate and extend in a second direction Y that crosses the vertical direction and the first direction; and a second electrode structure 220 including second electrodes MC1b and ML1b which are disposed alternately with the first electrodes and extend in the second direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a capacitor structure including a capacitor, and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing high-capacity data are in demand. Accordingly, methods for increasing the data storage capacity of semiconductor devices are being researched. Furthermore, highly integrated semiconductor devices are also in demand. For example, as one method for increasing the integration level of semiconductor devices, a semiconductor device in which memory cells and peripheral circuit regions are arranged one above the other has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION The present invention provides a semiconductor device including a capacitor structure with improved integration density and reliability, and a data storage system including the same.

[0004] However, the object of the present invention is not limited to the above object, and can be variously expanded within the scope of the idea and scope of the present invention. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment of the present invention includes a first semiconductor structure including a substrate, a circuit element on the substrate, a lower wiring structure electrically connected to the circuit element, and a capacitor structure spaced apart from the lower wiring structure; and a second semiconductor structure including: a plate layer disposed on the first semiconductor structure; gate electrodes stacked on the plate layer and spaced apart from each other along a direction perpendicular to an upper surface of the plate layer, the gate electrodes being sequentially stacked; and a channel structure extending through the gate electrodes and along the vertical direction, the capacitor structure including first electrode structures spaced apart from each other in a first direction parallel to an upper surface of the substrate and including first electrodes extending in the vertical direction and a second direction intersecting the first direction, and a second electrode structure including second electrodes alternately disposed with the first electrodes and extending in the second direction, each of the first electrodes and the second electrodes being formed by a first wall pattern having a first side. and a second wall pattern on the first wall pattern having a second side extending from the first side, wherein a side profile at a boundary between the first side and the second side may vary nonlinearly.

[0006] A semiconductor device according to an embodiment of the present invention includes a first lower electrode structure disposed on a substrate, spaced apart from each other in a first direction parallel to an upper surface of the substrate, extending in a second direction intersecting the first direction, connecting the first lower electrodes and including a first lower connection part extending in the first direction; a second lower electrode structure alternately disposed with the first lower electrodes, extending in the second direction, connecting the second lower electrodes and including a second lower connection part extending in the first direction; a first insulating layer disposed between the first lower electrode structure and the second lower electrode structure; a first intermediate electrode disposed on the first lower electrode and connecting the first intermediate electrode and extending in the first direction; a first intermediate electrode structure including a first intermediate connector vertically overlapping the first lower connector; a second intermediate electrode disposed on the second lower electrode and connecting the second intermediate electrode, extending in the first direction and including a second intermediate connector vertically overlapping the first lower connector; and a second insulating layer disposed between the first intermediate electrode structure and the second intermediate electrode structure, wherein each of the first intermediate electrode and the second intermediate electrode includes a first wall pattern having a first side surface MCS and a second wall pattern having a second side surface on the first wall pattern extending from the first side surface, and a side surface profile at a boundary between the first side surface and the second side surface may change nonlinearly.

[0007] A data storage system according to an embodiment of the present invention includes a semiconductor memory device including circuit elements, memory cells, a capacitor structure, and input / output pads on a substrate; and a controller electrically connected to the semiconductor memory device via the input / output pads and controlling the semiconductor memory device, wherein the capacitor structure includes first electrodes spaced apart in a first direction parallel to an upper surface of the substrate and extending in a second direction intersecting the first direction, a first electrode structure including first connecting portions connecting the first electrodes and extending in the first direction, and a first connecting portion alternately arranged with the first electrodes, The semiconductor device may include a second electrode structure including a second electrode extending in a second direction and a second connecting portion connecting the second electrode and extending in the first direction, and an insulating layer disposed between the first electrode structure and the second electrode structure, wherein each of the first electrode and the second electrode includes a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface on the first wall pattern, and a lower surface of the first connecting portion and a lower surface of the second connecting portion may be disposed at a higher level than a lower surface of the first wall pattern. [Effects of the Invention]

[0008] According to an embodiment of the present invention, a semiconductor device and a data storage system including the same may include a capacitor structure and a lower interconnection structure disposed at the same level as the capacitor structure. Each of a first electrode and a second electrode of the capacitor structure may include a first wall pattern having a first side surface and a second wall pattern extending from the first side surface, and the lower interconnection structure may include a peripheral contact plug and a peripheral interconnection having a line shape extending from the peripheral contact plug. This may improve line width roughness (LWR) of the first electrode and the second electrode of the capacitor structure and improve the interconnection alignment of the peripheral interconnection of the lower interconnection structure, thereby providing a semiconductor device and a data storage system including the same with improved reliability.

[0009] However, the effects of the present invention are not limited to the above-mentioned effects, and can be variously expanded within the scope of the present invention.

Brief Description of the Drawings

[0010] [Figure 1a] It is a schematic block diagram of a semiconductor device according to an embodiment of the present invention. [Figure 1b] It is a circuit diagram showing a charge pump circuit included in a voltage generator of a semiconductor device according to an embodiment. [Figure 1c] It is a schematic perspective view of a semiconductor device according to an embodiment. [Figure 2a] It is a schematic perspective view showing an embodiment of a capacitor structure of a semiconductor device. [Figure 2b] It is a plan view showing an embodiment of the first and second lower electrode structures of the capacitor structure of FIG. 2a. [Figure 2c] It is a plan view showing an embodiment of the first and second electrode structures of the capacitor structure of FIG. 2a. [Figure 3] It is a cross-sectional view showing an embodiment along the line I-I' of the capacitor structure of FIGS. 2b and 2c. [Figure 4a] It is a perspective view showing an embodiment of a lower wiring structure of a semiconductor device. [Figure 4b] It is a plan view showing an embodiment of the lower wiring structure of FIG. 4a. [Figure 5] It is a cross-sectional view showing an embodiment along the line II-II' of the lower wiring structure of FIG. 4b. [Figure 6a] It is a perspective view showing another embodiment of a capacitor structure of a semiconductor device. [Figure 6b] It is a plan view showing an embodiment of the first and second upper electrode structures of the capacitor structure of FIG. 6a. [Figure 7] It is a cross-sectional view showing an embodiment along the line III-III' of the capacitor structure of FIG. 6b. [Figure 8a] It is a perspective view showing another embodiment of a lower wiring structure of a semiconductor device. [Figure 8b] It is a plan view showing an embodiment of the lower wiring structure of FIG. 8a. [Figure 9]It is a cross-sectional view showing an embodiment along line IV-IV' of the lower wiring structure in FIG. 8b. [Figure 10] It is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. [Figure 11a] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11b] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11c] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11d] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11e] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11f] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 11g] It is a drawing showing an embodiment of a method for manufacturing a semiconductor device. [Figure 12] It is a drawing schematically showing a data storage system including a semiconductor device according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components on the drawings, and redundant descriptions for the same components are omitted.

[0012] FIG. 1a is a schematic block diagram of a semiconductor device according to an embodiment of the present invention.

[0013] Referring to FIG. 1a, the semiconductor device 10 can include a memory cell array 20 and a peripheral circuit 30. The semiconductor device 10 can be a memory device, and for example, can be a non-volatile memory such as a flash memory or a volatile memory such as a DRAM (dynamic random access memory) or an SRAM (static random access memory).

[0014] The memory cell array 20 may include a plurality of memory cells. The memory cells may be connected to a row decoder 33 via a plurality of word lines WL and to a read / write circuit 35 via a plurality of bit lines BL. In one example, memory cells arranged along the same row may be connected to the same word line WL, and memory cells arranged along the same column may be connected to the same bit line BL. In some embodiments, the memory cell array 20 may include a plurality of memory blocks, each of which may include a plurality of memory cells.

[0015] The peripheral circuit 30 can receive addresses ADDR, commands CMD, and control signals CTRL from outside the semiconductor device 10, and can transmit and receive data DATA to and from devices outside the semiconductor device 10. The peripheral circuit 30 can include a row decoder 33, a read / write circuit 35, control logic 37, and a voltage generator 38 that generates various voltages required for operation. Depending on the embodiment, the peripheral circuit 30 can further include various sub-circuits, such as an input / output circuit and an error correction circuit for correcting errors in data DATA read from the memory cell array 20.

[0016] The control logic 37 may be connected to the row decoder 33, the voltage generator 38, and the input / output circuits. The control logic 37 may control the overall operation of the semiconductor device 10. The control logic 37 may generate various internal control signals used within the semiconductor device 10 in response to the control signal CTRL. For example, the control logic 37 may adjust the voltage levels provided to the word lines WL and bit lines BL when performing a memory operation such as a program operation or an erase operation.

[0017] The row decoder 33 can select some of the memory cells in response to an address ADDR and can select at least one word line WL, and can transmit a voltage to the selected word line WL to perform a memory operation.

[0018] The read / write circuit 35 may be connected to the memory cell array 20 via bit lines BL. The read / write circuit 35 may include a write driver or a sense amplifier. Specifically, during a program operation, the read / write circuit 35 operates as a write driver to apply a voltage to the bit lines BL according to data DATA to be stored in the memory cell array 20. Meanwhile, during a read operation, the read / write circuit 35 operates as a sense amplifier to sense data DATA stored in the memory cell array 20.

[0019] The voltage generator 38 may include a controller 52 , an oscillator 54 , and a charge pump 56 .

[0020] The charge pump 56 may include a plurality of charge pumps, each of which may include at least one switch element and at least one pumping capacitor. The charge pump 56 may provide current through the row decoder 33 to apply operating voltages to the word lines WL of the memory cell array.

[0021] The controller 52 can control the operation of the oscillator 54. For example, the controller 52 can determine one of the plurality of charge pumps as a selected charge pump based on at least one of PVT (Process, Voltage, Temperature) information of the semiconductor device 10 and a target level of a power supply voltage that needs to be supplied. The controller 52 can deactivate the remaining charge pumps except for the selected charge pump.

[0022] The oscillator 54 can output a clock signal CLK. The oscillator 54 can operate in response to a control signal VGC from the controller 52. For example, the oscillator 54 can output the clock signal CLK to at least some of the charge pumps in response to the control signal VGC transmitted by the controller 52.

[0023] FIG. 1b is a circuit diagram showing a charge pump circuit included in a voltage generator of the semiconductor device according to the embodiment.

[0024] 1b, the charge pump circuit 56a may include a plurality of diodes DI, a plurality of pumping capacitors CAP1, and an output capacitor CAP2. The plurality of diodes DI may be connected in series with each other, and a plurality of pumping capacitors CAP1 may be connected to nodes between the plurality of diodes DI. A power supply voltage VCC having a predetermined level is input to the first diode, and the last diode may output an output current IOUT to an output node.

[0025] Each of the plurality of pumping capacitors CAP1 can be charged or discharged by a clock signal CLK or a complementary clock signal CLKB that has been phase-converted by an inverter to have an opposite phase to the clock signal CLK. For example, odd-numbered pumping capacitors CAP1 can be charged or discharged by the clock signal CLK, and even-numbered pumping capacitors CAP1 can be charged or discharged by the complementary clock signal CLKB.

[0026] FIG. 1c is a schematic perspective view of the semiconductor device according to the embodiment.

[0027] 1c, the semiconductor device 10 may include a peripheral circuit structure PERI, which is a first semiconductor structure, and a memory cell structure CELL, which is a second semiconductor structure. The memory cell structure CELL may be disposed on the peripheral circuit structure PERI. The memory cell structure CELL may be an area where the memory cell array 20 of FIG. 1a is disposed, and the peripheral circuit structure PERI may be an area where the peripheral circuit 30 of FIG. 1a is disposed. In some embodiments, the memory cell structure CELL may be disposed below the peripheral circuit structure PERI.

[0028] The memory cell structure CELL may include a first region R1 and a second region R2.

[0029] A first region R1 of the memory cell structure CELL may be a region in which the memory cell array 20 is disposed. A second region R2 of the memory cell structure CELL may correspond to a region for electrically connecting memory cells of the memory cell array 20 to the peripheral circuit 30. The second region R2 may be disposed at least at one end of the first region R1 in at least one direction, for example, a first direction (X direction).

[0030] 1a and 1b, the plurality of pumping capacitors CAP1 constituting the charge pump circuits 56, 56a may be disposed in the peripheral circuit structure PERI. For example, the plurality of pumping capacitors CAP1 may be disposed under the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI, but are not limited thereto. In another example, the plurality of pumping capacitors CAP1 may be disposed under the first region R1 of the memory cell structure CELL in the peripheral circuit structure PERI.

[0031] Figure 2a is a schematic perspective view showing one embodiment of a capacitor structure of a semiconductor device, Figure 2b is a plan view showing one embodiment of first and second lower electrode structures of the capacitor structure of Figure 2a, Figure 2c is a plan view showing one embodiment of first and second electrode structures of the capacitor structure of Figure 2a, and Figure 3 is a cross-sectional view showing one embodiment of the capacitor structure of Figure 2b and Figure 2c along line II'.

[0032] 2a to 3, the capacitor structure 200 may include first and second lower electrode structures 210B, 220B, first and second electrode structures 210, 220 disposed on the first and second lower electrode structures 210B, 220B, a first insulating layer IL0 disposed between the first and second lower electrode structures 210B, 220B, and a second insulating layer IL1 disposed between the first and second electrode structures 210, 220.

[0033] The capacitor structure 200 may form the pumping capacitor CAP1 of the charge pump circuits 56, 56a described in detail with reference to FIGS. 1a to 1c.

[0034] The first and second lower electrode structures 210B and 220B may be disposed on a substrate 201. The first and second lower electrode structures 210B and 220B may have different potentials.

[0035] The first bottom electrode structure 210B may include a first bottom electrode ML0a and a first bottom connector BCP1 connecting the first bottom electrode ML0a and extending in the first direction (X direction). The first bottom electrode ML0a may have a line shape protruding and extending in the second direction (Y direction) from the first bottom connector BCP1. The first bottom electrode ML0a may have a first finger portion FP1 branching from the first bottom connector BCP1.

[0036] The second bottom electrode structure 220B may include a second bottom electrode ML0b and a second bottom connector BCP2 connecting the second bottom electrode ML0b and extending in the first direction (X direction). The second bottom electrode ML0b may have a line shape protruding and extending in the second direction (Y direction) from the second bottom connector BCP2. The second bottom electrode ML0b may have a second finger portion FP2 branching from the second bottom connector BCP2.

[0037] The second bottom electrodes ML0b may be alternately arranged with the first bottom electrodes ML0a. The second bottom connector BCP2 may be spaced apart from the first bottom connector BCP1 in the second direction (Y direction). In one example, a barrier conductive film MB0 may be arranged between the first bottom electrode ML0a and the first insulating layer IL0 and between the second bottom electrode ML0b and the first insulating layer IL0. For example, the barrier conductive film MB0 may be arranged to extend on the side and bottom surfaces of the first bottom electrode ML0a and the second bottom electrode ML0b.

[0038] The first bottom electrode ML0a, the second bottom electrode ML0b, and the first insulating layer IL0 disposed between the first bottom electrode ML0a and the second bottom electrode ML0b may form a capacitor, and the capacitor formed by the first bottom electrode ML0a, the second bottom electrode ML0b, and the first insulating layer IL0 may have a capacitance C0.

[0039] The first and second electrode structures 210 and 220 may be disposed on the first and second lower electrode structures 210B and 220B. The first electrode structure 210 and the second electrode structure 220 may have different potentials. In this specification, the first electrode structure 210 may be referred to as a first intermediate electrode structure, and the second electrode structure 220 may be referred to as a second intermediate electrode structure.

[0040] The first electrode structure 210 may include first electrodes MC1a and ML1a and a first connecting portion CP1 connecting the first electrodes MC1a and ML1a and extending in a first direction (X direction). The first electrodes MC1a and ML1a may have a line shape protruding and extending in a second direction (Y direction) from the first connecting portion CP1. The first electrodes MC1a and ML1a may form first finger portions FP1 branching from the first connecting portion CP1. In one example, the first electrodes MC1a and ML1a may overlap the first bottom electrode ML0a of the first bottom electrode structure 210B in the vertical direction (Z direction). The first connecting portion CP1 may overlap the second bottom connecting portion BCP2 of the second bottom electrode structure 220B in the vertical direction (Z direction).

[0041] The second electrode structure 220 may include second electrodes MC1b, ML1b and a second connecting portion CP2 connecting the second electrodes MC1b, ML1b and extending in the first direction (X direction). The second electrodes MC1b, ML1b may have a line shape protruding and extending in the second direction (Y direction) from the second connecting portion CP2. The second electrodes MC1b, ML1b may form second finger portions FP2 branching from the second connecting portion CP2. The second electrodes MC1b, ML1b may overlap the second bottom electrode ML0b of the second bottom electrode structure 220B in the vertical direction (Z direction). The second connecting portion CP2 may overlap the first bottom connecting portion BCP1 of the first bottom electrode structure 210B in the vertical direction (Z direction).

[0042] The second electrodes MC1b, ML1b may be alternately arranged with the first electrodes MC1a, ML1a in the first direction (X direction). The second connecting part CP2 may be spaced apart from the first connecting part CP1 in the second direction (Y direction). The first electrodes MC1a, ML1a and the second electrodes MC1b, ML1b may include a conductive material, such as, but not limited to, tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0043] The first electrodes MC1a, ML1a and the second electrodes MC1b, ML1b may each include a first wall pattern MC1a, MC1b and a second wall pattern ML1a, ML1b extending from the first wall pattern MC1a, MC1b. In one example, the first wall patterns MC1a, MC1b may include a 1-1 wall pattern MC1a arranged on the first lower electrode ML0a and a 1-2 wall pattern MC1b arranged on the second lower electrode ML0b.

[0044] The first wall patterns MC1a and MC1b may include a first side surface MCS, and the second wall patterns ML1a and ML1b may include a second side surface MLS extending from the first side surface MCS. The first wall patterns MC1a and MC1b may have a width in a first direction (X direction) that linearly increases as they move in the vertical direction (Z direction). The first side surface MCS may have a linear shape. The second wall patterns ML1a and ML1b may have a second side surface MLS extending from the first side surface MCS and have a width in the first direction (X direction) that nonlinearly increases as they move in the vertical direction (Z direction). The second side surface MLS may have a curved shape. In one example, the side surface profile may change nonlinearly at a boundary point P1 between the first side surface MCS and the second side surface MLS.

[0045] Each of the first wall patterns MC1a, MC1b and the second wall patterns ML1a, ML1b has a line shape extending in the second direction (Y direction) and can be formed by a dual damascene process.

[0046] The bottom surfaces and first side surfaces MCS of the first wall patterns MC1a and MC1b and the second side surfaces MLS of the second wall patterns ML1a and ML1b can be covered with first barrier conductive films MBa and MBb. The 1-1 barrier conductive film MBa can extend along the bottom surface of the 1-1 wall pattern MC1a, the first side surface MCS of the 1-1 wall pattern MC1a and the second side surface MLS of the 2-1 wall pattern ML1a. The 1-2 barrier conductive film MBb can extend along the bottom surface of the 1-2 wall pattern MC1b, the first side surface MCS of the 1-2 wall pattern MC1b and the second side surface MLS of the 2-2 wall pattern ML1b.

[0047] The first wall patterns MC1a and MC1b can be integrally formed with the second wall patterns ML1a and ML1b.

[0048] The insulating layers IL0 and IL1 may be insulating layers including an insulating material, and may include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0049] The barrier conductive films MB0, MBa, and MBb may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof, but are not limited thereto.

[0050] The capacitor formed by the first-first wall pattern MC1a, the first-second wall pattern MC1b, and the second insulating layer IL1 may have a first capacitance C1. The capacitor formed by the second-first wall pattern ML1a, the second-second wall pattern ML1b, and the second insulating layer IL1 may have a second capacitance C2. The second capacitance C2 may be larger than the first capacitance C1.

[0051] The height of the first connecting portion CP1 and the second connecting portion CP2 in the vertical direction (Z direction) may be smaller than the height of the first electrodes MC1a, ML1a and the second electrodes MC1b, ML1b in the vertical direction (Z direction). In one example, the lower surfaces of the first connecting portion CP1 and the second connecting portion CP2 may be disposed at a higher level than the lower surfaces of the first wall patterns MC1a, MC1b. Although the lower surfaces of the first connecting portion CP1 and the second connecting portion CP2 are described as being disposed at a higher level than the boundary point P1 where the first side surface MCS of the first wall patterns MC1a, MC1b and the second side surface MLS of the second wall patterns ML1a, ML1b meet, the present invention is not limited thereto, and the lower surfaces of the first connecting portion CP1 and the second connecting portion CP2 may be disposed and / or formed at the same level as the boundary point P1.

[0052] The semiconductor device according to the embodiment includes a capacitor structure 200 including first electrodes MC1a, ML1a and second electrodes MC1b, ML1b, and the first electrodes MC1a, ML1a and second electrodes MC1b, ML1b may include first wall patterns MC1a, MC1b and second wall patterns ML1a, ML1b on the first wall patterns MC1a, MC1b, respectively. The first wall patterns MC1a, MC1b and second wall patterns ML1a, ML1b are formed by a dual damascene process, thereby improving line width roughness (LWR) of the first electrodes MC1a, ML1a and second electrodes MC1b, ML1b.

[0053] Figure 4a is an oblique view showing one embodiment of a lower wiring structure of a semiconductor device, Figure 4b is a plan view showing one embodiment of the lower wiring structure of Figure 4a, and Figure 5 is a cross-sectional view showing one embodiment of the lower wiring structure of Figure 4b along line II-II'.

[0054] 4a, 4b, and 5, the lower wiring structure 250 may be disposed under the first region R1 of the memory cell structure CELL in the peripheral circuit structure PERI described above with reference to Fig. 1c. The lower wiring structure 250 may be spaced apart in the first direction (X direction) from the capacitor structure 200 disposed under the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI.

[0055] The lower wiring structure 250 may include a first wiring structure 250A and a second wiring structure 250B. The first wiring structure 250A and the second wiring structure 250B may be alternately arranged in a first direction (X direction).

[0056] The first wiring structure 250A may include a first lower wiring 251 extending in the second direction (Y direction), a first peripheral contact plug 253 arranged on the first lower wiring 251, and a first peripheral wiring 255 arranged on the first peripheral contact plug 253 and extending in the second direction (Y direction).

[0057] The second wiring structure 250B may include a second lower wiring 252 extending in the second direction (Y direction), second peripheral contact plugs 254a, 254b arranged on the second lower wiring 252, and a second peripheral wiring 256 arranged on the second peripheral contact plugs 254a, 254b and extending in the second direction (Y direction).

[0058] The second lower interconnection 252 may be disposed at the same level as the first lower interconnection 251. The bottom surface and side surfaces of the first lower interconnection 251 and the bottom surface and side surfaces of the second lower interconnection 252 may be covered with a barrier conductive film BLa.

[0059] The first peripheral contact plug 253 may be disposed at the same level as the second peripheral contact plugs 254a and 254b.

[0060] The first and second lower interconnections 251 and 252 may have a line shape extending in the second direction (Y direction). The first peripheral contact plug 253 and the second peripheral contact plugs 254a and 254b may have a cylindrical shape as contact structures. The first peripheral contact plug 253 and the second peripheral contact plugs 254a and 254b may have a via hole shape. The first peripheral interconnection 255 and the second peripheral interconnection 256 may have a line shape extending in the second direction (Y direction).

[0061] The first peripheral contact plug 253 may be disposed in a central region on the first lower interconnection 251 between the first lower interconnection 251 and the first peripheral interconnection 255. However, without being limited thereto, the first peripheral contact plug 253 may be disposed to intersect with second peripheral contact plugs 254a and 254b disposed at the same level. In one example, the second peripheral contact plugs 254a and 254b may include a 2-1 contact plug 254a and a 2-2 contact plug 254b spaced apart in the second direction (Y direction) on the second lower interconnection 252.

[0062] The height of the first and second peripheral wirings 255 and 256 in the vertical direction (Z direction) can be greater than the height of the first and second lower wirings 251 and 252 in the vertical direction (Z direction).

[0063] The width of the first peripheral contact plug 253 may increase linearly in the vertical direction (Z direction). The first peripheral contact plug 253 has a third side surface CS, and the third side surface CS may have a cylindrical side surface shape.

[0064] The first peripheral wiring 255 may extend from the upper surface of the first peripheral contact plug 253 and have a fourth side surface LS extending from the third side surface CS of the first peripheral contact plug 253. In one example, the second peripheral contact plugs 254a and 254b may have a third side surface CS similar to the first peripheral contact plug 253, and the second peripheral wiring 256 may contact the upper surfaces of the second peripheral contact plugs 254a and 254b and have a fourth side surface LS extending from the third side surface CS of the second peripheral contact plugs 254a and 254b.

[0065] The side profile at a boundary point P2 where the third side surface CS of the first peripheral contact plug 253 and the fourth side surface LS of the first peripheral wiring 255 meet may change nonlinearly. Similarly, the side profile at a boundary point P2 where the third side surface CS of the second peripheral contact plug 254 and the fourth side surface LS of the second peripheral wiring 256 meet may change nonlinearly.

[0066] The first peripheral contact plugs 253 and the first peripheral wiring 255 may be provided and / or formed by a dual damascene process. The second peripheral contact plugs 254a and 254b and the second peripheral wiring 256 may also be provided and / or formed by a dual damascene process.

[0067] The top surfaces of the first peripheral wiring 255 and the second peripheral wiring 256 may be disposed at the same level as the top surfaces of the second wall patterns ML1a and ML1b in Fig. 3. In one example, the depth from the top surfaces of the first peripheral wiring 255 and the second peripheral wiring 256 to a boundary point P2 where the third side surface CS and the fourth side surface LS meet may be smaller than the depth from the top surfaces of the second wall patterns ML1a and ML1b in Fig. 3 to a boundary point P1 where the first side surface MCS and the second side surface MLS meet.

[0068] The semiconductor device according to the embodiment includes a lower interconnection structure 250 spaced apart from the capacitor structure in a first direction (X direction). The lower interconnection structure 250 includes peripheral contact plugs 253, 254a, and 254b and first and second peripheral interconnections 255 and 256 on the peripheral contact plugs 253, 254a, and 254b. The first peripheral contact plug 253 and the first peripheral interconnection 255, and the second peripheral contact plugs 254a and 254b and the second peripheral interconnection 256 may be formed by a dual damascene process. This minimizes misalignment of the first and second peripheral interconnections 255 and 256, thereby providing a lower interconnection structure 250 with improved reliability.

[0069] Figure 6a is an oblique view showing another embodiment of a capacitor structure of a semiconductor device, Figure 6b is a plan view showing an embodiment of first and second upper electrode structures of the capacitor structure of Figure 6a, and Figure 7 is a cross-sectional view showing an embodiment of the capacitor structure of Figure 6b along line III-III'.

[0070] Referring to FIG. 6a, the remaining configuration of the capacitor structure 200', except for the first and second upper electrode structures 210U and 220U, may be the same as or similar to the configuration of the capacitor structure 200 of FIG. 2a.

[0071] 6a to 7, the capacitor structure 200′ may include first and second bottom electrode structures 210B, 220B, first and second intermediate electrode structures 210L, 220L disposed on the first and second bottom electrode structures 210B, 220B, first and second upper electrode structures 210U, 220U disposed on the first and second intermediate electrode structures 210L, 220L, a first insulating layer IL0 disposed between the first and second bottom electrode structures 210B, 220B, a second insulating layer IL1 disposed between the first and second intermediate electrode structures 210L, 220L, and a third insulating layer IL2 disposed between the first and second upper electrode structures 210U, 220U.

[0072] The first and second lower electrode structures 210B and 220B may correspond to the first and second lower electrode structures 210B and 220B of the capacitor structure 200 of Fig. 2b. The first and second intermediate electrode structures 210L and 220L may correspond to the first and second electrode structures 210 and 220 of the capacitor structure 200 of Fig. 2c.

[0073] The first and second upper electrode structures 210U and 220U may be disposed on the first and second intermediate electrode structures 210L and 220L. The first and second upper electrode structures 210U and 220U may have different potentials.

[0074] The first upper electrode structure 210U may include first upper electrodes MC2a, ML2a and a first upper connector UCP1 connecting the first upper electrodes MC2a, ML2a and extending in the first direction (X direction). The first upper electrodes MC2a, ML2a may have a line shape protruding and extending in the second direction (Y direction) from the first upper connector UCP1. The first upper electrodes MC2a, ML2a may form first finger portions FP1 branching from the first upper connector UCP1. In one example, the first upper electrodes MC2a, ML2a may overlap the first electrodes MC1a, ML1a of the first intermediate electrode structure 210L and the first bottom electrode ML0a of the first bottom electrode structure 210B in the vertical direction (Z direction). The first upper connecting part UCP1 may overlap the second connecting part CP2 of the second intermediate electrode structure 220L and the first lower connecting part BCP1 of the first lower electrode structure 210B in the vertical direction (Z direction).

[0075] The second upper electrode structure 220U may include second upper electrodes MC2b, ML2b and a second upper connector UCP2 connecting the second upper electrodes MC2b, ML2b and extending in the first direction (X direction). The second upper electrodes MC2b, ML2b may have a line shape protruding and extending in the second direction (Y direction) from the second upper connector UCP2. The second upper electrodes MC2b, ML2b may form second finger portions FP2 branching from the second upper connector UCP2. In one example, the second upper electrodes MC2b, ML2b may overlap the second electrodes MC1b, ML1b of the second intermediate electrode structure 220L and the second bottom electrode ML0b of the second bottom electrode structure 220B in the vertical direction (Z direction). The second upper connecting part UCP2 may overlap the first connecting part CP1 of the first intermediate electrode structure 210L and the second lower connecting part BCP2 of the second lower electrode structure 220B in the vertical direction (Z direction).

[0076] The first top electrodes MC2a, ML2a and the second top electrodes MC2b, ML2b may be alternately arranged in a first direction (X direction). The first top connector UCP1 may be spaced apart from the second top connector UCP2 in a second direction (Y direction). The first top electrodes MC2a, ML2a and the second top electrodes MC2b, ML2b may include a conductive material.

[0077] The first upper electrodes MC2a, ML2a and the second upper electrodes MC2b, ML2b may each include a third wall pattern MC2a, MC2b and a fourth wall pattern ML2a, ML2b extending from the third wall pattern MC2a, MC2b. In one example, the third wall patterns MC2a, MC2b may contact the second wall patterns ML1a, ML1b. The third wall patterns MC2a, MC2b may include a 3-1 wall pattern MC2a arranged on the 2-1 wall pattern ML1a and a 3-2 wall pattern MC2b arranged on the 2-2 wall pattern ML1b.

[0078] The first wall patterns MC1a and MC1b can include a 1-1 side surface MCS1, and the second wall patterns ML1a and ML1b can include a 2-1 side surface MLS1 extending from the 1-1 side surface MCS1.

[0079] The third wall patterns MC2a and MC2b can include a first-second side surface MCS2, and the fourth wall patterns ML2a and ML2b can include a second-second side surface MLS2 extending from the first-second side surface MCS2.

[0080] The first wall patterns MC1a, MC1b and the third wall patterns MC2a, MC2b may have widths that increase linearly in the first direction (X direction) as they move in the vertical direction (Z direction). The first-1 side surface MCS1 and the first-2 side surface MCS2 may have a linear shape. The second wall patterns ML1a, ML1b and the fourth wall patterns ML2a, ML2b may have widths that increase nonlinearly in the first direction (X direction) as they move in the vertical direction (Z direction). The second-1 side surface MLS1 and the second-2 side surface MLS2 may have a curved shape.

[0081] The side profiles at the boundary point P1 between the first-1 side MCS1 and the second-1 side MLS1 and at the boundary point P1' between the first-2 side MCS2 and the second-2 side MLS2 may change nonlinearly.

[0082] The height of the third wall patterns MC2a and MC2b in the vertical direction (Z direction) may be greater than the height of the first wall patterns MC1a and MC1b in the vertical direction (Z direction). However, without being limited thereto, the height of the third wall patterns MC2a and MC2b in the vertical direction (Z direction) may be substantially the same as the height of the first wall patterns MC1a and MC1b in the vertical direction (Z direction).

[0083] The height of the fourth wall patterns ML2a and ML2b in the vertical direction (Z direction) may be greater than the height of the second wall patterns ML1a and ML1b in the vertical direction (Z direction). In one example, the width of the upper surfaces of the second wall patterns ML1a and ML1b in the first direction (X direction) may be substantially the same as the width of the upper surfaces of the fourth wall patterns ML2a and ML2b in the first direction (X direction).

[0084] Each of the third wall patterns MC2a and MC2b and the fourth wall patterns ML2a and ML2b has a line shape extending in the second direction (Y direction) and can be formed by a dual damascene process.

[0085] The bottom surfaces of the third wall patterns MC2a and MC2b, the first-second side surfaces MCS2 of the third wall patterns MC2a and MC2b, and the second-second side surfaces MLS2 of the fourth wall patterns ML2a and ML2b may be covered with the second barrier conductive films MB2a and MB2b. In one example, the second-first barrier conductive film MB2a may extend along the bottom surface of the third-first wall pattern MC2a, the first-second side surface MCS2 of the third-first wall pattern MC2a, and the second-second side surface MLS2 of the fourth-first wall pattern ML2a. In one example, the second-second barrier conductive film MB2b may extend along the bottom surface of the third-second wall pattern MC2b, the first-second side surface MCS2 of the third-second wall pattern MC2b, and the second-second side surface MLS2 of the fourth-second wall pattern ML2b. In one example, the second barrier conductive films MB2a and MB2b may include the same material as the first barrier conductive films MBa and MBb.

[0086] The capacitor formed by the 3-1 wall pattern MC2a, the 3-2 wall pattern MC2b, and the third insulating layer IL2 may have a third capacitance C3. The capacitor formed by the 4-1 wall pattern ML2a, the 4-2 wall pattern ML2b, and the third insulating layer IL2 may have a fourth capacitance C4. The fourth capacitance C4 may be larger than the third capacitance C3.

[0087] Figure 8a is an oblique view showing another embodiment of a lower wiring structure of a semiconductor device, Figure 8b is a plan view showing one embodiment of the lower wiring structure of Figure 8a, and Figure 9 is a cross-sectional view showing one embodiment of the lower wiring structure of Figure 8b along line IV-IV'.

[0088] 8a, 8b, and 9, the lower wiring structure 250′ may be disposed under the first region R1 of the memory cell structure CELL in the peripheral circuit structure PERI shown in FIG. 1c. The lower wiring structure 250′ may be spaced apart in the first direction (X direction) from the capacitor structure 200′ disposed under the second region R2 of the memory cell structure CELL in the structure PERI.

[0089] The lower wiring structure 250′ may include a first wiring structure 250A′ and a second wiring structure 250B′. The first wiring structure 250A′ may be alternately arranged with the second wiring structure 250B′ in the first direction (X direction).

[0090] The first wiring structure 250A' may include a first lower wiring 251 extending in the second direction (Y direction), a first peripheral contact plug 253 arranged on the first lower wiring 251, a first peripheral wiring 255 arranged on the first peripheral contact plug 253 and extending in the second direction (Y direction), third peripheral contact plugs 257a, 257b on the first peripheral wiring 255, and a third peripheral wiring 259 arranged on the third peripheral contact plugs 257a, 257b and extending in the second direction (Y direction).

[0091] The first wiring structure 250A' may be a wiring structure in which third peripheral contact plugs 257a and 257b and a third peripheral wiring 259 are added to the first wiring structure 250A of FIG. 4a.

[0092] The second wiring structure 250B' may include a second lower wiring 252 extending in the second direction (Y direction), second peripheral contact plugs 254a, 254b arranged on the second lower wiring 252, a second peripheral wiring 256 arranged on the second peripheral contact plugs 254a, 254b and extending in the second direction (Y direction), a fourth peripheral contact plug 258 on the second peripheral wiring 256, and a fourth peripheral wiring 260 on the fourth peripheral contact plug 258.

[0093] The second wiring structure 250B' may be a wiring structure in which a fourth peripheral contact plug 258 and a fourth peripheral wiring 260 are added to the second wiring structure 250B of FIG. 4a.

[0094] The third peripheral contact plugs 257a and 257b of the first wiring structure 250A' may be disposed at the same level as the fourth peripheral contact plug 258 of the second wiring structure 250B'. The third peripheral wiring 259 and the fourth peripheral wiring 260 may be disposed at the same level.

[0095] The third peripheral contact plugs 257a, 257b and the fourth peripheral contact plug 258 may have a cylindrical shape as contact structures. The third peripheral contact plugs 257a, 257b and the fourth peripheral contact plug 258 may have a via hole shape. The third peripheral wiring 259 and the fourth peripheral wiring 260 may have a line shape extending in the second direction (Y direction).

[0096] The third peripheral contact plugs 257a and 257b and the third peripheral wiring 259 may be provided and / or formed by a dual damascene process. The fourth peripheral contact plug 258 and the fourth peripheral wiring 260 may also be provided and / or formed by the dual damascene process.

[0097] The third peripheral contact plugs 257a and 257b may include a 3-1 peripheral contact plug 257a and a 3-2 peripheral contact plug 257b spaced apart in the second direction (Y direction) on the first peripheral wiring 255 between the first peripheral wiring 255 and the third peripheral wiring 259. The fourth peripheral contact plug 258 may be disposed in a central region of the second peripheral wiring 256 between the second peripheral wiring 256 and the fourth peripheral wiring 260. However, without being limited thereto, the fourth peripheral contact plug 258 may be disposed to intersect with the third peripheral contact plugs 257a and 257b disposed at the same level.

[0098] The height of the third and fourth peripheral wirings 259 and 260 in the vertical direction (Z direction) can be greater than the height of the first and second peripheral wirings 255 and 256 in the vertical direction (Z direction).

[0099] The width of the first peripheral contact plug 253 may increase linearly in the vertical direction (Z direction). The first peripheral contact plug 253 has a third-first side surface CS1, and the third-first side surface CS1 may have a cylindrical side surface shape.

[0100] The first peripheral wiring 255 may be in contact with the top surface of the first peripheral contact plug 253 and may have a fourth-1 side surface LS1 extending from the third-1 side surface CS1 of the first peripheral contact plug 253.

[0101] The width of the fourth peripheral contact plug 258 may increase linearly in the vertical direction (Z direction). The fourth peripheral contact plug 258 has a third-2 side surface CS2, which may have a cylindrical side surface shape. The third peripheral contact plugs 257a and 257b may have the same third-2 side surface CS2 as the fourth peripheral contact plug 258.

[0102] The fourth peripheral wiring 260 may extend from the top surface of the fourth peripheral contact plug 258 and have a fourth-second side surface LS2 extending from the third-second side surface CS2 of the fourth peripheral contact plug 258.

[0103] The side profile at the boundary point P2 where the 3-1 side CS1 of the first peripheral contact plug 253 and the 4-1 side LS1 of the first peripheral wiring 255 meet and at the boundary point P2' where the 3-2 side CS2 of the third peripheral contact plugs 257a, 257b and the 4-2 side LS2 of the third peripheral wiring 259 meet may change nonlinearly.

[0104] The top surfaces of the third peripheral wiring 259 and the fourth peripheral wiring 260 may be disposed at the same level as the top surfaces of the fourth wall patterns ML2a and ML2b in Fig. 7. In one example, the depth from the top surfaces of the third peripheral wiring 259 and the fourth peripheral wiring 260 to a boundary point P2' where the 3-2 side surface CS2 and the 4-2 side surface LS2 meet may be smaller than the depth from the top surfaces of the fourth wall patterns ML2a and ML2b in Fig. 7 to a boundary point P1' where the 1-2 side surface MCS2 and the 2-2 side surface MLS2 meet.

[0105] FIG. 10 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0106] Referring to FIG. 10, a semiconductor device 10 may include a peripheral circuit structure PERI including a substrate 201 and a memory cell structure CELL including a plate layer 101 .

[0107] The peripheral circuit structure PERI may include a substrate 201 , impurity regions 205 and isolation regions 209 in the substrate 201 , circuit elements 221 disposed on the substrate 201 , a peripheral region insulating layer 290 , and an underlying wiring structure 250 .

[0108] The substrate 201 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). An active region may be defined in the substrate 201 by an isolation region 209. An impurity region 205 containing impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer. For example, the substrate 201 may be bulk silicon or silicon-on-insulator (SOI).

[0109] The circuit elements 221 may include planar transistors. Each circuit element 221 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, impurity regions 205 may be disposed in the substrate 201 as source / drain regions.

[0110] The insulating layer IL may be disposed on the circuit elements 221 on the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed in different process steps. The insulating layer IL may be made of an insulating material.

[0111] The lower wiring structure 250 may be electrically connected to the circuit element 221 and the impurity region 205. The lower wiring structure 250 may include a lower wiring (e.g., first lower wiring 251 in FIG. 4a), a peripheral wiring (e.g., first peripheral wiring 255 in FIG. 4a), and a contact plug (e.g., first peripheral contact plug 253 in FIG. 4a) between the lower wiring and the peripheral wiring. The lower wiring and the peripheral wiring may have a line shape, and the contact plug may have a via hole shape. An electrical signal may be applied to the circuit element 221 through the lower wiring structure 250. The lower wiring structure 250 may also be connected to the circuit gate electrode 225 in a region not shown.

[0112] The capacitor structure 200 may be disposed on a second region R2 of the peripheral circuit structure PERI, spaced apart in a first direction (X direction) from the lower wiring structure 250. The capacitor structure 200 may be disposed on an isolation region 209 of a substrate 201. The capacitor structure 200 may include a lower electrode formed in the same process as the lower wiring of the lower wiring structure 250, the peripheral wiring, and a peripheral contact plug disposed between the lower wiring and the peripheral wiring, a first wall pattern, and a second electrode including a second wall pattern extending from the first wall pattern.

[0113] The memory cell structure CELL has first and second regions R1 and R2 and may include a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 140 alternately stacked with the gate electrode 130, a channel structure CH disposed to penetrate the stacked structure of the gate electrode 130, and a contact plug 170 connected to the gate electrode 130 and extending in the vertical direction. The memory cell structure CELL may further include a horizontal insulating layer 113 disposed under the gate electrode 130, a substrate insulating layer 121 disposed to penetrate the plate layer 101, a stud 185 on the contact plug 170, and a cell region insulating layer 190 covering the gate electrode 130.

[0114] In the memory cell structure CELL, the first region R1 may be a region where the gate electrode 130 is vertically stacked to form a memory cell or connected to the contact plug 170. The second region R2 may be an outer region of the plate layer 101.

[0115] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104, which are stacked in sequence. The plate layer 101 has a plate shape and may function as at least a part of a common source line of the semiconductor device 100. The plate layer 101 may include a conductive material, for example, a semiconductor material. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0116] The first and second horizontal conductive layers 102 and 104 may be sequentially stacked on the upper surface of the plate layer 101 in the region where the channel structure CH is disposed. The first horizontal conductive layer 102 may function as a part of a common source line of the semiconductor device 100, for example, may function as a common source line together with the plate layer 101. The first horizontal conductive layer 102 may be directly connected to a channel layer in the channel structure CH. The first and second horizontal conductive layers 102 and 104 may include a semiconductor material, for example, polycrystalline silicon.

[0117] The horizontal insulating layer 113 may be disposed on the plate layer 101 at the same level as the first horizontal conductive layer 102. The horizontal insulating layer 113 may include first and second horizontal insulating layers 111 and 112 alternately stacked on the plate layer 101. The horizontal insulating layer 113 may be a layer that remains after a portion of the horizontal insulating layer 113 is replaced with the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100. The horizontal insulating layer 113 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials.

[0118] The substrate insulating layer 121 may be disposed to penetrate the plate layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104. The substrate insulating layer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0119] The gate electrodes 130 may be stacked on the plate layer 101 at a vertical distance to form a stacked structure together with the interlayer insulating layer 140. The stacked structure may include lower and upper stacked structures stacked vertically. The gate electrodes 130 may include first upper gate electrodes 130U1 and 130U2 forming string select transistors, memory gate electrodes 130M forming a plurality of memory cells, and second lower gate electrodes 130L1 and 130L2 forming ground select transistors. The number of memory gate electrodes 130M forming memory cells may be determined depending on the capacity of the semiconductor device 100.

[0120] The gate electrodes 130 may be stacked in the vertical direction on the first region R1 and spaced apart from each other, and may extend to different lengths in the x direction to form a stepped structure. Due to the stepped structure, the lower gate electrode 130 may extend longer than the upper gate electrode 130, and each gate electrode 130 may have a contact region 130P exposed to the upper side from the interlayer insulating layer 140. The gate electrodes 130 may be connected to the contact plugs 170 at the contact regions 130P, which are edge regions.

[0121] The gate electrode 130 may include a metal material, such as tungsten (W). Depending on the embodiment, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. The entire gate electrode 130 may include the same material. In an exemplary embodiment, the gate electrode 130 may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0122] The interlayer insulating layers 140 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 140 may be disposed on the upper surface of the plate layer 101 to be spaced apart vertically and extend in the x-direction. The interlayer insulating layers 140 may include an insulating material such as silicon oxide or silicon nitride.

[0123] The channel structures CH may extend in the vertical direction (Z direction) through the gate electrode 130 and be connected to the plate layer 101. The channel structures CH may each form one memory cell string and may be arranged spaced apart from each other in rows and columns on the plate layer 101. The channel structures CH may be arranged to form a lattice pattern in the XY plane or may be arranged in a staggered pattern in one direction. The channel structures CH may have a columnar shape and have inclined sides that become narrower as they approach the plate layer 101.

[0124] The channel structure CH may include lower and upper channel structures CH1 and CH2 stacked in the vertical direction. The channel structure CH may have a form in which the lower channel structure CH1 and the upper channel structure CH2 are connected, and may have a bent portion due to a difference in width in the connection region. However, depending on the embodiment, the number of channel structures stacked in the vertical direction (Z direction) may vary. Each channel structure CH may include a channel layer disposed in a channel hole, a gate dielectric layer, a channel buried insulating layer, and an upper channel pad.

[0125] The contact plugs 170 may be connected to the contact regions 130P of the gate electrodes 130. The contact plugs 170 may penetrate at least a portion of the cell region insulating layer 190 and be connected to the contact regions 130P of the gate electrodes 130 exposed at the top. The contact plugs 170 may penetrate the gate electrodes 130 under the contact regions 130P, and may penetrate the second horizontal conductive layer 104, the horizontal insulating layer 113, and the plate layer 101 to be connected to the lower wiring structure 250 in the peripheral circuit structure PERI.

[0126] The contact plug 170 may be separated from the gate electrode 130 under the contact region 130P by a contact insulating layer 160. The contact plug 170 may be separated from the plate layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104 by a substrate insulating layer 121.

[0127] Each of the contact plugs 170 may have a shape that extends horizontally in the contact region 130P. The contact plug 170 may include a vertical extension portion 170V that extends along the vertical direction (Z direction) and a horizontal extension portion 170H that extends horizontally from the vertical extension portion 170V and contacts the gate electrode 130. The horizontal extension portion 170H may be disposed along the periphery of the vertical extension portion 170V, and the entire side surface may be surrounded by the gate electrode 130. The contact plug 170 may be separated from the gate electrode 130 below the contact region 130P, i.e., the gate electrode 130 that is not electrically connected to the contact plug 170, by the contact insulating layer 160.

[0128] The contact plug 170 may include a conductive material such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some embodiments, the contact plug 170 may include a barrier layer extending along the side and bottom surfaces, or may have an air gap therein.

[0129] The contact insulating layers 160 may be disposed below the contact region 130P to surround each side of the contact plug 170. The contact insulating layers 160 may be disposed spaced apart from each other in the vertical direction (Z direction) around each of the contact plugs 170. The contact insulating layers 160 may be disposed at substantially the same level as the gate electrodes 130. The contact insulating layers 160 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0130] The stud 185 may constitute a cell wiring structure electrically connected to a memory cell in the memory cell structure CELL. The stud 185 may be connected to the channel structure CH and the contact plug 170, and may be electrically connected to the channel structure CH and the gate electrode 130. The stud 185 may include a metal, such as tungsten (W), copper (Cu), or aluminum (Al).

[0131] The cell region insulating layer 190 may be disposed to cover the stacked structure of the gate electrode 130 and the contact plug 170. The cell region insulating layer 190 may be made of an insulating material and may be made of a plurality of insulating layers.

[0132] The through plugs 164 and the capacitor contacts 165 are disposed in a second region R2 of the memory cell region CELL, which is an outer region of the plate layer 101, and may extend to the peripheral circuit region PERI through the cell region insulating layer 190. The through plugs 164 and the capacitor contacts 165 may be disposed to connect the studs 185 of the memory cell region CELL to the lower wiring structure 250 of the peripheral circuit region PERI. The through plugs 164 and the capacitor contacts 165 may include a conductive material, such as a metal material such as tungsten (W), copper (Cu), or aluminum (Al). The through plugs 164 and the capacitor contacts 165 may be formed in the same process step as the contact plugs 170, may include the same material, and may have the same internal structure.

[0133] The capacitor structure 200 may be disposed in the second region R2 across the peripheral circuit region PERI and the memory cell region CELL. The capacitor structure 200 may store electric charges. The capacitor structure 200 may include a first electrode structure 210, a second electrode structure 220, and an insulating layer IL. The capacitor structure 200 may be disposed on an isolation region 209 and may vertically overlap the isolation region 209.

[0134] 11a to 11g are views showing an embodiment of a method for manufacturing a semiconductor device. A manufacturing process of the lower wiring structure 250 and the capacitor structure 200 of the peripheral circuit structure PERI of FIG. 10 will be described with reference to FIGS.

[0135] Referring to FIG. 11a, a first insulating layer IL0 on a substrate 201, first and second lower wirings 251, 252 on a first region R1, first and second lower electrodes ML0a, ML0b on a second region R2, a second insulating layer IL1 on the first insulating layer IL0, a conductive liner 301 on the second insulating layer IL1, and a first interlayer insulating film 302 on the conductive liner 301 can be formed sequentially.

[0136] The first insulating layer IL0 may be formed on the substrate 201. The first and second lower wirings 251 and 252 and the first and second lower electrodes ML0a and ML0b may be embedded in the upper surface of the first insulating layer IL0.

[0137] The first and second lower wirings 251, 252 on the first region R1 and the first and second lower electrodes ML0a, ML0b on the second region R2 may be formed at the same level. The first and second lower wirings 251, 252 and the first and second lower electrodes ML0a, ML0b may be formed by a damascene process. A barrier conductive film BLa may be formed between the first and second lower wirings 251, 252 and the first insulating layer IL0. A barrier conductive film MB0 may be formed between the first and second lower electrodes ML0a, ML0b and the first insulating layer IL0.

[0138] A second insulating layer IL1, a conductive liner 301, and a first interlayer insulating film 302 may be sequentially formed on the first insulating layer IL0.

[0139] The conductive liner 301 may include a conductive material, such as, but not limited to, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), and combinations thereof.

[0140] The first interlayer insulating film 302 may include, but is not limited to, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and combinations thereof.

[0141] Referring to FIG. 11b, the conductive liner 301 and the first interlayer insulating film 302 can be etched to form a first trench RT1a exposing the second insulating layer IL1 from the first region R1 and a second trench RT2a exposing the second insulating layer IL1 from the second region R2.

[0142] The first trench RT1a may overlap in the vertical direction (Z direction) with the first and second lower interconnections 251 and 252. The second trench RT2a may overlap in the vertical direction (Z direction) with the first and second lower electrodes ML0a and MLb0.

[0143] 11c, a hard mask 303 and a second interlayer insulating film 304 may be sequentially formed on the first interlayer insulating film 302. The hard mask 303 may cover the first interlayer insulating film 302 and fill the first trench RT1a and the second trench RT2a. The hard mask 303 may include, but is not limited to, a spin-on hard mask (SOH). A second interlayer insulating film 304 may be formed on the hard mask 303. In one example, the second interlayer insulating film 304 may include, but is not limited to, the same material as the first interlayer insulating film 302, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination thereof.

[0144] Referring to FIG. 11d, the second interlayer insulating film 304, the hard mask 303, the first interlayer insulating film 302, and the conductive liner 301 can be sequentially etched to form a first opening RT1b in the first region R1 and a second opening RT2b in the second region R2.

[0145] The first opening RT1b can penetrate the second interlayer insulating film 304, the hard mask 303, the first interlayer insulating film 302, and the conductive liner 301 to expose a region of the second insulating layer IL1 that overlaps with the first and second lower interconnections 251, 252.

[0146] The second opening RT2b can penetrate the second interlayer insulating film 304, the hard mask 303, the first interlayer insulating film 302, and the conductive liner 301 to expose a region of the second insulating layer IL1 that overlaps with the first and second bottom electrodes ML0a and MLb0.

[0147] 11e, a via hole VPa exposing the first lower interconnection 251 through the second insulating layer IL1 and a third opening WPa exposing the first and second lower electrodes ML0a and ML0b through the second insulating layer IL1 may be formed. The third opening WPa may be formed by etching through the first and second openings RT1b and RT2b. The via hole VPa may be cylindrical, and the third opening WPa may be trench-shaped extending in the second direction (Y direction) to expose the first and second lower electrodes ML0a and MLb0. In one example, the width Wa of the via hole VPa in the first direction (X direction) may be smaller than the width Wb of the third opening WPa in the first direction (X direction). Remaining portions of the second interlayer insulating film 304, the hard mask 303, and the first interlayer insulating film 302 may be removed after etching.

[0148] Referring to FIG. 11f, a third trench VPb, a fourth trench VPc, and a fifth trench WPb may be formed in the second insulating layer IL1 using the conductive liner 301 as an etch mask.

[0149] The third trench VPb overlaps the via hole VPa, so the third trench VPb can be integral with the via hole VPa. The third trench VPb can be formed on the via hole VPa and have a curved side surface extending from the linear side surface of the via hole VPa. The third trench VPb can have a first height H1 from the upper surface of the conductive liner 301 to the lower surface of the curved side surface along the third direction (Z direction).

[0150] The fourth trench VPc is configured as a region overlapping with the second lower interconnection 252, and may be connected to the second lower interconnection 252 through a via hole (or a through plug) in a region not shown. The depth of the fourth trench VPc in the vertical direction (Z direction) may be smaller than the depth of the third trench VPb in the vertical direction (Z direction).

[0151] The fifth trench WPb overlaps the third opening WPa, and thus the fifth trench WPb may be integral with the third opening WPa. The fifth trench WPb may be formed over the third opening WPa and have a curved side surface extending from the linear side surface of the third opening WPa. The fifth trench WPb may have a second height H2 of the curved side surface from the top surface of the conductive liner 301 along the third direction (Z direction). The second height H2 of the fifth trench WPb may be greater than the first height H1 of the third trench VPb. The fifth trench WPb may be formed by etching to a depth deeper from the top surface of the conductive liner 301 than the third trench VPb.

[0152] Referring to FIG. 11g, a first peripheral contact plug 253 and a first peripheral wiring 255 can be formed in the third trench VPb, a second peripheral wiring 256 can be formed in the fourth trench VPc, and first wall patterns MC1a, MC1b and second wall patterns ML1a, ML1b can be formed in the fifth trench WPb.

[0153] Before forming the first wall patterns MC1a, MC1b and the second wall patterns ML1a, ML1b, barrier conductive films MBa, MBb may be conformally formed along the bottom and side surfaces of the fifth trench WPb.

[0154] A barrier conductive film BLb can be formed along the bottom and side surfaces of the third trench VPb before forming the first peripheral contact plug 253 and the first peripheral wiring 255. A conductive film can be formed along the bottom and side surfaces of the fourth trench VPc before forming the second peripheral wiring 256.

[0155] In the method for manufacturing a semiconductor device according to the embodiment, the first electrode structure 210 and the second electrode structure 220 of the capacitor structure 200 are formed in the same process as the lower interconnection structure 250, and the first wall patterns MC1a, MC1b and the second wall patterns ML1a, ML1b constituting the first electrode structure 210 and the second electrode structure 220 are formed in a dual damascene process together with the peripheral contact plug 253 and the peripheral interconnection 255. As a result, a distance between the capacitor structure 200 and the lower interconnection structure 250 can be minimized, thereby providing a semiconductor device with improved integration density.

[0156] FIG. 12 is a diagram illustrating a data storage system including a semiconductor device according to an embodiment of the present invention.

[0157] 12 , a data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) device, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0158] The semiconductor device 1100 may be a nonvolatile memory device, for example, the NAND flash memory device described above with reference to FIGS. 1a to 1c. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0159] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on the embodiment.

[0160] In an exemplary embodiment, the upper transistors UT1 and UT2 may comprise string select transistors, and the lower transistors LT1 and LT2 may comprise ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0161] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0162] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 in the first structure 1100F via a first connecting wire 1115 extending to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 in the first structure 1100F via a second connecting wire 1125 extending to the second structure 1100S.

[0163] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0164] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control multiple semiconductor devices 1100.

[0165] The processor 1210 can control the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 can operate according to predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 can include a controller interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. can be transmitted via the controller interface 1221. The host interface 1230 can provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0166] Although the present invention has been described above with reference to an embodiment thereof, those skilled in the art will understand that various modifications and variations of the present invention are possible without departing from the spirit and scope of the present invention as set forth in the claims. [Explanation of symbols]

[0167] CELL 1st semiconductor structure 210 1st electrode structure PERI Second semiconductor structure 220 Second electrode structure 201 Substrate MC1a, MC1b First wall pattern 200 Capacitor Structure ML1a, ML1b Second Wall Pattern 250 Lower wiring structure 101 Plate Layer 130 gate electrode CH Channel Structure

Claims

1. a first semiconductor structure including a substrate, a circuit element on the substrate, a lower wiring structure electrically connected to the circuit element, and a capacitor structure spaced apart from the lower wiring structure; a second semiconductor structure including: a plate layer disposed on the first semiconductor structure; gate electrodes stacked on the plate layer and spaced apart from each other along a direction perpendicular to an upper surface of the plate layer; and a channel structure extending through the gate electrodes and along the vertical direction; The capacitor structure includes: a first electrode structure including first electrodes spaced apart from each other in a first direction parallel to an upper surface of the substrate and extending in the vertical direction and a second direction intersecting the first direction; a second electrode structure including second electrodes arranged alternately with the first electrodes and extending in the second direction; Each of the first electrode and the second electrode includes a first wall pattern having a first side surface and a second wall pattern having a second side surface extending from the first side surface on the first wall pattern; A semiconductor device, wherein a side profile at a boundary between the first side and the second side of the first and second electrodes changes nonlinearly.

2. the first side surface has a linear shape whose width in the first direction increases toward an upper portion in the vertical direction, The semiconductor device according to claim 1 , wherein said second side surface extends from said first side surface and has a curved shape.

3. The semiconductor device of claim 1 , wherein the capacitor structure further comprises a barrier conductive layer covering a bottom surface of the first wall pattern, the first side surface of the first wall pattern, and the second side surface of the second wall pattern.

4. the first electrode structure further includes a first connection portion connecting the first electrodes and extending in the first direction, The semiconductor device of claim 1 , wherein the second electrode structure further comprises a second connection portion spaced apart from the first connection portion in the second direction, connecting the second electrode, and extending in the first direction.

5. The semiconductor device according to claim 4 , wherein an upper surface of the first connecting portion and an upper surface of the second connecting portion are disposed at the same level as an upper surface of the second wall pattern.

6. The semiconductor device according to claim 4 , wherein a lower surface of the first connecting portion and a lower surface of the second connecting portion are disposed at a higher level than a lower surface of the first wall pattern.

7. The capacitor structure includes: a first lower electrode structure disposed between the substrate and the first electrode structure, the first lower electrode structure including a first lower electrode overlapping the first electrode and a first lower connection portion connecting the first lower electrode and extending in the first direction; a second lower electrode structure disposed between the substrate and the second electrode structure, the second lower electrode structure including a second lower electrode overlapping the second electrode and a second lower connection portion connecting the second lower electrode and extending in the first direction; the first lower connecting portion overlaps with the second connecting portion; The semiconductor device according to claim 4 , wherein the second lower connecting portion overlaps with the first connecting portion.

8. The capacitor structure includes: a first upper electrode structure disposed on the first electrode structure and including a first upper electrode overlapping the first electrode and a first upper connection part connecting the first upper electrode and extending in the first direction; a second upper electrode structure disposed on the second electrode structure and including a second upper electrode overlapping the second electrode and a second upper connection portion connecting the second upper electrode and extending in the first direction; the first upper connecting portion overlaps with the second connecting portion; The semiconductor device according to claim 4 , wherein the second upper connecting portion overlaps with the first connecting portion.

9. The semiconductor device according to claim 8 , wherein the height of the first upper electrode structure in the vertical direction is greater than the height of the first electrode structure in the vertical direction.

10. each of the first upper electrode and the second upper electrode includes a third wall pattern having a third side surface, and a fourth wall pattern extending from the third wall pattern on the third wall pattern and having a fourth side surface; The semiconductor device according to claim 8 , wherein a side profile at a boundary between said third side surface and said fourth side surface changes nonlinearly.

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