Ferroelectric devices and methods of producing the same

Abstract

To provide semiconductor devices with a ferroelectric layer having improved ferroelectricity, and methods of forming the same.SOLUTION: A method of forming a semiconductor device substrate 900 includes depositing a doped hafnium dioxide layer (ferroelectric layer 922) above a substrate 902, and the doped hafnium dioxide layer has a first oxygen vacancy concentration. The method further includes performing an ultra-high vacuum anneal process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration, and performing an oxygen anneal process on the doped hafnium dioxide layer to decrease the second oxygen vacancy concentration.SELECTED DRAWING: Figure 9G

Description

[Background technology]

[0001] Many modern electronic devices include electronic memory configured to store data. Memory can be volatile or non-volatile. Volatile memory stores data while power is supplied. Stores data, and non-volatile memory can store data even when power is removed. Ferroelectric memory devices are one promising candidate for next-generation nonvolatile memories. For example, a ferroelectric memory device is a capacitor-type ferroelectric random access memory. FeRAM and ferroelectric field effect transistor (FeFET). and FeFET devices offer fast write times, high endurance, low power consumption, and radiation This offers many advantages, such as being less susceptible to damage from Summary of the Invention [Problem to be solved by the invention]

[0002] The ferroelectricity of the ferroelectric layer depends on its crystalline state. The higher the dopant concentration and oxygen vacancies in the ferroelectric layer, the better the ferroelectric properties. Affects ferroelectric properties, but requires the formation of a high proportion of orthorhombic phase in the ferroelectric layer, or It is difficult to form ferroelectric layers with a good balance between dopants and oxygen vacancies. . [Means for solving the problem]

[0003] The present disclosure provides a method, comprising: forming a doped dioxide film on a layer; depositing a hafnium layer, the doped hafnium dioxide layer comprising a first oxygen The method includes increasing the first oxygen vacancy concentration to a second oxygen vacancy concentration. performing an ultra-high vacuum annealing process on the doped hafnium dioxide layer to To reduce the second oxygen vacancy concentration, oxygen atoms are deposited on the doped hafnium dioxide layer. and performing a neal process.

[0004] The present disclosure provides a method, comprising depositing a doped hafnium dioxide film on a layer. and depositing a doped hafnium dioxide layer, the doped hafnium dioxide layer being in a first crystalline phase. The method further comprises: forming the doped hafnium dioxide layer into an amorphous hafnium dioxide layer; performing an ion implantation process on the doped hafnium dioxide layer to form a pre-doped hafnium dioxide layer; To crystallize the doped hafnium dioxide layer in a second crystalline phase, and performing an annealing process on the hafnium dioxide layer.

[0005] The present disclosure provides a semiconductor device structure, the structure comprising a transistor disposed on a substrate. a transistor, an interconnect structure provided above the transistor, and a and a ferroelectric capacitor (FeCAP). The FeCAP includes a first metal layer, and the first metal The layer is a single crystal metal layer. The FeCAP further comprises a ferroelectric layer provided on the first metal layer. The ferroelectric layer contains more than 90% of the orthorhombic phase. The device further includes a second metal layer disposed on the dielectric layer. [Effects of the Invention]

[0006] The present disclosure provides a ferroelectric layer having improved ferroelectric properties, and a device comprising the ferroelectric layer. In some embodiments, the ferroelectric layer is a single The ferroelectric layer is disposed on a crystalline metal layer and contains more than 90% orthorhombic phase. In order to increase the proportion of orthorhombic phase in the morphology and / or to provide a layer for atomic migration To increase the space within the ferroelectric layer, a UHV annealing process or ion beam may be used after the deposition of the ferroelectric layer. The injection process is carried out. [Brief explanation of the drawings]

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features shown in the accompanying drawings have been arbitrarily exaggerated for clarity of illustration. It may be enlarged or reduced. [Figure 1A] FIG. 1A is a circuit diagram of a FeRAM cell, according to some embodiments. [Figure 1B] FIG. 1B is a cross-sectional side view of the FeRAM cell of FIG. 1A according to some embodiments. [Figure 2A] FIG. 2A is a circuit diagram of an FeFET cell, according to some embodiments. [Figure 2B] FIG. 2B is a cross-sectional side view of the FeFET cell of FIG. 2A according to some embodiments. [Figure 3] FIG. 3 is a cross-sectional side view of a ferroelectric layer formed on a polycrystalline metal layer according to some embodiments. [Figure 4] FIG. 4 is a cross-sectional side view of a ferroelectric layer formed on a single-crystal metal layer according to some embodiments. [Figure 5] FIG. 5 depicts the crystal structure of the single crystal metal layer and the ferroelectric layer of FIG. 4, according to some embodiments. [Figure 6] 6A and 6B are cross-sectional side views of a capacitor according to some embodiments. [Figure 7] 7A-7C depict various stages of forming a ferroelectric layer according to some embodiments. [Figure 8] 8A-8C depict various stages of forming a ferroelectric layer according to some embodiments. [Figure 9] 9A-9G are cross-sectional side views of semiconductor device structures at various stages in the manufacture of the structures, according to some embodiments. [Figure 10] FIG. 10 is the semiconductor device structure of FIG. 9G according to an alternative embodiment. [Figure 11] 11A-11F are cross-sectional side views of a transistor at various stages in fabrication, according to some embodiments. [Figure 12] FIG. 12 is the semiconductor device structure of FIG. 9G according to an alternative embodiment. [Figure 13] FIG. 13 is the semiconductor device structure of FIG. 12 according to an alternative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The following embodiments illustrate many different embodiments or implementations for implementing different features of the present disclosure. EXAMPLES PROVIDED To simplify the disclosure, specific examples of elements and arrangements are described below. Of course, these are examples and are not intended to be limiting. For example, In the description, the configuration of a first feature above or on a second feature refers to the first and second and the first and second features may be formed in direct contact with each other, and An embodiment in which an additional feature is formed between the first and second features so as not to be in direct contact. Additionally, the present disclosure may refer to repeated reference numbers and / or letters in various embodiments. This repetition is for the purposes of simplicity and clarity and is not intended to be a statement in itself. It is not intended to dictate the relationship between the various embodiments and / or configurations referenced.

[0009] Furthermore, "below," "belower," "lower," "upper," "upper," "top," "top" and "top" Spatial relative terms such as " " and " " refer to one element or feature depicted in the figure relative to another element or feature. Spatial relative terms can be used to facilitate descriptions that explain relationships between objects. It is intended to encompass different orientations of the device during use or operation in addition to the orientation shown. The device may be otherwise oriented (rotated 90 degrees or in other directions) and the same reference numerals used herein may be used interchangeably. Spatially relative descriptors may likewise be so interpreted.

[0010] Furthermore, when a number or a range of numbers is described using "about," "approximately," etc. The term includes a stated value, such as plus or minus 10% of the stated number. It is intended to encompass numbers within a reasonable range including, but not limited to, the number of times ... For example, the term "about 5 nm" encompasses dimensions in the range of 4.5 nm to 5.5 nm. .

[0011] Several variations of the exemplary methods and structures are described. Those skilled in the art will appreciate the scope of other embodiments. It will be readily understood that other modifications contemplated within the scope of the present invention may be made. Although aspects may be described in a particular order, various other method embodiments may be described in any logical order. The method may be performed in any order and may include fewer or more steps than those described herein. In some figures, some reference numerals of components or features shown therein may be different from those of other figures. Components or features may be omitted to avoid obscuring them, which may be due to the nature of the illustration. This is to make it easier to take pictures.

[0012] FIG. 1A is a circuit diagram of a FeRAM cell, according to some embodiments. As shown, the FeRAM cell 100 includes a transistor 104 and a capacitor 101. The FeRAM cell 100 is a two-transistor, two-capacitor (2T2C) FeRAM cell. The FeRAM cell may be of other types, such as: 1A is a side cross-sectional view of the FeRAM cell 100 of FIG. 1B. As shown in FIG. The AM cell 100 includes a transistor 104 disposed on a substrate 102. The transistor 104 includes a drain region 104a and a source region 104b provided in the substrate 102. The substrate 102 may be a semiconductor substrate such as a silicon wafer. 2 is gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), silicon carbide (SiC), other suitable semiconductor materials, and / or combinations thereof The substrate 102 may include silicon or a compound semiconductor such as an n-type dopant. The drain region 104a may be doped with a dopant such as a dopant of argon or a p-type dopant. The source region 104b is doped with a dopant, such as an n-type dopant or a p-type dopant. It is okay to do so.

[0013] A gate electrode 104c is disposed between the drain region 104a and the source region 104b and the substrate 10 2. The gate electrode 104c may include one or more layers. The bottom electrode 104c may include one or more work function layers and a bulk layer. In the form, the work function layer is TiN, TaN, TaAlC, TiC, TaC, Co, A l, a single layer of TiAl, HfTi, TiSi, TaSi, or TiAlC, or these materials The bulk layer may be a layer of conductive material, such as a metal. In some embodiments, the bulk layer may include W, Cu, Ti, A, or other conductive materials. The gate electrode 104c may include an adhesive layer, a barrier layer, a capping layer, or a The work function layer may include additional layers, such as any suitable layer. The work function layer and additional layers are optional. A gate dielectric layer 104d may be provided between the gate electrode 104c and the substrate 102. The gate dielectric layer 104d comprises a dielectric material. The gate dielectric layer 104d may comprise a high-k dielectric layer, and in these embodiments, The dielectric layer 104d may have a dielectric constant value greater than about 7.0, and may be made of hafnium, aluminum, or other suitable materials. aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof It may comprise a metal oxide or silicate.

[0014] The transistor 104 may be a planar transistor, a FinFET, or a gate-all-around transistor. Nanostructured transistors such as (GAA)FETs, nanosheet FETs, or nanowire FETs The transistor may be any suitable transistor.

[0015] As shown in FIG. 1B, in some embodiments, the gate electrode 104c is The source region 104b may be electrically connected to a line (WL), and the source region 104b may be electrically connected to a bit line (BL). The drain region 104a is electrically connected to the capacitor 101, and the capacitor 101 is driven The drain region 104a is electrically connected to one or more conductive wirings 110 and It may be electrically connected to the capacitor 101 through one or more conductive vias 108. The substrate 101, one or more conductive traces 110, and one or more conductive vias 108 are formed in a dielectric layer structure. The dielectric structure 106 and the features formed therein may be integrated into the interconnect structure. The dielectric structure 106 may be of a multi-layer structure, including multiple inter-metal dielectric (IMD) layers.

[0016] The capacitor 101 may be a ferroelectric capacitor (FeCAP). In the embodiment, the capacitor 101 includes a first electrode 112, a second electrode 116, and a first electrode The ferroelectric layer 114 is disposed between the first electrode 112 and the second electrode 116. In some embodiments, the ferroelectric layer 114 is a high-k dielectric having a dielectric constant greater than about 3.9. For example, the ferroelectric layer 114 may be a layer made of a material such as hafnium dioxide (HfO2). Other suitable ferroelectric materials may include high-k dielectrics such as hafnium-based oxide materials. In some embodiments, the ferroelectric layer 114 may be made of, for example, For example, zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium Suitable elements include chromium, scandium, gadolinium, other suitable elements, or combinations thereof. It can be an elementally doped hafnium-based layer.

[0017] In some embodiments, the ferroelectric layer 114 is a doped dipolar ferroelectric material having an orthorhombic phase. The doped hafnium dioxide layer is either monoclinic or tetragonal. Other crystalline phases may not exhibit ferroelectric properties. The hafnium oxide layer contains oxygen atoms that can move to two different positions under an applied electric field, forming an oblique The doped hafnium dioxide layer with the crystalline phase has two orthorhombic crystal forms. The crystal forms have an interconversion barrier that can be switched by applying an electric field. In some embodiments, the addition of dopant atoms to the lattice of the hafnium oxide layer is This can change the local stress and provide enough space for oxygen atoms to move, resulting in ferroelectricity. Larger dopants shift the plane of the monoclinic structure, and atoms move into the orthorhombic structure. In some embodiments, the doped halide dioxide The zirconium layer has a dopant concentration between about 40 mole percent and about 60 mole percent. For example, the ferroelectric layer 114 may contain Hf 0.6 Zr 0.4 O2~Hf 0. 4Zr 0.6 In some embodiments, the zirconium dopant may be O. The concentration may be outside of about 40 mol% to about 60 mol%. Aluminum, lanthanum, titanium , tantalum, silicon, yttrium, scandium, or other dopants such as gadolinium. For dopant (D), the dopant concentration may range from about 0.1 mol % to about 15 mol %. For example, the ferroelectric layer 114 is 0.01 Hf 0.99 O2~D 0.15 Hf 0.8 5O2. Zirconium and hafnium have similar electronic structures, so doping Zirconium as a dopant can have a relatively high dopant concentration, The oxides of hafnium and hafnium may be substantially the same. Crystallization in the orthorhombic phase produces a mixture of the two states. The orthorhombic phase then By this, the electrons are polarized into one of two states.

[0018] In some embodiments, when deposited, the doped hafnium dioxide layer is non- The alloy is in a crystalline or partially crystalline state and is subjected to an annealing process to increase the proportion of the orthorhombic phase. The doped hafnium dioxide layer is multiphase, which means that it contains all possible phases (single This means that the ferroelectric layer 114 is crystallized in a crystal structure (clinic, orthorhombic, cubic, tetragonal). The greater the proportion of the orthorhombic phase, the better the ferroelectric properties. The ferroelectric properties of the material depend on the dopant concentration (lattice distortion facilitates the movement of elements when an electric field is applied). ), oxygen vacancy concentration (oxygen vacancies create spaces for elements to move when an electric field is applied) (which can help form the dopant in the crystal) and the delicate balance between the dopant and oxygen concentration. It also depends on the

[0019] Various embodiments of the present disclosure may be used to provide a cellulose acetate solution having a cellulose acetate content of about 90%, for example, greater than about 98% or about 100%. % orthorhombic phase. The method is described in detail in Figures 4-8C.

[0020] The first electrode 112 may be made of W, TaN, TiN, Ti, Ru, Pt, Ir, or other suitable conductive material. The second electrode 116 comprises a conductive material. In an embodiment, the second electrode 116 comprises the same material as the first electrode 112 .

[0021] Figure 2A is a circuit diagram of a FeFET cell 200, according to some embodiments. 2B is a cross-sectional side view of the FeFET cell 200 of FIG. 2A, according to some embodiments. As shown in Figures 2A and 2B, the FeFET cell 200 includes a FeFET cell 202 disposed on a substrate 202. The substrate 202 may include the same material as the substrate 102. The T204 includes a source region 204a and a drain region 204b. and drain region 204b are connected to source region 104b and drain region 104a, respectively. A gate electrode 204c is disposed above the substrate 202, and the gate The electrode 204c may comprise the same material as the gate electrode 104c. The gate electrode 204c is disposed between the gate electrode 204c and the substrate 202. In some embodiments, A surface layer (not shown) may be provided between the ferroelectric layer 204d and the substrate 202. 204d may comprise the same material as the ferroelectric layer 114. The T204 is provided above the WL and BL, which are provided on the dielectric structure 206. In this embodiment, WL is electrically connected to the gate electrode 204c, and BL is electrically connected to the source region 204a. is electrically connected to

[0022] In some embodiments, the ferroelectric layer 204d is a doped hafnium dioxide layer. Similar to the ferroelectric layer 114 shown in FIG. 1B, the method described in FIGS. 4 to 8C The method increases the proportion of the orthorhombic phase in the ferroelectric layer 204d, which means that the ferroelectric layer 204 d to improve the ferroelectric properties.

[0023] FIG. 3 illustrates a ferroelectric layer 304 formed on a polycrystalline metal layer 304, according to some embodiments. As shown in FIG. 3, the polycrystalline metal layer 304 is made up of two or more crystals. A ferroelectric layer including phases 304a, 304b, and 304c formed on the polycrystalline metal layer 304. The ferroelectric layer 302 is also polycrystalline. The ferroelectric layer 302 has two or more crystalline phases 302a, 302b, and 302c. In order to increase the proportion of the orthorhombic phase, the ferroelectric An annealing process is performed on layer 302. A polycrystalline metal layer, such as polycrystalline metal layer 304 The ferroelectric layer 302 formed thereon has a dielectric constant of about 5%, e.g., about 20%, after the annealing process. It may have less than 90% orthorhombic phase, such as less than 0%.

[0024] FIG. 4 illustrates a ferroelectric layer 404 formed on a single crystal metal layer 404 according to some embodiments. 4, the single crystal metal layer 404 has a single crystal phase. The ferroelectric layer 402 formed on the single-crystal metal layer 404 also contains a single crystalline phase. In some embodiments, the ferroelectric layer 402 is a doped hafnium dioxide layer; The lattice constants (or lattice parameters) a and b of the single crystal metal layer 404 are determined by the doping in the orthorhombic phase. The lattice constants a and b of the doped hafnium dioxide layer are substantially the same as those of the single crystal metal layer. 404 may act as a seed layer for the ferroelectric layer 402 to crystallize on. The lattice constants a and b of the single crystal metal layer 404 are the same as those of the doped hafnium dioxide layer of the orthorhombic phase. When the lattice constants a and b are the same, the ferroelectric layer 40 formed on the single-crystal metal layer 404 2 attempts to match the orthorhombic phase. The lattice constant c of the single crystal metal layer 404 is Since the dimensions of the surface acting as a seed are different from those of the surface acting as a seed, the crystallization of the ferroelectric layer 402 is hardly affected. The interface characteristics of the single crystal metal layer 404 are more important than the thickness of the single crystal metal layer 404. It is essential.

[0025] In some embodiments, the single crystal metal layer 404 has a symmetric crystal structure with a lattice constant a The angle between a and b is about 90°. For example, the crystal structure of the single crystal metal layer 404 is a cubic crystal. , tetragonal, orthorhombic, or other suitable crystal structure. The crystal structure of the single crystal metal layer 404 may be simple cubic, body-centered, face-centered, or any other suitable structure. The ferroelectric layer 40 deposited on the single crystal metal layer 404 may also have a suitable cubic crystal structure. 2 is to match the cubic-like hafnium dioxide lattice cell with that of the single-crystal metal layer 404. As long as the lattice cell is closer to orthorhombic hafnium dioxide than to monoclinic hafnium dioxide, The lattice constants a and b of the single crystal metal layer 404 and the ferroelectric layer 4 Some degree of mismatch (e.g., about 5% to about 10%) between the lattice constants a and b of O2 For example, if the lattice constants a and b of the single crystal metal layer 404 are relatively small, the lattice constants a and b may be small. In this case, the lattice constant c of the ferroelectric layer 402 tends to be relatively large. When the lattice constants a and b of 4 are relatively large, the lattice constant c of the ferroelectric layer 402 is relatively small. The cells of the ferroelectric layer 402 tend to maintain their volume. In this case, the ferroelectric layer 402 has a lattice constant that matches the lattice constants a and b of the single crystal metal layer 404. It tends to crystallize with constants a and b. For mismatches greater than about 10%, i.e., greater than about 10 nm, the lattice relaxes and the layers It can be as thin as less than 1 m.

[0026] In some embodiments, the single crystal metal layer 404 is a NiAl layer. It has a cubic crystal structure and may be formed by any suitable method, such as physical vapor deposition (PVD). The nickel concentration in the NiAl layer is about 40 atomic % to about 45 atomic %. The nickel content can be in the range of 60 atomic %. The nickel content is determined by the size and crystallinity of the NiAl crystals. It may affect the nickel content, such as about 40 atomic % to about 45 atomic %. This leads to a more favorable match with the orthorhombic structure. For example, X-ray crystallography (XRD) In this case, a peak appears around 31-32°, which is the orthorhombic peak of hafnium dioxide. The peak is stronger at lower nickel concentrations, such as below 45 atomic percent. It is a cubic crystal with lattice constants a and b equal to each other, between about 0.286 nm and about 0.289 nm. be.

[0027] In some embodiments, the lattice constants a and b of the ferroelectric layer 402 are, respectively, single-crystal 4, in accordance with some embodiments. As shown in FIG. 5, the single crystal metal layer 4 404 may be a NiAl layer having a crystalline structure 502, and the ferroelectric layer 402 may be a NiAl layer having a crystalline structure 502. The ferroelectric layer 402 may be a doped hafnium dioxide layer having a lattice constant of 04. The number a may be double the lattice constant a' of the single crystal metal layer 404. For example, the lattice constant of the NiAl layer The lattice constants a' and b' are both about 0.286 nm, and the lattice constants a and b of the ferroelectric layer 402 are , which is about twice the lattice constants a' and b', may be about 0.572 nm. With lattice constants a and b being , the crystal structure of the ferroelectric layer 402 is substantially orthorhombic.

[0028] Referring back to FIG. 4, the ferroelectric layer 402 may be formed by atomic layer deposition (ALD), PVD, or chemical It may be formed by any suitable method, such as chemical vapor deposition (CVD). In some embodiments, a ferroelectric layer 402 is formed on a single-crystal metal layer 404 by ALD. In some embodiments, the ferroelectric layer 402 has a thickness of about 3 nm to about 20 nm, such as about 5 nm to about 20 nm. In some embodiments, the ferroelectric layer 402 has a thickness in the range of about 20 nm. nm or processed at a temperature of less than about 350°C, such as about 250°C to about 300°C. It is formed by treating at a temperature of 1000°C and adding additional An annealing process may be performed, for example, using oxygen gas, nitrogen gas, or the like. The ferroelectric layer 402 is heated at a temperature in the range of about 200° C. to about 600° C. in an appropriate environment such as hydrogen gas. In some embodiments, the heating may include heating to a temperature of from 1 second to 300 seconds. The process for forming the ferroelectric layer 402 is performed at a temperature of about 200° C. to about 600° C. It may be carried out at elevated temperatures.

[0029] The ferroelectric layer 402 shown in FIG. 4 is, for example, greater than 98% orthorhombic, 90% or more In addition, the orthorhombic phase may be increased to more than 90% orthorhombic. Of these, 80% of the orthorhombic phase of the ferroelectric layer 402 may be horizontally aligned, which is the ferroelectric Furthermore, the ferroelectric layer 402 has a thickness of about 5 nm to about 10 nm, such as about 10 nm to about 20 nm. It contains crystalline domains in the range of about 20 nm.

[0030] 6A and 6B are cross-sectional side views of a capacitor 600 according to some embodiments. In some embodiments, as shown in FIG. 6A, the capacitor 600 is made of a single crystal metal. layer 404 as a first electrode and metal layer 602 as a second electrode, and the ferroelectric layer 402 is a single The metal layer 602 is disposed between the crystalline metal layer 404 and the metal layer 602. The metal layer 602 may be a single crystal metal layer. The metal of the metal layer 602 is the same as that of the single crystal metal layer 404. It may or may not be the same as the metal.

[0031] In some embodiments, as shown in FIG. 6B, the capacitor 600 is a single crystal The metal layer 404 is a first electrode, the metal layer 604 is a second electrode, and the ferroelectric layer 402 is provided between the single crystal metal layer 404 and the metal layer 604. In some embodiments The metal layer 604 may be a polycrystalline metal layer. The metal of the metal layer 604 may be a monocrystalline metal layer 40. The metal layer 602 or the metal layer 604 may or may not be the same as the metal of the first metal layer. In some embodiments, the metal layer 602 or An optional annealing process is performed after the formation of the metal layer 604. The capacitor 600 may be used as the capacitor 101 shown in FIGS. 1A and 1B. .

[0032] 7A-7C illustrate various stages in forming a ferroelectric layer 704, according to some embodiments. As shown in FIG. 7A, a ferroelectric layer 704 is deposited on layer 702. 2 is a metal layer such as the first electrode 112 shown in FIG. 1B or a substrate 2 shown in FIG. 2B. In some embodiments, layer 702 may be a semiconductor layer such as the layer 702 shown in FIG. In some embodiments, layer 702 may be a single crystal metal layer 404. The ferroelectric layer 704 may be a dielectric layer such as a doped hafnium dioxide layer. and may be formed by any suitable method, such as CVD, ALD, or PVD. Ferroelectric layer 704 contains oxygen vacancies 706. The oxygen vacancies 706 in ferroelectric layer 704 as deposited O6 may range from about 2% to about 5%.

[0033] Next, as shown in FIG. 7B, the ferroelectric layer 704 is crystallized to reduce the concentration of oxygen vacancies 706. To increase the annealing efficiency, an ultra-high vacuum (UHV) annealing process is performed. In some embodiments, the UHV annealing process may be performed at a processing temperature ranging from about 20°C to about 450°C. e -8 Thor~le -3 Thor and others -3 It is carried out at a process pressure of less than 1000 kJ / cm². The HV anneal process reduces the pressure outside the ferroelectric layer 704, oxygen atoms leave the ferroelectric layer 704. The resulting concentration of oxygen vacancies 706 is The removal of oxygen atoms or the creation of additional oxygen vacancies increases the atomic This creates a space for the ferroelectric material to move within the ferroelectric layer 704, and the Under the UHV annealing process conditions described above, an increased orthorhombic phase can be obtained. In some embodiments, the proportion of orthorhombic phase does not increase, but increases as a result of the UHV annealing process. As a result, there is more room for the remaining oxygen atoms in the ferroelectric layer 704 to move, The relevance is expected to be relatively high.

[0034] After the UHV annealing process, the ferroelectric layer 704 crystallizes with the orthorhombic phase as the primary crystalline phase. Then, as shown in FIG. 7C, oxygen vacancies 706 are formed to improve reliability. An optional annealing process is performed on the ferroelectric layer 704 to reduce The process is carried out in an oxygen gas atmosphere at a temperature ranging from about 20°C to about 450°C, and at about 1 atm. The treatment may be carried out at a treatment pressure ranging from about 1 m to about 20 atm for a time ranging from about 1 minute to about 5 hours. After crystallization by the UHV annealing process, the crystalline phase of the ferroelectric layer 704 is substantially stable. The phase should not change following the optional annealing process. After the annealing process, the concentration of oxygen vacancies 706 is about 2% to about 5%. The device signal is reduced to pre-process levels. Reliability is improved.

[0035] The ferroelectric layer 704 formed by the UHV annealing process has an increased proportion of the orthorhombic phase. and / or as a result of more space for atoms in the ferroelectric layer 704 to move. The optional annealing process further improves device reliability. In some embodiments, ferroelectric layer 704 is the ferroelectric layer in capacitor 101. 114, and the UHV process and optional annealing process may be used to form the second electrode 1 In some embodiments, layer 702 may be formed before the formation of first electrode 16. 12 and ferroelectric layer 704 is ferroelectric layer 114. In some embodiments The ferroelectric layer 704 may be used as the ferroelectric layer 204d in the FeFET 204. The UHV process and optional annealing process are performed before the formation of the gate electrode 204c. In some embodiments, layer 702 may be formed on substrate 202 (or on substrate 202). The ferroelectric layer 704 is the ferroelectric layer 204d.

[0036] 8A-8C illustrate various stages in forming a ferroelectric layer 804, according to some embodiments. As shown in FIG. 8A, a ferroelectric layer 804 is deposited on layer 802. 2 may comprise the same material as layer 702. Ferroelectric layer 804 may comprise doped hafnium dioxide. The layer may be a silicon layer and may be formed by any suitable method, such as CVD, ALD, or PVD. The ferroelectric layer 804 contains oxygen vacancies 806. The oxygen in the ferroelectric layer 804 as deposited The voids 806 may range from about 2% to about 5%.

[0037] The as-deposited ferroelectric layer 804 is then de-crystalline, as shown in FIG. 8B. and ion-implanting the ferroelectric layer 804 to provide an amorphous phase in the ferroelectric layer 804. An implantation process 810 is performed. As mentioned above, in some embodiments, deposition The doped hafnium dioxide layer as deposited may be partially crystallized. The crystalline phase of the doped hafnium dioxide layer as deposited is approximately monoclinic, which The ion implantation process 810 does not result in a ferroelectric layer of doped hafnium dioxide. The dopant may be different from the dopant in the doped hafnium dioxide layer to substitute the element. The dopant 808 is introduced into the doped hafnium dioxide layer as deposited. As a result, the crystalline nature of the doped hafnium dioxide layer as deposited is eliminated. If so, the crystalline structure of the doped hafnium dioxide layer as deposited will be affected by the ion implantation process. The resulting doped diacid is destroyed by the dopant 808 from process 810. The hafnium chloride layer becomes an amorphous layer.

[0038] The ion implantation process 810 is performed with ion energies ranging from about 1 keV to about 10 keV. If the ion energy is less than about 1 keV, the as-deposited doping The monoclinic structure of the deposited hafnium dioxide layer is not destroyed. If Θ is greater than about 10 keV, manufacturing costs increase without significant benefit. The process dose is approximately 1e 13 / cm 2 ~approx. 1e 15 cm 2 The range may be: The on-implantation process 810 may lead to a shallow doping, such as about 10 nm or less. In some embodiments, the dopant 808 is phosphorus (P), arsenic (As), or phosphide. It may be a p-type or n-type dopant, such as iodine (B). The dopant 808 is gallium (Ga), antimony (Sb), germanium (Ge ), silicon (Si), or other suitable dopants. The applied hafnium dioxide layer is composed of zirconium, aluminum, lanthanum, titanium, and titanium. Dopants such as talc, silicon, yttrium, scandium, and gadolinium In some embodiments, ferroelectric layer 8 already contains a dopant different from that of ferroelectric layer 8. 04 contains two different dopants. For example, the first dopant is doped dioxide. The second dopant is formed in situ during the deposition of the hafnium layer. The doped hafnium dioxide is formed by an ion implantation process carried out after the deposition of the hafnium layer. It is introduced into the humid layer.

[0039] Next, as shown in FIG. 8C, annealing is performed on the ferroelectric layer 804 to form the orthorhombic phase. The annealing process is carried out at a processing temperature ranging from about 20°C to about 550°C. The annealing process may be carried out for a time ranging from about 1 second to about 1 hour. The ion implantation process for amorphizing the monoclinic phase is called the orthorhombic phase. Without the annealing process, the ferroelectric layer 804 would have both the monoclinic and orthorhombic phases after the annealing process. Therefore, it is important to remove the monoclinic phase before carrying out the annealing process. As a result, the resulting ferroelectric layer 804 is crystalline and contains a substantially orthorhombic phase.

[0040] In some embodiments, ferroelectric layer 804 is the ferroelectric layer 114, and the ion implantation process 810 may be performed prior to the formation of the second electrode 116. The annealing process may be performed before or after the formation of the second electrode 116. In some embodiments, layer 802 is the first electrode 112 and ferroelectric layer 804 is the ferroelectric layer 114. In some embodiments, the ferroelectric layer 804 is FeFE The ferroelectric layer 204d in the T204 may be used in the ion implantation process 810. The annealing process may be performed before the formation of the gate electrode 204c. In some embodiments, layer 802 may be formed on a substrate. 202 (or an interface layer formed on the substrate 202), and the ferroelectric layer 804 is a ferroelectric layer It is 204d.

[0041] 9A-9G illustrate various fabrication steps of a semiconductor device substrate 900 according to some embodiments. 9A, a semiconductor device structure 900 is formed on a substrate. 902 and one or more transistors 904 disposed on the substrate 902. 2 may be substrate 102, and transistor 904 may be the same transistor shown in FIG. 1B. Each transistor 904 may have a drain region 104a, a source region 104b, and a 04b, the source / drain region 906, which may be identical to the gate electrode 104c. 9. The electrode 908 includes a conductive contact 910 electrically connected to the source / drain region 906. The conductive contacts 910 may be provided to an interlevel dielectric (ILD) layer 912. A structure 914 is provided above the transistor 904. The interconnect structure 914 is shown in FIG. The dielectric structure 106 shown may be a conductive trace 916 and a conductive via 918 interconnecting the 1B. The conductive traces 110 and conductive vias 108 may be connected to each other.

[0042] Next, as shown in FIG. 9B, the source / drain regions 906 of each transistor 904 A conductive layer 920 is formed on the conductive via 918, which is electrically connected to one of the conductive layers. 920 may comprise the same material as the first electrode 112 shown in FIG. In some embodiments, the conductive layer 920 may be a single crystal metal, such as the single crystal metal layer 404 shown in FIG. Next, as shown in FIG. 9C, a ferroelectric layer 922 is formed on the conductive layer 920. The ferroelectric layer 922 may be the ferroelectric layer 402 shown in FIG. In an embodiment, the ferroelectric layer 922 may be the ferroelectric layer 704 shown in FIGS. 7A-7C, or is the ferroelectric layer 804 shown in FIGS. 8A to 8C. Next, as shown in FIG. 9D, A conductive layer 924 is formed on the ferroelectric layer 922. The conductive layer 924 is the same as the first conductive layer shown in FIG. 1B. 2 electrode 116, the same as the metal layer 602 shown in FIG. 6A or the metal layer 604 shown in FIG. 6B. It may contain one material.

[0043] Next, conductive layers 920, 922 are removed to form capacitor 926, as shown in FIG. 9E. 24 and ferroelectric layer 922 are patterned. Capacitor 926 is shown in FIGS. As a result, a ferroelectric layer 922 can be formed by the process described above. As a result, it may be FeCAP with improved ferroelectric properties. A dielectric layer 928 is formed on the substrate 921 to incorporate the capacitor 926. The dielectric layer 928 is It may be an IMD layer and may be part of the interconnect structure 914. The capacitor 926 is The interconnect structure 914 may be formed in a back-end of line (BEOL) process. In an embodiment, the capacitor 926 is a front-end-of-line (FEOL) or mid-line-of-line (MOL) process. Next, as shown in FIG. 9G, an interconnect structure 914 may be formed. Additional processes are performed to complete the process. A distribution layer (RDL) 930 is formed and contact pads 932 are formed on the RDL. The semiconductor device structure 900 includes a plurality of FeRAM cells (one transistor 904 and one The capacitor 926 is included.

[0044] 10 is the semiconductor device structure 900 of FIG. 9G according to an alternative embodiment. As shown in FIG. 9, an FeRAM cell 950 is formed in the interconnect structure 914. Each Fe The RAM cell 950 includes a transistor 952 electrically connected to a capacitor 926. The transistor 952 is a thin film transistor (TFT) formed in the BEOL process. Each transistor 952 may have a source / drain region 954 and a metal oxide layer 956, a gate dielectric layer 958, and a gate electrode 960. Region 954 may include a conductive material such as a metal or a metal nitride. In the present invention, the source / drain regions 954 include TiN, TaN, W, or WN. The oxide layer 956 serves as the channel region of the TFT. The metal oxide layer 956 is preferably indium gallium zinc oxide (IGZO), doped doped zinc oxide, doped indium oxide, doped cadmium, or other suitable The gate dielectric layer 958 comprises a metal oxide semiconductor material such as a metal oxide semiconductor material. , which may comprise the same material as the gate dielectric layer 104d shown in FIG. 1B, and the gate electrode 96 0 may comprise the same material as the gate electrode 104c shown in FIG. 1B. 52 is electrically connected to the capacitor by conductive traces 916 and conductive vias 918.

[0045] 11A-11F illustrate various stages in the fabrication of transistor 100, according to some embodiments. As shown in FIG. 11A, an optional interface layer 1102 is formed on a substrate 1102. 104 is formed, a ferroelectric layer 1106 is formed on the interface layer 1104, and a dummy gate 1 108 is formed on the ferroelectric layer 1106. The substrate 1102 is the same as the substrate 202 in FIG. ferroelectric layer 1106 may comprise the material of ferroelectric layer 704 of FIGS. 7A-7C, or It may comprise the same material as the ferroelectric layer 804 of Figures 8A-8C. Next, as shown in FIG. 11B, a ferroelectric layer 1106 and a dielectric layer 1108 are formed. The MI gate 1108 is patterned (interfacial layer 1104 omitted). Gate spacer 1110 is formed on the sides of the dummy gate 1108 and the ferroelectric layer 1106. Next, As shown in FIG. 1C, source / drain regions 1112 are formed on either side of the dummy gate 1108. The source / drain regions 1112 correspond to the source region 204a and the drain region 204b in FIG. Next, as shown in FIG. 11D, ILD layer 1 114 is formed above the source / drain regions 1112. In some embodiments, A contact etch stop layer (CESL) (not shown) is formed on the source / drain regions 111. 2, and an ILD layer 1114 is formed on the CESL. 08 is removed and a gate electrode 1116 is formed on the ferroelectric layer 1106. Gate electrode 1116 may comprise the same material as gate electrode 204c of FIG. 2B.

[0046] Next, as shown in FIG. 11E, conductive contacts 1118 are formed in the ILD layer 1114. The conductive contacts 1118 are electrically connected to the source / drain regions 1112. In some embodiments, a silicide layer (not shown) is formed between the conductive contact 1118 and the sole. In some embodiments, the source / drain region 1112 is formed between the source / drain region 1112 and the drain region 1112. As shown in FIG. 1, the ferroelectric layer 1106 is removed during the removal of the dummy gate 1108. Another ferroelectric layer 1120 is formed before the formation of the gate electrode 1116. Layer 1120 may be ferroelectric layer 704 of FIGS. 7A-7C or ferroelectric layer 80 of FIGS. 8A-8C. 4. In the embodiment shown in FIG. 11F, ferroelectric layer 110 6 may be a sacrificial layer, or a high-k dielectric layer that does not exhibit ferroelectric properties.

[0047] The transistor 100 is a FeFET including the ferroelectric layer 1106 or the ferroelectric layer 1120. The ferroelectric layer 1106 or the ferroelectric layer 1120 is shown in FIGS. 7A to 7C or 8A to 8C. The ferroelectric layer 1106 or the ferroelectric layer 112 is formed by the process described above. The ferroelectric properties of 0 are enhanced, leading to improved device performance and reliability.

[0048] 12 is the semiconductor device structure 900 of FIG. 9G according to an alternative embodiment. 2, instead of the capacitor 926 in the interconnect structure 914, a FeFET cell A FeFET cell 970 is formed in the interconnect structure 914. The FeFET cell 972 has a source / drain The gate electrode 970 includes a gate region 974, a ferroelectric layer 976, a metal oxide layer 978, and a gate electrode 980. The source / drain regions 974 are made of the same material as the source / drain regions 954 in FIG. The ferroelectric layer 976 may include the ferroelectric layer 704 of FIGS. 7A-7C or the ferroelectric layer 704 of FIGS. 8C. The metal oxide layer 978 may comprise the same material as the ferroelectric layer 804 of FIG. The gate electrode 980 may comprise the same material as the oxide layer 956 and the gate electrode 960. The FeFET 972 may be a TFT.

[0049] 13 is the semiconductor device structure 900 of FIG. 12 according to an alternative embodiment. 3, FeFET 972 is substantially the same as transistor 952 shown in FIG. However, instead of gate dielectric layer 958, FeFET 972 has a gold The ferroelectric layer 982 is disposed between the metal oxide layer 956 and the gate electrode 960. The ferroelectric layer 982 is the same as the ferroelectric layer 402 in FIG. 4 and the ferroelectric layer 70 in FIGS. 7A to 7C. 4, or may comprise the same material as ferroelectric layer 804 in FIGS. 8A-8C. In an embodiment, the gate electrode 960 is made of the same material as the single crystal metal layer 404 in FIG. Similar to transistor 1100, FeFET 972 may include ferroelectric layer 976 or The ferroelectric layer 976 or the ferroelectric layer 982 includes a ferroelectric layer 982. The ferroelectric layer 976 or the ferroelectric layer 982 is shown in FIGS. 7C, or the process described in FIGS. 8A to 8C. Ferroelectric layer 976 Alternatively, the ferroelectric properties of the ferroelectric layer 982 may be enhanced, leading to improved device performance and reliability. Gar.

[0050] 4, 7A-7C, or 8A-8C. The dielectric layer has improved ferroelectric properties. The ferroelectric layer is suitable for FeRAM, FeFET, or may be utilized in other suitable devices.

[0051] The present disclosure provides ferroelectric layers having improved ferroelectric properties. In the present invention, a ferroelectric layer is formed on a single-crystal metal layer, and the ferroelectric layer has an orthorhombic phase of more than 90%. In some embodiments, to increase the proportion of orthorhombic phase, and / or To increase the space within the layer for atoms to move, a UHV An annealing process or an ion implantation process is performed. For example, enhanced ferroelectric properties in the ferroelectric layer can lead to improved device performance and This leads to increased reliability.

[0052] One embodiment is a method, comprising: depositing doped hafnium dioxide on a layer; depositing a doped hafnium dioxide layer having a first oxygen vacancy concentration; The method includes: An ultra-high vacuum annealing process is performed on the doped hafnium dioxide layer to form a second oxygen-vacuum an oxygen annealing process on the doped hafnium dioxide layer to reduce the hole concentration; and performing the steps of:

[0053] Another embodiment is a method, comprising depositing a doped hafnium dioxide film on a layer. and depositing a doped hafnium dioxide layer, the doped hafnium dioxide layer being in a first crystalline phase. The method comprises: forming the doped hafnium dioxide layer into a partially crystallized layer; performing an ion implantation process on the doped hafnium dioxide layer to cause The doped hafnium dioxide layer is crystallized in a second crystalline phase by the addition of the doped hafnium dioxide. The method further includes performing an annealing process on the hafnium nitride layer.

[0054] A further embodiment is a semiconductor device structure. The structure includes a transistor disposed over a substrate. a transistor; an interconnect structure provided above the transistor; and a gate electrode connected to the interconnect structure. and a ferroelectric capacitor (FeCAP) formed on the first metal layer. The first metal layer is a single crystal metal layer. The FeCAP is a strong metal layer provided on the first metal layer. The FeCAP further includes a dielectric layer, the ferroelectric layer containing more than 90% of an orthorhombic phase. further includes a second metal layer disposed on the ferroelectric layer.

[0055] The above is a summary of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will be able to implement the same objectives as the embodiments presented here. and / or provide a basis for designing or modifying other processes and structures to achieve the same benefits. It should be understood that one skilled in the art can readily use the present disclosure as a foundation. Such equivalent constructions do not depart from, and are not intended to be construed as a departure from, the spirit and scope of the present disclosure. It should be understood that various modifications, substitutions, and alterations can be made without departing from the spirit and scope of the present invention. is. [Industrial Applicability]

[0056] The ferroelectric device and the method for forming the same disclosed herein are used in memory devices and manufacturing methods thereof. It can be applied to: [Explanation of symbols]

[0057] 100, 200, 950, 970: FeRAM cells 101, 926: Capacitor 102, 202, 902, 1102: Substrate 104, 904, 952, 1100: Transistors 104a, 204b: drain region 104b, 204a: Source region 104c, 204c, 908, 960, 980, 1116: gate electrodes 106, 206: Dielectric structure 108: Conductive via 110: Conductive wiring 112: 1st electrode 114, 204d, 302, 402, 804, 922, 976, 982, 1106, 1 120: Ferroelectric layer 116:Second electrode 204, 972:FeFET 304: Polycrystalline metal layer 302a, 302b, 302c, 302d, 304a, 304b, 304c: Crystal phase 404: Single crystal metal layer 502, 504: Crystal structure 600: Capacitor 602, 604: Metal layer 702, 802: layer 706, 806: oxygen vacancies 808: Dopant 900:Semiconductor device structure 906, 954, 974, 1112: Source / drain regions 910, 1118: Conductive contacts 914: Interconnection Structure 916: Conductive wiring 918: Conductive via 920, 924: Conductive layer 928: Dielectric layer 930:Redistribution layer (RDL) 932: Contact pad 956, 978: Metal oxide layer 958: Gate dielectric layer 1104:Interfacial layer 1108: Dummy Gate 1110: Gate spacer 1114:ILD layer BL: bit line DL: Drive line WL: Word line a, b, c, a', b': Lattice constant

Claims

1. depositing a doped hafnium dioxide layer on the layer, the hafnium oxide layer having a first oxygen vacancy concentration; the doped di-layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration. performing an ultra-high vacuum annealing process on the hafnium oxide layer; performing an oxygen annealing process to reduce the second oxygen vacancy concentration; A method comprising:

2. The method of claim 1 , wherein the first oxygen vacancy concentration ranges from about 2% to about 5%.

3. The method of claim 2 , wherein the second oxygen vacancy concentration ranges from about 5% to about 10%.

4. The method of claim 1 , wherein the layer is a first metal layer.

5. After the oxygen annealing process, a second metal is deposited on the doped hafnium dioxide layer. The method of claim 4 further comprising forming a layer.

6. The method of claim 1 , wherein the layer is an interfacial layer disposed on a substrate.

7. forming a dummy gate on the doped hafnium dioxide layer; Gate spacers are provided on the sides of the dummy gate and the doped hafnium dioxide layer. Forming and forming source / drain regions in the substrate; removing the dummy gate; forming a gate electrode on the doped hafnium dioxide layer; The method of claim 6 further comprising:

8. depositing a doped hafnium dioxide layer on the layer, the hafnium oxide layer being partially crystallized in a first crystalline phase; To amorphize the doped hafnium dioxide layer, performing an ion implantation process on the fluorine layer; to crystallize the doped hafnium dioxide layer in a second crystalline phase, performing an annealing process on the deposited hafnium dioxide layer; A method comprising:

9. 9. The method of claim 8, wherein the first crystalline phase is a monoclinic phase and the second crystalline phase is an orthorhombic phase. The method described.

10. During the deposition of the doped hafnium dioxide layer, a first dopant is added to the doped hafnium dioxide layer. a second dopant is introduced into the hafnium dioxide layer during the ion implantation process; 9. The method of claim 8, wherein the doped hafnium dioxide layer is introduced.

11. The first dopant is zirconium, aluminum, lanthanum, titanium, tantalum, containing silicon, yttrium, scandium, or gadolinium; The second dopant is phosphorus, arsenic, boron, gallium, antimony, germanium, or silicon.

12. The method of claim 8 wherein the layer is a first metal layer.

13. Prior to the annealing process, a second metal layer is deposited on the doped hafnium dioxide layer. The method of claim 12 further comprising forming.

14. The method of claim 8 , wherein the layer is an interfacial layer disposed on a substrate.

15. forming a dummy gate on the doped hafnium dioxide layer; Gate spacers are provided on the sides of the dummy gate and the doped hafnium dioxide layer. Forming and forming source / drain regions in the substrate; removing the dummy gate; forming a gate electrode on the doped hafnium dioxide layer; The method of claim 14 further comprising:

16. a transistor provided on a substrate; an interconnect structure disposed above the transistor; a ferroelectric capacitor (FeCAP) provided on the interconnect structure; Including, The FeCAP is a first metal layer that is a single crystal metal layer; a ferroelectric layer containing more than 90% of an orthorhombic phase disposed on the first metal layer; a second metal layer provided on the ferroelectric layer; Including, Semiconductor device structure.

17. 17. The semiconductor device structure of claim 16, wherein the first metal layer is a NiAl layer.

18. 18. The semiconductor of claim 17, wherein the ferroelectric layer is a doped hafnium dioxide layer. Device structure.

19. 20. The semiconductor device structure of claim 18, wherein the second metal layer is a single crystal metal layer.

20. 20. The semiconductor device structure of claim 18, wherein the second metal layer is a polycrystalline metal layer.

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