Semiconductor memory device

Abstract

To suppress an increase of a chip area.SOLUTION: A semiconductor memory device includes: a first laminate in which a plurality of insulating layers and a plurality of wiring layers 34 are alternately laminated; a plurality of memory pillars passing the first laminate in a first region and a second region; a plurality of contact plugs CC provided in a third region; and a first member SLTe dividing a part of the plurality of wiring layers in the third region. A first wiring layer includes a first portion, a second portion, a connection portion, and a third portion which is provided between the first portion and the second portion, connected to the connection portion and partially divided by the first member. A first terrace provided in the third portion and a second terrace provided in the third portion of a second wiring layer are disposed in parallel in a third direction.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as one type of semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-4446 [Patent Document 2] U.S. Patent Publication No. 2018 / 0076211 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a semiconductor memory device that can suppress an increase in chip area. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a first stack in which a plurality of insulating layers and a plurality of wiring layers including a first wiring layer and a second wiring layer provided above the first wiring layer are alternately stacked one layer at a time in a first direction; a plurality of memory pillars extending in the first direction and each passing through the first stack in a first region and a second region; a plurality of contact plugs extending in the first direction and provided in a third region located between the first region and the second region in a second direction intersecting the first direction, the contact plugs being respectively connected to a plurality of terraces included in the plurality of wiring layers; and a first member extending in the second direction and dividing a portion of each of the plurality of wiring layers in the third region in a third direction intersecting the first and second directions and divided into a plurality of pieces in the second direction. Each of the first wiring layer and the second wiring layer includes a first portion at least partially included in the first region, a second portion at least partially included in the second region, a connecting portion connecting the first portion and the second portion and extending in the second direction, and a third portion provided between the first portion and the second portion in the second direction and connected to the connecting portion in the third direction. A portion of the third portion included in the first wiring layer is divided in the third direction by a first member. The multiple terraces include a first terrace provided in the third portion of the first wiring layer and a second terrace provided in the third portion of the second wiring layer. The first terrace and the second terrace are arranged side by side in the third direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing the overall configuration of a semiconductor memory device according to an embodiment; [Figure 2] FIG. 1 is a circuit diagram of a memory cell array included in a semiconductor memory device according to an embodiment. [Figure 3] FIG. 1 is a perspective view showing an outline of a bonding structure of a semiconductor memory device according to an embodiment. [Figure 4] FIG. 1 is a plan view of a memory cell array included in a semiconductor memory device according to an embodiment. [Figure 5] FIG. 5 is an enlarged plan view of region ER in FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view of the memory area MA taken along line V1-V1 shown in FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view taken along line V2-V2 in FIG. 6. [Figure 8] FIG. 2 is a plan view of a pull-out region and a memory region in the vicinity thereof included in a semiconductor memory device according to an embodiment. [Figure 9] FIG. 1 is a conceptual diagram showing an example of the arrangement of terraces in a contact region included in a semiconductor memory device according to an embodiment. [Figure 10] 9 is a cross-sectional view taken along line V3-V3 in FIG. 8. [Figure 11] 9 is a cross-sectional view taken along line V4-V4 in FIG. 8. [Figure 12] 9 is a cross-sectional view taken along line V5-V5 in FIG. 8. [Figure 13] 13 is a cross-sectional view of the XY plane taken along line V6-V6 in FIGS. 11 and 12. FIG. [Figure 14] 1A and 1B are diagrams illustrating a plan view and a cross section of the vicinity of a protrusion provided in a semiconductor memory device according to an embodiment; [Figure 15] 1A to 1C are plan views of a lead-out region and its neighboring regions, illustrating a manufacturing process of the lead-out region included in a semiconductor memory device according to an embodiment. [Figure 16] 16 is a cross-sectional view taken along line V3-V3 in FIG. 15. [Figure 17] 16 is a cross-sectional view taken along line V4-V4 in FIG. 15. [Figure 18] 1A to 1C are plan views of a lead-out region and its neighboring regions, illustrating a manufacturing process of the lead-out region included in a semiconductor memory device according to an embodiment. [Figure 19] 19 is a cross-sectional view taken along line V4-V4 in FIG. 18. [Figure 20] 1A to 1C are plan views of a lead-out region and its neighboring regions, illustrating a manufacturing process of the lead-out region included in a semiconductor memory device according to an embodiment. [Figure 21] 21 is a cross-sectional view taken along line V4-V4 in FIG. 20. [Figure 22] 1A to 1C are plan views of a lead-out region and its neighboring regions, illustrating a manufacturing process of the lead-out region included in a semiconductor memory device according to an embodiment. [Figure 23] 23 is a cross-sectional view taken along line V4-V4 in FIG. 22. [Figure 24] 1A to 1C are plan views of a lead-out region and its neighboring regions, illustrating a manufacturing process of the lead-out region included in a semiconductor memory device according to an embodiment. [Figure 25]25 is a cross-sectional view taken along line V3-V3 in FIG. 24. [Figure 26] FIG. 10 is a plan view of a pull-out region and a memory region in the vicinity thereof included in a semiconductor memory device according to a first modified example. [Figure 27] 27 is a cross-sectional view taken along line V3-V3 in FIG. 26. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Here, subscripts are not limited to subscripts and superscripts, but also include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] A semiconductor memory device 1 according to an embodiment will be described below. In the following, the semiconductor memory device 1 will be described by taking as an example a three-dimensional stacked NAND flash memory in which memory cell transistors are arranged three-dimensionally.

[0009] 1 Configuration 1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that in Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0010] As shown in FIG. 1, the semiconductor memory device 1 includes an array chip 10 and a circuit chip 20. The semiconductor memory device 1 has a structure in which the array chip 10 and the circuit chip 20 are bonded together (hereinafter referred to as a "bonded structure"). Note that the semiconductor memory device 1 does not necessarily have a bonded structure. The semiconductor memory device 1 may have a structure in which a circuit and a memory cell array are formed on a semiconductor substrate.

[0011] The array chip 10 is a chip provided with an array of nonvolatile memory cell transistors. The circuit chip 20 is a chip provided with a circuit for controlling the array chip 10. The semiconductor memory device 1 of this embodiment is formed by bonding the array chip 10 and the circuit chip 20 together. Note that multiple array chips 10 may be provided. In this case, multiple array chips 10 may be bonded together so that they are stacked on the circuit chip 20.

[0012] The array chip 10 includes one or more memory cell arrays 11. The memory cell array 11 is a region in which non-volatile memory cell transistors are arranged three-dimensionally. In the example shown in FIG. 1, the array chip 10 includes one memory cell array 11.

[0013] The circuit chip 20 includes a sequencer 21, a voltage generating circuit 22, a row decoder 23, and a sense amplifier 24.

[0014] The sequencer 21 is a control circuit for the semiconductor memory device 1. For example, the sequencer 21 is connected to a voltage generation circuit 22, a row decoder 23, and a sense amplifier 24. The sequencer 21 controls the voltage generation circuit 22, the row decoder 23, and the sense amplifier 24. The sequencer 21 also controls the overall operation of the semiconductor memory device 1 under the control of an external controller. More specifically, the sequencer 21 executes write operations, read operations, erase operations, etc.

[0015] The voltage generation circuit 22 is a circuit that generates voltages used for write operations, read operations, erase operations, etc. For example, the voltage generation circuit 22 is connected to a row decoder 23 and a sense amplifier 24. The voltage generation circuit 22 supplies the generated voltages to the row decoder 23, the sense amplifier 24, etc.

[0016] The row decoder 23 is a circuit that decodes a row address. The row address is an address signal that specifies row-direction wiring (word lines and select gate lines, which will be described later) in the memory cell array 11. The row decoder 23 supplies the voltage applied from the voltage generating circuit 22 to the memory cell array 11 based on the result of decoding the row address.

[0017] The sense amplifier 24 is a circuit that writes and reads data. During a read operation, the sense amplifier 24 senses data read from the memory cell array 11. During a write operation, the sense amplifier 24 supplies a voltage corresponding to the write data to the memory cell array 11.

[0018] Next, the internal configuration of the memory cell array 11 will be described. The memory cell array 11 has a plurality of blocks BLK. A block BLK is, for example, a collection of a plurality of memory cell transistors from which data is erased collectively. The plurality of memory cell transistors in a block BLK are associated with rows and columns. In the example shown in FIG. 1, the memory cell array 11 includes four blocks BLK0, BLK1, BLK2, and BLK3.

[0019] Each block BLK includes multiple string units SU. The string units SU are a collection of multiple NAND strings that are collectively selected, for example, in a write or read operation. The NAND strings include multiple memory cell transistors connected in series. In the example shown in FIG. 1, each block BLK includes six string units SU0, SU1, SU2, SU3, SU4, and SU5. The number of blocks BLK in the memory cell array 11 and the number of string units SU in each block BLK are arbitrary.

[0020] 1.2 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell array 11 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell array 11. Note that the example shown in Fig. 2 shows the circuit configuration of one block BLK.

[0021] As shown in FIG. 2, the string unit SU includes a plurality of NAND strings NS.

[0022] The NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example shown in Fig. 2, the NAND string NS includes 38 memory cell transistors MC0 to MC37. The number of memory cell transistors MC included in the NAND string NS is arbitrary.

[0023] The memory cell transistor MC is a memory element that stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage film. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. The MONOS type uses an insulating film for the charge storage film. The FG type uses a conductor for the charge storage film. The following describes the case where the memory cell transistor MC is a MONOS type.

[0024] The select transistors ST1 and ST2 are switching elements. The select transistors ST1 and ST2 are used to select the string units SU during various operations. The number of select transistors ST1 and ST2 included in the NAND string NS is arbitrary. It is sufficient that the NAND string NS includes one or more select transistors ST1 and ST2.

[0025] The current paths of the select transistor ST2, memory cell transistors MC0 to MC37, and select transistor ST1 in the NAND string NS are connected in series. The drain of the select transistor ST1 is connected to a bit line BL. The source of the select transistor ST2 is connected to a source line SL.

[0026] The control gates of memory cell transistors MC0 to MC37 in the same block BLK are connected to word lines WL0 to WL37, respectively. More specifically, for example, block BLK includes six string units SU0 to SU5. Each string unit SU includes a plurality of memory cell transistors MC0. The control gates of the plurality of memory cell transistors MC0 in the block BLK are commonly connected to one word line WL0. The same is true for memory cell transistors MC1 to MC37.

[0027] The gates of the multiple select transistors ST1 in the string unit SU are commonly connected to one select gate line SGD. More specifically, the gates of the multiple select transistors ST1 in the string unit SU0 are commonly connected to a select gate line SGD0. The gates of the multiple select transistors ST1 in the string unit SU1 are commonly connected to a select gate line SGD1. The gates of the multiple select transistors ST1 in the string unit SU2 are commonly connected to a select gate line SGD2. The gates of the multiple select transistors ST1 in the string unit SU3 are commonly connected to a select gate line SGD3. The gates of the multiple select transistors ST1 in the string unit SU4 are commonly connected to a select gate line SGD4. The gates of the multiple select transistors ST1 in the string unit SU5 are commonly connected to a select gate line SGD5.

[0028] The gates of the select transistors ST2 in the block BLK are commonly connected to a select gate line SGS. Note that, similar to the select gate lines SGD, a different select gate line SGS may be provided for each string unit SU.

[0029] The word lines WL0 to WL37, the select gate lines SGD0 to SGD5, and the select gate line SGS are connected to a row decoder 23, respectively.

[0030] The bit line BL is commonly connected to one NAND string NS in each string unit SU of each block BLK. The same column address is assigned to the multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to a sense amplifier 24.

[0031] The source line SL is shared among, for example, a plurality of blocks BLK.

[0032] A set of multiple memory cell transistors MC connected to a common word line WL in one string unit SU is referred to as, for example, a “cell unit CU.” For example, write operations and read operations are performed in units of cell units CU.

[0033] 1.3 Bonding structure of semiconductor memory device Next, an outline of the bonding structure of the semiconductor memory device 1 will be described with reference to Fig. 3. Fig. 3 is a perspective view showing an outline of the bonding structure of the semiconductor memory device 1.

[0034] As shown in Fig. 3, the array chip 10 and the circuit chip 20 each include a plurality of bonding pads BP provided on surfaces facing each other. In the bonding structure, the bonding pad BP of the array chip 10 and the bonding pad BP of the circuit chip 20 are bonded together to form one bonding pad BP. In other words, the bonding pad BP is formed by bonding together an electrode (conductor) constituting the bonding pad BP provided on the array chip 10 and an electrode (conductor) constituting the bonding pad BP provided on the circuit chip 20. The array chip 10 and the circuit chip 20 are electrically connected via the pads BP.

[0035] Hereinafter, the surface where the array chip 10 and the circuit chip 20 are bonded together (hereinafter also referred to as the "bonding surface") will be referred to as the XY plane. The directions perpendicular to each other on the XY plane will be referred to as the X direction and the Y direction. The direction approximately perpendicular to the XY plane will be referred to as the Z direction.

[0036] 1.4 Planar layout of memory cell array Next, an example of a planar layout of the memory cell array 11 will be described with reference to FIG. 4. FIG. 4 is a plan view of the memory cell array 11. In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL, and the Y direction corresponds to the extension direction of the bit lines BL. Hatching is appropriately added to the plan view to make the drawing easier to understand. The hatching added to the plan view does not necessarily relate to the material or characteristics of the hatched components. In the cross-sectional views, illustrations of the configuration are appropriately omitted to make the drawing easier to understand. The configurations shown in each drawing are appropriately simplified.

[0037] As shown in FIG. 4, the memory cell array 11 includes, for example, four blocks BLK0 to BLK3.

[0038] The memory cell array 11 includes a stacked body (described later) including word lines WL and select gate lines SGD and SGS, a plurality of members SLT, and a plurality of members SHE. In the following description, the wiring layers corresponding to the word lines WL and select gate lines SGD and SGS are also collectively referred to as "stacked wiring."

[0039] The memory cell array 11 includes a memory area MA1, a draw-out area HA, and a memory area MA2. The memory area MA1, the draw-out area HA, and the memory area MA2 are arranged side by side in the X direction. When there is no need to distinguish between the memory areas MA1 and MA2, they are simply referred to as "memory area MA."

[0040] Each of the memory areas MA1 and MA2 is an area where memory cell transistors MC are arranged.

[0041] The lead-out region HA is a connection region between a plurality of wiring layers corresponding to the word lines WL and the select gate lines SGD and SGS, and a plurality of contact plugs. The lead-out region HA is disposed between the memory regions MA1 and MA2 in the X direction. The lead-out region HA includes a bridge region BR and a contact region CR.

[0042] The bridge region BR is a connection region between the memory regions MA1 and MA2. The bridge region BR is provided with multiple wiring layers corresponding to the word lines WL and the select gate lines SGS. The bridge region BR does not include a wiring layer corresponding to the select gate lines SGD. The wiring layer corresponding to the select gate lines SGD is separated between the memory regions MA1 and MA2. In the bridge region BR, a portion of each wiring layer extends in the X direction. For example, a contact plug connected to one wiring layer corresponding to either the word lines WL or the select gate lines SGS is connected to the corresponding wiring layer in the memory regions MA1 and MA2 via the bridge region BR. Meanwhile, the wiring layers corresponding to the select gate lines SGD in the memory regions MA1 and MA2 are electrically connected to each other via contact plugs and upper wirings provided in the memory regions MA1 and MA2.

[0043] The contact region CR is a region where multiple wiring layers corresponding to the word lines WL and select gate lines SGS are connected to corresponding contact plugs. In this embodiment, the contact region CR does not include a wiring layer corresponding to the select gate line SGD. The contact region CR is arranged parallel to the bridge region BR in the Y direction. In the contact region CR, the ends of the multiple wiring layers corresponding to the word lines WL and select gate lines SGS are drawn out in a stepped manner. Hereinafter, the region where the wiring layers corresponding to the word lines WL and select gate lines SGS are connected to the contact plugs will be referred to as a "terrace." The terrace is provided at the end of the wiring layer. No other wiring layer is provided above the terrace of each wiring layer. The multiple terraces are arranged in a stepped manner. The wiring layer corresponding to the select gate line SGD is connected to the corresponding contact plug in an end region in the X direction of the lead-out region HA that is not included in the bridge region BR or contact region CR.

[0044] The multiple members SLT each extend in the X and Z directions and are arranged side by side in the Y direction. Each of the multiple members SLT crosses the memory area MA1, the lead-out area HA, and the memory area MA2 in the X direction. Each member SLT has a structure in which an insulator is embedded in a slit, for example. Note that the member SLT is not limited to a single-layer structure of an insulator, but may have a multi-layer structure containing a conductor therein. The multiple members SLT include members SLTo and SLTe. The members SLTo and SLTe are processed together and embedded with the same material during the manufacturing process of the semiconductor memory device 1. That is, the members SLTo and SLTe formed together have the same layer structure, and corresponding layers each contain the same material. Therefore, the widths in the Y direction (cross-sectional shapes in the Y direction) of the members SLTo and SLTe are approximately the same to ensure the same embedded shapes. Note that the phrase "approximately the same" may include errors due to manufacturing variations.

[0045] The member SLTo separates stacked wirings adjacent in the Y direction via the member SLTo. Each of the regions separated by the multiple members SLTo corresponds to one block BLK. The contact region CR of block BLK(2i) (i is an integer greater than or equal to 0) and the contact region CR of block BLK(2i+1) are arranged to face each other in the Y direction via the member SLTo (to be plane-symmetric with the member SLTo as the plane of symmetry). More specifically, for example, the contact region CR of block BLK0 and the contact region CR of block BLK1 are arranged to face each other in the Y direction via the member SLTo. For example, the contact region CR of block BLK2 and the contact region CR of block BLK3 are arranged to face each other in the Y direction via the member SLTo.

[0046] The member SLTe is provided in the block BLK between two members SLTo adjacent in the Y direction. The member SLTe is divided into multiple parts in the X direction by one or more division regions SR provided in the contact region CR. In the example shown in FIG. 4, the member SLTe is divided into four parts in the X direction by three division regions SR1 to SR3. In the following description, when one of the division regions SR1 to SR3 is not specified, it will be simply referred to as a "division region SR." The member SLTe separates the wiring layers corresponding to the select gate lines SGD provided in the block BLK in the Y direction. Furthermore, the member SLTe divides in the Y direction part of each of the multiple wiring layers corresponding to the word lines WL and select gate lines SGS provided in the block BLK. In other words, by being divided by the division regions SR, the member SLTe does not electrically divide each of the multiple wiring layers corresponding to the word lines WL and select gate lines SGS in the Y direction. In other words, the wiring layers (either the word lines WL or the select gate lines SGS) adjacent in the Y direction via the member SLTe are connected to each other in the Y direction via the separation region SR. That is, the separation region SR is a connection region of the wiring layers adjacent in the Y direction via the member SLTe.

[0047] A plurality of members SHE are arranged in each of the memory regions MA1 and MA2. In the example shown in FIG. 4, in each of the memory regions MA1 and MA2, two members SHE are arranged between the adjacent members SLTo and SLTe. In each of the memory regions MA1 and MA2, the plurality of members SHE extend in the X direction and are aligned in the Y direction. Each of the plurality of members SHE arranged in the memory region MA1 crosses the memory region MA1. Each of the plurality of members SHE arranged in the memory region MA2 crosses the memory region MA2. Each member SHE has a structure in which an insulator is embedded. The member SHE separates, for example, the wiring layers corresponding to the select gate lines SGD adjacent in the Y direction via the member SHE. Each of the areas partitioned by the member SLT and the member SHE corresponds to one string unit SU.

[0048] 1.5 Planar layout of memory areas Next, an example of a planar layout of the memory area MA will be described with reference to Fig. 5. Fig. 5 is an enlarged plan view of the area ER in Fig. 4.

[0049] As shown in FIG. 5, a plurality of memory pillars MP, a plurality of contact plugs CV, and a plurality of bit lines BL are provided in the memory area MA.

[0050] The memory pillar MP is a pillar corresponding to the NAND string NS. One memory pillar MP functions as one NAND string NS. The structure of the memory pillar MP will be described in detail later. For example, the memory pillar MP has a substantially cylindrical shape extending in the Z direction. The memory pillar MP penetrates (passes through) a stacked body including the word line WL and the select gate lines SGD and SGS.

[0051] 5, the memory pillars MP in the memory area MA are arranged in a staggered pattern along the XY plane. The arrangement of the memory pillars MP can be designed arbitrarily. For example, the arrangement of the memory pillars MP does not have to be a staggered pattern.

[0052] A contact plug CV is provided on the memory pillar MP. The memory pillar MP is electrically connected to one of the bit lines BL via the contact plug CV. The contact plug CV is arranged to overlap the connected bit line BL in a plan view seen from the Z direction. Therefore, in a plan view, the position of the central axis of the memory pillar MP may differ from the position of the central axis of the contact plug CV.

[0053] The multiple bit lines BL each extend in the Y direction and are aligned in the X direction. The bit lines BL are arranged above the memory pillars MP. In a plan view, each bit line BL is arranged so as to overlap with at least one memory pillar MP for each string unit SU. The bit line BL is connected to one memory pillar MP of each string unit SU via a contact plug CV.

[0054] 1.6 Cross-sectional structure of memory area Next, an example of the cross-sectional structure of the memory area MA will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view of the memory area MA taken along line V1-V1 shown in Fig. 5.

[0055] As shown in FIG. 6, the memory cell array 11 includes insulating layers 31, 33, and 35, a semiconductor layer 32, wiring layers 34 and 39, insulators 36 and 37, and a conductor 38.

[0056] The insulating layer 31 includes, for example, silicon oxide (SiO). On the insulating layer 31, the semiconductor layer 32 is provided.

[0057] The semiconductor layer 32 is, for example, a plate-shaped semiconductor extending along the XY plane. The semiconductor layer 32 is used as the source line SL. The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. The semiconductor layer 32a is provided on the insulating layer 31. The semiconductor layer 32b is provided on the semiconductor layer 32a. The semiconductor layer 32c is provided on the semiconductor layer 32b. The semiconductor layer 32b is formed, for example, by replacing a sacrificial layer provided between the semiconductor layer 32a and the semiconductor layer 32c. The semiconductor layers 32a to 32c include, for example, silicon. The semiconductor layers 32a to 32c also include, for example, phosphorus (P) as a semiconductor impurity.

[0058] A stacked body SB is provided on the semiconductor layer 32. The stacked body SB is formed by alternately stacking a plurality of insulating layers 33 and a plurality of wiring layers 34 one by one in the Z direction. The plurality of wiring layers 34 included in the stacked body SB function as word lines WL and select gate lines SGD and SGS, respectively. In the example shown in FIG. 6, the stacked body SB includes 40 insulating layers 33 and 40 wiring layers 34 that are alternately stacked one by one on the semiconductor layer 32. In other words, 40 insulating layers 33 and 40 wiring layers 34 are alternately stacked one by one on the semiconductor layer 32. The 40 wiring layers 34 function as select gate lines SGS, word lines WL0 to WL37, and select gate lines SGD, respectively, in order from the side closest to the semiconductor layer 32. Note that a plurality of wiring layers 34 functioning as select gate lines SGS and SGD may be provided. The insulating layer 33 includes, for example, silicon oxide. For example, a titanium nitride (TiN) / tungsten (W) laminated structure is used as the conductive material of the wiring layer 34. In this case, the titanium nitride is formed so as to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of the tungsten when forming a film of tungsten by, for example, CVD (chemical vapor deposition), or as an adhesion layer to improve the adhesion of the tungsten.

[0059] The wiring layer 34 may also include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed so as to cover the conductive material. For example, in each of the wiring layers 34, the high-dielectric-constant material is provided so as to contact the insulating layers 33 or 35 provided above and below the wiring layer 34 and the side surfaces of the memory pillars MP. Titanium nitride is then provided so as to contact the high-dielectric-constant material. Tungsten is then provided so as to contact the titanium nitride and fill the interior of the wiring layer 34.

[0060] For example, when aluminum oxide is used as the high-dielectric-constant material, the memory cell transistor MC is also referred to as a MANOS (Metal-Aluminum-Nitride-Oxide-Silicon) type.

[0061] An insulating layer 35 is provided on the uppermost wiring layer 34 that functions as the select gate line SGD. In other words, the insulating layer 35 is provided on the stacked body SB. The insulating layer 35 includes, for example, silicon oxide.

[0062] A plurality of memory pillars MP are provided in the memory region MA. The memory pillars MP extend in the Z direction and pass through the stack SB. More specifically, the memory pillars MP pass through a plurality of wiring layers 34 corresponding to the select gate lines SGS, word lines WL0 to WL37, and select gate lines SGD stacked in the Z direction. In other words, the memory pillars MP pass through 40 wiring layers 34. The bottom surfaces of the memory pillars MP reach the semiconductor layer 32. Note that the memory pillars MP may have a structure in which a plurality of pillars are connected in the Z direction.

[0063] Each memory pillar MP includes, for example, a core film 40, a semiconductor film 41, and a stacked film 42. The core film 40 extends in the Z direction. For example, the upper end of the core film 40 is located above the uppermost wiring layer 34, and the lower end of the core film 40 is located in the same layer as the semiconductor layer 32. The semiconductor film 41 extends in the Z direction and covers the periphery of the core film 40. A portion of the side surface of the semiconductor film 41 contacts the semiconductor layer 32b. The stacked film 42 covers the side and bottom surfaces of the semiconductor film 41 except for the contact portion between the semiconductor film 41 and the semiconductor layer 32b. The core film 40 includes an insulator such as silicon oxide. The semiconductor film 41 includes, for example, silicon. The stacked film 42 includes a charge storage film. The configuration of the stacked film 42 will be described in detail later.

[0064] Memory cell transistors MC0 to MC37 are respectively formed by combining a memory pillar MP with a plurality of wiring layers 34 that function as word lines WL0 to WL37. Similarly, a select transistor ST1 is formed by combining a memory pillar MP with a wiring layer 34 that functions as a select gate line SGD. A select transistor ST2 is formed by combining a memory pillar MP with a wiring layer 34 that functions as a select gate line SGS.

[0065] A contact plug CV is provided on the semiconductor film 41 of each memory pillar MP. The contact plug CV has, for example, a substantially cylindrical shape extending in the Z direction. The contact plug CV includes a conductor 38. The conductor 38 includes, for example, copper as a conductive material. In the example shown in FIG. 6, multiple contact plugs CV connected in common to one wiring layer 39 are displayed in each cross-sectional region of the string unit SU separated by the members SLT and SHE. Memory pillars MP for which no contact plug CV is displayed are connected to different wiring layers 39 via contact plugs CV (not shown) in regions not shown. The wiring layers 39 to which each memory pillar MP is connected via the contact plugs CV function as bit lines BL.

[0066] The members SLTo divide the stacked body SB in the Y direction. In other words, the members SLTo divide the 40 wiring layers 34 in the Y direction. The members SLTo and SLTe (not shown) are buried in an insulator 36. The insulator 36 includes, for example, silicon oxide.

[0067] The member SHE divides the wiring layer 34 that functions as the select gate line SGD in the Y direction. In other words, the member SHE separates at least the wiring layer 34, among the multiple wiring layers 34, that is located farthest from the semiconductor layer 32. The upper end of the member SHE is located in a layer between the wiring layer 34 and the wiring layer 39. The lower end of the member SHE is located between the wiring layer 34 corresponding to the select gate line SGD and the uppermost layer of the wiring layer 34 corresponding to the word line WL. The height position of the bottom surface of the member SHE decreases depending on the number of wiring layers 34 corresponding to the select gate line SGD. The member SHE is filled with an insulator 37. The insulator 37 includes, for example, silicon oxide.

[0068] Next, an example of the cross-sectional structure of a memory pillar in the XY plane will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view taken along line V2-V2 in Fig. 6. More specifically, Fig. 7 shows the cross-sectional structure of a memory pillar MP in a layer that is parallel to the XY plane and includes the wiring layer 34.

[0069] As shown in FIG. 7, the stacked film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a block insulating film 45.

[0070] In a cross section including the wiring layer 34, the core film 40 is provided, for example, in the center of the memory pillar MP. The semiconductor film 41 surrounds the side surfaces of the core film 40. The tunnel insulating film 43 surrounds the side surfaces of the semiconductor film 41. The charge storage film 44 surrounds the side surfaces of the tunnel insulating film 43. The block insulating film 45 surrounds the side surfaces of the charge storage film 44. The wiring layer 34 surrounds the side surfaces of the block insulating film 45.

[0071] The semiconductor film 41 is used as the channels (current paths) of the memory cell transistors MC0 to MC37 and the select transistors ST1 and ST2. The tunnel insulating film 43 and the block insulating film 45 each contain, for example, silicon oxide. The charge storage film 44 has a function of storing charges and contains, for example, silicon nitride (SiN).

[0072] 1.7 Drawing Area Planar Layout Next, an example of a planar layout of the lead-out region HA will be described with reference to FIG. 8. FIG. 8 is a plan view of the lead-out region HA and the memory regions MA1 and MA2 in the vicinity thereof. The example shown in FIG. 8 corresponds to blocks BLK0 and BLK1 adjacent to each other in the Y direction. Note that the following description will focus on the layout of the contact region CR.

[0073] 8, terraces TR of a plurality of wiring layers 34 corresponding to the word lines WL and the select gate lines SGS are provided in the contact region CR. In a plan view seen from the Z direction, the terrace TR is a region that does not overlap with other wiring layers 34 provided above the wiring layer 34 and is a region to which a contact plug CC is connected. A contact plug CC is provided on each terrace TR. In addition, in an end region in the X direction of the lead-out region HA that is not included in the bridge region BR and the contact region CR, a contact plug CC is provided on the vicinity of the end of the wiring layer 34 corresponding to the select gate line SGD.

[0074] The shape of the terrace is similar to steps, terraces, rimstones, etc. In this embodiment, in one block BLK, steps extending in the X direction are arranged in three rows in the Y direction. Hereinafter, this arrangement will be referred to as a "three-row staircase." The number of rows in the Y direction may be multiple (two or more). In other words, a multi-row staircase may be used. In the example shown in FIG. 8, in each block BLK, a single-row staircase is provided between the member SLTo and the member SLTe in which the bridge region BR is provided, so as to be adjacent to the bridge region BR in the Y direction. Furthermore, a double-row staircase is provided between the member SLTo and the member SLTe in which the bridge region BR is not provided. In this case, the wiring layer 34 corresponding to each terrace of the double-row staircase is electrically connected to the bridge region BR via the separation region SR of the member SLTe.

[0075] The contact region CR includes, for example, one or more multistage processing regions ME and one or more deep digging regions DE. In the example shown in Fig. 8, the contact region CR includes three multistage processing regions ME1 to ME3 and three deep digging regions DE1 to DE3. Note that the number of multistage processing regions ME and deep digging regions DE is arbitrary.

[0076] In a plan view, the multi-stage processing area ME is a stepped area (multi-stage processed) extending from the center toward all four sides. The stack SB is recessed in the X and Y directions toward the center of the multi-stage processing area ME. In the example shown in FIG. 8, the center of the multi-stage processing area ME is positioned so as to straddle the member SLTo disposed between the block BLK0 and the block BLK1. In the following description, the area of ​​the multi-stage processing area ME that is recessed (the steps become lower) toward the memory area MA2 is referred to as the "front staircase section FS." The front staircase section FS is a staircase that slopes downward to the right from the left side of the page to the right side. On the other hand, the area of ​​the multi-stage processing area ME that is recessed (the steps become lower) toward the memory area MA1 is referred to as the "back staircase section RS." The back staircase section RS is a staircase that slopes upward to the right from the left side of the page to the right side. In other words, the multi-stage processing area ME includes a front staircase section FS and a back staircase section RS that face each other in the X direction. In the example shown in Figure 8, the left-hand area of ​​multi-stage machining area ME1 on the paper is referred to as the "front staircase section FS1," and the right-hand area of ​​multi-stage machining area ME1 on the paper is referred to as the "back staircase section RS1." Similarly, the left-hand area of ​​multi-stage machining area ME2 on the paper is referred to as the "front staircase section FS2," and the right-hand area of ​​multi-stage machining area ME2 on the paper is referred to as the "back staircase section RS2." The left-hand area of ​​multi-stage machining area ME3 on the paper is referred to as the "front staircase section FS3," and the right-hand area of ​​multi-stage machining area ME3 on the paper is referred to as the "back staircase section RS3."

[0077] The deep dig region DE is a region that is rectangular in plan view. The deep dig region DE is a region where multiple wiring layers 34 (and multiple insulating layers 33) are processed collectively (also referred to as "deep dig processing"). That is, the stacked body SB is recessed in the deep dig region DE. Note that the number of wiring layers 34 that are processed collectively in the deep dig region DE is arbitrary. The deep dig region DE1 includes the front staircase portion FS2 of the multi-stage processing region ME2. The deep dig region DE2 includes the front staircase portion FS3 of the multi-stage processing region ME3. The deep dig region DE3 includes the back staircase portion RS2 of the multi-stage processing region ME2 and the front staircase portion FS3 of the multi-stage processing region ME3 (i.e., the deep dig region DE2).

[0078] The contact region CR includes staircase regions SA1 to SA4 in which multiple terraces are arranged in three rows in the Y direction in a staircase pattern. The staircase region SA1 includes the left end region of the contact region CR in the X direction on the page and the front staircase portion FS1 of the multi-step processing region ME1. The staircase region SA2 includes the front staircase portion FS2 of the multi-step processing region ME2. The staircase region SA3 includes the back staircase portion RS2 of the multi-step processing region ME2. The staircase region SA4 includes the front staircase portion FS3 of the multi-step processing region ME3.

[0079] An example of the arrangement of terraces TR in the contact region CR will be described with reference to Fig. 9. Fig. 9 is a conceptual diagram showing an example of the arrangement of terraces TR in the contact region CR. The example shown in Fig. 9 shows the arrangement of terraces TR in blocks BLK0 and BLK1. In Fig. 9, one solid line frame corresponds to one terrace TR.

[0080] 9, three terraces TR are arranged side by side in the Y direction, so as to descend one step at a time in the direction away from the bridge region BR. In addition, in each staircase region SA, multiple terraces TR are arranged in the X direction, so as to form three steps each.

[0081] More specifically, in the staircase region SA1, three terraces TR corresponding to each of the word lines WL37 to WL35 are arranged in order in the Y direction away from the bridge region BR. Similarly, three terraces TR corresponding to each of the word lines WL34 to WL32 are arranged in order in the Y direction away from the bridge region BR. Three terraces TR corresponding to each of the word lines WL31 to WL29 are arranged in order in the Y direction away from the bridge region BR. Three terraces TR corresponding to each of the word lines WL28 to WL26 are arranged in order in the Y direction away from the bridge region BR. The staircase region SA1 includes a front staircase portion FS1. Therefore, in the X direction, from left to right on the paper, the terrace TR of the word line WL37, the terrace TR of the word line WL34, the terrace TR of the word line WL31, and the terrace TR of the word line WL28 are arranged in a staircase shape with three steps descending to the right. Similarly, in the X direction, the terraces TR of the word lines WL36, WL33, WL30, and WL27 are arranged in a staircase shape with three steps descending to the right. In the X direction, the terraces TR of the word lines WL35, WL32, WL29, and WL26 are arranged in a staircase shape with three steps descending to the right.

[0082] In the staircase region SA2, three terraces TR corresponding to each of the word lines WL25 to WL23 are arranged in order in the Y direction away from the bridge region BR. Similarly, three terraces TR corresponding to each of the word lines WL22 to WL20 are arranged in order in the Y direction away from the bridge region BR. Three terraces TR corresponding to each of the word lines WL19 to WL17 are arranged in order in the Y direction away from the bridge region BR. The staircase region SA2 includes a front staircase portion FS2. Therefore, in the X direction, from left to right on the paper, the terraces TR of the word line WL25, the terrace TR of the word line WL22, and the terrace TR of the word line WL19 are arranged in a staircase shape of three steps descending to the right. Similarly, in the X direction, the terraces TR of the word line WL24, the terrace TR of the word line WL21, and the terrace TR of the word line WL18 are arranged in a staircase shape of three steps descending to the right. In the X direction, the terraces TR of the word line WL23, the terraces TR of the word line WL20, and the terraces TR of the word line WL17 are arranged in a staircase shape with three steps each descending to the right.

[0083] In the staircase region SA3, three terraces TR corresponding to each of the word lines WL10 to WL8 are arranged in order in the Y direction away from the bridge region BR. Similarly, three terraces TR corresponding to each of the word lines WL13 to WL11 are arranged in order in the Y direction away from the bridge region BR. Three terraces TR corresponding to each of the word lines WL16 to WL14 are arranged in order in the Y direction away from the bridge region BR. The staircase region SA2 includes a back staircase portion RS2. Therefore, in the X direction, from left to right on the paper, the terrace TRs of the word line WL10, the terrace TRs of the word line WL13, and the terrace TRs of the word line WL16 are arranged in a staircase shape of three steps, each rising to the right. Similarly, in the X direction, the terrace TRs of the word line WL9, the terrace TRs of the word line WL12, and the terrace TRs of the word line WL15 are arranged in a staircase shape of three steps, each rising to the right. In the X direction, the terraces TR of the word line WL8, the terraces TR of the word line WL11, and the terraces TR of the word line WL14 are arranged in a staircase shape with three steps each rising to the right.

[0084] In the staircase region SA4, three terraces TR corresponding to each of the word lines WL7 to WL5 are arranged in order in the Y direction away from the bridge region BR. Similarly, three terraces TR corresponding to each of the word lines WL4 to WL2 are arranged in order in the Y direction away from the bridge region BR. Three terraces TR corresponding to each of the word lines WL1 and WL0 and the select gate line SGS are arranged in order in the Y direction away from the bridge region BR. The staircase region SA4 includes a front staircase portion FS3. Therefore, in the X direction, from left to right on the paper, the terrace TRs of the word line WL7, the terrace TRs of the word line WL4, and the terrace TRs of the word line WL1 are arranged in a staircase shape of three steps descending to the right. Similarly, in the X direction, the terrace TRs of the word line WL6, the terrace TRs of the word line WL3, and the terrace TRs of the word line WL0 are arranged in a staircase shape of three steps descending to the right. In the X direction, the terrace TR of the word line WL5, the terrace TR of the word line WL2, and the terrace TR of the select gate line SGS are arranged in a staircase shape with three steps going down to the right.

[0085] Each terrace TR of block BLK1 is arranged in the Y direction to face each terrace TR of block BLK0 across the member SLTo (plane symmetrically with the member SLTo as the plane of symmetry). For example, in block BLK0, the terrace TR of word line WL37, the terrace TR of word line WL36, and the terrace TR of word line WL35 are arranged in this order from the top to the bottom of the page. In contrast, in block BLK1, the terrace TR of word line WL37, the terrace TR of word line WL36, and the terrace TR of word line WL35 are arranged in this order from the bottom to the top of the page. The arrangement of the other terraces TR is similar.

[0086] 1.8 Cross-sectional structure of the pull-out area Next, an example of the cross-sectional structure of the lead-out region HA will be described with reference to Fig. 10 to Fig. 12. Fig. 10 is a cross-sectional view taken along line V3-V3 in Fig. 8. Fig. 11 is a cross-sectional view taken along line V4-V4 in Fig. 8. Fig. 12 is a cross-sectional view taken along line V5-V5 in Fig. 8.

[0087] First, a cross section along the Y direction will be described. Fig. 10 is a cross section showing a cross section of each terrace TR of word lines WL8 to WL10.

[0088] 10, the bridge region BR of the block BLK0 is provided on the left side of the page within the block BLK0. The bridge region BR is adjacent to the member SLTo. The bridge region BR includes a portion of each of the 39 wiring layers 34 corresponding to the select gate line SGS and the word lines WL0 to WL37. In the bridge region BR, the two surfaces of the member SLTo facing the Y direction contact the 39 wiring layers 34 corresponding to the select gate line SGS and the word lines WL0 to WL37.

[0089] For example, a terrace TR of the word line WL10 is provided between the bridge region BR and the member SLTe. A contact plug CC is provided on the terrace TR of the word line WL10. No wiring layer 34 corresponding to each of the word lines WL11 to WL37 is provided above the terrace TR of the word line WL10. Furthermore, between the member SLTe and the member SLTo provided between the block BLK0 and the block BLK1, the terrace TR of the word line WL9 and the terrace TR of the word line WL8 are arranged side by side from left to right on the page. Therefore, the terrace TR of the word line WL10, the terrace TR of the word line WL9 and the terrace TR of the word line WL8 are arranged side by side in the direction away from the bridge region BR. A contact plug CC is provided on each terrace TR of the word lines WL8 and WL9. No wiring layer 34 is provided above each terrace TR of the word lines WL8 and WL9.

[0090] 10, one surface of the member SLTe facing the Y direction is in contact with the terrace TR of the word line WL10. The other surface of the member SLTe facing the Y direction is in contact with the terrace of the terrace TR of the word line WL9. In other words, one surface of the member SLTe facing the Y direction is in contact with the 12 wiring layers 34 corresponding to the select gate line SGS and the word lines WL0 to WL10. The other surface of the member SLTe facing the Y direction is in contact with the 11 wiring layers 34 corresponding to the select gate line SGS and the word lines WL0 to WL9. In this way, the two surfaces of the member SLTe facing the Y direction are in contact with the wiring layers 34 that differ by one layer at positions facing each other in the Y direction of the contact region CR.

[0091] The members SLTo and SLTe have substantially the same cross-sectional shape in the Y direction.

[0092] The bridge region BR of block BLK1 is located on the right side of the page within block BLK1. The terraces TR of word lines WL10, WL9, and WL8 are arranged side by side in the direction away from the bridge region BR. Therefore, the terraces TR of blocks BLK0 and BLK1, which are located in the same layer, are arranged symmetrically with respect to the member SLTo located between blocks BLK0 and BLK1.

[0093] In this embodiment, an insulating layer 50 is provided between the semiconductor layer 32a and the semiconductor layer 32c in the lead-out region HA. That is, the semiconductor layer 32b is not formed in the lead-out region HA due to replacement. The insulating layer 50 includes, for example, silicon oxide. The semiconductor layer 32b may also be formed in the lead-out region HA.

[0094] 11 shows a cross section of each terrace TR of word lines WL35, WL32, WL29, WL26, WL23, WL20, WL17, WL8, WL11, WL14, WL5, and WL2 and select gate line SGS in block BLK0.

[0095] As shown in FIG. 11, staircase areas SA1, SA2, SA3, and SA4 are arranged side by side in the X direction from the left side of the paper to the right side of the paper.

[0096] The staircase region SA1 includes the front staircase portion FS1 of the multi-step processed region ME1. More specifically, the staircase region SA1 includes the terrace TR of the word line WL35 and the terrace TR of the word lines WL32, WL29, and WL26 of the front staircase portion FS1. The staircase region SA1, including its depth region in the Y direction (not shown), also includes the terrace TR of the word lines WL37 to WL26. Contact plugs CC are provided on the terrace TR of each of the word lines WL35, WL32, WL29, and WL26. In the staircase region SA1, the terrace TR of the word lines WL35, WL32, WL29, and WL26 are arranged in a staircase of three steps descending to the right from the left side of the drawing to the right side of the drawing.

[0097] The staircase region SA2 includes the front staircase portion FS2 of the multi-step processing region ME2. The staircase region SA2 is also included in the deep dig region DE1. Within the deep dig region DE1, nine wiring layers 34 and nine insulating layers 33 are processed collectively. Therefore, the staircase region SA2 is located below the staircase region SA1. More specifically, the staircase region SA2 includes the terrace TRs of the word lines WL23, WL20, and WL17 of the front staircase portion FS2. The staircase region SA2, including its depth region in the Y direction (not shown), also includes the terrace TRs of the word lines WL25 to WL17. Contact plugs CC are provided on the terrace TRs of the word lines WL23, WL20, and WL17. In the staircase region SA2, the terrace TRs of the word lines WL23, WL20, and WL17 are arranged in a staircase pattern of three steps descending to the right from the left side of the drawing.

[0098] The staircase region SA3 includes the back staircase portion RS2 of the multi-step processing region ME2. The staircase region SA3 is also included in the deep dig region DE3. Within the deep dig region DE3, 18 wiring layers 34 and 18 insulating layers 33 are processed collectively. Therefore, the staircase region SA3 is located lower than the staircase region SA2. In other words, the back staircase portion RS2 of the multi-step processing region ME2 is located lower than the front staircase portion FS2. More specifically, the staircase region SA3 includes the terraces TR of the word lines WL14, WL11, and WL8 of the back staircase portion RS2. The staircase region SA3, including the depth region in the Y direction (not shown), also includes the terraces TR of the word lines WL16 to WL8. Contact plugs CC are provided on the terraces TR of the word lines WL14, WL11, and WL8. In the staircase region SA3, the terraces TR of the word lines WL14, WL11, and WL8 are arranged in a staircase of three steps each, ascending to the right from the left side of the page.

[0099] The staircase region SA3 is provided in a protruding portion TP of the stacked body SB protruding in the Z direction. That is, the terraces TR included in the staircase region SA3 are provided in the protruding portion TP. For example, in the X direction, the left end of the protruding portion TP is formed as a back staircase portion RS2 by multi-stage processing in the multi-stage processing region ME2, and the other end is processed collectively by deep trench processing in the deep trench region DE2. As a result, the protruding portion TP is provided with a portion of the wiring layer 34 that is not continuous with the same wiring layer 34 provided in either the memory region MA1 or MA2 in the X direction (hereinafter referred to as an "isolated portion"). In the example shown in FIG. 11, the protruding portion TP includes 10 wiring layers 34 corresponding to the word lines WL8 to WL17. The protruding portion TP includes 12 wiring layers 34 corresponding to the word lines WL8 to WL19, including a depth region in the Y direction (not shown). Of these, the eleven wiring layers 34 corresponding to the word lines WL9 to WL19 each include an isolated portion of the wiring layer 34.

[0100] The staircase region SA4 includes the front staircase portion FS3 of the multi-step processing region ME3. The staircase region SA4 is also included in the deep dig regions DE2 and DE3. In the deep dig region DE2, nine wiring layers 34 and nine insulating layers 33 are processed together. In the deep dig region DE3, eighteen wiring layers 34 and eighteen insulating layers 33 are processed together. Therefore, the staircase region SA4 is located below the staircase region SA3. More specifically, the staircase region SA4 includes the word lines WL5 and WL2 of the front staircase portion FS3 and the terrace TR of the select gate line SGS. The staircase region SA4, including the depth region in the Y direction (not shown), also includes the terrace TR of the word lines WL7 to WL0 and the select gate line SGS. Contact plugs CC are provided on the terrace TR of the word lines WL5 and WL2 and the select gate line SGS. In the staircase region SA4, the terraces TR of the word lines WL5 and WL2 and the select gate line SGS are arranged in a staircase of three steps descending to the right from the left side of the paper to the right side of the paper.

[0101] Next, a cross section in the X direction along the member SLTe will be described.

[0102] As shown in FIG. 12, the member SLTe is divided in the X direction by division regions SR1 to SR3. A plurality of insulating layers 33 and a plurality of wiring layers 34 are stacked in the division regions SR. In the example shown in FIG. 12, a plurality of wiring layers 34 corresponding to the select gate lines SGS and the word lines WL0 to WL37 are provided in the division regions SR1 and SR3. A plurality of wiring layers 34 corresponding to the select gate lines SGS and the word lines WL0 to WL19 are provided in the division region SR2 corresponding to the protrusion TP. The wiring layers 34 of the same layer provided on both sides of the division region SR in the Y direction are connected to each other via the division region SR. In this embodiment, the division region SR2 is provided corresponding to the protrusion TP of the stacked body SB. As a result, the terraces TR of the word lines WL9, WL11, WL12, WL14, and WL15, which have the member SLTe provided between them at the protrusion TP and the bridge region BR, are connected to the bridge region BR via the division region SR2.

[0103] Next, an example of the cross-sectional structure in the XY plane of the wiring layer 34 corresponding to the word line WL11 in the contact region CR will be described with reference to Fig. 13. Fig. 13 is a cross-sectional view in the XY plane taken along line V6-V6 in Figs. 11 and 12. Fig. 13 shows the wiring layer 34 corresponding to the word line WL11 in the block BLK0. Note that, to simplify the description, word lines other than WL11 are omitted.

[0104] As shown in FIG. 13, for example, the wiring layer 34 corresponding to the word line WL11 includes a connection portion PB, a first portion P1, a second portion P2, and an isolated portion IP.

[0105] The connection portion PB corresponds to the bridge region BR and extends in the X direction.

[0106] The first portion P1 extends from the contact region CR to the memory region MA1 and is connected to the connection portion PB in the Y direction. The first portion P1 includes a portion provided in the memory region MA1. The first portion P1 is connected in the Y direction via the separation region SR1.

[0107] The second portion P2 extends from the contact region CR to the memory region MA2 and is connected to the connection portion PB in the Y direction. The second portion P2 includes a portion provided in the memory region MA2. The second portion P2 is connected in the Y direction via the separation region SR3.

[0108] The isolated portion IP is provided between the first portion P1 and the second portion P2 in the X direction and is connected to the connection portion PB in the Y direction. The terrace TR of the word line WL11 is provided in the isolated portion IP. On both sides of the isolated portion IP in the X direction, there are regions where the wiring layer 34 has been removed. As a result, the terrace TR provided in the isolated portion IP is not continuous with the first portion P1 and the second portion P2 in the X direction. The isolated portion IP can also be said to be a portion protruding in the Y direction from the connection portion PB in the XY plane. A separation region SR2 (i.e., a connection region of the wiring layer 34) is provided between the terrace TR of the word line WL11 and the connection portion PB. In other words, a portion of the isolated portion IP is separated in the Y direction by the member SLTe. In this case, the contact plug CC connected to the terrace TR can be electrically connected to the memory areas MA1 and MA2 via the separation region SR2 and the connection portion PB.

[0109] 1.9 Protrusion Layout Next, the layout of the protrusion TP will be described with reference to Fig. 14. Fig. 14 is a diagram showing a plan view and a cross section of the vicinity of the protrusion TP.

[0110] As shown in FIG. 14, the protrusion TP includes multiple wiring layers 34 corresponding to the word lines WL8 to WL19. The staircase region SA3 includes terraces TR for the word lines WL8 to WL16. A member SLTe is interposed between each of the terraces TR for the word lines WL8, WL9, WL11, WL12, WL14, and WL15 and the bridge region BR. The wiring layers 34 on which the terraces TR for the word lines WL8 and WL9 are provided extend toward the memory region MA1. In this state, a separation region SR2 is provided at the tip of the protrusion TP in the Z direction. More specifically, the separation region SR2 is provided so as to straddle in the X direction at least a portion of the wiring layer 34 corresponding to the word line WL19, which is the top layer in the protrusion TP. As a result, in the protrusion TP, the isolated portion of the wiring layer 34, which is interposed between the member SLTe and the bridge region BR, is connected to the bridge region BR via the separation region SR2. That is, the terraces TR of the word lines WL11, WL12, WL14, and WL15 are connected to the bridge region BR via the separation region SR2. The separation region SR2 does not have to be provided at the tip of the protrusion TP. The separation region SR2 may be located within the protrusion TP at a position where the terraces TR of the word lines WL11, WL12, WL14, and WL15 can be connected to the bridge region BR via the separation region SR2. For example, the separation region SR2 may be located at a position that straddles at least the terraces TR of the word lines WL16 and WL15 in the X direction.

[0111] 2. Manufacturing method of the pull-out area Next, an example of a manufacturing method of the lead-out region HA will be described with reference to Figs. 15 to 25. Figs. 15, 18, 20, 22, and 24 are plan views of the lead-out region HA and its neighboring region, illustrating manufacturing steps of the lead-out region HA. Fig. 16 is a cross-sectional view taken along line V3-V3 in Fig. 15. Fig. 17 is a cross-sectional view taken along line V4-V4 in Fig. 15. Fig. 19 is a cross-sectional view taken along line V4-V4 in Fig. 18. Fig. 21 is a cross-sectional view taken along line V4-V4 in Fig. 20. Fig. 23 is a cross-sectional view taken along line V4-V4 in Fig. 22. Fig. 25 is a cross-sectional view taken along line V3-V3 in Fig. 24.

[0112] In this embodiment, a method of forming a plurality of wiring layers 34 corresponding to the word lines WL and the select gate lines SGD and SGS will be described, in which, for example, a structure corresponding to each wiring layer 34 is formed using a sacrificial film 60, and then the sacrificial film 60 is replaced with a conductive material to form the wiring layer 34 (hereinafter referred to as "replace").

[0113] As shown in FIGS. 16 and 17, first, an insulating layer 50 is formed on the semiconductor layer 32a. Then, a semiconductor layer 32c is formed on the insulating layer 50. Then, 40 insulating layers 33 and 40 sacrificial films 60 are alternately stacked on the semiconductor layer 32c. In a process described below, the 40 sacrificial films 60 are replaced with 40 wiring layers 34 that function, from the bottom up, as the select gate lines SGS, word lines WL0 to WL37, and select gate lines SGD. For example, silicon nitride is used for the sacrificial films 60. As shown in FIGS. 15 to 17, first, from this state, the sacrificial films 60 and the underlying insulating layers 33 corresponding to the select gate lines SGD are removed in the contact region CR and the bridge region BR. Next, in the contact region CR, a resist mask 70 is used to form three rows (three steps) of stairs in the Y direction so that blocks BLK0 and BLK1 face each other. 16, two layers of sacrificial film 60 corresponding to word lines WL37-WL36 and the insulating layers 33 below each of them are processed. After the three rows of steps are formed, the resist mask 70 is removed. Note that the processing of the steps in the Y direction may be performed after the processing of the steps in the X direction.

[0114] As shown in FIGS. 18 and 19, multistage processing regions ME1 to ME3 are formed. More specifically, first, a resist mask 70 is formed to expose the central portions of the multistage processing regions ME1 to ME3. Next, the three sacrificial films 60 and the three insulating layers 33 are processed to form recesses corresponding to three steps. Next, slimming of the resist mask 70 and processing of the three sacrificial films 60 and the three insulating layers 33 are repeated to form the multistage processing regions ME1 to ME3, spreading out in all directions from the central portion. In each multistage processing region ME, a front staircase portion FS and a back staircase portion RS are formed. In the example shown in FIG. 19, in the cross section of the multistage processing region ME along line V4-V4, steps of the sacrificial film 60 corresponding to each of the word lines WL26, WL29, and WL32 are formed. After processing the multistage processing region ME, the resist mask 70 is removed.

[0115] As shown in FIGS. 20 and 21, deep dig regions DE1 and DE2 are formed. More specifically, a resist mask 70 corresponding to the deep dig regions DE1 and DE2 is first formed. Deep dig region DE1 includes a front staircase portion FS2 of the multi-stage processing region ME2. Deep dig region DE2 includes a front staircase portion FS3 of the multi-stage processing region ME3. In the deep dig regions DE1 and DE2, for example, nine layers of sacrificial film 60 and nine layers of insulating layer 33 are processed simultaneously. In the example shown in FIG. 21, in the cross section of deep dig regions DE1 and DE2 along line V4-V4, steps of the sacrificial film 60 corresponding to each of word lines WL23, WL20, and WL17 are formed. After processing the deep dig regions DE1 and DE2, the resist mask 70 is removed.

[0116] As shown in FIGS. 22 and 23, a deep dig region DE3 is formed. More specifically, a resist mask 70 corresponding to the deep dig region DE3 is first formed. The deep dig region DE3 includes a back staircase portion RS2 of the multi-stage processing region ME2 and a front staircase portion FS3 (deep dig region DE2) of the multi-stage processing region ME3. In the deep dig region DE3, for example, 18 layers of sacrificial film 60 and 18 layers of insulating layer 33 are processed all at once. In the example shown in FIG. 23, in the cross section of the deep dig region DE3 along line V4-V4, a protrusion portion TP including steps of the sacrificial film 60 corresponding to each of the word lines WL14, WL11, and WL8, as well as steps of the sacrificial film 60 corresponding to each of the word lines WL5 and WL2 and the select gate line SGS, are formed. After processing the deep dig region DE3, the resist mask 70 is removed.

[0117] As shown in FIGS. 24 and 25, in the memory regions MA1 and MA2, after forming the memory pillars MP, slits corresponding to the members SLTo and SLTi are formed. After replacing the semiconductor layer 32b, the sacrificial film 60 is removed from the side surfaces of the slits corresponding to the members SLTo and SLTi by wet etching. For example, if the sacrificial film 60 is silicon nitride, wet etching using hot phosphoric acid is performed. Next, the wiring layer 34 is formed. After the members SLTo and SLTi are buried with an insulator 36, contact plugs CC are formed, for example, as shown in FIG. 10. This forms the lead-out region HA.

[0118] 3. Effects of this embodiment With the configuration according to this embodiment, the semiconductor memory device can suppress an increase in chip area. This effect will be described in detail.

[0119] For example, in a three-dimensional stacked NAND flash memory, replacement is used as a method for forming multiple wiring layers 34 corresponding to multiple word lines WL and select gate lines SGD and SGS. For replacement, a member SLTe extending in the X direction may be provided within a block BLK so as to separate at least a portion of the wiring layer 34 extending in the X direction in the Y direction. Wiring layers 34 adjacent to each other in the Y direction via the member SLTe are connected to each other via a separation region SR of the member SLTe. Furthermore, for example, in one block BLK, a lead-out region HA may be provided between two memory regions MA1 and MA2 provided in the X direction, where the terraces TR of each wiring layer 34 are connected to contact plugs CC. Within the lead-out region HA, the multiple wiring layers 34 are processed into a staircase shape. This processing forms a protruding portion TP of the stacked body SB protruding in the Z direction. For example, when a multi-row terrace TR is provided on the protrusion TP, if the terrace TR and the connection portion PB (bridge region BR) are separated by a member SLTe, the contact plug CC in the protrusion TP of the stacked body SB, which has the member SLTe interposed between the corresponding terrace TR and the connection portion PB, cannot be electrically connected to the wiring layer 34 provided in the memory regions MA1 and MA2.

[0120] In contrast, with the configuration according to this embodiment, it is possible to provide a separation region SR of the member SLTe corresponding to the protrusion TP. As a result, even when the member SLTe is interposed between the terrace TR provided on the protrusion TP and the connection portion PB (bridge region BR), the terrace TR can be connected to the connection portion PB via the separation region SR of the member SLTe. This allows a multi-row staircase to be formed in the protrusion TP as well. This makes it possible to suppress an increase in the area of ​​the lead-out region HA. As a result, it is possible to suppress an increase in the chip area of ​​the semiconductor memory device 1.

[0121] Furthermore, since the length of the lead-out region HA in the X direction can be shortened, the length of the wiring layer 34 extending in the X direction can be shortened. This, for example, shortens the stabilization time of the voltage applied to the word line WL, thereby improving the processing performance of the semiconductor memory device 1.

[0122] 4. Modifications, etc. The semiconductor memory device according to the above embodiment includes a first stack (SB) in which a plurality of insulating layers (33) and a plurality of wiring layers (34) including a first wiring layer (WL11) and a second wiring layer (WL12) provided above the first wiring layer are alternately stacked one layer at a time in a first direction (Z direction); a plurality of memory pillars (MP) extending in the first direction and each passing through the first stack in a first region (MA1) and a second region (MA2); a plurality of contact plugs (CC) extending in the first direction and provided in a third region (HA) located between the first region and the second region in a second direction (X direction) intersecting the first direction, the contact plugs being respectively connected to a plurality of terraces included in the plurality of wiring layers; and a first member (SLTe) extending in the second direction, dividing a portion of each of the plurality of wiring layers in the third region in a third direction (Y direction) intersecting the first direction and the second direction, and being divided into a plurality of pieces in the second direction. Each of the first wiring layer and the second wiring layer includes a first portion (P1) at least a portion of which is included in the first region, a second portion (P2) at least a portion of which is included in the second region, a connection portion (PB) connecting the first portion and the second portion and extending in the second direction, and a third portion (IP) provided between the first portion and the second portion in the second direction and connected to the connection portion in the third direction. A portion of the third portion included in the first wiring layer is divided in the third direction by a first member. The multiple terraces include a first terrace provided in the third portion of the first wiring layer and a second terrace provided in the third portion of the second wiring layer. The first terrace and the second terrace are arranged side by side in the third direction.

[0123] The configuration according to the above embodiment can provide a semiconductor memory device that can suppress an increase in chip area.

[0124] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0125] 4.1 First Modification For example, as shown in Fig. 26 and Fig. 27, the members SLTo and SLTe may include a conductor. Fig. 26 is a plan view of a lead-out region and a memory region nearby the lead-out region in a semiconductor memory device. Fig. 27 is a cross-sectional view taken along line V3-V3 in Fig. 26.

[0126] 26 and 27, the members SLTo and SLTe include conductors LI and spacers SP. In this case, the members SLTo and SLTe formed collectively have the same layer structure, and corresponding layers include the same material.

[0127] The conductor LI is a conductor provided in the members SLTo and SLTe and extending in the XZ plane. The spacer SP is an insulator provided on the side surface of the conductor LI. In other words, the conductor LI is surrounded by the spacer SP in a planar view. In the example shown in FIGS. 26 and 27, the spacer SP is removed from the bottom surfaces of the members SLTo and SLTe, and the conductor LI is electrically connected to the semiconductor layer 32 (source line SL). The conductor LI contains, for example, tungsten and titanium nitride, or silicon. The spacer SP contains, for example, silicon oxide. Note that the spacer SP does not have to be removed from the bottom surfaces of the members SLTo and SLTe. That is, the conductor LI does not have to be electrically connected to the semiconductor layer 32.

[0128] In the above embodiment, "connected" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0129] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0130] 1...semiconductor memory device, 10...array chip, 11...memory cell array, 20...circuit chip, 21...sequencer, 22...voltage generation circuit, 23...row decoder, 24...sense amplifier, 31...insulating layer, 32, 32a to 32c...semiconductor layer, 33, 35, 50...insulating layer, 34, 39...wiring layer, 36, 37...insulator, 38...conductor, 40...core film, 41...semiconductor film, 42...laminated film, 43...tunnel insulating film, 44...charge storage film, 45...block insulating film, 60...sacrificial film, 70...resist mask, BLK , BLK0 to BLK3...block, DE1 to DE3...deep dig area, FS1 to FS3...front staircase part, MA1, MA2...memory area, MC0 to MC37...memory cell transistor, ME1 to ME3...multi-stage processing area, RS1, RS2, RS3...back staircase part, SA1 to SA4...staircase area, SB...stacked body, SGD, SGD0 to SGD5...select gate line, SR1 to SR3...separation area, ST1, ST2...select transistor, SU, SU0 to SU5...string unit, WL, WL0 to WL37...word line

Claims

1. a first laminate in which a plurality of insulating layers and a plurality of wiring layers including a first wiring layer and a second wiring layer provided above the first wiring layer are alternately laminated layer by layer in a first direction; a plurality of memory pillars extending in the first direction and each passing through the first stack in a first region and a second region; a plurality of contact plugs extending in the first direction and provided in a third region located between the first region and the second region in a second direction intersecting the first direction, the contact plugs being respectively connected to a plurality of terraces included in the plurality of wiring layers; a first member extending in the second direction, dividing a part of each of the plurality of wiring layers in the third region in a third direction intersecting the first direction and the second direction, and dividing the first member into a plurality of parts in the second direction; Equipped with Each of the first wiring layer and the second wiring layer is a first portion at least a portion of which is included in the first region; a second portion at least a portion of which is included in the second region; a connection portion that connects the first portion and the second portion and extends in the second direction; a third portion provided between the first portion and the second portion in the second direction and connected to the connecting portion in the third direction; Including, a part of the third portion included in the first wiring layer is divided in the third direction by the first member, the plurality of terraces include a first terrace provided in the third portion of the first wiring layer and a second terrace provided in the third portion of the second wiring layer, the first terrace and the second terrace are arranged side by side in the third direction. Semiconductor memory device.

2. the first stack includes a protruding portion protruding in the first direction in the third region, the third portion of the first wiring layer and the third portion of the second wiring layer are included in the protruding portion.

2. The semiconductor memory device according to claim 1.

3. a divided portion formed by dividing the first member is provided on the protruding portion; 3. The semiconductor memory device according to claim 2.

4. the first member extends in the second direction between the first terrace and the connection portion of the first wiring layer in the third direction; 2. The semiconductor memory device according to claim 1.

5. a first laminate in which a plurality of insulating layers and a plurality of wiring layers are alternately laminated one by one in a first direction; a plurality of memory pillars extending in the first direction and each passing through the first stack in a first region and a second region; a plurality of contact plugs extending in the first direction and provided in a third region located between the first region and the second region in a second direction intersecting the first direction, the contact plugs being connected to the plurality of wiring layers, respectively; a first member extending in the second direction, dividing each of the plurality of wiring layers in the first region and the second region in a third direction intersecting the first direction and the second direction, dividing a portion of each of the plurality of wiring layers in the third region in the third direction, and dividing the plurality of pieces in the second direction; Equipped with the first stack includes a protruding portion protruding in the first direction in the third region, The protrusion has a divided portion where the first member is divided. Semiconductor memory device.

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