Semiconductor system and method for manufacturing the same

Abstract

To provide a semiconductor system in which resin is prevented from protruding from the periphery of a semiconductor chip, and which has a high degree of freedom in mounting.SOLUTION: In a semiconductor system 1, a substrate 50 and a semiconductor chip 20 are electrically connected face down via an electrode portion 16, and the space between the substrate 50 and the semiconductor chip 20 is filled with a resin portion 14. When the portion between the substrate 50 and the semiconductor chip 20, including the electrode portion 16 and the resin portion 14, is defined as a connection portion 10, the external dimensions of the connection portion 10 in a cross section parallel to the substrate 50 are substantially the same for the portion contacting the chip connection surface 22 of the semiconductor chip 20 and the portion contacting the substrate 50.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor systems and methods for manufacturing semiconductor systems. [Background technology]

[0002] Conventionally, there have been known semiconductor systems including a semiconductor chip and an interposer, in which the semiconductor chip and the interposer are connected via solder and an underfill material is filled in the areas between the semiconductor chip and the interposer other than the solder. For example, Patent Document 1 discloses a semiconductor device in which a substrate and a semiconductor component are connected via connection bumps and an underfill material is injected into the gap between the substrate and the semiconductor component. The underfill material can be a liquid capillary flow underfill material, a nonconductive film (NCF), a nonconductive paste (NCP), or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. WO 2023 / 203765 ​​A1 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor system using the underfill material as described above has a problem in that the underfill material overflows from the periphery of the semiconductor chip.

[0005] Therefore, an object of the present invention is to provide a semiconductor system and a method for manufacturing the semiconductor system in which the protrusion of resin such as an underfill material from the periphery of a semiconductor chip is suppressed, thereby allowing for a high degree of freedom in packaging. [Means for solving the problem]

[0006] In the semiconductor system of the present invention, a substrate and a semiconductor chip are electrically connected face down via an electrode portion, and the space between the substrate and the semiconductor chip is filled with a resin portion. When the portion between the substrate and the semiconductor chip, including the electrode portion and the resin portion, is defined as a connection portion, the external dimensions of the connection portion in a cross section parallel to the substrate are substantially the same for the portion that contacts the electrode surface of the semiconductor chip and the portion that contacts the substrate.

[0007] The method for manufacturing a semiconductor system of the present invention is a method for manufacturing a semiconductor system comprising a substrate, a semiconductor chip, and a connection portion having an electrode portion and a resin portion arranged between the substrate and the semiconductor chip, and includes a chip component manufacturing process for manufacturing a chip component having the semiconductor chip and the connection portion, and a face-down mounting process for mounting the chip component face-down on the substrate, wherein the chip component manufacturing process includes a process for forming the resin portion and the electrode portion on a portion that will become the chip connection surface of the semiconductor chip, and the face-down mounting process includes a process for joining the resin portion of the connection portion and the substrate by hybrid bonding. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor system and a method for manufacturing the semiconductor system in which resin is prevented from spilling out from the periphery of a semiconductor chip, and which allows for a high degree of freedom in packaging. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor system according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a diagram for explaining the manufacturing process of the chip component. [Figure 2B] FIG. 2B is a diagram for explaining the manufacturing process of the chip component. [Figure 2C] FIG. 2C is a diagram for explaining the manufacturing process of the chip component. [Figure 3]FIG. 3 is a diagram showing how the chip component and the substrate are connected. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor system according to a second embodiment of the present invention. [Figure 5A] FIG. 5A is a cross-sectional view of a semiconductor package. [Figure 5B] FIG. 5B is a plan view of the semiconductor package. [Figure 6A] FIG. 6A is a cross-sectional view of a conventional semiconductor package. [Figure 6B] FIG. 6B is a plan view of a conventional semiconductor package. DETAILED DESCRIPTION OF THE INVENTION

[0010] (First embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a semiconductor system 1 according to a first embodiment of the present invention will be described.

[0011] (Semiconductor Systems) Fig. 1 is a cross-sectional view of a semiconductor system 1 according to a first embodiment of the present invention. As shown in Fig. 1, the semiconductor system 1 includes a semiconductor chip 20 and a substrate 50. The semiconductor chip 20 is electrically connected to the substrate 50 via a connection portion 10. A component formed by combining the semiconductor chip 20 and the connection portion 10 is called a chip component 30.

[0012] (Semiconductor chips and substrates) The semiconductor chip 20 is a chip on which a semiconductor is formed on a silicon wafer or the like. The substrate 50 is a component on which the semiconductor chip 20 is mounted. The substrate 50 is made of an insulating material and metal wiring. For example, semiconductor elements such as transistors are not formed on the substrate 50. The substrate 50 functions, for example, as an interposer. The area of ​​the surface of the substrate 50 on which the semiconductor chip 20 is mounted is larger than the area of ​​the surface of the semiconductor chip 20 facing the substrate 50. Two or more semiconductor chips 20 are usually mounted on the substrate 50. When two or more semiconductor chips 20 are mounted on the substrate 50, the semiconductor chips 20 may be electrically connected via metal wiring formed on the substrate 50.

[0013] (Semiconductor package) As an example of how the semiconductor system 1 of this embodiment is used, a semiconductor package 100 incorporating the semiconductor system 1 will be described. FIG. 5A is a cross-sectional view of the semiconductor package 100. In the example shown in FIG. 5A, two chip components 30 are mounted on a substrate 50. The two chip components 30 are electrically connected via connection pads 56 and a wiring layer 58 formed on the substrate 50. Note that the wiring layer 58 shown in FIG. 5A is an example and does not represent the actual layout of the wiring layer 58. Furthermore, the number of chip components 30 mounted on the substrate 50 is not limited to two. The number of chip components 30 mounted on the substrate 50 can be any appropriate number equal to or greater than one.

[0014] The semiconductor system 1 is connected to the package substrate 110 via a first solder portion 112. The first solder portion 112 may be, for example, a solder ball (solder bump). A second solder portion 114 is formed on the surface of the package substrate 110 opposite to the surface on which the first solder portion 112 is formed. The second solder portion 114 is used to electrically connect the semiconductor package 100 to other components. The second solder portion 114 may be, for example, a solder ball (solder bump). The semiconductor system 1 will be described below in order. Note that the reference numerals shown in FIG. 5A that have not yet been described will also be described in order with reference to other drawings.

[0015] (substrate) 1, the substrate 50 will be described in more detail. As shown in FIG. 1, the substrate 50 includes an insulating portion 54, a connection pad 56, and a wiring layer 58.

[0016] The insulating portion 54 is a portion formed from an insulating material. The type of insulating material is not particularly limited. Examples of insulating materials include polyimide, polyamide-imide, benzocyclobutene (BCB), and polybenzoxazole (PBO). The insulating portion 54 of this embodiment is formed from polyimide.

[0017] The wiring layer 58 refers to conductive wiring formed inside the substrate 50 or on the surface of the substrate 50. The wiring layer 58 is depicted in a simplified form in FIG. 1. An example of the material for the wiring layer 58 is copper. A layer of titanium or nickel may be formed between the copper and the insulating material to improve adhesion between the copper and the insulating material and to prevent copper from diffusing into the insulating material.

[0018] The surface of the insulating section 54 on which the semiconductor chip 20 is mounted is called the substrate connection surface 52. Connection pads 56 are formed on the substrate connection surface 52. The connection pads 56 are contact points on the substrate 50 side when electrically connecting the semiconductor chip 20 or the like to the substrate 50. The connection pads 56 are provided at positions corresponding to the positions of the electrode sections 16 of the connection section 10, which will be described later. Since the positions of the connection pads 56 correspond to the positions of the electrode sections 16, when the semiconductor chip 20 is mounted on the substrate 50 via the connection section 10, the connection pads 56 and the electrode sections 16 of the connection section 10 are connected to each other without any waste.

[0019] The material of the connection pads 56 can be the same as the material of the wiring layer 58. The material of the wiring layer 58 is, for example, copper. However, the material of the connection pads 56 may be different from the material of the wiring layer 58.

[0020] In addition, in the width direction 172, insulating portions 54 are exposed on the substrate connecting surface 52 between adjacent connection pads 56. As shown in Fig. 1, connection pads 56 or insulating portions 54 are formed on the portions of the substrate connecting surface 52 that contact the connection portions 10.

[0021] (Connection) Next, the connection portion 10 will be described. The connection portion 10 is a portion that connects the semiconductor chip 20 to the substrate 50. The connection portion 10 includes a resin portion 14 and an electrode portion 16. When the semiconductor chip 20 is mounted on the substrate 50, the surface of the semiconductor chip 20 that faces the substrate 50 is called the chip connection surface 22. The chip connection surface 22 is also the electrode surface of the semiconductor chip 20. The semiconductor chip 20 contacts the connection portion 10 at the chip connection surface 22.

[0022] The connection portion 10 fills the space from the chip connection surface 22 to the substrate connection surface 52. An arrow 171 shown in FIG. 1 indicates a direction perpendicular to the chip connection surface 22. The direction indicated by the arrow 171 is called the connection direction. The direction indicated by the arrow 172 is a direction perpendicular to the direction indicated by the arrow 171. The direction indicated by the arrow 172 is called the width direction (first direction).

[0023] (Shape of resin part) The resin portion 14 is a portion of the connection portion 10 that is made of insulating resin. The resin portion 14 is formed so as to define an electrode portion 16, which will be described later. In the cross section shown in FIG. 1, i.e., in a cross section on a plane parallel to the width direction 172 and the connection direction 171, the resin portions 14 are formed at predetermined intervals in the width direction 172. In the cross section shown in FIG. 1, the cross-sectional shape of one resin portion 14 is substantially rectangular. The rectangle includes a square. One resin portion 14 is continuous in the connection direction 171 from the chip connection surface 22 to the substrate connection surface 52. When the semiconductor system 1 is viewed in the connection direction 171, a plurality of electrode portions 16 are arranged, for example, in a matrix. The cross-sectional view shown in Fig. 1 shows a cross section of, for example, one column or row included in the matrix. Furthermore, when the semiconductor system 1 is viewed in the connection direction 171, the resin portion 14 is formed so as to surround the plurality of electrode portions 16. On the other hand, when the semiconductor system 1 is viewed in the connection direction 171, the electrode portions 16 are observed to have, for example, a circular or polygonal shape.

[0024] 1, the length of one resin part 14 in width direction 172 at chip connection surface 22 is indicated by length 80. For the same resin part 14, the length in width direction 172 at an intermediate position in connection direction 171 is indicated by length 81. Lengths 91 and 92 from the intermediate position to each surface shown in FIG. 1 are equal and are half the length 90 of resin part 14 in connection direction 171.

[0025] Furthermore, for the same resin part 14, the length in width direction 172 at board connection surface 52 is indicated by length 82. In resin part 14, the surface that contacts board connection surface 52 is called connection surface 12. Length 82 can also be said to be the length in width direction 172 at connection surface 12 of one target resin part 14.

[0026] Lengths 80, 81, and 82 are the same length. Here, "same" does not mean "strictly the same." "Same" means "substantially the same," that is, "there is no substantial difference." "Same length" means, for example, that lengths 81 and 82 are within a range of 95% to 105% of length 80.

[0027] Preferably, the length of one resin part 14 in width direction 172 is approximately constant in connection direction 171. Here, approximately constant means, for example, that the length of one resin part 14 in width direction 172 at any position in connection direction 171 is in the range of 95% to 105% of length 80.

[0028] (Resin material) The material of the resin portion 14 is, for example, polyimide, polyamideimide, benzocyclobutene, polybenzoxazole, etc. The material of the resin portion 14 is preferably the same as the material of the insulating portion 54. As will be explained later, when the material of the resin portion 14 and the material of the insulating portion 54 are the same, hybrid bonding is more likely to occur between the resin portion 14 and the insulating portion 54. In this embodiment, as described above, the material of the insulating portion 54 is polyimide. Therefore, the material of the resin portion 14 is also polyimide.

[0029] (Electrode shape) Next, the electrode portion 16 will be described. The electrode portion 16 is a portion of the connection portion 10 that electrically connects the semiconductor chip 20 and the substrate 50. The electrode portion 16 is formed between adjacent resin portions 14. In other words, the electrode portion 16 is formed in the region between the resin portions 14 that are formed at a predetermined interval in the width direction 172. The electrode portion 16 is also formed so as to fill the region between the resin portions 14.

[0030] The cross-sectional shape of the region between adjacent resin portions 14 is approximately rectangular. One electrode portion 16 is continuous in the connection direction 171 from the chip connection surface 22 to the substrate connection surface 52. Therefore, the cross-sectional shape of one electrode portion 16 is approximately rectangular. In other words, the shape of the electrode portion 16 corresponds to the gap formed by two adjacent resin portions 14.

[0031] 1 , for one electrode portion 16, the length in width direction 172 at chip connection surface 22 is indicated by length 83. For the same electrode portion 16, the length in width direction 172 at the middle position in connection direction 171 is indicated by length 84. Furthermore, for the same electrode portion 16, the length in width direction 172 at substrate connection surface 52 is indicated by length 85.

[0032] Lengths 83, 84, and 85 are the same length. Here, "same" does not mean "strictly the same." "Same" means "substantially the same," that is, "there is no substantial difference." "Same length" means, for example, that lengths 84 and 85 are within a range of 95% to 105% of length 83.

[0033] Preferably, the length of one electrode portion 16 in width direction 172 is approximately constant in connection direction 171. Here, approximately constant means, for example, that the length of one electrode portion 16 in width direction 172 at any position in connection direction 171 is in the range of 95% to 105% of length 83.

[0034] (Electrode material) The electrode portion 16 includes a first electrode portion 17 and a second electrode portion 18. The first electrode portion 17 is, for example, a metal seed layer 17 described later. The second electrode portion 18 is, for example, a plated electrode layer 18 described later. The first electrode portion 17 and the second electrode portion 18 are stacked in a connection direction 171. In this embodiment, the first electrode portion 17 further covers the periphery of the second electrode portion 18. The first electrode portion 17 is provided so as to contact the chip connection surface 22, and the second electrode portion 18 is provided so as to contact the connection pad 56. In other words, the first electrode portion 17 and the second electrode portion 18 are stacked in this order from the chip connection surface 22 to the substrate connection surface 52.

[0035] The first electrode portion 17 and the second electrode portion 18 are made of different materials. The material of the first electrode portion 17 can be, for example, copper. This allows the first electrode portion 17 to be well connected to the wiring, electrodes, etc. provided on the semiconductor chip 20.

[0036] The material of the second electrode portion 18 can be, for example, solder, which makes it easy to connect the connection pads 56 provided on the board connection surface 52 to the second electrode portion 18.

[0037] The above-mentioned materials for the first electrode portion 17 and the second electrode portion 18 are examples. The materials for the first electrode portion 17 and the second electrode portion 18 can be changed as appropriate. For example, the material for the second electrode portion 18 can be the same as the material for the connection pad 56. As will be explained later, when hybrid bonding is performed between the chip component 30 and the substrate 50, for example, hybrid bonding between the second electrode portion 18 and the connection pad 56 can be facilitated by making the material for the second electrode portion 18 the same as the material for the connection pad 56.

[0038] (Cross-sectional shape of connection part) The cross-sectional shape of the connection part 10 will be described. As described above, each resin part 14 in the cross section shown in FIG. 1 is formed to have a substantially rectangular cross-sectional shape. Furthermore, end resin parts 15 are formed at positions corresponding to both chip end faces 24 in the width direction 172 of the semiconductor chip 20. The electrode parts 16 are formed in the regions between adjacent resin parts 14. Therefore, the cross-sectional shape of the connection part 10 is substantially rectangular.

[0039] (Width of connection part) The length in width direction 172 of connection portion 10, i.e., the width of connection portion 10, will now be described. The length in width direction 172 of connection portion 10 at chip connection surface 22 is indicated by length 74. The length in width direction 172 of connection portion 10 at the middle position in connection direction 171 is indicated by length 76. The length in width direction 172 of connection portion 10 at substrate connection surface 52 is indicated by length 78.

[0040] Lengths 74, 76, and 78 are the same length. Here, "same" does not mean "strictly the same." "Same" means "substantially the same," that is, "there is no substantial difference." "Same length" means, for example, that lengths 76 and 78 are within a range of 95% to 105% of length 74.

[0041] Preferably, the length of the connection portion 10 in the width direction 172 is approximately constant in the connection direction 171. Here, approximately constant means, for example, that the length of the connection portion 10 in the width direction 172 at any position in the connection direction 171 is in the range of 95% to 105% of the length 74.

[0042] (Connection end face) Next, the positions of the chip end face 24, which is the end face in the width direction 172 of the semiconductor chip 20, and the connection portion end face 11, which is the end face in the width direction 172 of the connection portion 10, will be described. Line 70 is a line indicating the position of the chip end face 24, i.e., the chip end face position. Line 72 is a line indicating the position of the connection portion end face 11, i.e., the connection portion end face position.

[0043] In FIG. 1, line 70 and line 72 are located on the same straight line. This indicates that chip end face 24 and connection end face 11 are on the same straight line. In other words, when chip component 30 is viewed in the direction of arrow 150, connection end face 11 is not observed. Note that arrow 150 is parallel to connection direction 171 and indicates the direction from semiconductor chip 20 toward substrate 50. Viewing in the direction of arrow 150 is called a top view.

[0044] In the semiconductor system 1 of this embodiment, the chip end face position 70 and the connection portion end face position 72 are at the same position in the width direction 172. Here, "same" does not mean "strictly the same." "Same" means "substantially the same," that is, "there is no substantial difference." "There is no substantial difference" means, for example, the following.

[0045] Arrows 152 and 153 shown in FIG. 1 both indicate directions parallel to width direction 172. The direction indicated by arrow 152 is called the outward direction. The direction indicated by arrow 153 is called the inward direction. Line 721 indicates a position that is a length 96 away from chip end face position 70 in the outward direction 152. The position indicated by line 721 is called the outermost position. Line 722 indicates a position that is a length 97 away from chip end face position 70 in the inward direction 153. The position indicated by line 722 is called the innermost position 722. The connection portion end face position 72 is located within the range from the outermost position 721 to the innermost position 722 in the width direction 172.

[0046] (extension width) The specific positions of the outermost position 721 and the innermost position 722 will be described. First, the outermost position 721 will be described. Length 94 in FIG. 1 indicates the length in the width direction 172 of the semiconductor chip 20. Length 96 defining the outermost position 721 is 10 μm. Preferably, length 96 is 5 μm.

[0047] Length 94 is called the chip width. Length 96 is called the protrusion width (first allowable width). In the semiconductor system 1 of this embodiment, protrusion width 96 is 10 μm. Preferably, protrusion width 96 is 5 μm.

[0048] (Fit width) Next, the innermost position 722 will be described. The length 97 that defines the innermost position 722 is 10 μm. Preferably, the length 97 is 5 μm.

[0049] The length 97 is called the fitting width (second allowable width). In the semiconductor system 1 of this embodiment, the fitting width 97 is 10 μm. Preferably, the fitting width 97 is 5 μm. By doing so, when mounting a plurality of chip components 30 on the substrate 50, the semiconductor chips 20 can be mounted in close proximity, increasing the degree of freedom in mounting. In other words, when the shortest distance between adjacent chip components 30 (semiconductor chips 20 and connecting portions 10) is the same, the semiconductor chips 20 can be mounted at a higher density.

[0050] When the connection portion end face position 72 is located between the outermost position 721 and the innermost position 722 in the width direction 172, it is said that the chip end face position 70 and the connection portion end face position 72 are at the same position in the width direction 172, or that there is no substantial difference between their positions. In other words, the external dimensions of the cross section of the connection portion 10, from the surface in contact with the semiconductor chip 20 to the surface in contact with the substrate 50, are the same as the external dimensions of the electrode surface of the semiconductor chip 20, i.e., the chip connection surface 22, in the cross section.

[0051] The above explanations have been given taking the length in the width direction 172 as an example. Here, the direction perpendicular to both the width direction 172 and the connection direction 171 is defined as the depth direction (second direction). The above explanations also apply to the depth direction.

[0052] As described above, in the semiconductor system 1 of this embodiment, the external dimensions of the connection portion 10 in a cross section parallel to the substrate 50 are substantially the same at the portion in contact with the electrode surface of the semiconductor chip 20 and the portion in contact with the substrate. It is preferable that the external dimensions of the connection portion 10 are substantially the same from the portion in contact with the electrode surface of the semiconductor chip 20 to the portion in contact with the substrate 50. It is preferable that the external dimensions of the connection portion 10 are within a range of ±10 μm.

[0053] (Rectangularity of the cross section of the connection part 10 shown in FIG. 1) The rectangularity of the connection part 10 in the cross section shown in FIG. 1 , i.e., in a cross section perpendicular to the substrate connection surface 52, will be described. Here, rectangularity means (area inside the outline / area of ​​the circumscribed rectangle of the outline). To explain the rectangularity of the connection part 10 of the present disclosure in more detail, the rectangularity is calculated by dividing the area formed by the outline of the connection part 10 in the cross section of the connection part 10 by the area of ​​the smallest rectangle circumscribing the outline of the connection part 10. Here, the outline of the connection part 10 refers to the outline of the region indicated by the length 90 in the connection direction 171 and the lengths 74, 76, and 78 in the width direction 172 in the cross section shown in FIG. 1 . For example, the rectangularity is calculated based on a cross section of the connection part 10 perpendicular to the substrate connection surface 52 and passing through the center of the chip component 30 in a top view. The rectangularity of the connection part 10 of this embodiment in the cross section of the connection part 10 is 0.95 or more. When the rectangularity of the vertical cross section of the connection part 10 is 0.95 or more, it becomes possible to mount a plurality of semiconductor chips 20 in close proximity.

[0054] In the case of the method using an underfill material, the resin overflows significantly around the chip due to the formation of a fillet (see Figure 6A below). The area of ​​the circumscribed rectangle of the outline described above increases due to the overflow caused by the fillet, making it difficult to increase the rectangularity of the cross section of the connection. In the case of the method using an underfill material, the cross section perpendicular to the connection surface between the board and the resin section may be depicted as a rectangle in the drawings, but as mentioned above, the rectangularity is actually low, less than 0.9.

[0055] Furthermore, even when using the NCP or NCF method, because the uncured resin is pressed in, the resin is squeezed between the bump electrodes of the semiconductor chip and the electrodes of the interposer and is extruded to the surrounding area, causing the extruded resin to bulge and protrude significantly around the chip. Therefore, even when using the NCP or NCF method, it is difficult to increase the rectangularity of the cross section of the connection part. When using the NCP or NCF method, the cross section perpendicular to the connection surface between the substrate and the resin part may be depicted as a rectangle in the drawing, but as mentioned above, the rectangularity is actually low, less than 0.9.

[0056] (Traditional semiconductor system) Here, a semiconductor package 200 incorporating a conventional semiconductor system 201 will be described. Fig. 6A is a diagram showing a cross section of the conventional semiconductor package 200. Fig. 6B is a plan view of the semiconductor package 200 of Fig. 6A as seen from above, as seen in the direction of arrow 150. The arrows shown in Fig. 6A indicate the same directions as the arrows described in Fig. 1. Fig. 6B shows an arrow pointing in a depth direction 173 (second direction) in addition to an arrow pointing in a width direction 172 (first direction).

[0057] As shown in FIG. 6A, in a conventional semiconductor system 201, a semiconductor chip 20 and a substrate 50 are connected via solder 216. Furthermore, a resin filler 214 is disposed in areas where there is no solder 216, such as between the semiconductor chip 20 and the substrate 50. The resin filler 214 is, for example, an underfill material. In the conventional semiconductor system 201, the solder 216 and the resin filler 214 form a connection portion 210. Furthermore, the semiconductor chip 20 and the connection portion 210 form a chip component 230.

[0058] In a conventional semiconductor system 201, when viewed in the direction of arrow 150, resin filler 214 protrudes outward in direction 152 from semiconductor chip 20 in width direction 172. For example, if underfill is used as resin filler 214, a fillet with a base is formed on substrate connection surface 52 of substrate 50, causing resin filler 214 to protrude from semiconductor chip 20. The end face of semiconductor chip 20 is referred to as chip end face 24. The end of resin filler 214 is referred to as resin filler end 215. The length in width direction 172 from chip end face 24 to resin filler end 215 is indicated by length 232. Length 232 is called the protrusion width.

[0059] Length 231 in FIG. 6A indicates the length of semiconductor chip 20 in width direction 172. Length 231 is called the chip width. In conventional semiconductor system 201, protrusion width 232 exceeds 10 μm. The maximum length of conventional semiconductor system 201 in width direction 172 is indicated by length 234. In conventional semiconductor system 201, length 234 is 20 μm or more longer than length 231.

[0060] As described above, in the conventional semiconductor system 201, when multiple semiconductor chips 20 are mounted on the substrate 50, the resin filler 214 protrudes from the semiconductor chips 20, making it impossible to shorten the distance L2 between adjacent semiconductor chips 20. The distance L2 usually needs to be 2 mm or more.

[0061] In contrast, in the semiconductor system 1 of this embodiment, as shown in Fig. 1, the maximum length of the chip components 30 in the width direction 172 is approximately equal to the chip width 94. The maximum length of the chip components 30 in the width direction 172 is within ±10 µm at most. Therefore, in the semiconductor system 1 of this embodiment, it is possible to mount the chip components 30 in close proximity to each other.

[0062] 5B is a plan view of the semiconductor package 100 of FIG. 5A as viewed in the direction of arrow 150. For example, as shown in FIGS. 5A and 5B, in the semiconductor system 1 of this embodiment, when a plurality of chip components 30 are mounted on a substrate 50, the length of the chip components 30, including the connection portions 10, in the width direction 172 is short, so that the distance L1 between adjacent semiconductor chips 20 can be shortened. In other words, the semiconductor chips 20 can be mounted in close proximity. For example, the distance L1 can be 20 μm or less.

[0063] (Connection between chip components and board) The connection between the chip component 30 and the substrate 50 will now be described. In the semiconductor system 1 of this embodiment, the chip component 30 and the substrate 50 are generally joined by hybrid bonding. However, more specifically, the connection methods for the insulating portion and the conductive portion are different. The resin portion 14 of the connection portion 10 and the insulating portion 54 of the substrate 50 are joined by hybrid bonding. Meanwhile, the electrode portion 16 of the connection portion 10 and the connection pad 56 of the substrate 50 are connected by solder. These will be explained in order below.

[0064] (insulation part) In the substrate 50 of this embodiment, the insulating portion 54 is made of polyimide. The resin portion 14 of the connection portion 10 is also made of polyimide. The insulating portion 54 contacts the resin portion 14 of the connection portion 10 at the substrate connection surface 52 of the substrate 50. Therefore, the insulating portion 54 and the resin portion 14 are joined by hybrid bonding.

[0065] (conductor part) In the substrate 50 of this embodiment, the connection pads 56 are made of copper. On the other hand, the second electrode portions 18 of the connection portion 10 are made of solder. Therefore, the electrode portions 16 of the connection portion 10 and the connection pads 56 of the substrate 50 are connected by solder. By connecting them using solder, the electrode portions 16 and the connection pads 56 can be connected easily and reliably.

[0066] (Manufacturing method) A method for manufacturing the semiconductor system 1 will be described. In the following explanation, explanations of parts that can be manufactured using conventional technology will be omitted. First, the manufacturing process of the chip component 30 will be described with reference to Figs. 2A to 2C. Figs. 2A to 2C are diagrams showing cross sections of a semiconductor wafer 300 that will become the semiconductor chip 20.

[0067] (Formation of resin part) The formation of the resin portion 14 will be described with reference to FIG. 2A. First, the semiconductor chip 20 is prepared. The semiconductor chip 20 can be prepared using conventional techniques. A material that will become the resin portion 14, such as a polyimide precursor, is applied to the chip connection surface 22 of the semiconductor wafer 300 before dicing, and is cured as necessary. Next, the applied material is patterned using techniques such as photolithography, dry etching, and laser ablation, and is cured as necessary to obtain the resin portion 14.

[0068] The cross-sectional shape of each resin portion 14 is approximately rectangular. By patterning the resin portions 14 to have a predetermined shape, a gap portion 31 is formed between adjacent resin portions 14. The cross-sectional shape of the gap portion 31 is approximately rectangular. An electrode portion 16 is formed in the gap portion 31.

[0069] (Electrode formation) Next, the formation of the electrode portion 16 will be described. The electrode portion 16 can be formed by filling the void portion 31 (see FIG. 2A) with a conductive material. Filling the void portion 31 with the conductive material can be performed by the following methods when soldering. The first method involves forming a copper layer and a solder layer in this order on the entire surface of the resin portion 14 and the void portion 31 using a sputtering method, electroless plating, or the like to fill the void portion 31, and then removing the copper and solder from the resin portion 14 using a CMP method or a fly cutter. The second method involves forming a thin metal seed layer on the entire surface of the resin portion 14 and the void portion 31 using a sputtering method, electroless plating, or the like, and then depositing copper and solder in this order using the metal seed layer to fill the void portion 31 using an electrolytic plating method, and then removing the copper and solder from the resin portion 14 using a CMP method or a fly cutter. After removing the copper and solder from the resin portion 14, it is important to form a solder layer on the copper layer at the bottom of the void portion 31.

[0070] 2B and 2C are diagrams illustrating the second method described above as an example of a method for forming the electrode portion 16. FIG. 2B is a diagram illustrating a state in which a metal seed layer 17 is formed as a first electrode portion constituting part of the electrode portion 16 on the surface of the resin portion 14 and the inner surface of the void portion 31. The metal seed layer 17 is formed by seed sputtering. In the seed sputtering process, the metal seed layer 17 is formed by sputtering on the surface of the resin portion 14, the inner surface of the void portion 31, and the chip connection surface 22 exposed by the void portion 31. The formed metal seed layer 17 serves as an electrode in the next process, the electrolytic plating process. The method and material for forming the metal seed layer 17 are not particularly limited. The material of the metal seed layer 17 can be, for example, copper. Alternatively, the metal seed layer 17 may be formed by sputtering a Ti layer and a copper layer in this order.

[0071] FIG. 2C illustrates the state in which the electrode portion 16 is formed in the void portion 31. In the electroplating process, electroplating is performed using the metal seed layer 17 as an electrode. This electroplating forms a plating electrode layer 18 as a second electrode portion that constitutes part of the electrode portion 16 inside the void portion 31 and on the surface of the resin portion 14. The material of the plating electrode layer 18 is not particularly limited. For example, the material of the plating electrode layer 18 may be copper or a solder material. The material of the plating electrode layer 18 preferably includes at least a solder material. The plating electrode layer 18 may be composed solely of a solder layer, or may be composed of multiple layers including a copper layer as a lower layer and a solder layer as an upper layer. The metal seed layer 17 and the plating electrode layer 18 on the resin portion 14 are then removed using a CMP method or a method using a fly cutter. FIG. 2C illustrates the state after the metal seed layer 17 and the plating electrode layer 18 on the resin portion 14 have been removed.

[0072] The thickness of the copper layer is preferably at least 2 μm, since it is preferable that the thickness is greater than the diffusion area of ​​solder into copper during connection, and the thickness of the solder layer is preferably at least the thickness of the intermetallic compound formed between copper and solder, so it is preferably at least 3 μm.

[0073] The length of the electrode portion 16 in the connection direction 171 is set to be approximately equal to the length 90 of the resin portion 14 in the connection direction 171 .

[0074] When connecting metal materials by hybrid bonding, the conductive material can be filled into the gap 31 in the same manner as in the case of the above-described solder connection, except that a solder layer is not formed.

[0075] The method for filling the voids 31 with the conductive material is not limited to plating. For example, the voids 31 can also be filled with the conductive material by printing a conductive paste or the like.

[0076] The structure shown in Figure 2C can also be formed by other methods. For example, a bump electrode made of copper or copper on the bottom and solder on the top is first formed on a semiconductor wafer. A resin layer such as polyimide is then formed on top of the electrode so that it completely buries the electrode. After curing the resin layer as needed, the resin on the bump electrode is removed using a CMP method or a fly cutter to expose the electrode. When soldering, the copper layer should be thick enough to accommodate the solder diffusion area during connection, so it is preferably 2 μm or thicker. The solder layer should be thick enough to accommodate the copper-solder intermetallic compound, so it is preferably 3 μm or thicker.

[0077] Chip components 30 can be obtained by dicing semiconductor wafer 300, which has electrode portions 16 made of copper and solder formed thereon, into individual pieces. By dicing semiconductor wafer 300, which will become semiconductor chips 20, together with connection portions 10, which are formed on semiconductor wafer 300 and include cured resin portions 14, chip end face 24 and connection portion end face 11 are aligned, so that semiconductor chips 20 and connection portions 10 can be made substantially the same size in a plan view.

[0078] (Preparing the substrate) The preparation of the substrate 50 will now be described. The substrate 50 can be prepared using conventional techniques. However, the insulating portion 54 of the substrate 50 is formed of an insulating resin rather than silicon or the like. Furthermore, it is preferable that the insulating resin used is the same as that of the resin portion 14 of the chip component 30.

[0079] (Connection between chip components and board) The connection between the chip component 30 and the substrate 50 will be described with reference to Fig. 3. Fig. 3 is a diagram showing the state of connection between the chip component 30 and the substrate 50. As shown in Fig. 3, in the connection between the chip component 30 and the substrate 50 of this embodiment, the chip component 30 is connected face down to the substrate 50. In addition, in the connection between the chip component 30 and the substrate 50, hybrid bonding and solder connection are used in combination.

[0080] 3 indicate directions parallel to the connection direction 171. The direction indicated by the arrow 155 and the direction indicated by the arrow 156 are opposite to each other.

[0081] First, the connection surface 12 of the chip component 30 and the substrate connection surface 52 of the substrate 50 are smoothed by CMP (Chemical Mechanical Polishing) or the like. High smoothness of the connection surface 12 and the substrate connection surface 52, which are insulating parts, is preferable because it strengthens the bond between the insulating parts and reduces the pressure required during bonding. For the reasons mentioned above, it is preferable that the connection surface Ra is ≦ 0.3 nm. Then, the chip component 30 and the substrate 50 are connected. At this time, the chip component 30 is moved relative to the substrate 50 in the direction indicated by the arrow 155. Alternatively, the substrate 50 is moved relative to the chip component 30 in the direction indicated by the arrow 156.

[0082] At this time, the chip component 30 and the substrate 50 are aligned in the width direction 172 so that the resin portion 14 of the connection portion 10 contacts the insulating portion 54 of the substrate 50, and the electrode portion 16 of the connection portion 10 contacts the connection pad 56 of the substrate 50.

[0083] After the connection surface 12 of the connection portion 10 and the substrate connection surface 52 of the substrate 50 come into contact, the interface between the connection surface 12 and the substrate connection surface 52 is heated or pressure is applied to the interface as needed.

[0084] As described above, in the semiconductor system 1 of this embodiment, the connection between the resin portion 14 of the connection portion 10 and the insulating portion 54 of the substrate 50 is different from the connection between the electrode portion 16 of the connection portion 10 and the connection pad 56 of the substrate 50 in terms of the connection mechanism. The connection between the resin portion 14 and the insulating portion 54 is, for example, a hybrid bonding between polyimide materials, while the connection between the electrode portion 16 and the connection pad 56 is a solder connection. That is, the semiconductor system 1 of this embodiment has a hybrid bonding portion between resin materials and a solder connection portion between metal materials on the bonding surfaces of the chip component 30 and the substrate 50. This makes it possible to properly ensure electrical connection through the solder joints while suppressing resin extrusion from around the semiconductor chip, even when mounting multiple chip components 30 on a substrate 50 such as an RDL interposer, thereby enabling high-density mounting of multiple chip components 30.

[0085] The preferred application of heat and pressure for completing the hybrid bonding and the preferred application of heat and pressure for completing the solder connection may be performed, respectively. For example, to complete the solder connection, heating may be performed up to the melting temperature of the solder material used.

[0086] Furthermore, after the chip components 30 and the substrate 50 are connected, they may be separated into individual pieces by dicing, etc., as necessary. The semiconductor system 1 can be manufactured in the manner described above.

[0087] The manufacturing method of the semiconductor system 1 can be summarized as follows. (Resin part formation step) A material that will become the resin portion 14 is applied to the chip connection surface 22 of the semiconductor chip 20 and cured as necessary. The applied material is patterned using a technique such as photolithography and cured as necessary to obtain the resin portion 14 in which the void portion 31 is formed.

[0088] (Electrode part formation step) The electrode portion 16 is formed by filling the gap portion 31 with a conductive material.

[0089] (Step of connecting chip components to the board) A substrate 50 is prepared separately. A chip component 30 having an electrode portion 16 formed thereon is connected face down to the substrate 50. For this connection, as described above, the surfaces are polished, the surfaces are brought into contact with each other, and pressure or heat is applied as necessary. By going through the above steps, the semiconductor system 1 can be manufactured.

[0090] For example, a manufacturing method of a semiconductor system 1 according to the present embodiment is a manufacturing method of a semiconductor system 1 including a substrate 50, a semiconductor chip 20, and a connecting portion 10 having an electrode portion 16 and a resin portion 14 disposed between the substrate 50 and the semiconductor chip 20, and includes a chip component manufacturing process for manufacturing a chip component 30 having the semiconductor chip 20 and the connecting portion 10, and a face-down mounting process for mounting the chip component 30 face-down on the substrate 50, the chip component manufacturing process including a process for forming the resin portion 14 and the electrode portion 16 on a portion that will become the chip connecting surface 22 of the semiconductor chip 20, and the face-down mounting process including a process for joining the resin portion 14 of the connecting portion 10 to the substrate 50 by hybrid bonding. In this way, by joining the cured resin portion 14 of the connecting portion 10 to the substrate 50 by hybrid bonding in the face-down mounting process, protruding portions such as resin fillets and bulges are prevented from being formed between the substrate 50 and the semiconductor chip 20. Therefore, it is possible to prevent resin from spilling out from the periphery of the semiconductor chip 20, and the degree of freedom in mounting is increased.

[0091] Preferably, the chip component manufacturing process further includes a curing process for curing the resin portion 14, and the face-down mounting process includes a process for joining the cured resin portion 14 of the chip component 30 to the substrate 50 by hybrid bonding. This makes it possible to prevent uncured resin from spilling out from the periphery of the semiconductor chip 20, thereby increasing the degree of freedom in mounting. Preferably, the curing process for curing the resin portion 14 is a main curing process.

[0092] The chip component manufacturing process may also include a step of forming a resin portion 14 in the portion that will become the chip connection surface 22, a step of forming a void portion 31 in the resin portion 14, a hardening process step of hardening the resin portion 14, and a step of filling a conductive material into the void portion 31 in the resin portion 14 to form an electrode portion 16.

[0093] The chip component manufacturing process may also include a step of forming an electrode portion 16 on the portion that will become the chip connection surface 22, a step of forming a resin portion 14 around the electrode portion 16, and a hardening process step of hardening the resin portion 14.

[0094] The chip component manufacturing process may also include the steps of preparing a semiconductor wafer 300, forming resin portions 14 and electrode portions 16 on portions of the semiconductor wafer 300 that will become chip connection surfaces 22, and dicing the semiconductor wafer 300 on which the resin portions 14 and electrode portions 16 have been formed to manufacture individual chip components 30. By dicing the connection portions 10 including the resin portions 14 together in this manner, the chip end faces 24 and the connection portion end faces 11 are aligned, so that the semiconductor chips 20 and the connection portions 10 can be made to be substantially the same size in a plan view.

[0095] As such, the semiconductor system 1 of this embodiment comprises a chip component 30 and a substrate 50, and the chip component 30 has a semiconductor chip 20 and a connection portion 10 formed on the chip connection surface of the semiconductor chip 20, and the connection portion 10 has an electrode portion 16 and a resin portion 14 surrounding the electrode portion 16, and the bonding surface between the chip component 30 and the substrate 50 may have a hybrid bonding portion as a direct bonding portion where the resin portion 14 previously formed on the semiconductor chip 20 and the resin material constituting the substrate 50 are directly bonded.

[0096] (Second embodiment) A semiconductor system 1 according to a second embodiment of the present invention will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the semiconductor system 1 according to the second embodiment of the present invention. The following description will focus on differences from the semiconductor system 1 according to the first embodiment. Items that are not specifically described can be the same as those in the semiconductor system 1 according to the first embodiment.

[0097] The semiconductor system 1 of the second embodiment differs from the semiconductor system 1 of the first embodiment in the configuration of the electrode unit 16. In the semiconductor system 1 of the first embodiment, the electrode unit 16 includes a metal seed layer 17 and a plated electrode layer 18. In contrast, in the semiconductor system 1 of the second embodiment, the electrode unit 16 is made of a single conductive material. In other words, the electrode unit 16 of the semiconductor system 1 of the second embodiment has a single-layer structure.

[0098] The electrode portion 16 of the second embodiment may be formed by, for example, an electroless plating method, a method of filling and baking a conductive paste, a method of printing a conductive paste, or the like.

[0099] (Joining of electrode part and connection pad) In the semiconductor system 1 of the second embodiment, the electrode 16 and the connection pad 56 can be connected by, for example, hybrid bonding. When hybrid bonding the electrode 16 and the connection pad 56, it is preferable that the material of the electrode 16 and the material of the connection pad 56 are the same. For example, the material of the electrode 16 and the material of the connection pad 56 can both be copper. This allows the electrode 16 and the connection pad 56 to be connected by copper diffusion bonding. That is, the semiconductor system 1 of this embodiment has a hybrid bonded portion between resin materials and a hybrid bonded portion between metal materials at the bonding surfaces between the chip component 30 and the substrate 50. The hybrid bonded portion between metal materials includes metal diffusion bonding. As a result, even when mounting multiple chip components 30 on a substrate 50 such as an RDL interposer, using hybrid bonding for both the resin-to-resin and metal-to-metal bonding can prevent resin from spilling out from the periphery of the semiconductor chip, enabling high-density mounting of multiple chip components 30.

[0100] Even when the electrode portion 16 is composed of two or more layers, the electrode portion 16 and the connection pad 56 can be bonded by hybrid bonding. In this case, it is preferable that the material of the bonding surface of the electrode portion 16 with the connection pad 56 and the material of the bonding surface of the connection pad 56 with the electrode portion 16 are the same material.

[0101] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0102] For example, in the above description, polyimide, polyamideimide, benzocyclobutene, polybenzoxazole, and the like are given as examples of materials for the insulating portion 54. The material for the insulating portion 54 is not limited to these organic insulating materials. The material for the insulating portion 54 can also be, for example, silicon. In this case, it is preferable to form a portion of the substrate connecting surface 52 made of the same material as the resin portion 14 at a position that contacts the resin portion 14. For example, if the resin portion 14 is made of polyimide, a portion made of polyimide is formed on the substrate connecting surface 52. This allows the semiconductor chip 20 and the substrate 50 to be joined by hybrid bonding even if the insulating portion 54 is made of a material different from the material for the resin portion 14, such as silicon.

[0103] As described above, the semiconductor system 1 of this embodiment can provide a semiconductor system in which resin, such as an underfill material, is prevented from spilling out from around the semiconductor chip. A conventional method known as capillary flow underfill involves soldering the bump electrodes of the semiconductor chip to the electrodes of the interposer, then infiltrating a liquid uncured resin into the gap between the semiconductor chip and the interposer, followed by thermal curing. However, capillary flow underfill has several drawbacks, including the length of time it takes for the resin to penetrate the gap, the incomplete filling of the resin resulting in voids, and the formation of fillets that cause the resin to spill out significantly around the chip.

[0104] Another known method is the NCP method, in which uncured liquid resin is applied to the interposer before connecting the semiconductor chip, and then the bump electrodes of the semiconductor chip and the electrodes of the interposer are soldered onto the resin, followed by thermal curing. This method has several issues, including the resin getting caught between the bump electrodes of the semiconductor chip and the electrodes of the interposer, increasing the connection resistance, trapping air during connection between the semiconductor chip and the interposer, creating voids, and squeezing the uncured resin between the bump electrodes of the semiconductor chip and the electrodes of the interposer, causing the extruded resin to bulge and protrude significantly around the chip.

[0105] Another known method is the NCF method, in which an uncured resin film is formed on the electrode surface of the semiconductor chip or the electrode surface of the interposer, and then the bump electrodes of the semiconductor chip and the electrodes of the interposer are soldered together and the resin film is thermally cured. However, this method also has problems such as the resin getting caught between the bump electrodes of the semiconductor chip and the electrodes of the interposer, which increases the connection resistance, the air being trapped when connecting the semiconductor chip and the interposer, which creates voids, and the uncured resin being squeezed between the bump electrodes of the semiconductor chip and the electrodes of the interposer and being extruded to the surrounding area, causing the extruded resin to bulge and protrude significantly around the chip.

[0106] In contrast, in the semiconductor system of this embodiment, the substrate and semiconductor chip are electrically connected face-down via electrodes, and the space between the substrate and semiconductor chip is filled with resin. The cross-sectional contour of the resin, from the surface contacting the semiconductor chip to the surface contacting the substrate, is substantially the same as the contour of the electrode surface of the semiconductor chip. In other words, the resin portion forming the connection does not have any protruding portions, such as fillets or extrusion-induced bulges. Therefore, the semiconductor system 1 of this embodiment can provide a semiconductor system that suppresses the protrusion of resin, such as underfill material, from the periphery of the semiconductor chip, thereby increasing the flexibility of mounting. Furthermore, the semiconductor system of this embodiment achieves direct metal bonding between the bump electrodes of the semiconductor chip and the electrodes of the interposer without sandwiching resin, thereby reducing connection resistance.

[0107] (1) Semiconductor systems are The substrate and the semiconductor chip are electrically connected face down via the electrodes, The space between the substrate and the semiconductor chip is filled with resin. When a portion between the substrate and the semiconductor chip, including the electrode portion and the resin portion, is defined as a connection portion, The outer dimensions of the connection portion in a cross section parallel to the substrate are substantially the same at the portion in contact with the electrode surface of the semiconductor chip and at the portion in contact with the substrate.

[0108] (2) In the semiconductor system of (1), The outer dimensions of the connection portion in a cross section parallel to the substrate are substantially the same from the portion in contact with the electrode surface of the semiconductor chip to the portion in contact with the substrate.

[0109] (3) In the semiconductor system of (1) or (2), The end of the connection portion is within the range of the semiconductor chip when viewed from above.

[0110] (4) A method for manufacturing a semiconductor system includes: A method for manufacturing a semiconductor system including a substrate, a semiconductor chip, and a connecting portion having an electrode portion and a resin portion, the connecting portion being disposed between the substrate and the semiconductor chip, the method comprising: a chip component manufacturing process for manufacturing a chip component having the semiconductor chip and the connection portion; a face-down mounting step of mounting the chip component face-down on the substrate, the chip component manufacturing step includes a step of forming the resin portion and the electrode portion on a portion that will become a chip connection surface of the semiconductor chip, The face-down mounting step includes a step of joining the resin portion of the connection portion and the substrate by hybrid bonding.

[0111] (5) In the manufacturing method of the semiconductor system according to (4), the chip component manufacturing process further includes a curing treatment step of curing the resin portion, The face-down mounting step includes a step of joining the cured resin portion of the chip component to the substrate by hybrid bonding.

[0112] (6) In the manufacturing method of the semiconductor system according to (5), 6. The method for manufacturing a semiconductor system according to claim 5, wherein the chip component manufacturing process includes the steps of forming the resin portion in a portion that will become the chip connection surface, forming a void portion in the resin portion, hardening the resin portion, and filling the void portion in the resin portion with a conductive material to form the electrode portion.

[0113] (7) In the manufacturing method of the semiconductor system according to (5), 6. The method for manufacturing a semiconductor system according to claim 5, wherein the chip component manufacturing process includes a process of forming the electrode portion on a portion that will become the chip connection surface, a process of forming the resin portion around the electrode portion, and a hardening process of hardening the resin portion.

[0114] (8) In the method for manufacturing a semiconductor system according to (4) to (7), The chip component manufacturing process includes a step of preparing a semiconductor wafer, a step of forming the resin portion and the electrode portion on the portion of the semiconductor wafer that will become the chip connection surface, and a step of dicing the semiconductor wafer on which the resin portion and the electrode portion have been formed to manufacture the individual chip components. [Explanation of symbols]

[0115] 1. Semiconductor Systems 10 Connection 11 Connection end face 12 Connection surface 14 Resin part 15 End resin part 16 Electrode part 17 First electrode portion (metal seed layer) 18 Second electrode portion (plated electrode layer) 20 Semiconductor chips 22 Chip connection surface 24 Chip end face 30 Chip parts 31 Cavity 50 boards 52 PCB connection surface 54 Insulation section 56 connection pads 58 Wiring layer 70 Chip end position 72 Connection end position 94 chip width 96 Overhang width 97 Fitting width 100 Semiconductor Packages 110 Package substrate 112 First solder part 114 Second solder part 152 outward direction 153 Inward direction 171 Connection Direction 172 Width direction 300 semiconductor wafers 721 Outermost position 722 Innermost position

Claims

1. The substrate and the semiconductor chip are electrically connected face-down via the electrode portion. The space between the substrate and the semiconductor chip is filled with resin. When the portion between the substrate and the semiconductor chip, including the electrode portion and the resin portion, is used as a connecting portion, In a cross-section parallel to the substrate, the external dimensions of the connection portion are substantially the same for the portion in contact with the electrode surface of the semiconductor chip and the portion in contact with the substrate. The electrode portion is a semiconductor system having solder.

2. The semiconductor system according to claim 1, wherein the external dimensions of the connection portion in a cross-section parallel to the substrate are substantially the same from the portion in contact with the electrode surface of the semiconductor chip to the portion in contact with the substrate.

3. The semiconductor system according to claim 1 or 2, wherein the end of the connection portion is within the range of the semiconductor chip when viewed from above.

4. The semiconductor system according to claim 1, wherein the end face of the semiconductor chip and the end face of the connection portion are located on the same straight line.

5. A method for manufacturing a semiconductor system comprising a substrate, a semiconductor chip, and a connecting portion having an electrode portion and a resin portion disposed between the substrate and the semiconductor chip, A chip component manufacturing process for manufacturing the semiconductor chip and the chip component having the connection portion, The process includes a face-down mounting step of mounting the chip components face-down onto the substrate, The chip component manufacturing process includes the step of forming the resin portion and the electrode portion on the portion that will become the chip connection surface of the semiconductor chip. The face-down mounting process includes a step of joining the resin portion of the connection part and the substrate by hybrid bonding, A method for manufacturing a semiconductor system, wherein the step of forming the electrode portion includes a step of depositing solder.

6. The chip component manufacturing process further includes a curing process for curing the resin portion, The method for manufacturing a semiconductor system according to claim 5, wherein the face-down mounting step includes a step of joining the cured resin portion of the chip component and the substrate by hybrid bonding.

7. The method for manufacturing a semiconductor system according to claim 6, wherein the chip component manufacturing step includes a step of forming the resin portion on the portion that will become the chip connection surface, a step of forming a void portion on the resin portion, a curing step of curing the resin portion, and a step of filling the void portion on the resin portion with a conductive material to form the electrode portion.

8. The method for manufacturing a semiconductor system according to claim 6, wherein the chip component manufacturing step includes the step of forming the electrode portion on the portion that will become the chip connection surface, the step of forming the resin portion around the electrode portion, and the curing step of curing the resin portion.

9. The method for manufacturing a semiconductor system according to claim 5 or claim 6, wherein the chip component manufacturing process includes the steps of preparing a semiconductor wafer, forming the resin portion and the electrode portion on the portion of the semiconductor wafer that will become the chip connection surface, and manufacturing the chip component by dicing the semiconductor wafer on which the resin portion and the electrode portion are formed into individual pieces.

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