Semiconductor device

Abstract

To provide a semiconductor device that is less prone to the fluctuation in the electrical characteristic due to miniaturization.SOLUTION: A semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions, a gate insulating film provided over the oxide semiconductor film, and a first electrode overlapping the first region on the gate insulating film, and the first region is a CAAC oxide semiconductor region, and the pair of second regions and the pair of third regions are amorphous oxide semiconductor regions containing a dopant, and the dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. In this specification, a transistor refers to a semiconductor device, and an electric device including the transistor Optical devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices. [Background technology]

[0003] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are made of amorphous silicon and single-crystal silicon formed on a glass substrate. The silicon semiconductor is made of silicon or polycrystalline silicon. Semiconductor transistors are also used in integrated circuits (ICs).

[0004] A technology that uses metal oxides that exhibit semiconductor properties in transistors instead of the silicon semiconductors mentioned above. In this specification, metal oxides that exhibit semiconducting properties are referred to as oxide semiconductors. Let's call it the body.

[0005] For example, zinc oxide and In-Ga-Zn-O oxides are used as oxide semiconductors. A technology for fabricating a transistor and using it as a switching element for pixels in a display device. are disclosed (see Patent Documents 1 and 2).

[0006] In addition, in a transistor using an oxide semiconductor, A highly conductive oxide semiconductor containing nitrogen is placed between the source and drain electrodes as a buffer layer. By providing the oxide semiconductor, the contact resistance between the oxide semiconductor and the source electrode and the drain electrode can be reduced. A technique for reducing this has been disclosed (see Patent Document 3).

[0007] Furthermore, the source and drain regions of a transistor using an oxide semiconductor are self-aligned. As a method for forming the oxide semiconductor layer, the oxide semiconductor surface is exposed and subjected to argon plasma treatment. and a method for reducing the resistivity of the oxide semiconductor in the exposed portion has been disclosed (Non-Patent (See Reference 1).

[0008] However, in this method, the oxide semiconductor surface is exposed and then subjected to argon plasma treatment. By this process, the oxide semiconductor in the portions to become the source and drain regions is also etched. The source region and the drain region are thinned by etching (see FIG. 8 of Non-Patent Document 1). As a result, the resistance of the source and drain regions increases, and the over-energy caused by the thinning of the layers increases. The probability of defective products due to etching also increases.

[0009] This phenomenon occurs when the atomic radius of the ion species used in the plasma treatment of oxide semiconductors is large. This becomes more noticeable.

[0010] If the oxide semiconductor layer is thick enough, this is not a problem. When the thickness is set to nanometers or less, the oxide of the channel portion is required to prevent the short channel effect. The thickness of the semiconductor layer is required to be 20 nm or less, preferably 10 nm or less. When such a thin oxide semiconductor layer is used, the above-described plasma treatment is not preferable. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-135774 [Non-patent literature]

[0012] [Non-Patent Document 1] S. Jeon et al. “180nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application”, IEDM Tech. Dig., p.504, 2010. Summary of the Invention [Problem to be solved by the invention]

[0013] In integrated circuits using transistors, miniaturization of transistors is necessary for integration. .

[0014] In the miniaturization of transistors, the channel length is extremely shortened, and the threshold voltage This phenomenon is called the short channel effect, and the electrical characteristics change due to this short Suppressing the channel effect is one of the challenges in miniaturizing transistors.

[0015] Transistors using oxide semiconductors can operate at room temperature faster than transistors using silicon. It is known that the off-state current is small in This is thought to be because the carrier density is low.

[0016] One embodiment of the present invention is to provide a semiconductor device in which fluctuations in electrical characteristics due to miniaturization are unlikely to occur. The following are the challenges. [Means for solving the problem]

[0017] The means for solving the above problem is to form a channel in a transistor using an oxide semiconductor. The purpose is to provide a region containing a dopant in an oxide semiconductor film including the region. A pair of amorphous regions containing a dopant is provided in two locations in an oxide semiconductor film including a channel formation region. The dopant concentration in each region is different. The electric field generated in the drain region of the oxide semiconductor film reduces the electric field applied to the channel formation region. In this specification, the dopant The term "oxide semiconductor film" is a general term for elements added to an oxide semiconductor film including a channel formation region.

[0018] The oxide semiconductor in the channel formation region is non-single-crystal. When viewed from the direction perpendicular to the surface, the atomic arrangement is a triangle, a hexagon, an equilateral triangle, or a regular hexagon. When viewed from the direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are It contains crystalline portions arranged in layers. In this specification, these crystalline portions are referred to as c-axis oriented crystals. The oxide semiconductor having the c-axis oriented crystal is called a CAAC oxide semiconductor (CAAC-O S:c-axis aligned crystalline oxide semico The channel formation region is called a CAAC oxide semiconductor. By using this region, it is possible to suppress fluctuations in the electrical characteristics of transistors due to irradiation with visible light or ultraviolet light. The reliability of the semiconductor device can be improved.

[0019] Therefore, one aspect of the present invention is a method for manufacturing a semiconductor device comprising: a first region and a pair of second regions in contact with the side surfaces of the first region; and a pair of third regions in contact with side surfaces of the pair of second regions; and a gate insulating film provided on the nitride semiconductor film; and a second region on the gate insulating film overlapping the first region. The first region is a CAAC oxide semiconductor region, and a pair of second regions are The pair of third regions are amorphous oxide semiconductor regions containing a dopant. The dopant concentration of the third region is higher than the dopant concentration of the pair of second regions. is.

[0020] The oxide semiconductor film is an oxide semiconductor film containing two or more elements selected from In, Ga, Sn, and Zn. It is preferable to use a semiconductor film.

[0021] In the semiconductor device, the pair of third regions are provided with second electrodes and third electrodes electrically connected to each other. The electrode is

[0022] The pair of second regions and the pair of third regions are provided on the side surfaces of the gate insulating film and the first electrode. By adding dopants through the sidewall insulating film, self-alignment is achieved. That is, by providing the sidewall insulating film, a pair of The second region is a region where a small amount of dopant is added (referred to as a low concentration region in this specification). The pair of third regions can be formed by doping the dopant. It is possible to make it a region where a large amount of the substance is absorbed (referred to as a high concentration region in this specification). Furthermore, by providing a sidewall insulating film, the pair of second regions are separated into a channel forming region and a channel forming region. a first region acting as a source region and a pair of second regions acting as a drain region; It can be formed between the three regions.

[0023] The dopants added to the pair of second regions and the pair of third regions are hydrogen or a rare gas element. and the dopant contained in the pair of second regions and the pair of third regions is one or more elements selected from the group consisting of: The punt concentration is 1 x 10 19 atoms / cm 3 More than 1×10 22 atoms / cm 3 Below Furthermore, the dopant concentration of the pair of second regions is preferably 5×10 or less. 18 atoms / cm 3 5x10 or more 19 atoms / cm 3 and the dopant of the pair of third regions is less than The concentration is 5 x 10 19 atoms / cm 3 More than 1×10 22 atoms / cm 3 The following It is even more preferable that

[0024] In the semiconductor device of one embodiment of the present invention, the second electrode and the third electrode are a pair of third electrodes. The second region may be in contact with the upper surface of the first region, or may be in contact with the lower surfaces of the pair of third regions. That's fine.

[0025] The area where the gate insulating film is formed varies depending on how the sidewall insulating film is formed. Specifically, the area where the gate insulating film is formed is divided into a first area, a second area, and a third area. There are two types of configurations: one in which the first region is located on the first side, and the other in which the second region is located only on the first side.

[0026] When the sidewall insulating film is a nitride insulating film and the gate insulating film is an oxide insulating film The gate insulating film is formed by etching the nitride insulator and the oxide insulator at a selectivity ratio. It functions as an etching stopper when forming the gate wall insulating film, Excessive etching of the oxide semiconductor film in contact with the bottom surface can be suppressed. In the semiconductor device of this configuration, the gate insulating film has a first region, a pair of second regions, and a pair of third regions. The structure remaining on region 3.

[0027] When both the sidewall insulating film and the gate insulating film are made of oxide insulating films, the oxide By utilizing the etching selectivity of the insulating film and the first electrode, a pair of second regions and a pair of The gate insulating film provided on the third region can be etched. As a result, the semiconductor device of this configuration has a structure in which the gate insulating film remains on the first region.

[0028] A dopant for forming a low concentration region and a high concentration region of a transistor according to one embodiment of the present invention The addition of ions is carried out by ion doping or ion implantation. Furthermore, instead of the ion doping method or the ion implantation method, Plasma is generated in a gas atmosphere containing the dopant to be added, and the plasma is applied to the material to be doped. A dopant can also be added by performing Zuma treatment.

[0029] In addition, elements with large atomic radii, such as rare gases, are used as dopants, and the plasma treatment In the case of adding, the gate insulating film covers the oxide semiconductor film (the gate insulating film is the first region , provided on a pair of second regions and a pair of third regions). In the manufacturing process of a transistor, the above-described plasma treatment is performed in a state where the oxide semiconductor film is exposed. By this etching, portions of the oxide semiconductor film that become the pair of third regions are etched and thinned. This is because there is a possibility that

[0030] This prevents etching of the high concentration region of the oxide semiconductor film, In addition, the interface between the oxide semiconductor film and the gate insulating film can be kept clean. Since the temperature can be maintained, the electrical characteristics and reliability of the transistor can be improved. [Effects of the Invention]

[0031] According to one embodiment of the present invention, an oxide semiconductor device having good electrical characteristics and reliability and easy miniaturization can be obtained. It is possible to provide a semiconductor device using a compound semiconductor. [Brief explanation of the drawings]

[0032] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are diagrams illustrating band structures of an oxide semiconductor, an oxide semiconductor, and a metal material. [Figure 9] FIG. 1 is a cross-sectional view illustrating an example of a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating an example of a resistor element according to one embodiment of the present invention. [Figure 11] FIG. 1 is an example of a circuit diagram illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is an example of a circuit diagram illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is an example of a circuit diagram illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is an example of a circuit diagram illustrating one embodiment of the present invention. [Figure 15] FIG. 1 is a block diagram showing a specific example of a CPU and a partial circuit diagram thereof. DETAILED DESCRIPTION OF THE INVENTION

[0033] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. It should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. These are commonly used and their repeated explanations will be omitted.

[0034] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0035] In addition, terms such as first, second, and third used in this specification are used in order to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0036] The functions of "source" and "drain" are used when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are used interchangeably. The terms may be used interchangeably. (Embodiment 1)

[0037] In this embodiment, a structure and a manufacturing method of a transistor according to one embodiment of the present invention will be described. 1 to 3 will be used to explain this.

[0038] <Structure and Features of Transistor 100> FIG. 1A is a plan view of a transistor 100. Note that in FIG. The insulating film 102, the gate insulating film 111, and the interlayer insulating film 117 are not shown for convenience.

[0039] 1A, the first electrode 113 and the first electrode 113 are formed over the oxide semiconductor film 103. The sidewall insulating film 115 is provided on the side surface of the second electrode. The third electrode 119a and the third electrode 119b are exposed to the oxide semiconductor film 119a through the openings 116a and 116b. The second electrode 103 is provided on a pair of third regions 109a and 109b. The third electrode 119a and the third electrode 119b are in contact with the upper surfaces of the pair of third regions 109a and 109b. The transistor 100 is a top-gate, top-contact transistor. do.

[0040] FIG. 1B is a cross-sectional view of the transistor 100 taken along line A and B. An insulating base film 102 is provided on a substrate 101, and a first region is formed on the insulating base film 102. a pair of second regions 107a, 107b and a pair of third regions 109a, 109b; The oxide semiconductor film 103 includes a pair of second regions 107a and 107b. The pair of third regions 109a, 109b are provided in contact with the side surfaces of the first region 105. b is provided in contact with the side surfaces of the pair of second regions 107a and 107b.

[0041] A gate insulating film 111 is provided over the oxide semiconductor film 103. A first electrode 113 overlapping the first region 105 is provided on the first electrode 11. The side surfaces of the insulating film 115 are provided with sidewall insulating films 115a and 115b (sidewall insulating film 115 ) are provided adjacent to each other.

[0042] On the gate insulating film 111, the first electrode 113, and the sidewall insulating films 115a and 115b An interlayer insulating film 117 is provided on the substrate.

[0043] The second electrode 119a and the third electrode 119b are formed on the gate insulating film 111 and the interlayer insulating film 11 The pair of third regions 109a and 109b are connected to each other through openings 116a and 116b formed in the first region 109a. The gate insulating film 111 is provided in contact with the first region 105 and the pair of second regions 106. The first and second regions 107a and 107b are in contact with the first and second regions 107a and 107b and a pair of third regions 109a and 109b.

[0044] The ends of the second electrode 119a and the third electrode 119b may be tapered. The end of the first electrode 113 is preferably vertical. The first electrode 113 has a straight shape, and a sidewall insulating film 115 (sidewall insulating film) is formed on the first electrode 113. By forming an insulating film that will become insulating films 115a and 115b, and then performing highly anisotropic etching, , the sidewall insulating film 115 (sidewall insulating films 115a and 115b) is formed. You will be able to do this.

[0045] As will be described in detail later, a pair of second regions 107a and 107b are shown in FIGS. 1A and 1B. A region 107b corresponds to a region where the oxide semiconductor film 103 overlaps with the sidewall insulating film 115. Then, the sidewall insulating film 115 (sidewall insulating films 115a and 115b) is at least a part of the first electrode 113 other than the side surface of the first electrode 113 and the region in contact with the gate insulating film 111. may have a curved shape.

[0046] A first region 105, a pair of second regions 107a and 107b, and a pair of third regions 109a The oxide semiconductor film 103 including 109b is made of at least two selected from In, Ga, Sn, and Zn. The metal oxide contains the above elements. The metal oxide has a band gap of 2 eV or more. Preferably, the electron energy is 2.5 eV or more, more preferably 3 eV or more. The use of a wide band gap metal oxide reduces the off-state current of the transistor 100. It is possible.

[0047] In the transistor 100, the first region 105 functions as a channel formation region.

[0048] The first region 105 is the CAAC oxide semiconductor region described above. The conductor is not a single crystal, but it is also not made up of only amorphous material. AAC oxide semiconductors contain crystallized parts (crystalline parts), but one crystalline part and another crystalline part are not crystallized. The boundary between the two regions may not be clearly distinguishable. The portion may be substituted with nitrogen. The c-axis is aligned in a certain direction (for example, the surface of the substrate supporting the CAAC oxide semiconductor or the The direction may be perpendicular to the surface of the conductive film, the film surface, the interface, etc. The normal to the ab plane of each crystal part that constitutes the compound semiconductor is in a certain direction (for example, CAAC acid The direction perpendicular to the surface of the substrate supporting the oxide semiconductor, the surface of the CAAC oxide semiconductor film, the film surface, the interface, etc. The CAAC oxide semiconductor may be oriented as a conductor or a semiconductor depending on its composition. Depending on the composition, the CAAC oxide semiconductor can be either a conductor or an insulator. It can be transparent or opaque to light. Examples of CAAC oxide semiconductors include the surface and shape of the formed When observed from the direction perpendicular to the substrate surface or interface, triangular or hexagonal atoms are formed. The molecular arrangement is observed, and when the cross section of the formation is observed, it is possible to see that the metal atoms, or the metal atoms and oxygen atoms, Examples include materials in which a layered arrangement of carbon atoms (or nitrogen atoms) is observed.

[0049] The hydrogen concentration in the first region 105 is 1×10 20 atoms / cm 3 The following is preferably is 1 x 10 19 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The first region 105, which is a channel formation region, is a CAAC oxide semiconductor region. The transistor 100 with reduced hydrogen concentration has a BT (gate The threshold voltage fluctuation is small before and after the thermal bias stress test, so the device is stable. It has excellent electrical characteristics and can be said to be a highly reliable transistor.

[0050] The pair of second regions 107a, 107b and the pair of third regions 109a, 109b are conductive. The modulus is 10 S / cm or more and 1000 S / cm or less, preferably 100 S / cm or more and 1000 S / cm or less The conductivity of the pair of third regions 109a and 109b is set to be equal to or less than the conductivity of the pair of third regions 109a and 109b. The conductivity of the second regions 107a and 107b is higher than that of the first regions 107a and 107b. The on-current of the transistor 100 decreases.

[0051] In addition, the pair of second regions 107a and 107b and the pair of third regions 109a and 109b are , are amorphous regions containing dopants. The third regions 109a and 109b contain a dopant selected from hydrogen and rare gas elements. The above elements are added.

[0052] The dopant in the pair of second regions 107a, 107b and the dopant in the pair of third regions 109a, 109b Increasing the dopant concentration can increase the carrier density, but If the dopant is increased too much, it will hinder the movement of carriers, and the pair of second regions will By reducing the conductivity of the regions 107a, 107b and the pair of third regions 109a, 109b, This becomes the case.

[0053] Therefore, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b The dopant concentration is 5×10 18 atoms / cm 3 More than 1×10 22 atoms / c m 3 Furthermore, it is preferable that the dopant concentration of the pair of third regions 109a and 109b is less than 100%. The dopant concentration of the pair of second regions 107a and 107b is higher than the dopant concentration of the pair of second regions 107a and 107b. The dopant concentration of the pair of second regions 107a and 107b is 5×10 18 atoms / cm 3 5x10 or more 19 atoms / cm3 and a pair of third regions 109a, 1 The dopant concentration of 09b is 5×10 19 atoms / cm 3 More than 1×10 22 atom s / cm 3 The difference in dopant concentration is preferably: The sidewall insulating film 115 (sidewall insulating films 115a and 115b) is provided on the substrate 100. Since the dopant is added to the silicon substrate, the dopant is added in a self-aligned manner.

[0054] A pair of third regions 109a, 109b form the source and drain regions of the transistor 100. The transistor 100 has amorphous regions (low By providing the first region 105 of the channel forming region with the first and second regions 106 and 108, This can reduce the electric field applied to the first region 105, which is a channel formation region. Specifically, a pair of second regions 107a and 107b, which are low-concentration regions, and a pair of second regions 107b, which are high-concentration regions, A pair of third regions 109a and 109b are provided on both ends of the first region 105 of the channel forming region. By doing so, the transistor 100 has a barrier in the channel formed in the first region 105. Therefore, the pair of second regions 107a and 107b has the effect of hardly causing bending of the band end. By providing the first region 107b and the pair of third regions 109a and 109b, the short channel effect is suppressed. It is possible.

[0055] <Method for manufacturing transistor 100> Next, a manufacturing method of the transistor 100 will be described with reference to FIGS.

[0056] An insulating base film 102 is formed on a substrate 101. The insulating base film 102 is formed by a sputtering method, a C It can be formed by a VD method, a coating method, etc. The thickness of the base insulating film 102 is not limited. However, the thickness of the base insulating film 102 is preferably 50 nm or more.

[0057] There is no particular restriction on the material of the substrate 101, but it should be at least strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and A fire substrate or the like may be used as the substrate 101. Also, silicon or silicon carbide may be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium It is also possible to apply a substrate, an SOI substrate, etc., and a semiconductor element is provided on these substrates. The resulting material may be used as the substrate 101 .

[0058] A flexible substrate may be used as the substrate 101. In this case, the transistors may be fabricated directly on the flexible substrate, or may be fabricated on another substrate. After the transistor is formed, it may be peeled off and transferred to a flexible substrate. In order to peel the transistor and transfer it to a flexible substrate, a peeling It is advisable to provide an area where this is easy.

[0059] The base insulating film 102 is formed by removing impurities (e.g., alkali metals such as Li and Na) from the substrate 101. In addition to preventing the diffusion of ions such as ions, the transistor 100 is also This prevents the substrate 101 from being etched.

[0060] The base insulating film 102 may be a silicon oxide film, a gallium oxide film, or an aluminum oxide film. oxide insulating films, or nitride insulating films, such as silicon nitride films and aluminum nitride films a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film The base insulating film 102 has a single layer structure or a stacked layer structure of an insulating film made of an oxide. It is preferable that the portion in contact with the semiconductor film 103 contains oxygen.

[0061] When the base insulating film 102 is formed by sputtering, a silicon target, a quartz target, Using a target containing oxygen, such as an aluminum target or an aluminum oxide target, The ratio of oxygen in the atmospheric gas to the total atmospheric gas is The oxygen content in the atmospheric gas is 6% by volume or more, and preferably 50% by volume or more. By increasing the ratio, it is possible to form an insulating film that releases oxygen when heated.

[0062] It is also preferable that hydrogen in the target is removed as much as possible. An oxide target of pm or less, preferably 10 ppm or less, more preferably 1 ppm or less By using the above, the hydrogen concentration in the base insulating film 102 can be reduced, and the electrical characteristics of the transistor 100 can be improved. For example, fused silica has an OH group content of 10 ppm or less. Of course, the target of synthetic quartz with low OH group concentration is preferable. A marker may also be used.

[0063] Furthermore, in the fabrication of the transistor 100, alkali metals such as Li and Na are used as impurities. Therefore, it is preferable to reduce the content of impurities such as alkali metals in the substrate 101. When a glass substrate containing alkali metal is used, the base insulating film 102 is It is preferable to form the nitride insulating film by using a silicon dioxide film, and further to form the oxide film on the nitride insulating film. It is preferable to laminate a nitride insulating film.

[0064] Here, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less. silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0 atomic % or more and 10 atomic % or less Silicon nitride oxide refers to a material that contains more oxygen than silicon dioxide in its composition. indicates a material with a high nitrogen content, for example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 atomic % to 55 atomic %; silicon 25 atomic % to 35 atomic %; hydrogen 10 atomic % % or more and 25 atomic % or less. However, the above range is based on the Rutherford method. Rutherford Backscattering Spectroscopy (RBS) rometry) and Hydrogen Forward Scattering (HFS) The content ratio of the constituent elements is The total of these does not exceed 100 atomic percent.

[0065] The base insulating film 102 contains oxygen in a portion in contact with the oxide semiconductor film 103. Therefore, an insulating film that releases oxygen when heated is used as the base insulating film 102. The phrase "oxygen is released by heating" refers to the TDS (Thermal Dispersion Strength) Oxygen atoms were detected by thermal desorption spectroscopy (TDE). The amount of oxygen released converted to 1.0 x 10 18 atoms / cm 3 Above, preferably 3.0 x10 20 atoms / cm 3 This means that the above is the case.

[0066] The following describes a method for quantifying the amount of released oxygen by converting it into oxygen atoms using TDS analysis.

[0067] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of released gas is calculated from the ratio of the integral value of the film spectrum to the reference value of the standard sample. The reference value of the standard sample is the integral of the spectrum of the sample containing the specified atom. is the ratio of the atomic density to the value.

[0068] For example, the TDS analysis results of a silicon wafer containing a predetermined density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using formula 1 Here, all of the spectra detected at mass number 32 obtained by TDS analysis can be It is assumed that the mass number is 32 and that CH3OH exists. It is not considered here because it has low affinity. The abundance ratio of the oxygen molecule, which contains the oxygen atom with mass number 18, in nature is Not taken into consideration as it is an extremely small amount.

[0069]

number

[0070] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the material is subjected to TDS analysis is shown in Fig. 1. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The standard test was carried out using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. 1 x 10 as a fee 16 atoms / cm 3 Measurement using a silicon wafer containing hydrogen atoms This is the numerical value.

[0071] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0072] In addition, N O2 is the amount of oxygen molecules released. In the case of an insulating film, when converted to oxygen atoms, The amount of oxygen released is twice the amount of oxygen molecules released.

[0073] An example of an insulating film that releases oxygen when heated is silicon oxide (SiO X ( X>2)) and silicon oxide (SiO X (X>2)) is a silicon atom It contains more than twice the number of oxygen atoms per unit volume. The numbers of carbon atoms and oxygen atoms are values ​​measured by Rutherford backscattering spectroscopy.

[0074] By using an insulating film that releases oxygen by heating as the base insulating film 102, it is possible to form an oxide semiconductor Oxygen is supplied to the base insulating film 102 and the oxide semiconductor film 103, and the interface states of the base insulating film 102 and the oxide semiconductor film 103 are reduced. Therefore, charges that may be generated due to the operation of the transistor 100 can be reduced. Therefore, the trapping at the interface between the insulating film 102 and the oxide semiconductor film 103 can be suppressed. The transistor 100 can be one with little deterioration in electrical characteristics.

[0075] Furthermore, charges may be generated due to oxygen vacancies in the oxide semiconductor film 103. Oxygen vacancies in semiconductors are formed when some of the oxygen vacancies act as donors and electron carriers. That is, in the transistor 100, one of the oxygen vacancies in the oxide semiconductor film 103 The part becomes a donor, and electrons as carriers are generated, and the threshold voltage of the transistor 100 The voltage of the electrons in the oxide semiconductor film 103 changes in the negative direction. The formation of the oxide semiconductor film 103 is due to oxygen vacancies occurring near the interface between the oxide semiconductor film 103 and the base insulating film 102. The oxygen is sufficiently released from the base insulating film 102 to the oxide semiconductor film 103. This compensates for oxygen vacancies in the oxide semiconductor film 103, which cause the threshold voltage to shift in the negative direction. It is possible to do so.

[0076] That is, by using an insulating film that releases oxygen by heating as the base insulating film 102, The interface state between the conductive film 103 and the base insulating film 102 and the oxygen vacancies in the oxide semiconductor film 103 and the influence of charge trapping at the interface between the oxide semiconductor film 103 and the base insulating film 102 is reduced. Can reduce the sound.

[0077] Next, the oxide semiconductor film 103 is formed over the base insulating film 102 .

[0078] Specifically, the oxide semiconductor film 140 is formed as a CAAC oxide semiconductor film in its entirety. Then, a dopant is added to the oxide semiconductor film 140 to form a pair of second regions 107a and The oxide semiconductor film 103 is formed by forming the third regions 107b and the pair of third regions 109a and 109b. Then, a pair of second regions 107a, 107b and a pair of second regions 107c, 107d are formed by adding a dopant. The oxide semiconductor film is a CAAC oxide semiconductor film before the third regions 109a and 109b are formed. A method for producing the conductive film 140 will be described.

[0079] There are two methods for manufacturing the oxide semiconductor film 140, which is a CAAC oxide semiconductor film. do.

[0080] One method is to form an oxide semiconductor while heating the substrate (for convenience, 1 The other method is to form an oxide semiconductor in two separate steps, This is a method of manufacturing the film by performing two heat treatments (for convenience, this is called the 2-step method).

[0081] First, a method for forming the oxide semiconductor film 140 by a one-step method will be described.

[0082] First, a film was formed by a sputtering method using the oxide semiconductor material described in the oxide semiconductor film 103. The substrate 101 on which the base insulating film 102 is formed is heated. For convenience, the formed oxide semiconductor film is referred to as an oxide semiconductor film 130. The substrate 101 is heated. The temperature is 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. The oxide semiconductor film 130 may be formed to a thickness of 1 nm to 50 nm.

[0083] Here, the sputtering apparatus for forming the oxide semiconductor film 130 will be described in detail below. Reveal.

[0084] The treatment chamber for forming the oxide semiconductor film 130 has a leakage rate of 1×10 -10 Pa·m 3 / It is preferable that the time is set to 10 seconds or less, so that when the film is formed by the sputtering method, the The inclusion of impurities can be reduced.

[0085] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. An external leak is when gas enters the vacuum system from outside due to a small hole or poor seal. Internal leaks are leaks from partitions such as valves in the vacuum system or leaks from internal components. Leak rate is 1×10 -10 Pa·m 3 / sec or less Therefore, measures must be taken to prevent both external and internal leaks.

[0086] To reduce external leakage, it is advisable to seal the opening and closing parts of the processing chamber with metal gaskets. Tal gaskets are made of gold coated with iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a metal gasket. Metal gaskets have a higher adhesion than O-rings and are less susceptible to external leaks. In addition, passivation such as iron fluoride, aluminum oxide, and chromium oxide can reduce the By using coated metal materials, the released gases including hydrogen generated from metal gaskets are reduced. This suppresses the internal leakage and also reduces the internal leakage.

[0087] The materials used for the inner walls of the processing chamber are aluminum, chromium, Titanium, zirconium, nickel or vanadium, or these with iron, chromium and nickel It is also possible to use a material coated with an alloy material containing at least one of iron, chromium and nickel. The alloy material containing at least one of copper and nickel is rigid, heat-resistant, and suitable for processing. Here, in order to reduce the surface area of ​​the inner wall of the processing chamber, the surface irregularities of the member are polished. Alternatively, the material may be treated with iron fluoride, iron oxide, or the like to reduce the amount of released gas. It may be coated with a passivating material such as aluminum or chromium oxide.

[0088] Furthermore, it is preferable to provide an atmospheric gas refiner immediately before introducing the atmospheric gas into the processing chamber. In this case, the length of the piping from the refiner to the treatment chamber should be 5 m or less, preferably 1 m or less. By keeping the length of the piping to 5m or less or 1m or less, the effects of gas released from the piping can be minimized. It can be reduced depending on the size.

[0089] The exhaust from the processing chamber is performed by a roughing pump such as a dry pump, a sputter ion pump, and a turbo pump. It is advisable to use a suitable combination of a sub-pump and a high vacuum pump such as a cryopump. While the polymer pump excels at pumping large molecules, it has poor pumping ability for hydrogen and water. Therefore, a cryopump with high water pumping capacity and a sputter ion pump with high hydrogen pumping capacity are used. It is effective to use a combination of

[0090] The adsorbates present in the processing chamber are adsorbed on the inner wall and do not affect the pressure in the processing chamber. This causes gas emission when the processing chamber is evacuated. Therefore, there is a correlation between the leak rate and the exhaust speed. Although it is not necessary to use a pump with high exhaust capacity, the adsorbed matter in the treatment chamber is desorbed as much as possible. It is important to evacuate the treatment chamber beforehand. Baking can increase the desorption rate of adsorbed substances by about 10 times. Baking can be done at temperatures between 100°C and 450°C. By introducing air into the device while removing adsorbed substances, the desorption rate of water, which is difficult to desorb by exhausting air alone, can be increased. can be made even larger.

[0091] In the sputtering method, the power supply for generating plasma is an RF power supply, A A C power supply, a DC power supply, etc. can be used as appropriate.

[0092] When the oxide semiconductor film 130 is formed by a sputtering method, a target containing zinc is used. Metal oxide targets containing indium, gallium, tin, and A metal oxide target containing two or more elements selected from zinc can be used. The target may be, for example, a quaternary metal oxide, such as In-Sn-Ga-Zn-based metal oxide. oxides, and ternary metal oxides such as In-Ga-Zn metal oxides and In-Sn-Zn metal oxides. Metal oxides, In-Al-Zn metal oxides, Sn-Ga-Zn metal oxides, Al-Ga -Zn-based metal oxides, Sn-Al-Zn-based metal oxides, and In-Hf-Zn-based metal oxides , In-La-Zn metal oxide, In-Ce-Zn metal oxide, In-Pr-Zn Metal oxides, In-Nd-Zn metal oxides, In-Sm-Zn metal oxides, In-E In-Zn metal oxides, In-Gd-Zn metal oxides, In-Tb-Zn metal oxides , In-Dy-Zn metal oxide, In-Ho-Zn metal oxide, In-Er-Zn Metal oxides, In-Tm-Zn metal oxides, In-Yb-Zn metal oxides, In-L In-Zn based metal oxides, binary metal oxides such as In-Zn based metal oxides and Sn-Zn In-Ga based metal oxides, and single elemental oxides containing indium, tin or zinc A target such as a metal oxide can be used.

[0093] As an example of the target, a metal oxide target containing In, Ga, and Zn (In-G a-Zn-based metal oxide) In2O3:Ga2O3:ZnO=1:1:1 [molar ratio The composition ratio is In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] or a target having a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [mo The target has a composition ratio of In2O3:Ga2O3:ZnO=2:1:8[ It is also possible to use a target having a composition ratio of [molar ratio].

[0094] The atmospheric gas may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, a rare gas and oxygen atmosphere, or a mixture of rare gas and oxygen. The atmospheric gas may be a mixture of hydrogen, water, hydroxyl, or hydride. It is preferable to use a high-purity gas from which impurities have been removed.

[0095] By using the sputtering apparatus, the oxide semiconductor film 130 in which hydrogen contamination is reduced can be formed. can be formed.

[0096] Alternatively, the base insulating film 102 and the oxide semiconductor film 130 may be formed in succession under vacuum. For example, after removing impurities including hydrogen on the surface of the substrate 101 by heat treatment or plasma treatment, The base insulating film 102 is formed without exposure to the atmosphere, and then the oxide film 103 is formed without exposure to the atmosphere. In this way, hydrogen on the surface of the substrate 101 can be removed by forming a compound semiconductor film 130. The impurities contained in the substrate 101 are reduced, and the interface between the substrate 101 and the insulating film 102 and the insulating film 102 are This can prevent atmospheric components from adhering to the interface with the oxide semiconductor film 130. It is possible to manufacture a highly reliable transistor 100 with good electrical characteristics.

[0097] Next, a first photolithography step is performed to form a resist mask on the oxide semiconductor film 130. Using this resist mask, a first etching step is carried out to form island-shaped oxide regions. The resist mask is used in the photolithography process and also in the For this purpose, an ink jet method, a printing method, or the like can be appropriately used.

[0098] In the first etching step, the edge portions of the island-shaped oxide semiconductor film 132 are tapered. It is preferable to perform etching so that the edge portions of the island-shaped oxide semiconductor film 132 are tapered. This can improve the coverage of the gate insulating film 111 to be formed later. When a photolithography process is used, etching is performed while the resist mask is being recessed. This allows the tapered shape to be formed.

[0099] The first etching step may be a dry etching or a wet etching, The etching solution for wet etching is phosphoric acid, acetic acid, and A solution of nitric acid, ammonia hydrogen peroxide (31% by weight hydrogen peroxide solution, 28% by weight ammonia water) : water = 5:2:2 (volume ratio)). (manufactured by Gakusha) may also be used.

[0100] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4) and the like) are preferred.

[0101] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur or the like can be used.

[0102] As dry etching, parallel plate type RIE (Reactive Ion Etching) ng) method and ICP (Inductively Coupled Plasma) The etching method (combined plasma etching) can be used. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode, The temperature of the electrode on the substrate side, etc., is adjusted appropriately.

[0103] After the oxide semiconductor film 132 is formed, heat treatment is performed, and the oxide semiconductor film 140 is formed. The temperature of the heat treatment is 150°C or higher and 650°C or lower, preferably 250°C or higher and 450°C or lower. The reaction is carried out in an oxidizing atmosphere or an inert atmosphere. The oxidizing atmosphere is oxygen, ozone, or nitrogen. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases such as oxygen. The above-mentioned oxidizing gases are less than 10 ppm, and the atmosphere is filled with nitrogen or rare gases. The treatment time should be between 3 minutes and 24 hours. The longer the treatment time, the more the amorphous region will be formed. However, if the oxide semiconductor film is heated for more than 24 hours, The heat treatment is not preferable because it reduces productivity. Alternatively, the gate insulating film 111 may be formed after the formation of the insulating film 2.

[0104] The heat treatment allows hydrogen to be released from the oxide semiconductor film 132 and the base insulating film 102 The oxide semiconductor film 132 and the oxide semiconductor film 102 are partially oxidized to the oxygen atoms contained in the oxide semiconductor film 132 and the oxide semiconductor film 102. The conductor film 132 is diffused in the vicinity of the interface.

[0105] There are no particular limitations on the heat treatment device used for the heat treatment, and the heat transfer from a heating element such as a resistance heating element is The apparatus may be equipped with a device for heating the object to be treated by induction or heat radiation. For example, an electric furnace or , GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (L Rapid Thermal Anneal (RTA) equipment The LRTA device can be used with a halogen laser. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure nato The radiation of light (electromagnetic waves) emitted from lamps such as sodium lamps and high-pressure mercury lamps can cause The GRTA device is a device that uses high-temperature gas to heat food. be.

[0106] Here, a method for forming the oxide semiconductor film 140 by a two-step method will be described.

[0107] A first oxide semiconductor film is formed, and then heated for 40 minutes under an atmosphere of nitrogen, oxygen, a rare gas, or dry air. A first heat treatment is performed at a temperature of 0° C. to 750° C. The first heat treatment forms a first oxide film. a first crystalline oxide semiconductor film having a crystalline region is formed in a region including a surface of the oxide semiconductor film; Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and A second heat treatment is performed at a temperature of 0° C. or higher and 750° C. or lower to crystallize the first crystalline oxide semiconductor film. The second oxide semiconductor film is then crystallized upward as a seed for growth (second The first crystalline oxide semiconductor film formed as described above The second crystalline oxide semiconductor film is used as the oxide semiconductor film 130, and the first photolithography The lithography step and the first etching step are performed to form an oxide semiconductor film 132. By performing heat treatment after the formation of the oxide semiconductor film 132 described in the step-by-step method, The semiconductor film 140 can be formed. The treatment equipment is used for the heat treatment performed after the formation of the oxide semiconductor film 132 described in the one-step method. Any of the heat treatment devices may be used.

[0108] Next, the gate insulating film 111 and the first electrode 113 are formed on the oxide semiconductor film 140 ( The gate insulating film 111 is formed in the same manner as the base insulating film 102. The thickness of the gate insulating film 111 is preferably 1 nm or more and 300 nm or less, more preferably 5 It is preferable to set the thickness to between 100 nm and 50 nm.

[0109] The gate insulating film 111 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, or the like. silicon oxide film, silicon oxynitride film, aluminum oxynitride film, or silicon nitride oxide film The gate insulating film 111 may have a single layer structure of a selected insulating film or a laminated structure of these insulating films. In particular, it is preferable that oxygen be contained in a portion in contact with the oxide semiconductor film 103. An insulating film that releases oxygen by heating may be used as the gate insulating film 111. By using an insulating film from which oxygen is released, defects occurring in the oxide semiconductor film 103 can be repaired. As a result, deterioration of the electrical characteristics of the transistor 100 can be suppressed.

[0110] Also, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x> 0, y>0, z>0), hafnium aluminate (HfAl x O y (x>0, y>0) ), and other high-k materials can be used. High-k materials have a high dielectric constant. Therefore, for example, it is possible to obtain the same gate insulating film capacitance as when a silicon oxide film is used as the gate insulating film. Therefore, the physical thickness of the gate insulating film can be increased while maintaining the gate The gate insulating film 111 can be formed of the high-k material in a single layer structure. Alternatively, it may be used as a laminated structure with the insulating film.

[0111] The first electrode 113 is formed by forming a conductive film using the above-mentioned conductive material by a sputtering method. A second photolithography step is performed to form a resist mask over the conductive film, and then The resist mask is used in a second etching process to form a first electrode 113. The thickness of the first electrode 113 is not particularly limited, and may vary depending on the electrical resistance of the conductive material used and the manufacturing process. The time required for this can be determined appropriately.

[0112] The gate insulating film 111 and the conductive film to be the first electrode 113 are not exposed to the air. It is preferable to form the layers continuously.

[0113] The first electrode 113 is made of a conductive material such as aluminum, titanium, chromium, nickel, copper, or iron. Elemental metals consisting of tritium, zirconium, molybdenum, silver, tantalum, or tungsten Metals or alloys containing metals as the main component are used in a single layer structure or a multilayer structure. Single layer structure of aluminum film containing titanium, and double layer structure of titanium film laminated on aluminum film , a two-layer structure in which a titanium film is laminated on a tungsten film, a copper-magnesium-aluminum alloy Two-layer structure with copper film laminated on gold film, titanium film and aluminum film laminated on the titanium film There are three-layer structures, such as a laminate of indium oxide and a titanium film on top of that. A transparent conductive material containing tin oxide or zinc oxide may be used. It also functions as a wiring.

[0114] In addition, between the first electrode 113 and the gate insulating film 111, an In—Ga—Zn— O film, nitrogen-containing In-Sn-O film, nitrogen-containing In-Ga-O film, nitrogen-containing I n-Zn-O film, Sn-O film containing nitrogen, In-O film containing nitrogen, metal nitride film (I It is preferable to provide a film of 5 eV, preferably 5.5 eV. V or more, and in the electrical characteristics of the transistor 100, the threshold voltage is set to The transistor 100 can be a so-called normally-off transistor. For example, when an In-Ga-Zn-O film containing nitrogen is used, at least the oxide An In-Ga-Zn-O film having a higher nitrogen concentration than the compound semiconductor film 140, specifically 7 atomic % or more. is used.

[0115] Next, sidewall insulating films 115a and 115b are formed. 5 (including the sidewall insulating films 115a and 115b) are formed on the underlayer insulating film 102 and the gate It is formed of any of the insulating films described above for the insulating film 111.

[0116] The transistor 100 includes a first region 105, a pair of second regions 107a, 107b, and a In both of the pair of third regions 109a and 109b, a gate insulating film 111 is provided. To achieve such a structure, the gate insulating film 111 and the sidewall insulating film 115 (including sidewall insulating films 115a and 115b) is etched by etching with By using such a structure, the sidewall insulating film 115 is formed. During this process, the gate insulating film 111 can be made to function as an etching stopper. By using the gate insulating film 111 as an etching stopper, the oxide semiconductor film 1 40. Furthermore, the sidewall insulating film 11 The end point of etching when forming the gate electrode 5 can also be easily detected. By making the insulating film 111 function as an etching stopper, the sidewall insulating film The width of 115 (sidewall insulating films 115a and 115b in FIG. 1B) is The pair of second regions 107a, which are low-concentration regions, and the width of the pair of second regions 107b, which are low-concentration regions, are easily controlled. The range of 107b is the width of the sidewall insulating film 115 (the sidewall insulating film in FIG. 1(B)). The low concentration is determined according to the width of the contact area between the gate insulating film 111 and the films 115a and 115b. The larger the range of the concentration region, the larger the first region 10 that functions as a channel forming region. 5 can reduce the electric field applied to the

[0117] First, a sidewall insulating film 115a and a second insulating film 115b are formed on the gate insulating film 111 and the first electrode 113. The insulating film 114 that will become 115b is formed (see FIG. 3B). It can be formed in the same manner as the film 102 and can be any of the insulating films listed above. The thickness of the film 114 is not particularly limited, but by performing the third etching process on the insulating film 114, Sidewall insulating films 115a and 115b are formed (see FIG. 3(C)). The etching process is a highly anisotropic etching process. b is formed in a self-aligned manner by performing a highly anisotropic etching process on the insulating film 114. Here, dry etching is preferred as highly anisotropic etching. For example, trifluoromethane (CHF3), octafluoromethane (OCF4), Fluorine-containing gases such as cyclobutane (C4F8) and tetrafluoromethane (CF4) It can be used with noble gases such as helium (He) or argon (Ar) or hydrogen (H2) Furthermore, dry etching may be performed by applying a high frequency voltage to the substrate. It is preferable to use reactive ion etching (RIE).

[0118] The dopant concentration of the pair of second regions 107a and 107b is the same as that of the sidewall insulating film. The thickness of the pair of second regions 107a and 107b corresponds to the thickness of the pair of second regions 115a and 115b. The dopant concentration of the sidewall insulating films 115a and 115b is adjusted to the above-mentioned value. The thickness of the first electrode 113 and the thickness of the second electrode 114 may be determined. The thickness of the insulating films 115a and 115b is the thickness of the first insulating film 115a from the surface in contact with the gate insulating film 111. This refers to the top of the surface that is in contact with the electrode 113.

[0119] The range of the pair of second regions 107a and 107b, which are low concentration regions, is The width of the insulating film 115 (here, the sidewall insulating films 115a and 115b in FIG. 1(B) The width of the gate insulating film 111 is determined by the sidewall insulating film. The width of the film 115 corresponds to the thickness of the first electrode 113, so that the pair of second regions 107 The thickness of the first electrode 113 may be determined so that the range of a and 107b is within a desired range. stomach.

[0120] Next, a process of adding a dopant 150 to the oxide semiconductor film 140 is performed. 103 is formed (see FIG. 3(D)).

[0121] The dopant 150 to be added is one or more elements selected from hydrogen or rare gas elements. The dopant 150 can be added to the oxide semiconductor film 140 by ion implantation. The ion doping method or the ion implantation method can be used. By using a doping method or an ion implantation method, the dopant 150 is doped to a depth (the doping region) becomes easier to control, and the dopant 150 is doped into the oxide semiconductor film 140 with precision. In addition, it is possible to add a layer by ion doping or ion implantation. The dopant 150 may be added while the substrate 101 is heated. Instead of ion doping or ion implantation, dopants to be added and generating plasma in a gas atmosphere containing the compound, and performing plasma treatment on the material to be added. Dopants can also be added.

[0122] Hydrogen functions as an electron donor (donor) in the oxide semiconductor film 140, and the oxide semiconductor film The rare gas element also creates defects in the oxide semiconductor film 140, which can cause oxidation. The compound semiconductor film 140 is made N-type. Note that hydrogen is easily diffused, and the channel forming region If hydrogen diffuses into the first region 105, the transistor characteristics may be deteriorated. Therefore, it is preferable to use a rare gas element as the dopant 150.

[0123] In addition, an element with a large atomic radius such as a rare gas is used as the dopant 150, and the plasma treatment In the case of adding, the gate insulating film is a first region, a pair of second regions, and a pair of third regions. For example, the transistor 100 may have a source region A pair of third regions 109a and 109b, which will become drain regions, are exposed. When the plasma treatment is performed, the pair of third regions 109a and 109b of the oxide semiconductor film 140 are The portion that will become 9b may be etched and thinned. a first region 105, a pair of second regions 107a, 107b, and a pair of third regions 109a; 109b, the gate insulating film 111 is formed on the oxide semiconductor film 14 Prevents etching of the portions that will become the pair of third regions 109a and 109b of 0, thereby suppressing thinning. In addition, the interface between the oxide semiconductor film 103 and the gate insulating film 111 can be kept clean. Therefore, the electrical characteristics and reliability of the transistor 100 can be improved.

[0124] When the dopant 150 is added to the oxide semiconductor film 140, the dopant 150 is The oxide semiconductor film 140 passes through the film 111 and the sidewall insulating films 115a and 115b. The amount of the dopant 150 added to the oxide semiconductor film 140 is The region where doping occurs through only the gate insulating film 111 is doped, and the region where doping occurs through the gate insulating film 111 and the sidewall is doped. The area doped through the wall insulating films 115a and 115b is smaller. The pair of second regions 107a, 107b and the pair of third regions 109a, 109b are self-contained. The dopant 150 is formed in a well-aligned manner (see FIG. 3(E)). The oxide semiconductor film 140 in the region overlapping with the oxide semiconductor film 3 is not doped.

[0125] Furthermore, a pair of second regions 107a and 107b and a pair of third regions 109a and 109b The crystallinity of the dopant 150 is reduced due to damage caused by the addition of the dopant 150, and the dopant 150 becomes an amorphous region. The amount of damage can be reduced by adjusting the amount of dopant 150 added, The pair of second regions 107a, 107b and the pair of third regions 109a, 109b are completely It is also possible to form the pair of second regions 107 so as not to become amorphous regions. a, 107b and a pair of third regions 109a, 109b are formed in at least the first region 105 The ratio of amorphous regions is larger than that of the amorphous regions.

[0126] After adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as that performed when forming the compound semiconductor film 140, but The temperature at which the regions 107a and 107b and the pair of third regions 109a and 109b do not crystallize is preferable.

[0127] Note that the process of adding the dopant 150 to the oxide semiconductor film 140 may be performed multiple times. When the treatment of adding the dopant 150 to the oxide semiconductor film 140 is performed multiple times, The number 150 may be the same for all the multiple times, or may be changed for each processing. For example, after forming the first electrode 113 as shown in FIG. 3(A), a dopant 150 is added. A process of adding SiO 2 (first addition process) is performed to form sidewall insulating films 115a and 115b. After that, a process of adding the dopant 150 again (a second addition process) may be performed. The dopant 150 in the first doping process and the second doping process may be the same element or different elements. It can be plain.

[0128] Next, the gate insulating film 111, the sidewall insulating films 115a and 115b, and the first electrode 1 An insulating film that will become the interlayer insulating film 117 is formed on the insulating film 113, and a second insulating film is formed on the insulating film and the gate insulating film 111. The third photolithography step and the fourth etching step are performed to form openings 116a and 116b. The third photolithography step and the fourth etching step form the first photo The same process as the lithography process and the first etching process may be carried out.

[0129] The interlayer insulating film 117 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or The silicon nitride film may be formed by sputtering, CVD, or the like. It is preferable to use a film that does not easily release oxygen when heated for the interlayer insulating film 117. The pair of second regions 107a and 107b and the pair of third regions 109a and 109b are introduced. Specifically, the CVD method is used to produce a thin film using silane gas as the main material. Select an appropriate source gas from nitrogen oxide gas, nitrogen gas, hydrogen gas, and rare gas, and The substrate temperature should be between 300°C and 550°C. By using the VD method, it is possible to produce a film that does not easily release oxygen when heated.

[0130] Next, the pair of third regions 109a and 109b are connected through the openings 116a and 116b. Then, a second electrode 119a and a third electrode 119b are formed (see FIG. 1B).

[0131] The second electrode 119a and the third electrode 119b each function as wiring, and the first electrode 113 and the like.

[0132] In the transistor 100, the second electrode 119a and the third electrode 119b are in contact with each other. The pair of third regions 109a and 109b are regions with high conductivity to which dopants are added. Therefore, the second electrode 119a and the third electrode 119b and the pair of third regions 109a Since the contact resistance of 109b can be reduced, the on-current of the transistor 100 can be increased. This can be done.

[0133] The second electrode 119a and the third electrode 119b are electrically conductive as described above, similar to the first electrode 113. A conductive film is formed using a material, and the conductive film is subjected to a fourth photolithography step and a fifth etching step. The fourth photolithography step and the fifth etching step are performed to form the insulating film. The etching process may be the same as the first photolithography process and the first etching process. good.

[0134] In this manner, the transistor 100 can be manufactured.

[0135] As described above, in one embodiment of the disclosed invention, problems associated with miniaturization can be solved. As a result, it becomes possible to make the transistor size sufficiently small. By making the size of the capacitors sufficiently small, the area occupied by the semiconductor device is reduced, This increases the number of devices that can be produced, thereby reducing the manufacturing cost per semiconductor device. In addition, semiconductor devices are becoming smaller while maintaining the same functionality, so if the size is to be kept the same, Furthermore, a semiconductor device with further improved functionality can be realized. The reduction in size can also have the effect of increasing the speed of operation and reducing power consumption. According to one embodiment of the present invention, miniaturization of a transistor including an oxide semiconductor can be achieved. This embodiment can provide various effects associated therewith. It can be appropriately combined with the above form.

[0136] (Embodiment 2) In this embodiment, a transistor having a structure partially different from that of the transistor 100 described in Embodiment 1 is used. We will now explain about Zista 200.

[0137] <Structure and Features of Transistor 200> The transistor 200 is a transistor in which the shape of the gate insulating film 111 of the transistor 100 is different. It is a pedestrian.

[0138] FIG. 4A is a plan view of the transistor 200. In FIG. 4A, the base insulating layer The insulating film 202, the gate insulating film 211, and the interlayer insulating film 217 are not shown for convenience.

[0139] 4A, the first electrode 213 and the first electrode 213 A sidewall insulating film 215 is provided on the side surface of the second electrode. The third electrode 219a and the third electrode 219b are exposed to the oxide semiconductor film 219b through the openings 216a and 216b. The second electrode 219a is provided on the third region 209a, 209b of the semiconductor substrate 203. The third electrode 219b is in contact with the upper surfaces of the third regions 209a and 209b. The transistor 200 is a top-gate, top-contact type transistor.

[0140] FIG. 4B is a cross-sectional view of the transistor 200 taken along a line C and D. An insulating base film 202 is provided on a substrate 201, and a first region is formed on the insulating base film 202. region 205, a pair of second regions 207a, 207b and a pair of third regions 209a, 209 The oxide semiconductor film 203 includes a pair of second regions 207a and 207b. The pair of third regions 209a, 209b are provided in contact with the side surfaces of the first region 205. b is provided in contact with the side surfaces of the pair of second regions 207a and 207b.

[0141] A gate insulating film 211 is provided over the oxide semiconductor film 203. , and is in contact with the first region 205. On the gate insulating film 211, The first electrode 213 is provided with a sidewall. Insulating films 215a and 215b are provided in contact with each other.

[0142] The second electrode 219a and the third electrode 219b are connected to the first electrode 213 and the sidewall insulation. Openings 216a and 216b of an interlayer insulating film 217 provided on the insulating films 215a and 215b are formed. The third regions 209a and 209b are in contact with the upper surfaces of the pair of third regions 209a and 209b via the gap.

[0143] The ends of the second electrode 219a and the third electrode 219b may be tapered. The end of the first electrode 213 is preferably vertical. The first electrode 213 is formed in a straight shape, and a sidewall insulating film 215 (sidewall insulating By forming an insulating film that becomes the film 215a, 215b) and performing highly anisotropic etching, By forming the sidewall insulating film 215 (sidewall insulating films 215a and 215b), This can be done.

[0144] 4A, the second regions 207a and 207b are formed on the sides of the oxide semiconductor film 203. This corresponds to the region overlapping with the sidewall insulating film 215. is at least a part of the first electrode 213 other than the side surface of the first electrode 213 and the region in contact with the gate insulating film 211. has a curved shape.

[0145] The transistor 100 has a gate insulating film 111 formed between the first region 105 and a pair of second regions 10 7a, 107b and the pair of third regions 109a, 109b, the opening 11 6a and 116b are provided on the gate insulating film 111 and the interlayer insulating film 117. In the transistor 200, the gate insulating film 211 is in contact with only the first region 205, so that the opening The portions 216 a and 216 b are provided only on the interlayer insulating film 217 .

[0146] In the transistor 200, the gate insulating film 211 is in contact with the first region 205. Therefore, the gate insulating film 211 does not cover the oxide semiconductor film 203 along the shape (step). In other words, the gate insulating film 211 has a portion that overcomes the step of the oxide semiconductor film 203. The gate insulating film 211 does not have a portion where it crosses over the step of the oxide semiconductor film 203. Since there is no gate insulating film 211, the transistor 200 does not generate leakage current due to the gate insulating film 211. Therefore, the gate insulating film 211 can be made thicker and the breakdown voltage of the gate insulating film 211 can be increased. The transistor can be operated even when the film 211 is thinned to nearly 5 nm. By thinning the gate insulating film 211, the short channel effect can be suppressed and the transistor can be This allows for faster operation of the star.

[0147] Furthermore, since the transistor 200 does not have a step-overcoming portion of the gate insulating film 211, The electrode 213, the pair of second regions 207a, 207b, and the pair of third regions 209a, 209b are connected to each other. Therefore, the transistor 200 has a channel Even when the length is reduced, the fluctuation in the threshold voltage can be reduced.

[0148] <Method of manufacturing transistor 200> Next, a manufacturing method of the transistor 200 will be described with reference to FIGS.

[0149] In the method for manufacturing the transistor 200, before forming the insulating film 210 that will become the gate insulating film 211, The process in step 3 (the process of forming the oxide semiconductor film 140 in FIG. 2) is the same as that in the transistor 100. Therefore, reference can be made to the first embodiment (see FIG. 2). Note that the substrate 201 and the underlying insulating film 202 is the same as the substrate 101 and the base insulating film 102 described in the first embodiment. good.

[0150] Next, the insulating film 210 is formed over the oxide semiconductor film 140. The insulating film 210 is the same as that described in Embodiment 1. The insulating film 210 is formed of a material that can be used as the gate insulating film 111. A conductive film 212 to be a first electrode 213 is formed thereon (see FIG. 5A). The conductive material can be used for the first electrode 113 described in Embodiment 1. The conductive film 212 can be formed by sputtering in the same manner as in the first embodiment. good.

[0151] The insulating film 210 and the conductive film 212 are formed successively without being exposed to the air. is preferred.

[0152] The insulating film 210 and the conductive film 212 are processed to form a gate insulating film 211 and a first electrode 213. By this processing, the shape of the gate insulating film 111 of the transistor 100 is different from that of the gate insulating film 111 of the transistor 100. The gate insulating film 211 can be formed. The process is carried out by appropriately using the photolithography process and etching process described in the first embodiment. The thickness of the gate insulating film 211 is determined appropriately based on the details explained in the first embodiment. Just do it.

[0153] Next, a sidewall is formed on the oxide semiconductor film 140, the gate insulating film 211, and the first electrode 213. An insulating film 214 that will become the insulating films 215a and 215b is formed (see FIG. 5(B)). The film 214 is formed of a material that can be used as the base insulating film 102 in the first embodiment. Thereafter, the insulating film 214 is processed to form sidewall insulating films 215a and 215b. (See FIG. 5(C)). The insulating film 214 is processed into sidewall insulating films 215a and 215b. The method is to form the insulating film 114 described in the first embodiment into sidewall insulating films 115a and 115b. The same method as for processing 15b can be used.

[0154] The thickness of the sidewall insulating films 215a and 215b is set to be equal to the thickness of the oxide semiconductor film 203 to be formed later. The surface of the oxide semiconductor film 140 is in contact with the first electrode 213. The dopant of the pair of second regions 207a and 207b to be formed later is The concentration of arsenic in the sidewall insulating films 215a and 215b corresponds to the thickness of the sidewall insulating films 215a and 215b. The dopant concentrations of the second regions 207a and 207b are set to the values ​​described in the first embodiment. As shown in the figure, the thickness of the sidewall insulating films 215a and 215b and the thickness of the first electrode 213 are Just decide the size.

[0155] The range of the pair of second regions 207a and 207b, which are low concentration regions, is The width of the insulating film 215 (here, the sidewall insulating films 215a and 215b in FIG. 4(B) The width of the low concentration region is determined by the width of the oxide semiconductor film 203. This reduces the electric field applied to the first region 205 that functions as a channel forming region. The width of the sidewall insulating film 215 corresponds to the thickness of the first electrode 213. Therefore, the range of the pair of second regions 207a and 207b is set to a desired range. The thickness of the first electrode 213 may be determined.

[0156] Next, a process of adding a dopant 150 to the oxide semiconductor film 140 is performed (see FIG. 5D). The process of adding the dopant 150 to the oxide semiconductor film 140 is the same as that in Embodiment 1. By this process, the first region 205 and the pair of second regions 207a , 207b and a pair of third regions 209a, 209b are formed (see FIG. 5(E)). The first region 205, the pair of second regions 207a, and the The first region 07b and the pair of third regions 209a and 209b are the same as the first region described in the first embodiment. 105, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b It has the same configuration as above.

[0157] Furthermore, the dopant 150 can be added by ion doping or ion implantation. For example, a method other than the injection of a gas containing a dopant can be used. Plasma is generated in the atmosphere, and the material to be added (here, the oxide semiconductor film 140) is The plasma treatment is carried out by irradiating the plasma using a device such as: Dry etching equipment, plasma CVD equipment, high density plasma CVD equipment, etc. The plasma treatment may be performed while the substrate 201 is being heated.

[0158] As in the transistor 200, a pair of third regions 209a and 209b of the oxide semiconductor film 140 When the portion to be formed as 9b is exposed, a rare gas element is used as a dopant and plasma treatment is performed. When the doping is carried out in this manner, a pair of third regions 209a and 209b are formed as described in the first embodiment. Therefore, the pair of third regions 209 When the portions of the oxide semiconductor film 140 that are to become 209a and 209b are exposed, the dopant is It is preferable to use hydrogen as the hydrogen atom.

[0159] Note that the process of adding the dopant 150 to the oxide semiconductor film 140 is the same as that in Embodiment 1. can be performed multiple times.

[0160] After adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as that performed when forming the compound semiconductor film 140, but The temperature at which the regions 207a, 207b and the pair of third regions 209a, 209b do not crystallize is preferable.

[0161] Next, the interlayer insulating film 217, the openings 216a and 216b, the second electrode 219a and the third electrode 219b are formed. The electrode 219b is formed by the interlayer insulating film 117, the openings 116a, 116b, and the The second electrode 119a and the third electrode 119b may be formed in the same manner as the second electrode 119a and the third electrode 119b. A transistor 200 can be manufactured (see FIG. 4B).

[0162] The transistor 200 described in this embodiment can achieve the same effects as those in the first embodiment. Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0163] (Embodiment 3) In this embodiment mode, a transistor having a structure partially different from that of the transistor described in the previous embodiment mode is used. Next, the controller 300 will be described.

[0164] <Structure and Features of Transistor 300> The transistor 300 includes a pair of third regions of the second electrode 219a and the third electrode 219b. It differs from transistor 200 in the surfaces in contact with 209a and 209b.

[0165] FIG. 6A is a plan view of the transistor 300. In FIG. 6A, the base insulating layer The insulating film 302, the gate insulating film 311, and the interlayer insulating film 317 are not shown for convenience.

[0166] 6A, the first electrode 313 and the first electrode 313 A sidewall insulating film 315 is provided on the side surface of the second electrode. The third electrode 319a and the third electrode 319b are formed in the third region 309a and the third region 309b of the oxide semiconductor film 303. The transistor 300 has a top gate structure and a bottom contact structure. This is a transistor.

[0167] FIG. 6B is a cross-sectional view of the transistor 300 between E and F. A base insulating film 302 is provided on a substrate 301, and a first region is formed on the base insulating film 302. a pair of second regions 307a, 307b and a pair of third regions 309a, 309b; b, a second electrode 319a, and a third electrode 319b are provided. The pair of second regions 307a and 307b are in contact with the side surfaces of the first region 305. The pair of third regions 309a and 309b are provided between the pair of second regions 307a and It is provided adjacent to the side of 307b.

[0168] A gate insulating film 311 is provided over the oxide semiconductor film 303. , and is in contact with the first region 305. On the gate insulating film 311, The first electrode 313 is provided with a sidewall. Insulating films 315a and 315b are provided in contact with each other.

[0169] On the gate insulating film 311, the first electrode 313, and the sidewall insulating films 315a and 315b An interlayer insulating film 317 is provided on the substrate.

[0170] The ends of the second electrode 319a and the third electrode 319b may be tapered. The end of the first electrode 313 is preferably vertical. The first electrode 313 is formed in a straight shape, and a sidewall insulating film 315 (sidewall insulating By forming an insulating film that becomes the film 315a, 315b) and performing highly anisotropic etching, By forming the sidewall insulating film 315 (sidewall insulating films 315a and 315b), This can be done.

[0171] 6A, the second regions 307a and 307b are formed on the sides of the oxide semiconductor film 303. This corresponds to the region overlapping with the sidewall insulating film 315. is at least a part of the first electrode 313 other than the side surface of the first electrode 313 and the region in contact with the gate insulating film 311. has a curved shape.

[0172] In the transistor 300, the gate insulating film 311 is in contact with the first region 305. Therefore, the gate insulating film 311 does not cover the oxide semiconductor film 303 along the shape (step). In other words, the gate insulating film 311 has a portion that overcomes the step of the oxide semiconductor film 303. There is no part where the gate insulating film 311 goes over the step of the oxide semiconductor film 303. Since there is no gate insulating film 311, the transistor 300 does not generate leakage current due to the gate insulating film 311. Therefore, the gate insulating film 311 can be made thicker and the breakdown voltage of the gate insulating film 311 can be increased. The transistor can be operated even when the film 311 is thinned to nearly 5 nm. By thinning the gate insulating film 311, the short channel effect can be suppressed and the transistor This allows for faster operation of the star.

[0173] Furthermore, since the transistor 300 does not have a step-overcoming portion of the gate insulating film 311, The electrode 313, the pair of second regions 307a and 307b, and the pair of third regions 309a and 309b are Therefore, the transistor 300 has a channel Even when the length is reduced, the fluctuation in the threshold voltage can be reduced.

[0174] In addition, in the transistor 300 shown in FIG. 6, the gate insulating film 311 is in contact with the first electrode 313. Although the gate insulating film 311 is provided only in the region corresponding to the first embodiment, Similarly, the third regions 309a, 309b (and also the second electrode 319a and the third electrode 31 9b) may also be provided on the

[0175] <Method of manufacturing transistor 300> Next, a method for manufacturing the transistor 300 will be described with reference to FIGS.

[0176] A base insulating film 302 is formed on a substrate 301, and a second electrode 319a and a second electrode 319b are formed on the base insulating film 302. A conductive film that will become the second electrode 319a and the third electrode 319b is formed, and the conductive film is processed to form the second electrode 319a and the third electrode 319b. The substrate 301 and the base insulating film 302 are the same as those described in the first embodiment. The conductive film may have the same structure as the substrate 101 and the base insulating film 102 described in the embodiment. Conductive materials that can be used for the second electrode 119a and the third electrode 119b described in 1 The conductive film is formed by sputtering, as in the first embodiment. The conductive film may be processed by the photolithography process described in Embodiment 1. and etching steps may be used as appropriate.

[0177] The oxide semiconductor film 34 is formed over the base insulating film 302, the second electrode 319a, and the third electrode 319b. The oxide semiconductor film 340 is formed using the oxide semiconductor film described in Embodiment 1 (see FIG. 7A). It can be formed in the same manner as the compound semiconductor film 140 (see FIG. 2).

[0178] Next, a gate electrode 319a, a third electrode 319b, and an oxide semiconductor film 340 were formed over the second electrode 319a, the third electrode 319b, and the oxide semiconductor film 340. An insulating film 311 and a first electrode 313 are formed. An insulating film that will become the gate insulating film 311 is formed. The gate insulating film 311 and the first electrode 313 are They may be formed in the same manner as the gate insulating film 211 and the first electrode 213 in the second embodiment.

[0179] Next, a sidewall is formed on the oxide semiconductor film 340, the gate insulating film 311, and the first electrode 313. An insulating film 314 that will become the insulating films 315a and 315b is formed (see FIG. 7(B)). The film 314 is formed of a material that can be used as the base insulating film 102 in the first embodiment. Thereafter, the insulating film 314 is processed to form sidewall insulating films 315a and 315b. (See FIG. 7(C)). The insulating film 314 is processed into sidewall insulating films 315a and 315b. The method is to form the insulating film 114 described in the first embodiment into sidewall insulating films 115a and 115b. The same method as for processing 15b can be used.

[0180] The thickness of the sidewall insulating films 315a and 315b is set to be equal to the thickness of the oxide semiconductor film 303 later. The surface of the oxide semiconductor film 340 is in contact with the first electrode 313. The dopant of the pair of second regions 307a and 307b to be formed later is The concentration of arsenic in the sidewall insulating films 315a and 315b corresponds to the thickness of the sidewall insulating films 315a and 315b. The dopant concentrations of the second regions 307a and 307b are set to the values ​​described in the first embodiment. As shown in the figure, the thickness of the sidewall insulating films 315a and 315b and the thickness of the first electrode 313 are Just decide the size.

[0181] The range of the pair of second regions 307a and 307b, which are low concentration regions, is The width of the insulating film 315 (here, the sidewall insulating films 315a and 315b in FIG. 6(B) The width of the low concentration region is determined by the width of the oxide semiconductor film 340. This reduces the electric field applied to the first region 305 which functions as a channel forming region. The width of the sidewall insulating film 315 corresponds to the thickness of the first electrode 313. Therefore, the range of the pair of second regions 307a and 307b is set to a desired range. The thickness of the first electrode 313 may be determined.

[0182] Next, a process of adding the dopant 150 to the oxide semiconductor film 340 is performed (see FIG. 7D). The process of adding the dopant 150 to the oxide semiconductor film 340 is the same as that in Embodiment 1. By this process, the first region 305 and the pair of second regions 307a , 307b and a pair of third regions 309a, 309b are formed (see FIG. 7(E)). The first region 305, the pair of second regions 307a, and the The first region 307b and the pair of third regions 309a and 309b are the same as the first region described in the first embodiment. 105, a pair of second regions 107a, 107b and a pair of third regions 109a, 109b It has the same configuration as above.

[0183] Furthermore, like the transistor 200, the transistor 300 has an oxide semiconductor film 340. The dopant 150 is added in a state where a part of the dopant 150 is exposed. As a method for adding 50, plasma treatment can be used as in the second embodiment. The plasma treatment is the same as the plasma treatment described in the second embodiment.

[0184] As in the transistor 300, a pair of third regions 309a and 309b of the oxide semiconductor film 340 When the portion to be formed as 9b is exposed, a rare gas element is used as a dopant and plasma treatment is performed. When doped in this manner, a pair of third regions 309a and 309b are formed as described in the first embodiment. Therefore, the pair of third regions 309 may be etched and thinned. When the portions of the oxide semiconductor film 340 that will become 309a and 309b are exposed, the dopant is It is preferable to use hydrogen as the hydrogen atom.

[0185] Further, the gate insulating film 311 is formed in the third regions 309a and 309b (and In addition, the second electrode 319a and the third electrode 319b may also be provided on the second electrode 319a and the third electrode 319b. Even if the oxide semiconductor film 340 is not oxidized, the treatment of adding the dopant 150 to the oxide semiconductor film 340 can be performed. At this time, the dopant 150 is mixed with the gate insulating film 311 and the sidewall insulating films 315a, 315b, 315c, 315d, 315e, 315f, 315g, 315h ... 15b and is added to the oxide semiconductor film 340. Noble gas elements can be used as Panto 150 without any problems.

[0186] Note that the process of adding the dopant 150 to the oxide semiconductor film 340 is the same as that in the first embodiment. can be performed multiple times.

[0187] After adding the dopant 150, a heat treatment may be performed. The heat treatment may be performed in the same manner as that performed when forming the compound semiconductor film 340, but The temperature at which the regions 307a, 307b and the pair of third regions 309a, 309b do not crystallize is preferable.

[0188] Next, the first electrode 313, the second electrode 319a, the third electrode 319b, and the sidewall On the interlayer insulating films 315a and 315b, the layer described in the first embodiment is formed as an interlayer insulating film 317. The insulating film 117 is formed in the same manner as the insulating film 117. In this manner, the transistor 300 is fabricated. This is possible (see Figure 6(B)).

[0189] The transistor 300 described in this embodiment can achieve the same effects as those in the first embodiment. Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0190] (Fourth embodiment) In this embodiment, in the transistors described in Embodiments 1 to 3, The first region, the pair of second regions, and the pair of third regions included in the compound semiconductor film form a transistor. The influence of the electrical characteristics on the transistor shown in Figure 6 is explained using a band diagram. The following description will be given taking the printer 300 as an example.

[0191] 8A and 8B are cross-sections of the transistor 300 (see FIG. 6B) between G and H. The energy band diagram (schematic diagram) in FIG. 8(B) shows the source and drain regions. The voltage between the gate regions is set to an equipotential (VD=0V). The first region 305 (OS1) and a pair of second regions 307a and 307b (OS2) are and a pair of third regions 309a and 309b (referred to as OS3). The film 303, the second electrode 319a and the third electrode 319b (assumed to be metal) It is a transistor having

[0192] The channel forming region of the transistor 300 is formed by OS1. To remove and desorb as much impurities as possible, such as moisture (including hydrogen), to achieve high purity. The oxide semiconductor is made intrinsic (I-type) by By doing so, the Fermi level (Ef) is It can be made the same level as i).

[0193] The low concentration region of the transistor 300 is formed of OS2, and the source region and The drain region is formed by OS3. OS2 and OS3 are formed by the same , remove and desorb impurities such as moisture (including hydrogen) from the film as much as possible to achieve high purity. By this, an oxide semiconductor is made to be intrinsic (I-type) or as close to intrinsic as possible, and and then adding one or more dopants selected from hydrogen or rare gas elements. This causes the oxygen vacancies to form, or the OS2 and OS In 3, the carrier density is higher than in OS1, and the Fermi level is closer to the conduction band. do.

[0194] FIG. 8A shows a vacuum level (referred to as Evac), a first region 305 (referred to as OS1), a pair of a pair of second regions 307a and 307b (referred to as OS2); a pair of third regions 309a and 309b; b (defined as OS3), the second electrode 319a and the third electrode 319b (defined as metal) Here, IP is the ionization potential, Ea is the electron affinity, Eg is the band gap, Wf is the work function, Ec is the bottom of the conduction band, and Ev is the valence charge. The upper end of the electron band, Ef, indicates the Fermi level. The symbols at the end of each symbol are 1 for OS1. , 2 indicates OS2, 3 indicates OS3, and m indicates metal. The metal assumed has a Wf_m of 4.1 eV (such as titanium).

[0195] OS1 is a highly purified oxide semiconductor with extremely low carrier density, so Ef_1 The dopant is added to OS2 and OS3. It is an oxide semiconductor with a high carrier density, and Ec_2 and Ef_2 are The oxide semiconductors shown in OS1, OS2, and OS3 have band gaps (E g) is said to be 3.15 eV and the electron affinity (Ea) is 4.3 eV.

[0196] As shown in Figure 8(B), the channel formation region OS1 and the low concentration region OS2 are in contact. When the two contact, carriers move so that the Fermi levels of OS1 and OS2 coincide. The band edges of OS1 and OS2 are bent. When the drain region of OS3 is in contact with the source region of OS2, the Fermi levels of OS2 and OS3 are the same. As a result, carriers move and the band edges of OS2 and OS3 bend. When the OS3 in the source and drain regions comes into contact with metal, the The carriers move so that the Fermi levels of the tal coincide, and the band edge of OS3 bends. Gar.

[0197] In this way, the OS1 that becomes the channel and the second electrode 319a and the third electrode 319b are Oxide semiconductors with high carrier density and a difference in carrier density between them and metals The formation of the OS2 and OS3 bodies allows the oxide semiconductor film 303 to contact the metal. The contact can be made ohmic and the contact resistance can be reduced. As a result, the on-current of the transistor 300 can be increased. The band edge bending of S1 can be reduced, so the short channel of transistor 300 This can reduce the leakage effect.

[0198] (Embodiment 5) In this embodiment, an example of a transistor different from the transistor described in the previous embodiment will be described. This will be explained with reference to FIG.

[0199] 9A is a cross-sectional view of the transistor 400, and FIG. 9B is an enlarged view of the dotted line portion of FIG. 9A. That's quite a picture.

[0200] The structure of the transistor 400 is as follows: A base insulating film 402 is provided on a substrate 401. On the base insulating film 402, a first region 405, a pair of second regions 407a, and four 07b, a pair of third regions 409a, 409b and a pair of fourth regions 410a, 410b The oxide semiconductor film 403 includes a pair of fourth regions 410a and 410b. A second electrode 419a and a third electrode 419b are provided in the first region 405. A pair of second regions 407a, 407b, a pair of third regions 409a, 409b, and a pair of Gates are formed on the fourth regions 410a and 410b, the second electrode 419a, and the third electrode 419b. An insulating film 411 is provided. A first electrode 413 overlaps with the first region 405 to form a gate electrode. It is provided on an insulating film 411 .

[0201] The transistor 400 is a top-gate, top-contact transistor. Unlike the transistor 100, the transistor 200, and the transistor 300, a pair of fourth The regions 410a and 410b are provided.

[0202] A substrate 401, an underlying insulating film 402, a first region 405, a gate insulating film 411, a first electrode 4 13, the second electrode 419a and the third electrode 419b are the same as those of the substrate 10 described in the first embodiment. 1, an underlying insulating film 102, a first region 105, a gate insulating film 111, a first electrode 113, a The second electrode 119a and the third electrode 119b can be formed in the same manner.

[0203] The first region 405, which is a channel forming region, is made of the CAAC oxide semiconductor described in the first embodiment. The pair of fourth regions 410a and 410b are also CAAC regions described in the first embodiment. The pair of second regions 407a and 407b and the pair of third regions 407a and 407b are oxide semiconductor regions. 409a and 409b are amorphous regions containing dopants, and the dopants are The same as that described in the embodiment 1. In addition, the dopant of the pair of second regions 407a and 407b The dopant concentration of the first region 409a is different from the dopant concentration of the pair of third regions 409a, 409b. The dopant of the pair of second regions 407a, 407b and the pair of third regions 409a, 409b The range of the dopant concentration is the range of the dopant concentration described in the first embodiment.

[0204] The transistor 400 is formed by forming the oxide semiconductor film 140 described in Embodiment 1 and then The dopant concentration is controlled by using the first electrode 413, the second electrode 419a and the third electrode 419b. different regions (first region 405, a pair of second regions 407a, 407b and a pair of third regions A pair of fourth regions 409a, 409b, and a pair of fourth regions 410a, 410b can be formed. Cut.

[0205] The pair of third regions 409a and 409b are formed by the second electrode 419a and the third electrode 419b. The second electrode 419a and the third electrode 41 By reducing the thickness of the third regions 409a and 409b, the range of the pair of third regions 409a and 409b can be expanded. This can be done.

[0206] The transistors 100, 200, and 300 are The first electrode and the sidewall insulating film provided in the transistor are used to deposit a dopant. The regions with different concentrations (the first region, the pair of second regions, and A pair of third regions is formed in the transistor.

[0207] As described above, the transistor 400 has the following characteristics: A pair of second regions 407a, 407b and a pair of third regions 40 9a and 409b are provided, and the voltage applied to the first region 405, which is a channel forming region, Since the field can be relaxed, the short channel effect can be suppressed.

[0208] In addition to the transistor 400, a transistor different from the transistor described in the above embodiment may be used. As an example of a transistor, transistor 500 will be described.

[0209] FIG. 9C is a cross-sectional view of the transistor 500, and FIG. 9D is an enlarged view of the dotted line portion of FIG. 9C. That's quite a picture.

[0210] The structure of the transistor 500 is as follows: A base insulating film 402 is provided on a substrate 401. On the base insulating film 402, a first electrode 413 and a second electrode 414 are formed. On the gate insulating film 411, a first region 40 is provided. 5, a pair of second regions 407a, 407b, a pair of third regions 409a, 409b, and a An oxide semiconductor film 403 including a pair of fourth regions 410a and 410b is provided. A second electrode 419a and a third electrode 419b are provided on the fourth regions 410a and 410b. An insulating film 420 is provided on the first region 405 .

[0211] The transistor 500 is a bottom-gate, top-contact transistor. Unlike the transistor 100, the transistor 200, and the transistor 300, a pair of fourth The regions 410a and 410b are provided.

[0212] A substrate 401, an underlying insulating film 402, a first region 405, a gate insulating film 411, a first electrode 4 13, the second electrode 419a and the third electrode 419b are the same as those of the substrate 10 described in the first embodiment. 1, an underlying insulating film 102, a first region 105, a gate insulating film 111, a first electrode 113, a The second electrode 119a and the third electrode 119b can be formed in the same manner. Since the transistor 500 has a bottom gate structure, the first electrode 413 is connected to the second electrode It is preferable that the first electrode 419a and the third electrode 419b have a tapered shape. By forming the gate insulating film 411 in a tapered shape, the coverage of the gate insulating film 411 can be improved. .

[0213] The first region 405, which is a channel forming region, is made of the CAAC oxide semiconductor described in the first embodiment. The pair of fourth regions 410a and 410b are also CAAC regions described in the first embodiment. The pair of second regions 407a and 407b and the pair of third regions 407a and 407b are oxide semiconductor regions. 409a and 409b are amorphous regions containing dopants, and the dopants are The same as that described in the embodiment 1. In addition, the dopant of the pair of second regions 407a and 407b The dopant concentration of the first region 409a is different from the dopant concentration of the pair of third regions 409a, 409b. The dopant of the pair of second regions 407a, 407b and the pair of third regions 409a, 409b The range of the dopant concentration is the range of the dopant concentration described in the first embodiment.

[0214] The transistor 500 includes the oxide semiconductor film 411 described in Embodiment 1 over the gate insulating film 411. After forming the insulating film 140, the second electrode 419a, the third electrode 419b, and the insulating film 420 are formed. By using this, regions with different dopant concentrations (first region 405, a pair of second regions 407a, 407b, a pair of third regions 409a, 409b, a pair of fourth regions 410a, 410 The insulating film 420 can be formed by adding a dopant to the first region 405. It is necessary to form the film thick enough so that it does not get damaged.

[0215] The pair of third regions 409a and 409b are connected to the second electrode 419a and the third electrode 419b. The second electrode 419a and the third electrode 419b are formed in a tapered shape. By reducing the thickness of the pole 419b, the range of the pair of third regions 409a, 409b is expanded. It is possible.

[0216] The transistors 100, 200, and 300 are The first electrode and the sidewall insulating film provided in the transistor are used to deposit a dopant. The regions with different concentrations (the first region, the pair of second regions, and A pair of third regions is formed in the transistor.

[0217] As a result, the transistor 500 is configured as follows: A pair of second regions 407a, 407b and a pair of third regions 40 9a and 409b are provided, and the voltage applied to the first region 405, which is a channel forming region, Since the field can be relaxed, the short channel effect can be suppressed.

[0218] (Sixth embodiment) In this embodiment, a resistor element using an oxide semiconductor to which a dopant is added will be described with reference to FIGS. Describe the child.

[0219] 10A shows a resistor element 600. The configuration of the resistor element 600 will be described below. A base insulating film 602 is provided on a substrate 601. A dopant is deposited on the base insulating film 602. An oxide semiconductor film 603 containing fluorine is provided on the oxide semiconductor film 603. In other words, the resistor 600 includes the oxide semiconductor film 60 The oxide semiconductor film 603 to which a dopant is added is, for example, The gate insulating film 211 is formed on the oxide semiconductor film 140 shown in FIG. 2 (see FIGS. 5A and 5B). and the first electrode 213 is formed by adding a dopant after the first electrode 213 is formed. The conductive films 604a and 604b can be formed by the first conductive film described in the above embodiment. The electrode can be formed from a conductive material that can be used for an electrode.

[0220] 10B shows the resistor element 610. The configuration of the resistor element 610 will be described below. A base insulating film 602 is provided on a substrate 601. A dopant is deposited on the base insulating film 602. An oxide semiconductor film 603 containing arsenic is provided on the oxide semiconductor film 603. A conductive film 606 is provided in contact with part of the insulating film 606 and the oxide semiconductor film 603. The resistor 610 also includes the oxide semiconductor film 60 The oxide semiconductor film 603 to which a dopant is added is, for example, The gate insulating film 211 is formed on the oxide semiconductor film 140 shown in FIG. 2 (see FIGS. 5A and 5B). and the first electrode 213 is formed by adding a dopant after the first electrode 213 is formed. The insulating film 606 can be formed by the base insulating film and the gate insulating film described in the previous embodiment. In addition, the conductive films 604a and 604b may be formed by using an interlayer insulating film as appropriate. The first electrode can be formed from the conductive material described above that can be used for the first electrode. Therefore, the resistor element 610 is formed by the oxide film in contact with the conductive films 604a and 604b, which function as a resistor. The current path of the semiconductor film 603 can be made constant, and a resistor having a more accurate resistance value can be obtained. It is an element.

[0221] (Embodiment 7) FIG. 11A is a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. An example of a memory cell is shown below. a transistor 1160 and a transistor 1162 using an oxide semiconductor for a channel formation region. It is composed of:

[0222] The transistor 1162 using an oxide semiconductor for a channel formation region is It can be made by

[0223] As shown in FIG. 11A, the gate electrode of the transistor 1160 and the gate electrode of the transistor 116 The first transistor is electrically connected to one of the source electrode and the drain electrode of the second transistor. The line (1st Line: also called source line) and the source electrode of the transistor 1160 are It is electrically connected to the second wiring (also called the bit line) and the transistor. The drain electrode 1160 is electrically connected to the third wiring (3rd Line (also called the first signal line) and the source electrode or drain electrode of the transistor 1162 The other of the four lines is electrically connected to the fourth line (also called the second signal line). and the gate electrode of the transistor 1162 are electrically connected to each other.

[0224] A transistor using a material other than an oxide semiconductor, such as single-crystal silicon, in the channel formation region. Since the transistor 1160 can operate at a sufficiently high speed, by using the transistor 1160, It is possible to read out stored contents at high speed. The transistor 1162 used in the formation region has a smaller off-state current than the transistor 1160. Therefore, by turning off the transistor 1162, Therefore, the potential of the gate electrode of the transistor 1160 can be maintained for a very long time. It is Noh.

[0225] By utilizing the feature that the potential of the gate electrode can be maintained, it is possible to write information, It can be stored and read.

[0226] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 1162 is turned on as a potential at which the transistor 1162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 1160 ( After that, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned off. By turning off the transistor 1162, the gate of the transistor 1160 is turned off. The potential of the port electrode is maintained (maintained).

[0227] The off-state current of the transistor 1162 is smaller than that of the transistor 1160. The potential of the gate electrode of the transistor 1160 is maintained for a long time. If the potential of the gate electrode of the transistor 1160 is a potential that turns the transistor 1160 on, The transistor 1160 is kept in an on state for a long time. If the potential of the gate electrode of the transistor 1160 is a potential that turns the transistor 1160 off, For example, the transistor 1160 is kept off for a long period of time.

[0228] Next, the reading of information will be described. As described above, when the transistor 1160 is in the ON state, When the ON or OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When the transistor 1160 is turned on, the potential of the second wiring changes depending on whether the transistor 1160 is turned on or off. For example, when the transistor 1160 is on, the potential of the first wiring The potential of the second wiring is decreased relative to the first wiring. In this state, the potential of the second wiring does not change.

[0229] In this way, in the state where the information is held, the potential of the second wiring is compared with a predetermined potential. This allows the information to be read out.

[0230] Next, the rewriting of information will be explained. The rewriting of information is performed by writing and storing the above information. That is, the potential of the fourth wiring is set to the ON state of the transistor 1162. This turns on the transistor 1162. A potential (potential related to the new information) is applied to the gate electrode of transistor 1160. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 1162. By turning off the starter 1162, the new information is held.

[0231] In this way, the memory cell according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. In other words, high-speed operation of the semiconductor device having memory cells is realized.

[0232] FIG. 11(B) shows an example of a circuit diagram of a memory cell which is an extension of the memory cell shown in FIG. 11(A). Shown below.

[0233] The memory cell 1100 shown in FIG. 11B has a first wiring SL (source line) and a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line) a fifth wiring WL (word line), a transistor 1164 (first transistor), A transistor 1161 (second transistor) and a transistor 1163 (third transistor) The transistor 1164 and the transistor 1163 are A material other than an oxide semiconductor is used for a channel formation region. A compound semiconductor is used for the channel formation region.

[0234] Here, the gate electrode of the transistor 1164 and the source electrode of the transistor 1161 or The first wiring SL and one of the drain electrodes are electrically connected. The source electrode of the transistor 1164 is electrically connected to the drain electrode of the transistor 1164. The second electrode and the source electrode of the transistor 1163 are electrically connected. The wiring BL and the drain electrode of the transistor 1163 are electrically connected to each other. The line S1 and the other of the source electrode and the drain electrode of the transistor 1161 are electrically connected. The fourth wiring S2 and the gate electrode of the transistor 1161 are electrically connected. The fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected to each other.

[0235] Next, the operation of the circuit will be specifically described.

[0236] When writing to the memory cell 1100, the first wiring SL is set to 0 V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1163 is in an off state and the transistor 1161 is in an on state. Note that, when writing is completed, the potential of the fourth wiring S1 is changed before the potential of the third wiring S1 is changed. The wiring S2 is set to 0 V, and the transistor 1161 is turned off.

[0237] As a result, after writing data "1", the node connected to the gate electrode of the transistor 1164 After writing data "0", the potential of node A is approximately 2V. 0V. A charge corresponding to the potential of the third wiring S1 is accumulated in the node A. The off-state current of the transistor 1161 is is small compared to the potential of the gate electrode of the transistor 1164, and the potential of the gate electrode of the transistor 1164 is maintained for a long time. do.

[0238] Next, when reading the memory cell, the first wiring SL is set to 0V and the fifth wiring WL is set to 2V. V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the At this time, the transistor 1163 is in an on state, and the transistor The resistor 1161 is in the OFF state.

[0239] If data is "0", that is, node A is at approximately 0V, transistor 1164 is in the off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. When the voltage at node A is "1", that is, when node A is at about 2 V, transistor 1164 is in an on state. Therefore, the resistance between the second wiring BL and the first wiring SL is low. Data "0" and "1" can be read out from the difference in the resistance state of the memory cell. The second wiring BL is set to 0V during writing, but it is not necessary to set it to a floating state or a potential of 0V or higher. The third wiring S1 is set to 0V during readout, but it can be set to a floating state. It does not matter if the capacitor is in a negative state or is charged to a potential of 0 V or higher.

[0240] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in an on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0241] In this embodiment, for ease of understanding, a memory cell of the minimum storage unit (1 bit) will be explained. However, the configuration of the memory cells is not limited to this. For example, the memory cells can be connected in multiple ways to form a more sophisticated semiconductor device. By using these, it is possible to configure NAND type and NOR type semiconductor devices. The configuration is not limited to that shown in FIG. 11(A) or FIG. 11(B), and can be changed as appropriate.

[0242] FIG. 12 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0243] The semiconductor device shown in FIG. 12 includes m fifth wirings WL(1) to WL(m) and a fourth wiring S 2(1) to S2(m), n second wirings BL(1) to BL(n) and third wiring S1 (1) to S1(n), and a plurality of memory cells 1100(1, 1) to 1100(m, n) are arranged vertically. Memory cells arranged in a matrix of m rows x n columns (m and n are natural numbers). 1110, the second wiring and the third wiring driving circuit 1111, the fourth wiring and the fifth wiring It is composed of peripheral circuits such as a wiring driving circuit 1113 and a readout circuit 1112. As other peripheral circuits, a refresh circuit or the like may be provided.

[0244] Consider memory cell 1100(i, j) as a representative of each memory cell. Rule 1100(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second The wiring BL(j), the third wiring S1(j), the fifth wiring WL(i) and the fourth wiring S2(i ), and the first wiring. A first wiring potential Vs is applied to the first wiring. In addition, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S 1(n) is connected to the second wiring and third wiring driver circuit 1111 and the readout circuit 1112. Also, the fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) is connected to the fourth wire and the fifth wire driving circuit 1113.

[0245] The operation of the semiconductor device shown in Fig. 12 will be described. In this configuration, writing and reading for each row are performed. Perform the extraction.

[0246] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The potential Vs of the first wiring is set to 0V, the potential of the fifth wiring WL(i) is set to 0V, and the potentials of the second wirings BL(1) to BL( The fourth wiring S2(i) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 1161 is turned on. The third wiring S1(1) to S1(n) is in a 2V state. The column to which data "0" is written is set to 0V. Before the potential of the lines S1(1) to S1(n) changes, the fourth line S2(i) is set to 0V, The transistor 1161 is turned off. The unselected fifth wiring WL is set to 0 V. The fourth wiring S2 is set to 0V.

[0247] As a result, the gate voltage of the transistor 1164 of the memory cell in which data "1" is written is The potential of the node connected to the electrode (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the memory cell becomes approximately 0 V (see FIG. 11B and FIG. 12). The potential of node A of the unselected memory cells remains unchanged.

[0248] When reading out the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The first wiring potential Vs is 0V, the fifth wiring WL(i) is 2V, and the fourth wiring S2(i) is 0V. The third wiring S1(1) to S1(n) are set to 0V, and the second wiring BL(1) to BL(n) are set to The connected read circuit is set to an operating state. In the read circuit, for example, The data "0" and "1" can be read out from the difference in the resistance state of the unselected The fifth wiring WL is set to 0V, and the unselected fourth wiring S2 is set to 0V. Although the wiring BL is set to 0V, it may be in a floating state or charged to a potential above 0V. The third wiring S1 was set to 0V during readout, but it may be in a floating state or at a voltage above 0V. It doesn't matter if it's charged to a certain extent.

[0249] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in an on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0250] (Embodiment 8) In this embodiment, an example of a circuit diagram of a memory cell having a capacitor is shown. The memory cell 1170 shown in FIG. 1 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a The wiring S2, the fifth wiring WL, the transistor 1171 (first transistor), and the transistor The transistor 1172 (second transistor) and the capacitor element 1173 are included. The transistor 1171 uses a material other than an oxide semiconductor for a channel formation region. The transistor 1172 has a channel formation region formed using an oxide semiconductor.

[0251] Here, the gate electrode of the transistor 1171 and the source electrode of the transistor 1172 One of the drain electrodes and one of the electrodes of the capacitor 1173 are electrically connected to each other. The first wiring SL and the source electrode of the transistor 1171 are electrically connected to each other. The second wiring BL and the drain electrode of the transistor 1171 are electrically connected to each other. The wiring S1 and the other of the source electrode and the drain electrode of the transistor 1172 are electrically connected to each other. The fourth wiring S2 and the gate electrode of the transistor 1172 are electrically connected to each other. The fifth wiring WL and the other electrode of the capacitor 1173 are electrically connected to each other. .

[0252] Next, the operation of the circuit will be specifically described.

[0253] When writing to the memory cell 1170, the first wiring SL is set to 0V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1172 is turned on. In this case, before the potential of the third wiring S1 changes, the fourth wiring S2 is set to 0 V, and the transistor The inverter 1172 is turned off.

[0254] As a result, after writing data "1", the gate electrode of the transistor 1171 is connected to The potential of the node (hereinafter referred to as node A) is about 2V. After writing data "0", the potential of node A becomes approximately 0V.

[0255] When reading the memory cell 1170, the first wiring SL is set to 0 V, and the fifth wiring WL is set to 2V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and it is connected to the second wiring BL. At this time, the transistor 1172 is turned off. do.

[0256] The state of the transistor 1171 when the fifth wiring WL is set to 2 V will be described. The potential of the node A that determines the state of the transistor 1171 is determined by the capacitance between the fifth wiring WL and the node A. C1 and the capacitance C2 between the gate electrode and the source electrode and the drain electrode of the transistor 1171 Depends on.

[0257] Although the third wiring S1 was set to 0V during readout, it may be set to a floating state or a voltage of 0V or more. The data "1" and data "0" are just definitions for convenience. The opposite is also fine.

[0258] The potential of the third wiring S1 during writing is set to a value that is lower than the value that the transistor 1172 is turned off after writing. In addition, when the potential of the fifth wiring WL is 0V, the transistor 1171 is in an off state. The potentials of the data "0" and "1" can be selected within the range. When the potential is data "0", the transistor 1171 is turned off, and when the potential is data "1", the transistor 1172 is turned off. In this case, the transistor 1171 is turned on. The threshold voltage of the transistor 1171 is also an example. Any threshold value may be used as long as it is within the range.

[0259] Also, a selection transistor having a first gate electrode and a second gate electrode; An example of a NOR type semiconductor memory device using memory cells having the following structure will be described with reference to FIG. 13(B). I will explain.

[0260] The semiconductor device according to one embodiment of the present invention shown in FIG. 13B has I rows (I is a natural number of 2 or more) A memory cell array having a plurality of memory cells arranged in a matrix in columns (J is a natural number). It is equipped with (i).

[0261] The memory cell array shown in FIG. 13B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix (a natural number of i) and i word lines W L (word lines WL_1 to WL_i), and i capacitance lines CL (capacitance lines CL_1 to CL_i). a capacitance line CL_i) and i gate lines BGL (gate line BGL_1 to gate line BGL _i), j bit lines BL (bit lines BL_1 to BL_j), and source lines SL and.

[0262] Furthermore, each of the plurality of memory cells 1180 (memory cells 1180(M,N) (where , N is a natural number between 1 and j, and M is a natural number between 1 and i) 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ) and.

[0263] In the semiconductor memory device, the capacitance element includes a first capacitance electrode, a second capacitance electrode, and The capacitance element is composed of a dielectric layer overlapping the first capacitance electrode and the second capacitance electrode. Charge is accumulated between the first and second capacitance electrodes in response to a voltage applied between the first and second capacitance electrodes.

[0264] The transistor 1181 (M, N) is an N-channel transistor, and has a source electrode, a drain electrode, and a The semiconductor device has a drain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device, the transistor 1181 is not necessarily an N-channel transistor. You don't have to.

[0265] One of the source electrode and the drain electrode of the transistor 1181(M,N) is connected to the bit line BL _N, and the first gate electrode of the transistor 1181(M,N) is connected to the word line WL _M, and the second gate electrode of the transistor 1181(M,N) is connected to the gate line BG The source and drain electrodes of the transistor 1181(M,N) are connected to By configuring one of the terminals to be connected to the bit line BL_N, the The data can be read out.

[0266] The transistor 1181(M,N) is the selected transistor in the memory cell 1180(M,N). It functions as a register.

[0267] The transistor 1181(M,N) is a transistor using an oxide semiconductor for a channel formation region. A transistor can be used.

[0268] The transistor 1182(M,N) is a P-channel transistor. In the semiconductor memory device of this type, the transistor 1182 is not necessarily a P-channel transistor. It doesn't have to be star.

[0269] One of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to the source line SL The other of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to The gate electrode of the transistor 1182(M,N) is connected to the bit line BL_N. The other of the source electrode and drain electrode of the transistor 1181(M, N) is connected to the other of the source electrode and drain electrode of the transistor 1181(M, N).

[0270] The transistor 1182(M,N) is an output transistor in the memory cell 1180(M,N). The transistor 1182 (M, N) has a function as a single-circuit transistor. A transistor using crystalline silicon for a channel formation region can be used.

[0271] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M. The second capacitor electrode of 1183(M,N) is connected to the source electrode of the transistor 1181(M,N). The capacitor 1183(M,N) is connected to the other of the drain electrodes. It has the function as.

[0272] The voltages of the word lines WL_1 to WL_i are controlled by a driver using, for example, a decoder. It is controlled by an operating circuit.

[0273] The voltages of the bit lines BL_1 to BL_j are respectively controlled by a driver using a decoder, for example. It is controlled by an operating circuit.

[0274] The voltages of the capacitance lines CL_1 to CL_i are respectively controlled by a driving circuit using a decoder, for example. It is controlled by the path.

[0275] The voltages of the gate lines BGL_1 to BGL_i are respectively set by the gate line driving circuit, for example. It is controlled using a path.

[0276] The gate line driving circuit may be configured such that, for example, a diode and a first capacitor electrode are connected to the anode and It is configured by a circuit having a capacitance element electrically connected to the gate line BGL.

[0277] By adjusting the voltage of the second gate electrode of transistor 1181, transistor 1 Therefore, the threshold voltage of the transistor 181 that functions as a selection transistor can be adjusted. The threshold voltage of the transistor 1181 is adjusted to reduce the source voltage of the transistor 1181 in the off state. Therefore, the current flowing between the source electrode and the drain electrode can be minimized. The data retention period in the circuit can be extended. The voltage required for readout can be lower than that of conventional semiconductor devices, reducing power consumption It is possible.

[0278] (Embodiment 9) In this embodiment, an example of a semiconductor device including the transistor described in the above embodiment will be described. , will be described with reference to FIG.

[0279] Figure 14(A) shows a so-called DRAM (Dynamic Random Access Memory) An example of a semiconductor device having a structure corresponding to a memory cell shown in FIG. The memory cell array 1120 has a configuration in which a plurality of memory cells 1130 are arranged in a matrix. The memory cell array 1120 has m first wirings and n second wirings. In this embodiment, the first wiring is called a bit line BL, and the second wiring is called a bit line BL. The line is called a word line WL.

[0280] The memory cell 1130 is composed of a transistor 1131 and a capacitor element 1132. The gate electrode of the transistor 1131 is connected to the first wiring (word line WL). In addition, one of the source electrode and the drain electrode of the transistor 1131 is connected to the second wiring. (bit line BL), and the source electrode or drain electrode of the transistor 1131 The other electrode is connected to one of the electrodes of the capacitor element. The transistor 1131 is connected to the capacitance line CL and is given a constant potential. The transistors shown in the embodiment are applied.

[0281] The transistor in which an oxide semiconductor is used for a channel formation region, which is described in the above embodiment, The off-state current is smaller than that of a transistor using single crystal silicon for the channel formation region. Therefore, the so-called DRAM shown in FIG. When the transistor is applied to a semiconductor device, a substantially nonvolatile memory can be obtained. It is possible.

[0282] Figure 14(B) shows a so-called SRAM (Static Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell shown in FIG. The array 1140 is configured such that a plurality of memory cells 1150 are arranged in a matrix. In addition, the memory cell array 1140 includes a first wiring (word line WL), a second wiring (word line WL), and a The memory cell has a plurality of wirings (bit lines BL) and a plurality of third wirings (inverted bit lines / BL).

[0283] The memory cell 1150 includes a first transistor 1151, a second transistor 1152, and a third transistor 1153. The third transistor 1153, the fourth transistor 1154, and the fifth transistor 1155 , and a sixth transistor 1156. The transistor 1152 functions as a selection transistor. One of the first transistor 1153 and the fourth transistor 1154 is an n-channel transistor (here, The other is a p-channel transistor (here, is the third transistor 1153). That is, the third transistor 1153 and the fourth The CMOS circuit is formed by the fifth transistor 1154. The sixth transistor 1155 and the sixth transistor 1156 form a CMOS circuit.

[0284] First transistor 1151, second transistor 1152, fourth transistor 115 The fourth and sixth transistors 1156 are n-channel transistors, and in the previous embodiment, The third transistor 1153 and the transistor shown in the embodiment can be applied. The fifth transistor 1155 is a p-channel transistor made of a material other than an oxide semiconductor. A material (for example, single crystal silicon) is used for the channel formation region.

[0285] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0286] (Embodiment 10) A CPU using at least a part of a transistor in which an oxide semiconductor is used for a channel formation region (Central Processing Unit) can be configured.

[0287] FIG. 15(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an arithmetic logic unit (ALU). nit) 1191, ALU controller 1192, instruction decoder 1193 , interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8, rewritable ROM 1199 and ROM interface (ROM I / F) 1 The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM I / F 1189 may be provided on a separate chip. The CPU shown in 15(A) is merely an example of a simplified configuration, and the actual CPU They have a wide variety of configurations depending on their use.

[0288] The instructions input to the CPU via the Bus I / F 1198 are decoded. The signal is input to the ALU controller 1192, the interrupt controller 1194, register controller 1197, timing controller 119 It is entered into 5.

[0289] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0290] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. It has an internal clock generator that generates the clock signal CLK2, and Supply to the road.

[0291] In the CPU shown in FIG. 15A, a register 1196 is provided with a storage element. The storage element of the starter 1196 can be the storage element described in the eighth embodiment. Cut.

[0292] In the CPU shown in FIG. 15A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the memory element of the data storage device 1196, data is stored by a phase inversion element or a capacitance element. Select whether to hold data by the element. If the capacitance is set to 0, the power supply voltage is supplied to the storage element in the register 1196. If data retention in the element is selected, data is rewritten to the capacitive element. This allows the supply of power supply voltage to the storage element in the register 1196 to be stopped.

[0293] Regarding the power supply shutdown, as shown in FIG. 15(B) or 15(C), the memory element group and the power supply A switching element is provided between nodes to which the potential VDD or the power supply potential VSS is applied. The circuits shown in Figures 15(B) and 15(C) will be explained below. .

[0294] 15B and 15C, a switching element that controls the supply of a power supply potential to a memory element is shown. A memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region, An example is shown below.

[0295] The memory device shown in FIG. 15B includes a switching element 1141 and a memory element 1142. Specifically, each of the storage elements 1142 has a The memory element described in the eighth embodiment can be used. The memory element 1142 receives a high-level power supply potential VD Furthermore, each memory element 1142 included in the memory element group 1143 is supplied with a signal D. The potential of the signal IN and the potential of the low-level power supply potential VSS are applied.

[0296] In FIG. 15B, a switching element 1141 is formed by using an oxide semiconductor as a channel formation region. The transistor has a gate electrode connected to the Switching is controlled by signal SigA.

[0297] In FIG. 15B, the switching element 1141 has only one transistor. However, there is no particular limitation to the configuration, and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0298] In addition, in FIG. 15B, the switching element 1141 The supply of a high-level power supply potential VDD to each memory element 1142 is controlled. Even if the supply of the low-level power supply potential VSS is controlled by the switching element 1141, good.

[0299] In addition, in FIG. 15C, each memory element 1142 included in the memory element group 1143 is provided with a switch. A low-level power supply potential VSS is supplied via the switching element 1141. An example is shown in FIG. 11. The switching element 1141 controls the switching of each memory element included in the memory element group 1143. The supply of a low-level power supply potential VSS to 1142 can be controlled.

[0300] A switch is provided between the memory element group and a node to which the power supply potential VDD or VSS is applied. When the power supply voltage is stopped, the CPU operation is temporarily stopped. It is possible to retain data even if the power is turned off, and power consumption can be reduced. For example, a user of a personal computer may input information into an input device such as a keyboard. Even when the input of information is stopped, the CPU operation can be stopped, thereby reducing power consumption. The force can be reduced.

[0301] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0302] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0303] 100 transistors 101 Substrate 102 Undercoat insulating film 103 Oxide semiconductor film 105 First Area 107a Second Area 107b Second Area 109a The Third Region 109b The Third Realm 111 Gate insulating film 113 First electrode 114 insulating film 115 Sidewall insulating film 115a Sidewall insulating film 115b Sidewall insulating film 117 Interlayer insulating film 119a second electrode 119b Third electrode 116a opening 116b opening 130 Oxide semiconductor film 132 Oxide semiconductor film 140 Oxide semiconductor film 150 Dopant 200 transistors 201 Substrate 202 Undercoat insulating film 203 Oxide semiconductor film 205 First Area 207a Second Area 207b Second Area 209a The Third Region 209b The Third Realm 210 insulating film 211 Gate insulating film 212 Conductive film 213 First electrode 215 Sidewall insulating film 215a Sidewall insulating film 215b Sidewall insulating film 216a opening 216b opening 214 insulating film 217 Interlayer insulating film 219a Second electrode 219b Third electrode 300 transistors 301 Substrate 302 Undercoat insulating film 303 Oxide semiconductor film 305 First Area 307a Second Area 307b Second Realm 309a The Third Realm 309b The Third Realm 311 Gate insulating film 313 First electrode 314 Insulating film 315 Sidewall insulating film 315a Sidewall insulating film 315b Sidewall insulating film 317 Interlayer insulating film 319a Second electrode 319b Third electrode 340 Oxide semiconductor film 400 transistors 401 Substrate 402 Undercoat insulating film 403 Oxide semiconductor film 405 First Area 407a Second Realm 407b Second Realm 409a Third Realm 409b Third Realm 410a Fourth Region 410b Fourth Realm 411 Gate insulating film 413 First electrode 419a Second electrode 419b Third electrode 420 insulating film 500 transistors 600 Resistor element 601 Substrate 602 Undercoat insulating film 603 Oxide semiconductor film 604a Conductive film 604b Conductive film 606 Insulating film 610 Resistor element 1100 memory cells 1110 memory cell array 1111 Wiring drive circuit 1112 readout circuit 1113 Wiring drive circuit 1120 Memory Cell Array 1130 memory cells 1131 Transistor 1132 Capacitor element 1140 Memory Cell Array 1141 Switching element 1142 Memory element 1143 Memory Element Group 1150 memory cells 1151 Transistor 1152 transistor 1153 Transistor 1154 transistor 1155 transistor 1156 Transistor 1160 transistor 1161 Transistor 1162 transistor 1163 Transistor 1164 transistor 1170 memory cells 1171 Transistor 1172 transistors 1173 Capacitor 1180 memory cells 1181 Transistor 1182 transistor 1183 Capacitor 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM

Claims

1. a first insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first insulating film and having a channel formation region; a second insulating film having a region in contact with an upper surface of the oxide semiconductor film and functioning as a gate insulating film; a first conductive film having a region in contact with an upper surface of the second insulating film and functioning as a gate electrode; a third insulating film having a region in contact with an upper surface of the first conductive film; a second conductive film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the third insulating film, the second conductive film functioning as a source electrode; a third conductive film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the third insulating film, and having a function as a drain electrode; When viewed in a cross section in a channel length direction, the oxide semiconductor film includes a first region overlapping with the first conductive film, a pair of second regions in contact with the first region, and a pair of third regions located outside the pair of second regions; the second region has a region that is not in contact with the third insulating film, the third region has a region in contact with the third insulating film, the second conductive film does not have a region overlapping with the second insulating film and does not have a region overlapping with the first conductive film; The third conductive film does not have a region overlapping with the second insulating film and does not have a region overlapping with the first conductive film.

2. a first insulating film; an oxide semiconductor film having a region in contact with an upper surface of the first insulating film and having a channel formation region; a second insulating film having a region in contact with an upper surface of the oxide semiconductor film and functioning as a gate insulating film; a first conductive film having a region in contact with an upper surface of the second insulating film and functioning as a gate electrode; a third insulating film having a region in contact with an upper surface of the first conductive film; a second conductive film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the third insulating film, the second conductive film functioning as a source electrode; a third conductive film having a region in contact with an upper surface of the oxide semiconductor film and a region in contact with an upper surface of the third insulating film, and having a function as a drain electrode; When viewed in a cross section in a channel length direction, the oxide semiconductor film includes a first region overlapping with the first conductive film, a pair of second regions in contact with the first region, and a pair of third regions located outside the pair of second regions; the second region has a region that is not in contact with the third insulating film, the third region has a region in contact with the third insulating film, the second conductive film does not have a region overlapping with the second insulating film and does not have a region overlapping with the first conductive film; the third conductive film does not have a region overlapping with the second insulating film and does not have a region overlapping with the first conductive film; The oxide semiconductor film contains indium, gallium, and zinc.

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