Semiconductor device

Abstract

To provide a technique of manufacturing a semiconductor device including a transistor with high performance and high reliability.SOLUTION: A protective conductive film for protecting an oxide semiconductor layer when a wiring layer is formed of a conductive layer is formed between the oxide semiconductor layer and the conductive layer and two-step etching is performed. A first etching step employs an etching method in which the protective conductive film is etched less easily than the conductive layer and the etching selection ratio between the conductive layer and the protective conductive layer is high. A second etching step employs an etching method in which the protective conductive film is etched more easily than the oxide semiconductor layer and the etching selection ratio between the protective conductive film and the oxide semiconductor layer is high.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, oxide semiconductors that exhibit semiconducting properties have been attracting attention. The body can be applied to a transistor.

[0003] There are many etching methods for oxide semiconductors that are highly reproducible and can obtain the desired shape. Among them, a structure containing an oxide semiconductor containing In, Ga, and Zn is being investigated. In the method for processing a film formed on a semiconductor substrate, an oxide semiconductor layer of a transistor is etched with a halogen-based gas. A technology for chipping has been reported (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-42067 Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, some transistors have a structure in which a wiring layer is provided on a semiconductor layer. However, in the manufacturing process of such a transistor, the conductive layer is etched. When etching the conductive layer on such a semiconductor layer, halogen is also used. The gas used is

[0006] Therefore, when an oxide semiconductor is used as the semiconductor layer in the above structure, the conductive layer is etched. When etching is performed, the oxide semiconductor layer may be etched at the same time.

[0007] If the oxide semiconductor layer is etched in this way, the thickness of the oxide semiconductor layer will be uneven. This causes variations in transistor characteristics and reduces reliability. .

[0008] In a method for manufacturing a semiconductor device including a transistor using an oxide semiconductor, In the etching process, the oxide semiconductor layer located below the conductive layer may be etched. One of the objectives of the present invention is to provide a technology that reduces the

[0009] In a method for manufacturing a semiconductor device including a transistor using an oxide semiconductor, Technology to reduce the impact on transistor characteristics caused by thinning of the conductor layer One of the purposes is to provide the following.

[0010] Also, a technique for manufacturing a semiconductor device having a high-performance, highly reliable transistor is provided. This is one of the purposes of the organization. [Means for solving the problem]

[0011] In a method for manufacturing a semiconductor device including a structure in which a wiring layer is stacked over an oxide semiconductor layer, The conductive layer is etched to form the wiring layer. A protective conductive film for protecting the oxide semiconductor layer is formed between the oxide semiconductor layer and the conductive layer.

[0012] The protective conductive film and conductive layer formed on the oxide semiconductor layer are etched in two steps. The two-stage etching process is performed in two stages: the first etching, which etches the conductive layer; and a third step of etching the protective conductive film until the underlying oxide semiconductor layer is exposed. This is the etching process 2.

[0013] In the first etching step, the oxide semiconductor layer is etched simultaneously with the conductive layer. To prevent the conductive layer from being etched, the conductive layer is made thicker than the etching stopper. On the other hand, in the second etching step, the oxide semiconductor layer The protective conductive film is etched from the oxide semiconductor layer so as to be removed without residue in the exposed region. The membrane must be easily broken down.

[0014] Therefore, the first etching step is performed under conditions where the etching selectivity between the conductive layer and the protective conductive film is high. The second etching step is performed under the condition that the etching selectivity between the protective conductive film and the oxide semiconductor layer is It is carried out under high conditions.

[0015] In this specification, the etching rate of A divided by the etching rate of B is referred to as "A For example, the etching selectivity between the conductive layer and the protective conductive film is defined as the etching selectivity between A and B. The "selectivity ratio" means the value obtained by dividing the etching rate of the conductive layer by the etching rate of the protective conductive film. In this specification, "high etching selectivity" means an etching selectivity of 1 or more. It means that the

[0016] The conductive layer has a high etching selectivity with respect to the protective conductive film, so even if the protective conductive film is thin, It can function as an etching stopper.

[0017] By thinning the protective conductive film, the time required to etch the protective conductive film can be shortened. can.

[0018] The first etching is performed using a chlorine-based gas, and the second etching is performed using a chlorine-based gas and a fluorine-based gas. It is preferable to use a mixed gas of nitrogen-based gases.

[0019] Specifically, the chlorine-based gas may be a mixture of BCl3 and Cl2. An example of a mixed gas of a nitrogen-based gas and a fluorine-based gas is a mixed gas of SF6 and Cl2.

[0020] As a preferred embodiment of one aspect of the method for manufacturing a semiconductor device disclosed in this specification, specifically, The configuration will be explained below.

[0021] One embodiment of a method for manufacturing a semiconductor device disclosed in this specification is a method for forming a gate electrode layer. A gate insulating film is formed on the gate electrode layer, an oxide semiconductor layer is formed on the gate insulating film, and an oxide semiconductor layer is formed on the gate insulating film. A protective conductive film is formed on the compound semiconductor layer, a conductive layer is formed on the protective conductive film, and a resist is formed on the conductive layer. A resist mask is formed, and a first etching process using a chlorine-based gas is performed using the resist mask. The conductive layer is selectively etched to expose the protective conductive film, and the resist mask is used to Then, a second etching process using a mixture of chlorine-based gas and fluorine-based gas is carried out to selectively The protective conductive film is then etched to expose the oxide semiconductor layer and form a wiring layer. An insulating film is formed on the compound semiconductor layer, the protective conductive film, and the wiring layer, and in a first etching step, The protective conductive film is less likely to be etched than the conductive layer, and etching selectivity between the conductive layer and the protective conductive film is low. In the second etching step, the protective conductive film is formed thicker than the oxide semiconductor layer. It is easily etched under conditions where the etching selectivity between the protective conductive film and the oxide semiconductor layer is high. conduct.

[0022] One embodiment of a method for manufacturing a semiconductor device disclosed in this specification includes forming an oxide semiconductor layer, A protective conductive film is formed over the oxide semiconductor layer, a conductive layer is formed over the protective conductive film, and a laser is formed over the conductive layer. A resist mask is formed, and a first etching process using a chlorine-based gas is performed using the resist mask. In the process, the conductive layer is selectively etched to expose the protective conductive film, and the resist mask is removed. The second etching step uses a mixed gas of chlorine-based gas and fluorine-based gas. selectively etching the protective conductive film to expose the oxide semiconductor layer and form a wiring layer; A gate insulating film is formed on the wiring layer, and a gate insulating film is formed in a region on the gate insulating film that overlaps with the oxide semiconductor layer. a protective conductive film formed on the conductive layer; and a first etching step for etching the protective conductive film from the conductive layer. The second etching is performed under conditions in which the etching selectivity between the conductive layer and the protective conductive film is high. In the etching process, the protective conductive film is more easily etched than the oxide semiconductor layer. The etching is performed under conditions where the etching selectivity between the film and the oxide semiconductor layer is high.

[0023] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, The thickness of the insulating layer is preferably equal to or less than the thickness of the oxide semiconductor layer.

[0024] In one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, for example, In the etching step, the etching selectivity between the conductive layer and the protective conductive film is 4 or more, preferably 6 or more. The second etching step is performed such that the etching selectivity between the protective conductive film and the oxide semiconductor layer is 3. It is sufficient if it is 0 or more, preferably 45 or more.

[0025] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, the wiring layer is made of a material It is preferable to form a laminated structure having a film containing aluminum as the material.

[0026] In one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, for example, It is preferable to form a laminated structure having a titanium film below the film containing aluminum.

[0027] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, It is preferable to form the insulating film using a tungsten film.

[0028] In one embodiment of the method for manufacturing a semiconductor device disclosed in this specification, for example, The body layer is preferably formed using a film containing indium, gallium, and zinc. [Effects of the Invention]

[0029] The conductive layer is etched with a high etching selectivity, thereby etching the oxide semiconductor layer. can be reduced.

[0030] The etching process can be controlled with precision, resulting in a thin, normally-on A transistor including an oxide semiconductor layer can be manufactured.

[0031] In addition, the occurrence of variations in the film thickness of the oxide semiconductor layer can be reduced, and the lead of the transistor can be reduced. It is possible to manufacture a semiconductor device having a high-performance, highly reliable transistor by suppressing the current flowing through the transistor. It is possible. [Brief explanation of the drawings]

[0032] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 3] 1A and 1B are a plan view and a cross-sectional view of a semiconductor device; [Figure 4] FIG. [Figure 5] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram of a semiconductor device. [Figure 6] 1A and 1B are diagrams illustrating electronic devices. [Figure 7] STEM images described in Example 1. [Figure 8] 1 is a STEM image of a comparative example described in Example 1. [Figure 9] STEM images described in Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments. When explaining the configuration of the invention using drawings, the same reference numerals are used in common between different drawings. Also, when referring to similar items, the same hatch pattern is used and a special symbol is added. Also, for convenience, insulating layers may not be shown in the top view.

[0034] In the following explanation, ordinal numbers such as 1st and 2nd are added for the convenience of explanation. This does not limit the number.

[0035] (Embodiment 1) This embodiment describes a method for manufacturing a semiconductor device including a transistor according to one embodiment of the present invention. We will explain about this.

[0036] First, a gate electrode layer 102 is selectively formed over a substrate 100 (see FIG. 1A).

[0037] The substrate 100 may have an insulating surface. For example, a glass substrate or a quartz substrate may be used. Plate, semiconductor substrate with an insulating layer on its surface, or stainless steel with an insulating layer on its surface A substrate or the like may be used.

[0038] The gate electrode layer 102 may be formed using a conductive material. A conductive material film may be formed and then processed by photolithography.

[0039] A gate insulating film 104 is formed to cover the gate electrode layer 102, and an oxide film is formed on the gate insulating film 104. Then, a compound semiconductor layer 106 is selectively formed (see FIG. 1(B)).

[0040] The gate insulating film 104 is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride. The insulating film may be formed using silicon dioxide or the like, and is preferably formed by a sputtering method. Moisture and hydrogen are removed as much as possible from the gate insulating film 104 in contact with the oxide semiconductor layer 106. It is preferable to remove the insulating film 104. Alternatively, a plurality of layers may be laminated.

[0041] Note that "silicon oxynitride" refers to a material whose composition contains more oxygen than nitrogen. Preferably, Rutherford Backscattering Spectroscopy (RBS) is used. Backscattering Spectrometry and Hydrogen Forward Scattering Spectrometry (HF When measured using S: Hydrogen Forward Scattering The composition range is 50 atomic % to 70 atomic % of oxygen, 0.5 atomic % to 15 atomic % of nitrogen, This refers to a material containing silicon in the range of 25 atomic % to 35 atomic %.

[0042] Note that "silicon nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. Preferably, the composition range is as follows, as measured by RBS and HFS: Oxygen 5-30 atomic %, nitrogen 20-55 atomic %, silicon 25-35 atomic % However, silicon oxynitride or silicon nitride oxide is not included. When the total of the constituent atoms is 100 atomic %, the content ratio of nitrogen, oxygen, and silicon is as above. shall be included within the scope of

[0043] The gate insulating film 104 is made of aluminum oxide, tantalum oxide, hafnium oxide, or oxide. Yttrium silicate, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen Doped hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen is added Hafnium aluminate (HfAl x O y (x>0, y>0)), etc. The thickness of the insulating film is not particularly limited, but it is preferable to form the insulating film in a thickness greater than 1000 mm when the semiconductor device is miniaturized. In this case, it is desirable to thin it to ensure the operation of the transistor. When silicon is used, the thickness is 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. m or less.

[0044] As mentioned above, when the gate insulating film is thinned, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating film 104 is coated with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x> 0, y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y >0), nitrogen-doped hafnium aluminate (HfAl x O y (x>0, y>0 It is recommended to use high-k materials such as By using it for the insulating film 104, it is possible to suppress gate leakage while ensuring electrical characteristics. It is possible to increase the film thickness. , silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Alternatively, it may have a laminated structure with a film containing the above.

[0045] The oxide semiconductor forming the oxide semiconductor layer 106 is an oxide semiconductor from which impurities such as water and hydrogen are removed. The oxide semiconductor is made so that impurities that act as carrier donors other than the main component of the oxide semiconductor are not included as much as possible. By purifying it and supplying sufficient oxygen, it becomes intrinsic (i-type) or substantially intrinsic (i-type) A gate-type oxide semiconductor is used.

[0046] As described above, the oxide semiconductor layer 106 used in the transistor contains impurities such as hydrogen. It is highly purified by sufficiently removing the oxygen and supplying it. Specifically, it is desirable that the hydrogen concentration in the oxide semiconductor layer 106 is 5×10 19 ato ms / cm 3 Below 5×10 18 atoms / cm 3 Below 5, preferably x10 17 atoms / cm3 Note that the hydrogen in the oxide semiconductor layer 106 is The concentration is determined by secondary ion mass spectrometry (SIMS). This is measured by spectroscopic analysis. The energy gap caused by oxygen deficiency is filled by supplying sufficient oxygen. In the oxide semiconductor layer 106 in which the defect levels are reduced, the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 For example, the off-state current (here, unit channel width ( The value per 1 μm is 100 zA (1 zeptoampere is 1 × 10 -21 A) Below In this way, the i-type (intrinsic) or substantially i-type By using the oxide semiconductor layer 106, a transistor with excellent off-state current characteristics can be obtained. You can get the data.

[0047] The sodium concentration in the oxide semiconductor layer 106 is 5×10 16 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 or less, more preferably 1 × 10 15 at oms / cm 3 The lithium concentration in the oxide semiconductor layer 106 is 5×10 15 atoms / cm 3 Less than 1 × 10 15 atoms / cm 3 The following applies: The potassium concentration of the oxide semiconductor layer 106 is 5×10 15 atoms / cm 3 The following is preferred: 1×10 15 atoms / cm 3 Note that in the oxide semiconductor layer 106 The sodium, lithium, and potassium concentrations were measured by secondary ion mass spectrometry. Alkali metals and alkaline earth metals are harmful to oxide semiconductors. Among alkali metals, sodium is particularly important for oxide semiconductors. If the insulating film in contact with the + In addition, the oxide semiconductor In the conductor, it breaks the bond between metal and oxygen or interrupts the bond. Deterioration of transistor characteristics (e.g., normally-on (negative shift of threshold voltage), mobility In addition, it can cause variations in characteristics. This is particularly noticeable when the concentration of hydrogen in the oxide semiconductor is sufficiently low. The hydrogen concentration in the semiconductor is 5×10 19 cm -3 Below, especially 5x10 18 cm -3 Below In some cases, it is highly desirable to have the alkali metal concentration at the above value.

[0048] Such highly purified oxide semiconductors are extremely sensitive to interface states and interface charges. Therefore, the state of the interface between the gate insulating film 104 and the oxide semiconductor layer 106 (interface state, interface It is important to adjust the charge and other properties to be appropriate. The gate insulating film 104 in contact with the oxide semiconductor is preferably of high quality. "The gate insulating film 104 is of high quality" means that the surface or the film of the gate insulating film 104 is It contains few defects, has few defect states and interface states that trap charges, and generates no fixed charges. Examples include the difficulty of producing them.

[0049] The gate insulating film 104 is formed by, for example, microwave irradiation (for example, a frequency of 2.45 GHz). Forming it using the high density plasma CVD method is preferred because it is dense and can increase the dielectric strength voltage. The highly purified oxide semiconductor layer and the high-quality gate insulating film are formed in close contact with each other. This is because, by doing so, the interface state density can be reduced and the interface characteristics can be improved.

[0050] Of course, any material that can form a high-quality insulating layer as the gate insulating film 104 can be used. Other film forming methods such as tartering and plasma CVD may also be used.

[0051] The gate insulating film 104 in contact with the oxide semiconductor layer 106 contains a group 13 element and oxygen. Many oxide semiconductor materials contain elements from Group 13. Insulating materials containing group 13 elements are compatible with oxide semiconductors, and when they are in contact with the oxide semiconductor layer, By using the insulating layer, the state of the interface with the oxide semiconductor layer can be kept good. The insulating film 116 which functions as a protective film for the oxide semiconductor film, which will be described later, is also The insulating material may contain a group 13 element and oxygen.

[0052] Here, the insulating material containing a Group 13 element is an insulating material containing one or more Group 13 elements. The insulating material containing a Group 13 element is, for example, gallium oxide, oxide, These include aluminum oxide, aluminum gallium oxide, and aluminum gallium oxide. Here, aluminum gallium oxide is a material that has a gallium content (atomic %) of aluminum. Gallium aluminum oxide refers to a material with a high content (atomic %) of aluminum. This indicates that the gallium content (atomic %) is higher than the total amount (atomic %) of the alloy.

[0053] For example, when a gate insulating film is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide for the gate insulating film, the oxide semiconductor layer and the gate insulating film The interface characteristics can be maintained good. By providing the insulating layer in contact with the oxide semiconductor layer, hydrogen pile-up at the interface between the oxide semiconductor layer and the insulating layer can be prevented. It is to be noted that when an element in the same group as the component element of the oxide semiconductor is used for the insulating layer, For example, if a material containing aluminum oxide is used, the same effect can be obtained. It is also effective to form an insulating layer using aluminum oxide. Therefore, the use of this material is effective in preventing water from entering the oxide semiconductor layer. This is also preferable in terms of preventing the intrusion of bacteria.

[0054] In addition, the insulating layer in contact with the oxide semiconductor layer 106, for example, the gate insulating film 104, is formed in an oxygen atmosphere. By heat treatment under atmospheric pressure or oxygen doping, the insulating material is made to have more oxygen than the stoichiometric composition ratio. It is preferable to make the state of oxygen doping. Oxygen doping means adding oxygen to the bulk. The term "bulk" clearly indicates that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. In addition, oxygen doping is done by adding plasma oxygen to the bulk. Oxygen doping includes oxygen plasma doping, which involves the use of oxygen plasma doping. Oxygen doping can also be performed by ion implantation or ion doping. This may be done using the ping method.

[0055] For example, when gallium oxide is used as an insulating layer in contact with the oxide semiconductor layer 106, oxygen By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to GaO x (x=3+α, 0<α<1). When aluminum oxide is used as an insulating layer, heat treatment in an oxygen atmosphere or oxygen doping By performing the tapping, the composition of aluminum oxide is changed to AlO x (x=3+α, 0<α<1) Alternatively, a gallium oxide insulating layer can be used as an insulating layer in contact with the oxide semiconductor layer 106. When aluminum (aluminum gallium oxide) is used, heat treatment under an oxygen atmosphere By performing oxygen doping, gallium aluminum oxide (aluminum gallium oxide) ) composition of Ga x Al 2-x O 3+α (0 <x<2、0<α<1)とすることができる。

[0056] By performing oxygen doping treatment, an insulating film having a region with more oxygen than the stoichiometric composition ratio can be obtained. The insulating layer having such a region and the oxide semiconductor layer are in contact with each other. As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer or reducing oxygen deficiency defects at the interface between the oxide semiconductor layer and the insulating layer, and The hydrogenated oxide semiconductor layer is made into an i-type or nearly i-type oxide semiconductor. It is possible.

[0057] The insulating layer having a region with more oxygen than the stoichiometric composition ratio is formed in the gate insulating film 104. Instead, an insulating film (for example, an insulating film described later) formed as a protective film for the oxide semiconductor layer 106 116, etc.), and the insulating film formed as the gate insulating film 104 and the protective film It may be applied to both.

[0058] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors In addition, it is preferable to contain gallium (Ga). Also, tin (S) is used as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is also preferable that the stabilizer contains aluminum (Al). It's nice.

[0059] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), aluminium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0060] The oxide semiconductor forming the oxide semiconductor layer 106 is a quaternary metal oxide, In -Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Z n-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, In -Hf-Al-Zn oxides and ternary metal oxides such as In-Ga-Zn oxides (I Also written as GZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn- Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-H f-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr -Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu- Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Z n-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn In-Yb-Zn oxides, In-Lu-Zn ​​oxides, and binary metal oxides In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, and single-element metal oxides Indium oxide, tin oxide, zinc oxide, etc. can be used. -Zn-based oxide means an oxide having In, Ga, and Zn as its main components, The ratio of In, Ga, and Zn is not important. Also, metal elements other than In, Ga, and Zn may be included. That's fine.

[0061] The oxide semiconductor layer 106 has the chemical formula InMO3(ZnO) m (m>0) Here, M is selected from Zn, Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and and Mn, or Ga and Co.

[0062] In addition, a thin film of an oxide semiconductor that forms the oxide semiconductor layer 106 is formed by a sputtering method. For example, the target for this purpose is a composition ratio of In2O3:Ga2O3:Zn. Using an oxide semiconductor film deposition target with O = 1:1:1 [molar ratio], In-Ga-Z The material and composition of the target are not limited to those mentioned above, and examples thereof include: , oxide semiconductor film deposition target of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] Here, for example, the In-Ga-Zn oxide film is an In-Ga-Zn oxide film. It means an oxide film containing indium (In), gallium (Ga), and zinc (Zn). The composition ratio is not particularly limited.

[0063] In addition, when an In-Zn oxide is used as the oxide semiconductor, the composition of the target to be used is The composition ratio, in atomic ratio, is In:Zn=50:1 to 1:2 (converted to molar ratio, In2O3: ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (in terms of molar ratio) Then, In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=15: The ratio is 1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO=15:2 to 3:4). For example, a target used for forming an In-Zn-O based oxide semiconductor has an atomic ratio of In: When Zn:O=X:Y:Z, Z>1.5X+Y.

[0064] In addition, In-Sn-Zn oxide can be called ITZO, and the target used The composition ratio of In:Sn:Zn is 1:2:2, In:Sn:Zn is 2:1, in atomic ratio. 3. In:Sn:Zn=1:1:1 or In:Sn:Zn=20:45:35, etc. An oxide target is used.

[0065] The thickness of the semiconductor film to be the oxide semiconductor layer 106 is set to 3 nm or more and 30 nm or less. If the semiconductor film to be the oxide semiconductor layer 106 is too thick (for example, if the film thickness is too large), This is because there is a risk that the transistor will become normally on when the device is fabricated using a silicon nitride film (SiO2) or silicon nitride film (SiO2: 50 nm or more).

[0066] Here, the semiconductor film that becomes the oxide semiconductor layer 106 is an In—Ga—Zn—O-based oxide. It is formed in a reduced pressure atmosphere by sputtering using a semiconductor film formation target.

[0067] The filling rate of the oxide semiconductor film forming target is 90% or more and 100% or less, preferably The filling rate is 95% or more and 99.9% or less. By using the hot plate, the oxide semiconductor film to be deposited can be a dense film.

[0068] For example, the oxide semiconductor layer can be formed as follows.

[0069] First, the substrate is held in a film-forming chamber maintained under reduced pressure, and the substrate temperature is kept at 200°C or higher. 500°C or less, preferably more than 300°C but not more than 500°C, more preferably 350°C or more Heat to 450°C or less.

[0070] Next, while removing the remaining moisture in the film-forming chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed. A sufficiently purified high-purity gas is introduced, and an oxide semiconductor layer is formed on a substrate using the target. To remove the residual moisture in the deposition chamber, a cryopump is used as an exhaust means. Use an adsorption type vacuum pump such as an ion pump or titanium sublimation pump. The exhaust means is preferably a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen, water, hydroxyl groups, or water. Since impurities such as chlorines (and more preferably compounds containing carbon atoms) have been removed, Therefore, hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of any impurity can be reduced.

[0071] When the substrate temperature during film formation is low (for example, 100°C or less), hydrogen atoms are introduced into the oxide semiconductor. It is preferable to heat the substrate at the above-mentioned temperature because there is a risk of contamination with substances containing the substrate. By heating the substrate at the above temperature and depositing the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, when the substrate is heated to the above-mentioned temperature, the oxide semiconductor layer is formed. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer are removed. The concentration of impurities can be sufficiently reduced. This can reduce damage to the

[0072] As an example of film formation conditions, the distance between the substrate and the target is 60 mm, and the pressure is 0.4 Pa. The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the film formation atmosphere was oxygen (oxygen flow rate ratio The atmosphere should be 100%. When a pulsed DC power supply is used, the powder particles generated during film formation are This is preferable because it reduces the amount of particles and dust and also reduces the film thickness distribution.

[0073] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. The reverse sputtering is performed to generate plasma, and the oxide semiconductor layer adheres to the surface where the oxide semiconductor layer is to be formed. It is preferable to remove powdery substances (also called particles or dust). This is a method in which a voltage is applied to the substrate, plasma is generated near the substrate, and the surface of the substrate is modified. Instead of argon, gas such as nitrogen, helium, or oxygen may be used.

[0074] Note that preheating before the formation of the oxide semiconductor layer 106 can be performed to dehydrate or It may be dehydrogenated.

[0075] Note that before forming a semiconductor film to be the oxide semiconductor layer 106, residual moisture in a film formation chamber and It is preferable to remove hydrogen sufficiently. Before formation, use an adsorption-type vacuum pump (e.g., cryopump, ion pump, titanium sublimation pump). It is preferable to use a pump (evacuation pump) to perform evacuation.

[0076] The oxide semiconductor layer is formed by depositing a first crystalline oxide semiconductor layer on the first crystalline oxide semiconductor layer. A stacked layer structure including a second crystalline oxide semiconductor layer that is thicker than the first crystalline oxide semiconductor layer may be used. The oxide semiconductor layer having a layer structure can be formed by the following method.

[0077] First, a first crystalline oxide semiconductor film having a thickness of 1 nm to 10 nm is formed on the gate insulating film 104. The first crystalline oxide semiconductor layer is formed by sputtering. The substrate temperature during film formation by sputtering is set to 200°C or higher and 400°C or lower. Then, the chamber atmosphere in which the substrate is placed is set to nitrogen or dry air, and the first heat treatment is performed. The temperature of the heat treatment is 400°C or higher and 750°C or lower.

[0078] Although it depends on the substrate temperature during film formation and the temperature of the first heat treatment, As a result, crystallization occurs from the film surface, and crystals grow from the surface to the inside of the film, and the c-axis is oriented. The heat treatment causes zinc and oxygen to gather on the surface of the film, resulting in a hexagonal top surface. One or more layers of graphene-type two-dimensional crystals made of zinc and oxygen are formed on the top surface. These grow in the film thickness direction and become stacked layers. Crystal growth proceeds from the top to the inside and then from the inside to the bottom.

[0079] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer. The second oxide semiconductor layer is formed by a sputtering method. The substrate temperature during film formation is set to 200°C or higher and 400°C or lower. By setting the temperature at 400° C. or less, the first crystalline oxide semiconductor layer is formed on and in contact with the surface of the first crystalline oxide semiconductor layer. The precursors are aligned in the oxide semiconductor layer, and so-called order can be imparted to the oxide semiconductor layer.

[0080] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a second heating process is performed. The temperature of the heat treatment is 400°C or higher and 750°C or lower. The heat treatment is performed under a nitrogen atmosphere, an oxygen atmosphere, or the like to form a second crystalline oxide semiconductor layer. The second crystalline oxide semiconductor layer is formed by performing the process under an atmosphere of nitrogen or a mixed atmosphere of nitrogen and oxygen. The second heat treatment increases the density of the first crystalline oxide semiconductor and reduces the number of defects. The conductor layer acts as a nucleus and crystal growth proceeds in the film thickness direction, i.e., from the bottom to the inside, to form a second crystalline oxide. A semiconductor layer is formed.

[0081] Further, the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above manufacturing method One of the features of the oxide semiconductor layer is that it has a c-axis orientation. The crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer are made of crystals having a c-axis orientation (C Axis Aligned Crystal (CAAC) containing oxides Note that the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer are partially fused. It has grain boundaries.

[0082] In a broad sense, oxides containing CAAC are non-single crystals that are perpendicular to the ab plane. When viewed from the outside, the atomic arrangement is triangular, hexagonal, equilateral triangular, or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from any direction, it contains a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to oxides.

[0083] CAAC is not a single crystal, but it is not composed of only amorphous material. AAC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is Sometimes it is not possible to clearly distinguish.

[0084] When CAAC contains oxygen, a part of the oxygen may be replaced by nitrogen. The c-axis of each crystalline part that constitutes C is aligned in a certain direction (for example, the substrate surface supporting the CAAC, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of C, etc.

[0085] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Or something like that.

[0086] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from various directions, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, Then, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of such crystals include:

[0087] The stack of the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer is By using this material in transistors, it is possible to create transistors with stable electrical characteristics and high reliability. It can be achieved.

[0088] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer. This can be done by etching the oxide semiconductor layer. It can be formed by using a method such as lithography. The mask may be formed by any method. Of course, these may be used in combination. Good too.

[0089] Next, the oxide semiconductor layer 106 is subjected to heat treatment (third heat treatment). The oxide semiconductor layer can be dehydrated or dehydrogenated by heating in an inert atmosphere. The temperature of the heat treatment is 250°C or higher and 700°C or lower, preferably 450°C or higher and 60°C or lower. The temperature is set to 0° C. or less. It is preferable that the temperature is set to be lower than the distortion point of the substrate. The heat treatment is carried out at 450°C for 1 hour in a nitrogen atmosphere. The timing is not limited to this, and may be after the oxide semiconductor layer 106 is formed. The atmosphere in which the heat treatment is performed is not limited to a nitrogen atmosphere, and may be a mixed gas of oxygen gas and nitrogen gas. The atmosphere may be a dry atmosphere, an oxygen atmosphere, or air from which moisture has been sufficiently removed (Dry Air). After the heat treatment, the oxide semiconductor layer 106 is heated to a temperature of 1000° C. for 1 hour, and then heated to a temperature of 1000° C. for 1 hour. It is preferable to prevent re-incorporation of hydrogen.

[0090] Further, the oxide semiconductor layer that has been subjected to the third heat treatment may be subjected to a fourth heat treatment. The heat treatment in step 4 is performed in an oxidizing atmosphere to supply oxygen to the oxide semiconductor layer. The oxygen vacancies generated in the oxide semiconductor layer during the third heat treatment are filled by the supply of the oxygen. Therefore, the fourth heat treatment can also be called an oxygen-adding treatment. For example, the temperature may be 200° C. or higher and lower than the strain point of the substrate. Preferably, the temperature is 250° C. or higher and 450° C. or higher. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the more the amorphous region is formed. However, if the oxide semiconductor layer is heated for more than 24 hours, Such treatment is undesirable because it reduces productivity.

[0091] By performing such heat treatment, an oxide semiconductor layer containing reduced impurities can be formed. This makes it possible to realize a transistor with extremely excellent characteristics.

[0092] Next, a protective conductive film 107 is formed to cover the gate insulating film 104 and the oxide semiconductor layer 106. Then, a conductive layer 108 that will later become a wiring layer 112 is formed on the protective conductive film 107 (FIG. 1C )reference).

[0093] The protective conductive film 107 is formed later when the wiring layer 112 is formed by etching the conductive layer 108. The protective conductive film 10 protects the oxide semiconductor layer 106 present below the conductive layer 108. Examples of conductive materials for forming the conductive layer 7 include W and Mo. Examples of the conductive material include Ti, Al, Ta, and nitrides thereof. Note that the conductive layer 108 may be a single layer or a stack of multiple layers. In this embodiment, the conductive layer 108 has a stacked structure of Ti\Al\Ti.

[0094] In addition, when a metal film having a high oxygen affinity is used for the metal film in contact with the oxide semiconductor layer 106, Therefore, oxygen is easily extracted from the oxide semiconductor layer 106, and the oxide semiconductor layer 106 is altered. There is a risk of injury.

[0095] Therefore, a metal film having low oxygen affinity is used for the metal film in contact with the oxide semiconductor layer 106. In this embodiment, the metal film in contact with the oxide semiconductor layer 106 is preferably a protective conductive film. The W film is 107.

[0096] The protective conductive film 107 using W has a higher oxygen affinity than the Ti used as the conductive layer 108. By providing the protective conductive film 107 using W, the oxide semiconductor layer 106 and the Ti film Since the oxide semiconductor layer 106 is formed in contact with the oxide semiconductor layer 106, the effect of extracting oxygen from the oxide semiconductor layer 106 is weaker. Therefore, the contact interface between the W film and the oxide semiconductor layer 106 is unlikely to be altered. The substantial thickness reduction of the oxide semiconductor layer 106 due to the deterioration of a part of the oxide semiconductor layer 106 is reduced. It is possible.

[0097] Next, a resist mask 110 is selectively formed over the conductive layer 108 (see FIG. 1(D)). The resist mask 110 may be formed by photolithography.

[0098] Next, the conductive layer 108 and the protective conductive film 107 are etched using the resist mask 110. Etching is performed to form the wiring layer 112 and the conductive layer 114. The etching process for forming the conductive layer 114 is performed by over-etching the oxide semiconductor. In order to minimize the thickness loss of the layer 106, etching is performed in two stages.

[0099] First, the conductive layer 108 is formed using a resist mask 110 until the protective conductive film 107 is exposed. The conductive layer 108 is selectively etched (first etching step). The wiring layer 112 is formed by arranging the wiring layer 112 so as to form at least the source electrode of the transistor. and the drain electrode (see FIG. 1(E)).

[0100] In the first etching step, the protective conductive film 107 is etched away from the conductive layer 108. The etching is performed under conditions where the etching selectivity between the conductive layer 108 and the protective conductive film 107 is high. For example, a chlorine-based gas can be used as the etching gas. Examples of the chlorine-containing compounds include CCl4, SiCl4, BCl3, and Cl2. Particularly preferred is BC A mixture of I3 and Cl2 gas is used.

[0101] Next, the protective conductive film 107 is selectively etched until the oxide semiconductor layer 106 is exposed. (second etching step). Here, the protective conductive film 107 is etched to leave the conductive layer 1 In the second etching step, the oxide semiconductor layer 10 6, the protective conductive film 107 is removed without leaving any residue, and the oxide semiconductor layer 10 Preferably, 6 is not etched.

[0102] In the second etching step, the protective conductive film 107 is etched more thoroughly than the oxide semiconductor layer 106. The etching selectivity between the protective conductive film 107 and the oxide semiconductor layer 106 is high. For example, a mixture of chlorine-based gas and fluorine-based gas is used as the etching gas. Here, the mixed gas of chlorine-based gas and fluorine-based gas is particularly preferably uses a mixture of SF6 and Cl2 gas.

[0103] As described above, due to the effect of the protective conductive film 107, the portion that will become the channel forming region While maintaining the thickness of the oxide semiconductor layer 106, the wiring layer 112 in the portion that will become the channel formation region is formed. The wiring layer 112 is formed by using such an etching method. As a result, even if the substrate 100 is a large-area substrate, the channel formation region within the substrate surface can be formed. This can reduce variations in the thickness of the oxide semiconductor layer 106 in some areas.

[0104] Then, the resist mask 110 is removed. It is preferable to form an insulating film 116 on the layer. The insulating film 116 is made of silicon oxide, silicon nitride, and the like. The insulating film may be formed of silicon oxynitride or silicon dioxide by sputtering. The insulating film 116 can be made of the same material as the gate insulating film 104. do.

[0105] After the insulating film 116 is formed, a fourth heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 250°C. For example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere is sufficient. The fourth heat treatment reduces variations in the electrical characteristics of the transistors. When the insulating film 116 contains oxygen, it can be dehydrated or dehydrogenated. Oxygen is supplied to the oxide semiconductor layer 106, and oxygen vacancies in the oxide semiconductor layer 106 are compensated for, thereby forming an i-type An (intrinsic) semiconductor layer or an oxide semiconductor layer that is as close to i-type as possible can also be formed.

[0106] In this embodiment, the fourth heat treatment is performed after the insulating film 116 is formed. The timing of the heat treatment is not limited to this. For example, the fourth heat treatment may be performed after the third heat treatment. The third heat treatment may be performed as the fourth heat treatment, or the fourth heat treatment may be performed as the third heat treatment. The second heat treatment may also serve as the third heat treatment.

[0107] The oxide semiconductor layer 106 is formed by the above-described method and is highly purified. The transistor with this structure has a current value in the off state (off-state current value) of 1 μm per 1 μm of channel width. It can be reduced to less than 100zA / μm at 85°C and less than 100zA / μm at 85°C. In other words, the off-state current can be reduced to near the measurement limit or below. do.

[0108] In one embodiment of the semiconductor device disclosed in the present specification, a high-performance, high-reliability transistor It is possible to create a

[0109] This embodiment mode can be freely combined with other embodiment modes.

[0110] (Embodiment 2) The present invention is not limited to the embodiment shown in the first embodiment. For example, The semiconductor device may have a top gate structure in which a gate electrode layer is disposed on a wiring layer.

[0111] First, a base insulating layer 201 is preferably formed on a substrate 200, and an oxide film is formed on the base insulating layer 201. Then, a nitride semiconductor layer 206 is selectively formed (see FIG. 2(A)).

[0112] The substrate 200 may be the same as the substrate 100 of the first embodiment.

[0113] The base insulating layer 201 is made of the same material and formed as the gate insulating film 104 of the first embodiment. It can be formed by the method.

[0114] The oxide semiconductor layer 206 is made of the same material and has the same shape as the oxide semiconductor layer 106 of the first embodiment. It can be formed by a forming method.

[0115] Next, a protective conductive film 207 is formed to cover the base insulating layer 201 and the oxide semiconductor layer 206. Then, a conductive layer 208, which will later become a wiring layer 212, is formed on the protective conductive film 207 (FIG. 2(B)). reference).

[0116] The protective conductive film 207 is made of the same material and formed by the same method as the protective conductive film 107 of the first embodiment. The conductive layer 208 can be formed by the same method as the conductive layer 108 in Embodiment 1. In this embodiment, the conductive layer 208 can be formed by the following materials and forming methods. A Ti\Al\Ti layered structure is used.

[0117] In addition, when a metal having a high oxygen affinity is used as a metal film in contact with the oxide semiconductor layer, the oxide semiconductor layer can be easily oxidized. This tends to extract oxygen from the oxide semiconductor layer, which may result in alteration of the oxide semiconductor layer.

[0118] Therefore, it is preferable to use a metal having low oxygen affinity for the metal film in contact with the oxide semiconductor layer. In this embodiment, the metal film in contact with the oxide semiconductor layer is a W film that is a protective conductive film. It is used.

[0119] The protective conductive film using W has a lower oxygen affinity than Ti used as the conductive layer 208. By providing a protective conductive film using W, the oxide semiconductor layer and the Ti film are formed in contact with each other. Therefore, the action of extracting oxygen from the oxide semiconductor layer is weakened, and the W film and the oxide semiconductor layer Therefore, the contact interface between the oxide semiconductor layer and the oxide semiconductor layer is hardly deteriorated. Therefore, the substantial decrease in the film thickness of the compound semiconductor layer can be reduced.

[0120] Next, a resist mask 210 is selectively formed over the conductive layer 208 (see FIG. 2C). The resist mask 210 is formed by photolithography in the same manner as the resist mask 110 of the first embodiment. It can be formed by a granulating method.

[0121] Next, the conductive layer 208 and the protective conductive film 207 are etched using a resist mask 210. Etching is performed to form the wiring layer 212 and the conductive layer 214. The wiring layer 212 is At least the source electrode and drain electrode of the transistor are formed. The etching process for forming the conductive layer 214 is performed by over-etching the oxide semiconductor. In order to minimize the thickness loss of the layer 206, etching is performed in two stages.

[0122] First, the conductive layer 208 is formed using a resist mask 210 until the protective conductive film 207 is exposed. is selectively etched (first etching step). The resulting layer is then processed to form the wiring layer 212 (see FIG. 2(D)).

[0123] In the first etching step, the protective conductive film 207 is etched away from the conductive layer 208. The etching is performed under conditions where the etching selectivity between the conductive layer 208 and the protective conductive film 207 is high. For example, a chlorine-based gas can be used as the etching gas. Examples of the fluorine-containing compound include CCl4, SiCl4, BCl3 and Cl2. Particularly preferred is BCl A mixture of 3 and Cl2 is used.

[0124] Next, the protective conductive film 207 is selectively etched until the oxide semiconductor layer 206 is exposed. (second etching step). Here, the protective conductive film 207 is etched to leave the conductive layer 2 In the second etching step, the oxide semiconductor layer 20 6, the protective conductive film 207 is removed without leaving any residue, and the oxide semiconductor layer 20 Preferably, 6 is not etched.

[0125] In the second etching step, the protective conductive film 207 is etched more than the oxide semiconductor layer 206. The etching selectivity between the protective conductive film 207 and the oxide semiconductor layer 206 is high. For example, a mixture of chlorine-based gas and fluorine-based gas is used as the etching gas. Here, the mixed gas of chlorine-based gas and fluorine-based gas is particularly preferably uses a mixture of SF6 and Cl2 gas.

[0126] As described above, due to the effect of the protective conductive film 207, the portion that will become the channel forming region While maintaining the thickness of the oxide semiconductor layer 206, the wiring layer 212 in the portion that will become the channel formation region is formed. The wiring layer 212 is formed by using such an etching method. As a result, even if the substrate 200 is a large-area substrate, the channel formation region within the substrate surface can be formed. This can reduce variations in the film thickness of the oxide semiconductor layer 206 in some areas.

[0127] Then, the resist mask 210 is removed. A gate insulating film 204 is formed on the layer, and a gate electrode layer 20 is formed on the layer by overlapping with the oxide semiconductor layer 206. 2 is selectively formed. Through the above steps, the transistor 220 of this embodiment is completed ( 2(F)). The gate insulating film 204 is the same as the gate insulating film 104 in the first embodiment. The gate electrode layer 202 can be formed by the material and the forming method of the first embodiment. The insulating layer 104 can be formed using the same material and method as those of the gate electrode layer 102 and the like.

[0128] Note that also in this embodiment, the oxide semiconductor layer is highly purified. The transistor including the oxide semiconductor layer 206 is in an off state. The current value (off-state current value) is less than 10 A / μm per 1 μm of channel width at 85°C. It can be reduced to a level of less than 100 zA / μm, i.e., near the measurement limit or can reduce the off-state current to near the measurement limit or below.

[0129] In one embodiment of the semiconductor device disclosed in the present specification, a high-performance, high-reliability transistor It is possible to create a

[0130] This embodiment mode can be freely combined with other embodiment modes.

[0131] The present invention is not limited to the embodiments shown in the first and second embodiments, and the gist of the present invention is It may be in a different form as long as it does not deviate from the above.

[0132] (Embodiment 3) In this embodiment, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. This will be described with reference to FIG. 3. The liquid crystal display panel shown in FIG. 3 is the same as that shown in the first embodiment. However, the present invention is not limited to this and may be applied to the first or second embodiment. 3A and 3C show a transistor 401. 4001, a transistor 4011, and a liquid crystal element 4013 are disposed between a first substrate 4001 and a second substrate 4002. 3(a) is a plan view of the panel sealed with a sealing material 4005 between the panel and a plate 4006. FIG. 3B) corresponds to a cross-sectional view taken along line MN in FIG. 3A or FIG. 3C.

[0133] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealing material 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the driving circuit 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealing material 4005, and a second substrate 4006. 4006, the first substrate 4001 is sealed together with the liquid crystal layer 4008. In an area different from the area surrounded by the sealing material 4005, a separately prepared substrate is A signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on the are.

[0134] The method for connecting the separately formed drive circuit is not particularly limited, and may be a COG method. For example, a wire bonding method or a TAB method can be used. 3C is an example of mounting a signal line driver circuit 4003 by the COG method. This is an example of mounting a signal line driver circuit 4003 by this method.

[0135] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 3B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4010 included in the scanning line driver circuit 4004. In FIG. 3B, the transistors 4011 and 4010 are provided with insulating layers. A layer 4041, an insulating layer 4042, and an insulating layer 4021 are provided.

[0136] The transistor 4010 and the transistor 4011 are the same as those in the first embodiment or the second embodiment. In this embodiment, the transistor 40 10. The transistor 4011 is an n-channel transistor.

[0137] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033 .

[0138] It is to be noted that the first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. It can be used on plastics such as polyester film or acrylic resin film, or glass. For example, metals, ceramics, etc. can be used.

[0139] The columnar spacers 4035 are obtained by selectively etching the insulating layer. The distance (cell gap) between the electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. The counter electrode layer 4031 is The transistor 4010 is electrically connected to a common potential line provided on the same substrate. Using the connection portion, the counter electrode layer 4031 is connected to the counter electrode layer 4032 via conductive particles disposed between the pair of substrates. The conductive particles contained in the sealing material 4005 can be electrically connected to the conductive wire. To have.

[0140] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. In this case, a horizontal electric field type liquid crystal is used. For this reason, the electrode arrangement is different from that shown in Fig. 3. For example, the pixel electrodes are arranged on the same insulating layer. The layer and the common electrode layer are arranged side by side, and a horizontal electric field is applied to the liquid crystal layer. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. It is optically isotropic, so alignment treatment is not required, and viewing angle dependency is small.

[0141] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0142] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is provided in the order of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the inner side. The thickness may be appropriately set depending on the materials of the light plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a black matrix may be provided.

[0143] An insulating layer is provided over the transistor 4011 and the transistor 4010 in contact with the oxide semiconductor layer. A protective insulating layer 4042 is formed on the insulating layer 4041. Note that in order to reduce the surface unevenness of the transistor, the protective insulating layer 4042 is formed as a planar insulating layer. The insulating layer 4021 may be used to cover the insulating film.

[0144] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic materials such as imide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. ), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to achieve high insulation. A layer 4021 may be formed.

[0145] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, An IFCOATER or the like can be used. Firing process of insulating layer 4021 and annealing of semiconductor layer By combining these functions, it becomes possible to manufacture a semiconductor device efficiently.

[0146] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , indium tin oxide containing titanium oxide, indium tin oxide (also known as ITO), in Conductive materials with transparency such as indium zinc oxide and silicon oxide-doped indium tin oxide A conductive material can be used. Also, a material consisting of 1 to 10 graphene sheets can be used. may also be used.

[0147] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel driver circuit 4006 are separately formed. Various signals and potentials applied to the unit 4002 are supplied from the FPC 4018.

[0148] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the It is formed from the same conductive film as the source electrode and the drain electrode.

[0149] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected to each other.

[0150] In FIG. 3, a signal line driver circuit 4003 is formed separately and is mounted on the first substrate 4001. Although an example of mounting is shown, the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented as follows.

[0151] The liquid crystal display panel described in this embodiment mode is the same as the electric display panel described in Embodiment Mode 1 or 2. It is made up of highly reliable transistors with excellent electrical characteristics, ensuring excellent quality. It is possible to provide a liquid crystal display panel having such a structure.

[0152] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0153] (Fourth embodiment) In this embodiment, an example of electronic paper will be shown as one mode of a semiconductor device.

[0154] The transistor described in Embodiment 1 or 2 is electrically connected to a switching element. It may also be used in electronic paper, which uses the connected elements to drive electronic ink. The paper is also called an electrophoretic display (electrophoretic display), and is as easy to read as paper. Furthermore, it has the advantage of being able to consume less power and be made thinner and lighter than other display devices. are.

[0155] Electrophoretic displays can be of various forms, but the first one has a positive charge. The microcapsules containing the negatively charged particles and the negatively charged second particles are then mixed with a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to display only the color of the particles that have gathered on one side. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0156] Thus, electrophoretic displays are devices in which materials with high dielectric constants move to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0157] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Furthermore, color display is possible by using color filters or particles containing pigments.

[0158] In addition, the above-mentioned micro-electrodes are appropriately arranged on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the capsule, display can be performed. An active matrix substrate obtained by the transistor of form 2 can be used. .

[0159] The first particles and the second particles in the microcapsules are made of a conductive material and an insulating material. , semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of electrochromic materials, magnetophoretic materials, and composite materials of these. Just use

[0160] Figure 4 shows an active matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the transistor shown in Embodiment 1 or 2. It can be fabricated in the same way as a transistor, has good electrical properties, and is a highly reliable transistor. .

[0161] The electronic paper in Figure 4 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a first electrode layer and a second electrode layer, and a current is applied to the first electrode layer and the second electrode layer. This is a method of displaying by creating a potential difference and controlling the orientation of spherical particles.

[0162] In FIG. 4, transistor 581 is a bottom-gate transistor. The transistor described in Embodiment 1 or 2 can be used.

[0163] The source electrode or the drain electrode of the transistor 581 is formed by insulating layers 583 and 585. In the opening formed in the first electrode layer 587, the first electrode layer 587 is in contact with the first electrode layer 587 and is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and the second electrode layer 588, a black region 590a and a white region 59b are formed. 0b, and a spherical particle 589 filled with liquid is placed on a pair of substrates 580 and 59. 6, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin. do.

[0164] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential line provided over the same substrate as the transistor 581. The common connection portion is disposed between the pair of substrates 580 and 596. The second electrode layer 588 can be electrically connected to a common potential line through the conductive particles. Cut.

[0165] It is also possible to use an electrophoretic element instead of the twist ball. The body contains positively charged white particles and negatively charged black particles, each measuring 10 μm to 2 Microcapsules with a size of about 0.1 μm are used. When an electric field is applied to the microcapsules by the first electrode layer and the second electrode layer, White particles and black particles move in opposite directions, allowing for white or black to be displayed. The display element that applies this principle is an electrophoretic display element, and is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display, the image that has been displayed can be retained. Therefore, it is necessary to separate the semiconductor device with a display function (simply a display device, or a display device) from the radio wave source. The displayed image is preserved even if the device (also called a semiconductor device) is moved away. This becomes possible.

[0166] Through the above steps, an electronic device having the transistor described in Embodiment 1 or 2 can be manufactured. The electronic paper described in this embodiment can be manufactured using the same method as in Embodiment 1. Alternatively, the transistor having favorable electrical characteristics and high reliability, which is described in Embodiment 2, may be used. Therefore, it is possible to produce electronic paper with good quality.

[0167] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh.

[0168] (Embodiment 5) In this embodiment, a storage medium (memory element) is shown as an example of a semiconductor device. In this embodiment, the transistor including the oxide semiconductor described in Embodiment 1 and the transistor including the oxide semiconductor or Transistors using other materials are formed on the same substrate.

[0169] 5A and 5B show an example of the configuration of a semiconductor device. FIG. 5A shows a cross section of the semiconductor device. FIG. 5(A) shows the semiconductor device in a plan view. It corresponds to the cross section along A1-A2 and B1-B2. An example of a circuit diagram when the device is used as a memory element is shown in FIG. 5(A) and FIG. 5(B). The semiconductor device shown in FIG. 1 has a transistor 360 using a first semiconductor material in the lower part. The transistor 362 includes a second semiconductor material in the upper portion. The first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, silicon dioxide, and silicon dioxide. Silicon germanium, silicon carbide, or gallium arsenide can be used, and single crystal It is preferable to use semiconductors. Transistors using such semiconductor materials have high speed operation. On the other hand, transistors using oxide semiconductors can be used for a long time due to their characteristics. It allows charge retention.

[0170] The transistor 360 in FIG. 5 is a substrate comprising a semiconductor material (e.g., silicon). The channel forming region 316 is provided in the channel forming region 300, and the The impurity region 320 is formed by the metal compound region 324 in contact with the impurity region 320. A gate insulating film 308 is provided on the panel forming region 316, and a gate insulating film 308 is provided on the gate insulating film 308. and a gate electrode 310 formed thereon.

[0171] The substrate 300 containing a semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a multi-crystal semiconductor substrate, or a silicon carbide substrate. Crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. are used Generally, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. In this specification, however, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. This also includes substrates with a structure in which a semiconductor layer made of The substrate layer is not limited to a silicon semiconductor layer. In addition, the SOI substrate may be formed on an insulating substrate such as a glass substrate. The term "internal semiconductor device" also includes a structure in which a semiconductor layer is provided on a substrate via an insulating layer.

[0172] An electrode 326 is connected to a portion of the metal compound region 324 of the transistor 360. Here, the electrode 326 functions as a source electrode or a drain electrode of the transistor 360. In addition, an element isolation insulating layer 306 is provided to surround the transistor 360. An insulating layer 328 is provided to cover the transistor 360. To achieve this, the transistor 360 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, if the characteristics of the transistor 360 are important, A sidewall insulating layer is provided on the side of the electrode 310, and an impurity layer including a region with a different impurity concentration is formed. An object area 320 may also be provided.

[0173] The transistor 360 can be fabricated using known techniques. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium The transistor 360 using arsenic or the like is characterized by its high speed operation. Therefore, by using the transistor as a readout transistor, it is possible to read out information. It can be dispensed at high speed.

[0174] After forming the transistor 360, but before forming the transistor 362 and the capacitor element 364 As a process, the insulating layer 328 is subjected to CMP processing to expose the upper surface of the gate electrode 310. The process for exposing the upper surface of the gate electrode 310 includes etching in addition to CMP. However, in order to improve the characteristics of the transistor 362, It is desirable to keep the surface of the insulating layer 328 as flat as possible.

[0175] Next, a conductive layer is formed on the gate electrode 310, the insulating layer 328, etc., and the conductive layer is selectively 5. The semiconductor device shown in FIG. The semiconductor device transistor 362 has a gate electrode 348a and a gate electrode covering the gate electrode 348a. a gate insulating film 346, and a gate electrode 348a provided on the gate insulating film 346 so as to overlap the gate electrode 348a. and a conductive film electrically connected to the oxide semiconductor layer 344. 341a, a source electrode 342a and a conductive film 341b, and a drain electrode 342b. For details, refer to the description of the transistor in Embodiment 1 or 2. 5, the gate insulating film 346 is formed on the oxide semiconductor layer 344. However, the present invention is not limited to this and may be applied to at least the gate voltage The electrode 326 covers the conductive film 341a and the source electrode 342a. The gate electrode 310 is electrically connected to the conductive film 341b and the drain electrode 342b. It is sufficient to provide a connection.

[0176] In the semiconductor device shown in FIG. 5, an insulating layer 357 is provided over the transistor 362. A conductive layer is formed on the insulating layer 357 so as to at least partially overlap the drain electrode 342b. That is, the conductive layer 358 functions as one electrode of the capacitor 364. Here, the insulating layer 357 can be formed of the same material as the gate insulating film 346. The conductive layer 358 can be formed of the same material as the gate electrode 348a.

[0177] An insulating layer 350 is provided on the insulating layer 357 and the conductive layer 358. A wiring 354 is provided on the insulating layer 350, and the wiring 354 is connected to the gate insulating film 346, The source electrode 342a is connected to the insulating layer 350 through an opening formed therein. The wiring 354 overlaps with at least part of the oxide semiconductor layer 344 of the transistor 362. It is designed to do so.

[0178] In the semiconductor device shown in FIG. 5, the transistor 360 and the transistor 362 In particular, the source of the transistor 360 The source region or the drain region is provided so as to partly overlap with the oxide semiconductor layer 344. The wiring 354 is provided so as to overlap with at least part of the oxide semiconductor layer 344. In addition, the transistor 362 and the capacitor 364 overlap with the transistor 360. For example, the conductive layer 358 of the capacitor 364 is formed in the same manner as the transistor 3 60 and the gate electrode 310 are provided so as to overlap at least a part of the gate electrode 310. By adopting this layout, it is possible to achieve high integration of the semiconductor device. For example, When a memory cell is constructed using the semiconductor device, the minimum processing dimension is F, and the memory cell The area occupied by the building is 15F. 2 ~25F 2 It is possible to do so.

[0179] FIG. 5C shows an example of a circuit diagram in the case where the semiconductor device is used as a memory element. In FIG. 5C, one of a source electrode and a drain electrode of a transistor 362, One electrode of the capacitor 364 and the gate electrode of the transistor 360 are electrically connected. In addition, the first wiring (also called the source line) and the transistor 3 The source electrode of 60 is electrically connected to the second wiring (2nd Line: bit line). The drain electrode of the transistor 360 is electrically connected to the drain electrode of the transistor 360. The third line (also called the first signal line) and the source voltage of the transistor 362 The other of the source electrode and drain electrode is electrically connected to a fourth line (4th Line: The second signal line (also referred to as a second signal line) and the gate electrode of the transistor 362 are electrically connected to each other. A fifth wiring (also called a word line) and a capacitor element 364 The other electrode is electrically connected.

[0180] The transistor 362 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 362, the source of the transistor 362 one of the source electrode and drain electrode of the capacitor 364, one of the electrodes of the transistor 36 The potential of the node (hereinafter referred to as node FG) electrically connected to the gate electrode of By including the capacitor element 364, This makes it easier to retain the charge given to node FG and to read out the retained information. It becomes easier.

[0181] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to The transistor 362 is turned on by applying a potential to the transistor 362. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, the charges that give two different potential levels (hereinafter referred to as low level) are accumulated. Either a low level charge or a high level charge is given. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 362. By turning off the capacitor 362, the node FG is in a floating state, and therefore, As described above, a predetermined amount of charge is retained at node FG. By storing and holding the charge, information can be stored in the memory cell.

[0182] Since the off-state current of the transistor 362 is extremely small, the charge supplied to the node FG is Therefore, no refresh operation is required or This makes it possible to reduce the frequency of refresh operations significantly, thereby significantly reducing power consumption. In addition, even if there is no power supply, the memory contents can be maintained for a long period of time. It is possible to do this.

[0183] When reading out the stored information (reading), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge applied, transistor 360 assumes different states. If 360 is an n-channel type, when a high-level charge is held at node FG, The apparent threshold voltage V of the transistor 360 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 360 when th_L become lower Here, the apparent threshold is the value at which the transistor 360 is turned on. Therefore, the potential of the fifth wiring is V t h_H and V th_L By setting the potential V0 between the two, the charge held in node FG is For example, if a high level charge is applied during writing, , the potential of the fifth wire is V0 (>V th_H ), transistor 360 is in the "ON" state. When a low level charge is applied, the potential of the fifth wire becomes V0( <V th_L ), transistor 360 remains in the "off state." The potential of the wiring 5 is controlled to read out the on / off state of the transistor 360 ( The stored information can be read by reading out the potential of the second wiring.

[0184] In addition, when the stored information is rewritten, a predetermined amount of data is written. By supplying a new potential to the node FG that holds the charge, new information is stored in the node FG. Specifically, the potential of the fourth wiring is set to a value that is higher than the potential of the fourth wiring when the transistor 362 is turned on. The transistor 362 is turned on by applying a potential to the third wiring. A potential (potential related to new information) is supplied to node FG, and a predetermined amount of charge is applied to node FG. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 362. By turning off the transistor 362, the node FG receives the new information. That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. It is possible to overwrite the stored information.

[0185] The transistor 362 described in this embodiment is formed using a highly purified and intrinsic oxide semiconductor. By using the layer 344, the off-state current of the transistor 362 can be sufficiently reduced. By using such transistors, memory contents can be retained for an extremely long period of time. Therefore, a semiconductor device capable of performing the above-described operations can be obtained.

[0186] In the semiconductor device described in this embodiment, the transistor 360 and the transistor By overlapping the layers 362, a semiconductor device with a sufficiently high degree of integration can be realized.

[0187] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0188] (Sixth embodiment) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0189] In this embodiment, the electrical characteristics obtained in any one of the above embodiments are good and reliable. An example of an electronic device incorporating a highly efficient transistor will be described with reference to FIG.

[0190] FIG. 6A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. The personal computer includes the transistor described in the above embodiment. This allows for the realization of a notebook-type personal computer with good quality and high reliability.

[0191] FIG. 6B shows a personal digital assistant (PDA), which has a main body 3021 including a display unit 3023 and a An external interface 3025 and operation buttons 3024 are provided. The Stylus 3022 is an accessory for the PDA. Therefore, it has good quality and is highly reliable. Personal digital assistants (PDAs) will be realized.

[0192] FIG. 6C shows an electronic device manufactured by mounting the electronic paper shown in the above embodiment as a component. FIG. 6C shows an example of an electronic book. For example, electronic book 2700 The device is made up of two housings, housing 2701 and housing 2703. The housing 2703 is integrated with a shaft 2711, and is opened around the shaft 2711. This configuration allows the book to be opened and closed like a paper book. This configuration also makes it possible to withstand stronger external shocks. In addition, the shaft portion 2711 can be removed to separate the housing 2701 and the housing 2703. It is also possible.

[0193] The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 6C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 6C).

[0194] FIG. 6C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The surface may be provided with a keyboard, a pointing device, etc. On the back or side, there are external connection terminals (earphone terminal, USB terminal, AC adapter and It is equipped with a terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. It may also be composed.

[0195] The electronic book 2700 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0196] FIG. 6(D) shows a mobile phone, which is composed of two housings, housing 2800 and housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and a Phone 2804, pointing device 2806, camera lens 2807, external connection terminal The housing 2801 also includes a power supply 2808 for charging the portable information terminal. It is equipped with a solar cell 2810, an external memory slot 2811, etc. Also, the antenna It is built in the housing 2801. Note that the mobile phone is similar to the transistor shown in the above embodiment. It includes a star as at least one component.

[0197] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0198] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the lens 2802, allowing video calls. The speaker 2803 and microphone 2804 are not limited to voice calls, but are also used for video calls. It is possible to talk, record, play, etc. Furthermore, the housing 2800 and the housing 2801 can be slid As shown in Figure 6(D), the unfolded state can be folded into an overlapping state, making it easy to carry. Suitable miniaturization is possible.

[0199] The external connection terminal 2808 can be used to connect various cables such as an AC adapter and a USB cable. It is possible to charge the battery and to communicate data with a personal computer, etc. , a recording medium can be inserted into the external memory slot 2811 for storing and transferring a larger amount of data. The semiconductor device described in Embodiment 5 can be used as the recording medium. According to the fifth embodiment, a transistor capable of sufficiently reducing an off-state current is used. As a result, a semiconductor device capable of retaining stored contents for an extremely long period of time can be obtained.

[0200] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0201] FIG. 6(E) shows a digital camera, which includes a main body 3051, a display unit (A) 3057, and an eyepiece. 3053, operation switch 3054, display unit (B) 3055, battery 3056, etc. Note that the digital camera includes the transistor described in the above embodiment. This results in a high-quality, highly reliable digital camera.

[0202] As described above, the electronic devices described in this embodiment include the semiconductor device according to the above embodiment. This allows for the realization of high-quality electronic devices. [Example]

[0203] In this example, an example of the transistor in Embodiment 1 was fabricated, and Transmission Electron Microscope) measurement In addition, a STEM image of the cross-sectional shape of the transistor was observed.

[0204] In this example, a glass substrate was used as the substrate 100. The gate electrode layer 102 was formed by sputtering. The gate insulating film was formed using a tungsten target in a gate insulating film device with a thickness of 100 nm. The insulating film 104 is formed by using a silicon oxynitride target in a sputtering device, and has a thickness of 1. The oxide semiconductor layer 106 was grown at a pressure of 0.6 Pa and a direct current (DC) power supply of 5 kW. The substrate temperature was 200°C, and the deposition atmosphere was a mixture of argon and oxygen (oxygen:argon = 5 In the sputtering equipment, an In-Ga-Zn oxide semiconductor target was used under the conditions of 0:50. The thickness was 1000 nm. The protective conductive film 107 was formed by sputtering using a tungsten target. The thickness was 50 nm.

[0205] The conductive layer 108 is made up of a first conductive film 108A and a second conductive film 108B from the protective conductive film 107 side. A three-layer laminate structure was formed to form the first conductive film 108B and the third conductive film 108C. The first conductive film 108A is formed of Ti and has a thickness of 100 nm, and the second conductive film 108B is formed of A The third conductive film 108C is formed of Ti and has a thickness of 400 nm. The thickness was set to 100 nm.

[0206] In this example, ICP (Inductively Coupled Plasma) In this example, two-stage etching was performed using an inductively coupled plasma (ICP) device. The conductive layer is processed and the etching to form the conductive layer 108 is performed using a mixed gas of BCl3 and Cl2 ( After the first etching step, the gas species is changed to SF The second etching step was carried out using a mixed gas of 6 and Cl2.

[0207] The conditions for the first etching step were ICP power of 0 W, bias power of 1500 W, Pressure: 2.0 Pa, gas flow ratio of BCl3 to Cl2: 750 sccm:150 sccm The etching time was extended by 20 seconds to perform over-etching.

[0208] In the first etching step conditions of this example, the etching rate of Ti is 86.10 nm / min, the etching rate of Al is 98.40nm / min, and the etching rate of W is 12 .20nm / min.

[0209] The first conductive layer 108 is a Ti film that is in contact with the protective conductive film 107 of the conductive layer 108 having a laminated structure. The etching selectivity of the film 108A to the protective conductive film 107, which is a W film, is 86.10 nm / min divided by the etching rate of W, 12.20 nm / min. So the result is 7.06.

[0210] In the second etching process conditions in this example, the ICP power was 2000 W, the bias power was 100 W, and the Power 300W, pressure 1.5Pa, gas flow ratio of SF6 to Cl2 540sccm: The etching time was extended by 15 seconds to perform overetching. In this way, the transistor of the example was fabricated.

[0211] Under the conditions of this example, the etching rate of W was 98.40 nm / min, and that of In-Ga-Zn The etching rate of the oxide semiconductor was 2.15 nm / min.

[0212] The protective conductive film 107 is a W film, and the oxide semiconductor is an In-Ga-Zn oxide semiconductor. The etching selectivity of the W layer 106 is 98.40 nm / min. This is divided by the etching rate of a-Zn-based oxide semiconductor, 2.15 nm / min. The result was 45.77.

[0213] The conductive layer 108 having a laminated structure is processed without providing a protective conductive film 107 below the conductive layer 108. The etching process is performed using a mixture of BCl3 and Cl2 gas (first etching step). The transistors of the example and the comparative example were fabricated. The cross-sectional shapes of each sample were then observed using STEM.

[0214] FIG. 7 shows the structure of the connection portion between the oxide semiconductor layer 106 and the conductive layer 108 of the transistor of this embodiment. 8 shows a cross-sectional STEM image of the oxide semiconductor layer 106 and the conductive layer 107 of the transistor of the comparative example. A cross-sectional STEM image of the connection point 108 is shown.

[0215] In the transistor of this embodiment, the oxide semiconductor layer 1 in the portion that does not overlap with the conductive layer 108 The thickness of the oxide semiconductor layer 106 (hereinafter referred to as the first thickness) and the portion overlapping with the conductive layer 108 is The difference between the film thickness of the conductive layer 106 (hereinafter referred to as the second film thickness) is approximately 1 nm. It was. On the other hand, in the comparative transistor, the oxide semiconductor is simultaneously etched when the conductive layer 108 is etched. Since the oxide semiconductor layer 106 was also etched, the first and second thicknesses of the oxide semiconductor layer 106 were The difference in film thickness was about 20 nm.

[0216] From the above results, it is clear that the oxide semiconductor layer 106 provided under the conductive layer 108 is In this example, the protective conductive film 107 was overetched by about 20 nm. As a result, the oxide semiconductor layer 106 provided under the conductive layer 108 is almost completely etched. As described above, by the method for manufacturing a transistor of this example, an oxide semiconductor To reduce excessive etching of the conductor layer and variations in the thickness of the oxide semiconductor layer. This allows for improved productivity and allows transistors to be manufactured with high yield. It can be seen that... [Example]

[0217] In this embodiment, another example that can be used as the condition for the second etching step will be shown. The structure and manufacturing process of the transistor of this example are the same as those of the second etching process. The second etching process conditions in this example are the same as those in Example 1. The ICP power is 2 000W, bias power 300W, pressure 1.5Pa, gas flow rate of SF6 and Cl2 The ratio was 450sccm:630sccm, and the etching time was extended by 15 seconds. As a result, the transistor of the example was fabricated and STEM measurements were performed. The transistor of this example was subjected to STEM observation of its cross-sectional shape.

[0218] FIG. 9 shows the structure of the connection portion between the oxide semiconductor layer 106 and the conductive layer 108 of the transistor of this embodiment. A cross-sectional STEM image is shown.

[0219] In the transistor manufactured under the conditions of the second etching step of this example, the oxide semiconductor There was almost no difference between the first and second film thicknesses of the conductor layer 106, and the difference was approximately 1 nm. In this example, the protective conductive film 107 prevents the oxide film provided under the conductive layer 108 from The semiconductor layer 106 was hardly etched.

[0220] As shown in FIG. 9, the first conductive film 108A, the second conductive film 108B, and the third conductive film 108C are It can be seen that the ends of the conductive film 108C are almost aligned and form a continuous shape. The first conductive film 108A, the second conductive film 108B, and the third conductive film 108C The first conductive film 108A and the second conductive film 108B have a continuous shape with reduced steps at their ends. Coverage of the films formed on the second conductive film 108B and the third conductive film 108C can be improved.

[0221] As described above, by the method for manufacturing a transistor of this example, an excess edge of the oxide semiconductor layer can be removed. This can reduce variations in the thickness of the oxide semiconductor layer and the semiconductor film. It is clear that this improves the efficiency and enables transistors to be fabricated with a high yield. In addition, by controlling the etching process, it is possible to process it into a good shape, This makes it possible to suppress the leakage current of transistors and create high-performance, highly reliable transistors. You will realize something. [Explanation of symbols]

[0222] 100 boards 102 gate electrode layer 104 Gate insulating film 106 Oxide semiconductor layer 107 Protective conductive film 108 Conductive layer 108A conductive film 108B Conductive film 108C conductive film 110 Resist mask 112 Wiring layer 114 Conductive layer 116 Insulating film 120 transistors 200 boards 201 Undercoat insulation layer 202 gate electrode layer 204 Gate insulating film 206 Oxide semiconductor layer 207 Protective Conductive Film 208 Conductive Layer 210 Resist mask 212 Wiring layer 214 Conductive layer 220 transistors 300 boards 306 Element isolation insulating layer 308 Gate insulating film 310 Gate electrode 316 Channel formation region 320 Impurity region 324 Metal compound area 326 Electrode 328 Insulating Layer 341a Conductive film 341b Conductive film 342a Source electrode 342b Drain electrode 344 Oxide semiconductor layer 346 Gate insulating film 348a Gate electrode 350 insulating layer 354 Wiring 357 Insulating Layer 358 Conductive Layer 360 Transistor 362 transistors 364 Capacitor 580 board 581 Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 595 Filling material 596 PCB 2700 e-books 2701 Case 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 External Memory Slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4041 Insulation layer 4042 Insulation layer

Claims

1. a first transistor, a second transistor, and a capacitor; one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to one of the source electrode and the drain electrode of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate electrode of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the silicon semiconductor layer; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; an oxide semiconductor layer having a region located above the second conductive film and including a channel formation region of the second transistor; a third conductive film having a region located above the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive film having a region located above the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth conductive film that functions as the other electrode of the capacitor element; the oxide semiconductor layer does not have a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with the first conductive film, the first conductive film and the second conductive film are spaced apart from each other in a plan view; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to one of the source electrode and the drain electrode of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate electrode of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the silicon semiconductor layer; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; an oxide semiconductor layer having a region located above the second conductive film and including a channel formation region of the second transistor; a third conductive film having a region located above the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive film having a region located above the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth conductive film that functions as the other electrode of the capacitor element; the oxide semiconductor layer does not have a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with a channel formation region of the first transistor, the first conductive film and the second conductive film are spaced apart from each other in a plan view; Semiconductor device.

3. a first transistor, a second transistor, and a capacitor; one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to one of the source electrode and the drain electrode of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate electrode of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the silicon semiconductor layer; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; an oxide semiconductor layer having a region located above the second conductive film and including a channel formation region of the second transistor; a third conductive film having a region located above the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive film having a region located above the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth conductive film that functions as the other electrode of the capacitor element; the oxide semiconductor layer does not have a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with the first conductive film, the first conductive film and the second conductive film are spaced apart from each other in a plan view; the fifth conductive film is separated from the oxide semiconductor layer in a plan view. Semiconductor device.

4. a first transistor, a second transistor, and a capacitor; one of the source electrode and the drain electrode of the second transistor is always electrically connected to the gate electrode of the first transistor; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to one of the source electrode and the drain electrode of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate electrode of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the silicon semiconductor layer; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; an oxide semiconductor layer having a region located above the second conductive film and including a channel formation region of the second transistor; a third conductive film having a region located above the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth conductive film having a region located above the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the second transistor; a fifth conductive film that functions as the other electrode of the capacitor element; the oxide semiconductor layer does not have a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with the first conductive film, the fifth conductive film has a region overlapping with a channel formation region of the first transistor, the first conductive film and the second conductive film are spaced apart from each other in a plan view; the fifth conductive film is separated from the oxide semiconductor layer in a plan view. Semiconductor device.

5. In any one of claims 1 to 4, each of the third conductive film and the fourth conductive film includes a first film containing titanium and a second film containing aluminum disposed above the first film; Semiconductor device.

6. In any one of claims 1 to 5, the oxide semiconductor layer contains In, Ga, and Zn; Semiconductor device.

7. In any one of claims 1 to 6, the oxide semiconductor layer contains indium oxide; Semiconductor device.

Images