Semiconductor device

Abstract

To provide a semiconductor device that can prevent a conductor layer from being exposed at a cut surface of a substrate.SOLUTION: A semiconductor device (100, 300) includes a substrate (10). The substrate includes a base material (11), a first conductor layer (12), and a second conductor layer (13). The base material has a first main surface (11a) and a second main surface (11b) opposite the first main surface. The first conductor layer and the second conductor layer are disposed on the first main surface and the second main surface, respectively. In plan view, the first conductor layer is spaced apart from the outer periphery of the first main surface, and the second conductor layer is spaced apart from the outer periphery of the second main surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2022-81300 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a substrate.

[0003] The substrate has a base material, a first conductor layer, a second conductor layer, a first electrolytically plated layer, and a second electrolytically plated layer. The base material has a first main surface and a second main surface opposite the first main surface. The first conductor layer and the second conductor layer are disposed on the first main surface and the second main surface, respectively. The first electrolytically plated layer and the second electrolytically plated layer are disposed on the first conductor layer and the second conductor layer, respectively. The substrate is obtained by cutting a single pre-cut substrate that includes multiple substrates. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-81300 A [Summary] One substrate included in the pre-cut substrate is referred to as the first substrate, and the other substrate adjacent to the first substrate is referred to as the second substrate. In order to form the first electrolytic plated layer and the second electrolytic plated layer by electrolytic plating, it is necessary that a connection exists between the first conductor layer on the first substrate and the first conductor layer on the second substrate, or that a connection exists between the second conductor layer on the first substrate and the second conductor layer on the second substrate. From another perspective, it is necessary that either the first conductor layer reaches the outer periphery of the first main surface or the second conductor layer reaches the outer periphery of the second main surface.

[0005] As a result, when the pre-cut substrate is cut, the first conductor layer or the second conductor layer is present on the cut surface, which may cause burrs or short circuits between the first conductor layer and the second conductor layer.

[0006] The semiconductor device of the present disclosure includes a substrate. The substrate has a base material, a first conductor layer, and a second conductor layer. The base material has a first main surface and a second main surface opposite the first main surface. The first conductor layer and the second conductor layer are disposed on the first main surface and the second main surface, respectively. In a plan view, the first conductor layer is spaced apart from the outer periphery of the first main surface, and the second conductor layer is spaced apart from the outer periphery of the second main surface. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device 100. [Figure 2] FIG. 2 is a bottom view of the semiconductor device 100. [Figure 3] FIG. 1 is a cross-sectional view of a semiconductor device 100. [Figure 4] 1A to 1C are diagrams illustrating the manufacturing process of the semiconductor device 100. [Figure 5] FIG. 10 is a plan view illustrating the hole drilling step S2. [Figure 6A] FIG. 10 is a plan view illustrating the conductor layer patterning step S3. [Figure 6B] FIG. 10 is a bottom view illustrating the conductor layer patterning step S3. [Figure 7] FIG. 10 is a plan view illustrating the electroless plating step S4. [Figure 8A] FIG. 10 is a plan view illustrating the electroless plating step S5. [Figure 8B] FIG. 10 is a bottom view illustrating the electroless plating step S5. [Figure 9] FIG. 10 is a plan view illustrating a resist forming step S6. [Figure 10] FIG. 10 is a plan view illustrating a semiconductor element mounting step S7. [Figure 11] FIG. 10 is a plan view illustrating the wire bonding step S8. [Figure 12] FIG. 10 is a cross-sectional view illustrating a resin sealing step S9. [Figure 13] FIG. 2 is a plan view of the semiconductor device 200. [Figure 14] 10 is a plan view illustrating a conductor layer patterning step S3 in manufacturing the semiconductor device 200. FIG. [Figure 15] FIG. 2 is a plan view of the semiconductor device 300. [Figure 16] FIG. 2 is a bottom view of the semiconductor device 300.

[0008] [Detailed explanation] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device according to the first embodiment will be described below. The semiconductor device according to the first embodiment is designated as semiconductor device 100.

[0010] FIG. 1 is a plan view of the semiconductor device 100. Note that the sealing resin 50 is not shown in FIG. 1. FIG. 2 is a bottom view of the semiconductor device 100. FIG. 3 is a cross-sectional view of the semiconductor device 100. As shown in FIGS. 1 to 3, the semiconductor device 100 has a substrate 10, a resist 20, a semiconductor element 30, bonding wires 40 and 41, and sealing resin 50.

[0011] The substrate 10 includes a base material 11, a conductor layer 12, a conductor layer 13, and a conductor layer 14. The base material 11 includes a main surface 11a, a main surface 11b, and a side surface 11c. The main surface 11b is the surface opposite to the main surface 11a. The main surface 11a and the main surface 11b are end surfaces of the base material 11 in the thickness direction. The normal direction of the main surface 11a (main surface 11b) is defined as a first direction DR1. The semiconductor device 100 viewed along the first direction DR1 is referred to as a planar view. The longitudinal direction of the base material 11 in the planar view is aligned with a second direction DR2. The second direction DR2 is perpendicular to the first direction DR1. The direction perpendicular to the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The side surface 11c is continuous with the main surface 11a and the main surface 11b. The base material 11 is formed of an electrically insulating material. The substrate 11 is made of, for example, BT (Bismaleimide-Triazine) resin.

[0012] The conductor layer 12 is disposed on the principal surface 11a. The conductor layer 12 is made of a conductive material. The conductor layer 12 is made of, for example, copper. The conductor layer 12 has a conductor pattern 12a, a conductor pattern 12b, a conductor pattern 12c, and a conductor pattern 12d. The conductor layer 12 (the conductor patterns 12a, 12b, 12c, and 12d) are spaced apart from the outer periphery of the principal surface 11a in a plan view. From another perspective, the conductor layer 12 is located inside the outer periphery of the principal surface 11a in a plan view.

[0013] The conductor pattern 12a has a land 12aa and a land 12ab. In a plan view, the land 12aa is located at one end of the conductor pattern 12a, and the land 12ab is located at the other end of the conductor pattern 12a. The outer periphery of the land 12ab includes a partial arc. The central angle of the partial arc is, for example, 180° or more. The conductor pattern 12b has a land 12ba and a land 12bb. In a plan view, the land 12ba is located at one end of the conductor pattern 12b, and the land 12bb is located at the other end of the conductor pattern 12b. The outer periphery of the land 12bb includes a partial arc. The central angle of the partial arc is, for example, 180° or more.

[0014] Conductive pattern 12c has land 12ca and land 12cb. In plan view, land 12ca is located at one end of conductive pattern 12c, and land 12cb is located at the other end of conductive pattern 12c. The outer periphery of land 12cb includes a partial arc. The central angle of the partial arc is, for example, 180° or more. Conductive pattern 12d has land 12da and land 12db. In plan view, land 12da is located at one end of conductive pattern 12d, and land 12db is located at the other end of conductive pattern 12d. The outer periphery of land 12db includes a partial arc. The central angle of the partial arc is, for example, 180° or more.

[0015] The conductor layer 13 is disposed on the principal surface 11b. The conductor layer 13 is formed of a conductive material, for example, copper. The conductor layer 13 has conductor patterns 13a, 13b, 13c, and 13d. The conductor layer 13 (conductor patterns 13a, 13b, 13c, and 13d) are spaced apart from the outer periphery of the principal surface 11b in a plan view. From another perspective, the conductor layer 13 is located inside the outer periphery of the principal surface 11b in a plan view.

[0016] The conductor patterns 13a, 13b, 13c, and 13d are rectangular in shape with their longitudinal directions aligned with the second direction DR2 in plan view. The conductor patterns 13a, 13b, 13c, and 13d overlap the lands 12ab, 12bb, 12cb, and 12db in plan view.

[0017] The minimum value of the creepage distance between the conductor layer 12 (conductor pattern 12a, conductor pattern 12b, conductor pattern 12c, conductor pattern 12d) and the conductor layer 13 (conductor pattern 13a, conductor pattern 13b, conductor pattern 13c, conductor pattern 13d) along the main surface 11a, the side surface 11c, and the main surface 11b is, for example, 1.8 times or more the thickness of the base material 11.

[0018] The substrate 10 is formed with through holes 15a, 15b, 15c, and 15d. The through hole 15a extends along the first direction DR1 and penetrates the substrate 11 and the land 12ab. The conductor pattern 13a is exposed from the through hole 15a. The through hole 15b extends along the first direction DR1 and penetrates the substrate 11 and the land 12bb. The conductor pattern 13b is exposed from the through hole 15b. The through hole 15c extends along the first direction DR1 and penetrates the substrate 11 and the land 12cb. The conductor pattern 13c is exposed from the through hole 15c. The through hole 15d extends along the first direction DR1 and penetrates the substrate 11 and the land 12db. The conductor pattern 13d is exposed from the through hole 15d.

[0019] The conductor layer 14 is disposed on the inner wall surface of the through hole 15a, on the conductor pattern 13a exposed from the through hole 15a, on the inner wall surface of the through hole 15b, on the conductor pattern 13b exposed from the through hole 15b, on the inner wall surface of the through hole 15c, on the conductor pattern 13c exposed from the through hole 15c, on the inner wall surface of the through hole 15d and on the conductor pattern 13d exposed from the through hole 15d. The conductor layer 14 is formed of a conductive material. For example, the conductor layer 14 is formed of copper. For example, the conductor layer 14 is an electroless plated layer (a layer formed by electroless plating).

[0020] Conductive pattern 12a, conductor pattern 12b, conductor pattern 12c, and conductor pattern 12d are electrically connected to conductor pattern 13a, conductor pattern 13b, conductor pattern 13c, and conductor pattern 13d, respectively, via conductor layer 14. Resin layer 16 may be embedded inside through hole 15a, through hole 15b, through hole 15c, and through hole 15d. Resin layer 16 may be embedded inside conductor layer 14.

[0021] Substrate 10 further has electroless plated layer 17 and electroless plated layer 18. Electroless plated layer 17 covers the surfaces (top and side surfaces) of conductor layer 12 (conductor patterns 12a, 12b, 12c, and 12d). Electroless plated layer 18 covers the surfaces (top and side surfaces) of conductor layer 13 (conductor patterns 13a, 13b, 13c, and 13d).

[0022] Electroless plated layer 17 and electroless plated layer 18 are each composed of, for example, multiple layers. The multiple layers are, for example, a nickel layer, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. The multiple layers may also be a nickel layer and a gold layer formed on the nickel layer.

[0023] The resist 20 is disposed on the main surface 11a so as to partially cover the electroless plated layer 17. It is sufficient that the resist 20 covers at least the electroless plated layer 17 disposed on the surfaces of the lands 12ab, 12bb, 12cb, and 12db. The resist 20 is formed of, for example, solder resist.

[0024] 1 to 3, the number of semiconductor elements 30 is two. These two semiconductor elements 30 may be referred to as semiconductor element 30A and semiconductor element 30B, respectively. The semiconductor elements 30 are, for example, light-emitting diodes (LEDs). However, the semiconductor elements 30 are not limited to this.

[0025] The semiconductor element 30 has a back surface electrode 31 and a front surface electrode 32. The semiconductor element 30A is disposed on the land 12ba such that the back surface electrode 31 faces the land 12ba with the electroless plating layer 17 and the bonding material 33 interposed therebetween. The semiconductor element 30B is disposed on the land 12da such that the back surface electrode 31 faces the land 12da with the electroless plating layer 17 and the bonding material 33 interposed therebetween. As a result, the semiconductor element 30A is electrically connected to the conductive pattern 12b, and the semiconductor element 30B is electrically connected to the conductive pattern 12d. The bonding material 33 is, for example, a solder alloy, a conductive adhesive, or the like.

[0026] One end of the bonding wire 40 is connected to the surface electrode 32 of the semiconductor element 30A, and the other end is connected to the land 12aa. This electrically connects the semiconductor element 30A to the conductor pattern 12a. One end of the bonding wire 41 is connected to the surface electrode 32 of the semiconductor element 30B, and the other end is connected to the land 12ca. This electrically connects the semiconductor element 30A to the conductor pattern 12c. The bonding wires 40 and 41 are made of, for example, gold.

[0027] The sealing resin 50 is disposed on the substrate 10 (main surface 11a) so as to cover the semiconductor element 30A, the semiconductor element 30B, the bonding wire 40, and the bonding wire 40. The sealing resin 50 is made of a resin material. When the semiconductor element 30 is an LED, the sealing resin 50 is made of a resin material that transmits light generated by the LED.

[0028] <Method of Manufacturing the Semiconductor Device 100> A method for manufacturing the semiconductor device 100 will be described below.

[0029] Fig. 4 is a manufacturing process diagram of the semiconductor device 100. As shown in Fig. 4, the manufacturing method of the semiconductor device 100 includes a preparation step S1, a hole drilling step S2, a conductor layer patterning step S3, an electroless plating step S4, an electroless plating step S5, a resist formation step S6, a semiconductor element mounting step S7, a wire bonding step S8, a resin sealing step S9, and a singulation step S10.

[0030] In the preparation step S1, a substrate 60 is prepared. The substrate 60 has a main surface 60a and a main surface 60b. The main surface 60b is the surface opposite to the main surface 60a. The main surfaces 60a and 60b are end surfaces of the substrate 60 in the thickness direction. A conductor layer 12 and a conductor layer 13 are disposed on the main surface 60a and the main surface 60b, respectively. The substrate 60 includes a plurality of substrates 11.

[0031] Fig. 5 is a plan view illustrating the hole drilling step S2. As shown in Fig. 5, through holes 15a, 15b, 15c, and 15d are formed by performing hole drilling using laser irradiation, a drill, or the like.

[0032] FIG. 6A is a plan view illustrating the conductor layer patterning step S3. FIG. 6B is a bottom view illustrating the conductor layer patterning step S3. As shown in FIGS. 6A and 6B, in the conductor layer patterning step S3, the conductor layers 12 and 13 are etched to pattern the conductor layers 12 and 13. As a result, the conductor layer 12 has conductor patterns 12a, 12b, 12c, and 12d. As a result, the conductor layer 13 has conductor patterns 13a, 13b, 12c, and 12d. The etching is performed using resist patterns formed on the conductor layers 12 and 13 as a mask. The resist patterns are formed by depositing photoresist on the conductor layers 12 and 13 and then exposing and developing the deposited photoresist.

[0033] 7 is a plan view illustrating the electroless plating step S4. As shown in FIG. 7, in the electroless plating step S4, electroless plating is performed to form a conductor layer 14 on the inner wall surface of through hole 15a, on conductive pattern 13a exposed from through hole 15a, on the inner wall surface of through hole 15b, on conductive pattern 13b exposed from through hole 15b, on the inner wall surface of through hole 15c, on conductive pattern 13c exposed from through hole 15c, on the inner wall surface of through hole 15d, and on conductive pattern 13d exposed from through hole 15d. After the conductor layer 14 is formed, a resin layer 16 is embedded.

[0034] FIG. 8A is a plan view illustrating the electroless plating step S5. FIG. 8B is a bottom view illustrating the electroless plating step S5. As shown in FIGS. 8A and 8B, in the electroless plating step S5, electroless plating is performed to form an electroless plated layer 17 covering the surface of the conductor layer 12, and an electroless plated layer 18 covering the surface of the conductor layer 13. FIG. 9 is a plan view illustrating the resist forming step S6. As shown in FIG. 9, in the resist forming step S6, the constituent material of the resist 20 is applied and hardened to form the resist 20.

[0035] Fig. 10 is a plan view illustrating the semiconductor element mounting step S7. As shown in Fig. 10, in the semiconductor element mounting step S7, first, the semiconductor element 30A is placed on the land 12ba with the electroless plating layer 17 and the bonding material 33 interposed therebetween, and the semiconductor element 30B is placed on the land 12da with the electroless plating layer 17 and the bonding material 33 interposed therebetween. Second, heating is performed to bond the back electrode 31 and the electroless plating layer 17 together.

[0036] 11 is a plan view illustrating the wire bonding step S8. As shown in FIG. 11, in the wire bonding step S8, wire bonding is performed to connect the surface electrodes 32 of the semiconductor element 30A to the lands 12aa with bonding wires 40, and also to connect the surface electrodes 32 of the semiconductor element 30B to the lands 12ca with bonding wires 41.

[0037] 12 is a cross-sectional view illustrating the resin sealing step S9. As shown in FIG. 12, in the resin sealing step S9, the semiconductor element 30A, the semiconductor element 30B, the bonding wire 40, and the bonding wire 41 are sealed by, for example, transfer molding. In the singulation step S10, the base material 60 is diced along the boundaries between adjacent base materials 11 to singulate the base material 60 into a plurality of semiconductor devices 100. In this way, the structure of the semiconductor device 100 shown in FIGS. 1 to 3 is formed.

[0038] <Effects of the semiconductor device 100> The effects of the semiconductor device 100 will be described in comparison with a semiconductor device according to a comparative example.

[0039] FIG. 13 is a plan view of semiconductor device 200. As shown in FIG. 13, in semiconductor device 200, conductor layer 12 (conductor patterns 12a, 12b, 12c, and 12d) reach the outer periphery of main surface 11a in a plan view. In semiconductor device 200, the surface of conductor layer 12 is covered with electrolytic plating layer 19 rather than electroless plating layer 17. Although not shown, the surface of conductor layer 13 (conductor patterns 13a, 13b, 13c, and 13d) is covered with electrolytic plating layer rather than electroless plating layer 18. In these respects, the configuration of semiconductor device 200 differs from the configuration of semiconductor device 100.

[0040] 14 is a plan view illustrating the conductor layer patterning step S3 in manufacturing the semiconductor device 200. As shown in FIG. 14, in the manufacturing method of the semiconductor device 200, after the conductor layer 12 is patterned in the conductor layer patterning step S3, the conductor layer 12 on one substrate 11 and the conductor layer 12 on another substrate 11 adjacent to the one substrate 11 are connected to each other. This is because, in the manufacturing method of the semiconductor device 200, an electrolytic plating step is performed to form the electrolytic plated layer 19 instead of the electroless plating step S5, and in this electrolytic plating step, it is necessary to make the entire conductor layer 12 on the substrate 60 conductive.

[0041] In the manufacturing method of the semiconductor device 200, the conductor layer 12 on one substrate 11 and the conductor layer 12 on another substrate 11 adjacent to the one substrate 11 are connected to each other, and therefore, when the dicing is performed in the singulation step S10, the conductor layer 12 reaches the outer periphery of the main surface 11a in a plan view, and the conductor layer 12 is exposed at the cut surface during dicing. As a result, copper sulfide precipitated when the conductor layer 12 and the conductor layer 13 are sulfurized may short-circuit the conductor layer 12 and the conductor layer 13. Furthermore, in the manufacturing method of the semiconductor device 200, the conductor layer 12 on one substrate 11 is cut from the conductor layer 12 on the other substrate 11 adjacent to the one substrate 11 by dicing, and therefore, burrs may occur in the conductor layer 12 at the cut surface.

[0042] On the other hand, in the manufacturing method of the semiconductor device 100, the surface of the conductor layer 12 is covered with the electroless plating layer 17, so there is no need to connect the conductor layer 12 on one base material 11 to the conductor layer 12 on another base material 11 adjacent to the one base material 11. As a result, the dicing cut in the singulation step S10 prevents the conductor layer 12 from reaching the outer periphery of the main surface 11a in plan view, and the conductor layer 12 is not exposed on the cut surface during dicing.

[0043] In this way, the semiconductor device 100 suppresses short circuits between the conductor layers 12 and 13 and the generation of burrs on the cut surfaces of the conductor layers 12. If the minimum value of the creepage distance between the conductor layers 12 and 13 along the main surface 11a, the side surface 11c, and the main surface 11b is 1.8 times or more the thickness of the base material 11, it is possible to more reliably suppress short circuits between the conductor layers 12 and 13.

[0044] (Second embodiment) The semiconductor device according to the second embodiment will be described below. The semiconductor device according to the second embodiment is designated as semiconductor device 300.

[0045] <Configuration of Semiconductor Device 300> The configuration of the semiconductor device 300 will be described below.

[0046] FIG. 15 is a plan view of the semiconductor device 300. The sealing resin 50 is not shown in FIG. 15. FIG. 16 is a bottom view of the semiconductor device 300. As shown in FIGS. 15 and 16, in the semiconductor device 300, the conductor layer 12 does not have the conductor patterns 12c and 12d, and the conductor layer 13 does not have the conductor patterns 13c and 13d. Furthermore, in the semiconductor device 300, the substrate 10 does not have the through-holes 15c and 15d. Furthermore, in the semiconductor device 300, the conductor patterns 12a, 12b, 13a, and 13b are rectangular in shape with their longitudinal directions aligned with the second direction DR2 in a plan view. Except for these points, the configuration of the semiconductor device 300 is the same as that of the semiconductor device 100.

[0047] <Effects of the semiconductor device 300> In the semiconductor device 300, the conductor layer 12 is spaced apart from the outer periphery of the main surface 11a, and the conductor layer 13 is spaced apart from the outer periphery of the main surface 11b, which prevents short circuits between the conductor layers 12 and 13 and prevents burrs from being generated on the cut surfaces of the conductor layer 12. In the semiconductor device 300, it is not necessary to extend the conductor layer 12 to reach the outer periphery of the main surface 11a, and it is not necessary to extend the conductor layer 13 to reach the outer periphery of the main surface 11b, so the areas of the conductor patterns 12a, 12b, 13a, and 13c can be reduced, which enables reduction in manufacturing costs.

[0048] (Addendum) Embodiments of the present disclosure include the following configurations.

[0049] <Appendix 1> a substrate; the substrate has a base material, a first conductor layer, and a second conductor layer; the substrate has a first main surface and a second main surface opposite the first main surface, the first conductor layer and the second conductor layer are disposed on the first main surface and the second main surface, respectively; A semiconductor device, wherein, in a plan view, the first conductor layer is spaced apart from an outer peripheral edge of the first main surface, and the second conductor layer is spaced apart from an outer peripheral edge of the second main surface.

[0050] <Appendix 2> the substrate further has a side surface continuous to the first main surface and the second main surface, The semiconductor device described in Appendix 1, wherein the minimum value of the creepage distance between the first conductor layer and the second conductor layer along the first main surface, the second main surface, and the side surface is 1.8 times or more the thickness of the base material.

[0051] <Appendix 3> the substrate further comprises a first electroless plated layer and a second electroless plated layer; 3. The semiconductor device according to claim 1, wherein the first electroless plated layer and the second electroless plated layer are disposed on the first conductor layer and the second conductor layer, respectively.

[0052] <Appendix 4> A semiconductor element; and a bonding wire, the first conductor layer has a first conductor pattern and a second conductor pattern; the first conductor pattern has a first land, the second conductor pattern has a second land, the semiconductor element is disposed on the first land, 4. The semiconductor device according to claim 3, wherein the bonding wire is connected to the semiconductor element at one end and to the second land at the other end.

[0053] <Appendix 5> the first conductor pattern has a third land at an end opposite to the first land, the second conductor pattern has a fourth land at an end opposite to the second land, In a plan view, an outer peripheral edge of the third land has a first partial arc, In a plan view, an outer peripheral edge of the fourth land has a second partial arc, 5. The semiconductor device according to claim 4, wherein a central angle of the first partial arc and a central angle of the second partial arc are 180° or greater.

[0054] <Appendix 6> Further provided with a sealing resin, 6. The semiconductor device according to claim 4, wherein the sealing resin is disposed on the substrate so as to cover the semiconductor element and the bonding wires.

[0055] <Appendix 7> the semiconductor element is an LED, 7. The semiconductor device according to claim 6, wherein the sealing resin is formed of a resin material that transmits light generated by the LED.

[0056] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0057] 10 substrate, 11 base material, 11a, 11b main surface, 11c side surface, 12 conductor layer, 12a conductor pattern, 12aa, 12ab lands, 12b conductor pattern, 12ba, 12bb lands, 12c conductor pattern, 12ca, 12cb lands, 12a conductor pattern, 12da, 12db lands, 13 conductor layer, 13a, 13b, 13c, 13d conductor pattern, 14 conductor layer, 15a, 15b, 15c, 15d through hole, 16 resin layer, 17 electroless plating layer, 18 electroless plating layer, 19 electrolytic plating layer, 20 resist, 30, 30A, 30B semiconductor element, 31 back electrode, 32 front electrode, 33 bonding material, 40 bonding wire, 41 bonding wire, 50 sealing resin, 60 Base material, 60a, 60b main surfaces, 100, 200, 300 semiconductor device, DR1 first direction, DR2 second direction, DR3 third direction, S1 preparation process, S2 hole drilling process, S3 conductor layer patterning process, S4, S5 electroless plating process, S6 resist formation process, S7 semiconductor element mounting process, S8 wire bonding process, S9 resin sealing process, S10 singulation process.

Claims

1. a substrate; the substrate has a base material, a first conductor layer, and a second conductor layer; the substrate has a first major surface and a second major surface opposite to the first major surface, the first conductor layer and the second conductor layer are disposed on the first main surface and the second main surface, respectively; In a plan view, the first conductor layer is spaced apart from an outer peripheral edge of the first main surface, and the second conductor layer is spaced apart from an outer peripheral edge of the second main surface.

2. the substrate further has a side surface continuous to the first main surface and the second main surface, 2. The semiconductor device according to claim 1, wherein a minimum value of a creepage distance between the first conductor layer and the second conductor layer along the first main surface, the second main surface, and the side surface is 1.8 times or more the thickness of the base material.

3. the substrate further comprises a first electroless plated layer and a second electroless plated layer; 2. The semiconductor device according to claim 1, wherein the first electrolessly plated layer and the second electrolessly plated layer are disposed on the first conductor layer and the second conductor layer, respectively.

4. A semiconductor element; and a bonding wire, the first conductor layer has a first conductor pattern and a second conductor pattern; the first conductor pattern has a first land; the second conductor pattern has a second land, the semiconductor element is disposed on the first land, 4. The semiconductor device according to claim 3, wherein one end of the bonding wire is connected to the semiconductor element, and the other end is connected to the second land.

5. the first conductor pattern has a third land at an end opposite to the first land, the second conductor pattern has a fourth land at an end opposite to the second land, In a plan view, an outer peripheral edge of the third land has a first partial arc, In a plan view, an outer peripheral edge of the fourth land has a second partial arc, The semiconductor device according to claim 4 , wherein a central angle of the first partial arc and a central angle of the second partial arc are equal to or greater than 180°.

6. Further provided with a sealing resin, 5. The semiconductor device according to claim 4, wherein the sealing resin is disposed on the substrate so as to cover the semiconductor element and the bonding wires.

7. the semiconductor element is an LED, The semiconductor device according to claim 6 , wherein the sealing resin is made of a resin material that transmits light generated by the LED.

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