Semiconductor device

Abstract

To provide a semiconductor device capable of improving durability.SOLUTION: A semiconductor device according to an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a first conductive part, a fifth semiconductor region of the second conductivity type, a second conductive part, and a second electrode. A first depth in a first direction from an upper surface of the fourth semiconductor region to a lower end of a first insulating layer is 1.05 μm or more. A distance in the first direction from the upper surface of the fourth semiconductor region to a boundary between the first semiconductor region and the second semiconductor region is 2.8 μm or more. A ratio of the distance to the first depth is 2.15 or more and 3.05 or less. A second depth in the first direction from the upper surface of the fourth semiconductor region to the lower end of a second insulating layer is 1.05 μm or more. The ratio of the distance to the second depth is 2.15 or more and 3.05 or less.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. It is desirable for semiconductor devices to have high withstand voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168659 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving the withstand voltage. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a first conductive portion, a fifth semiconductor region of the second conductivity type, a second conductive portion, and a second electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region includes a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction extending from the first electrode toward the first semiconductor region. The first semiconductor region is provided on the first semiconductor region and has a lower impurity concentration of the first conductivity type than the first semiconductor region. The third semiconductor region is provided on the first portion. The fourth semiconductor region is provided on the third semiconductor region. The first conductive portion faces the third semiconductor region via a first insulating layer in a second direction perpendicular to the first direction extending from the first electrode toward the first semiconductor region. A first depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the first insulating layer is 1.05 μm or more. A distance in the first direction from the upper surface of the fourth semiconductor region to a boundary between the first semiconductor region and the second semiconductor region is 2.8 μm or more. A ratio of the distance to the first depth is 2.15 or more and 3.05 or less. The fifth semiconductor region is provided on the second portion. The second conductive portion faces the fifth semiconductor region in the second direction via a second insulating layer. A second depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the second insulating layer is 1.05 μm or more. A ratio of the distance to the second depth is 2.15 or more and 3.05 or less. The second electrode is provided on the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged perspective cross-sectional view of a portion II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] 4A and 4B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 5] 5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a part of FIG. [Figure 7] FIG. 7 is a graph illustrating the profile of the n-type impurity concentration in the semiconductor device according to the embodiment. [Figure 8] 8(a) to 8(c) show simulation results showing the characteristics of the semiconductor device according to the embodiment. [Figure 9] FIG. 9 shows another simulation result showing the characteristics of the semiconductor device according to the embodiment. [Figure 10] FIG. 10 shows another simulation result showing the characteristics of the semiconductor device according to the embodiment. [Figure 11] FIG. 11 shows another simulation result showing the characteristics of the semiconductor device according to the embodiment. [Figure 12] 12(a) to 12(f) show other simulation results showing the characteristics of the semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and each drawing, elements similar to those already described are designated by the same reference numerals, and detailed description will be omitted as appropriate. In the following description and drawings, n + , n, n -and p, p - The notation indicates the relative level of each impurity concentration. That is, a notation with a "+" indicates a relatively higher impurity concentration than a notation with neither a "+" nor a "-" and a notation with a "-" indicates a relatively lower impurity concentration than a notation with neither. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment, Fig. 2 is an enlarged perspective cross-sectional view of a portion II in Fig. 1, and Fig. 3 is a cross-sectional view taken along the line III-III in Fig. 1. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIGS. + Type (first conductivity type) drain region 1 (first semiconductor region), n - type (first conductivity type) drift region 2 (first semiconductor region), p - type (second conductivity type) base region 3 (third semiconductor region), n-type source region 4 (fourth semiconductor region), p - Semiconductor region 5 (fifth semiconductor region), p - The semiconductor region 6 includes a first conductive portion 11, a first insulating layer 11a, a second conductive portion 12, a second insulating layer 12a, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), and a gate pad 23. In FIG. 2, the source electrode 22 is indicated by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. + The direction toward the drain region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the n-type drift region 2 is called "up" and the opposite direction is called "down." These directions are- The shape is based on the relative position to the drift region 2 and is independent of the direction of gravity.

[0010] 1, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are spaced apart from each other and electrically isolated from each other.

[0011] As shown in FIG. 2, a drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The drain region 1 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 2 is n + The n-type drain region 1 is provided on the n-type drain region 1. - The drift region 2 is n + The n-type drain region 1 is electrically connected to the drain electrode 21. - The n-type impurity concentration in the n-type drift region 2 is + The n-type impurity concentration in the n-type drain region 1 is lower than that in the n-type drain region 2.

[0012] n - As shown in FIGS. 1 to 3, the drift region 2 includes a first portion 2a and a second portion 2b. The second portion 2b is located around the first portion 2a in the XY plane (first plane). The first portion 2a is located in the cell region. The cell region is a region through which current mainly flows when the semiconductor device 100 is in operation. The second portion 2b is located in the termination region. The termination region is a region in which a depletion layer extends toward the periphery of the semiconductor device 100 when the semiconductor device 100 is at its breakdown voltage.

[0013] As shown in Figures 2 and 3, - The n-type base region 3 is provided on the first portion 2a. The n-type source region 4 is - The first conductive portion 11 is provided on the first portion 2a via a first insulating layer 11a. The first conductive portion 11 is connected to the p - It faces the shape base area 3.

[0014] As shown in Figure 3, p - The semiconductor region 5 is provided on the second portion 2b. The second conductive portion 12 is provided on the second portion 2b via the second insulating layer 12a. The second conductive portion 12 is connected to the p - The semiconductor region 5 faces the semiconductor region 5 .

[0015] p - On the n-type semiconductor region 5, no n-type semiconductor region such as the n-type source region 4 is provided. - In the upper portion of the n-type semiconductor region 5, no n-type semiconductor region is provided at a position aligned with the n-type source region 4 in the X direction. - A part of the semiconductor region 5 is present.

[0016] p - The semiconductor region 6 is provided on the second portion 2b as shown in FIG. - The semiconductor region 5 has a p - Shape base region 3 and p - The second conductive portion 12 is located between the first conductive portion 12 and the second conductive portion 6. - Semiconductor region 5 and p - It is located between the semiconductor region 6. - The length of the semiconductor region 6 in the X direction is p - The length of the semiconductor region 5 in the X direction is longer than that of the semiconductor region 5 .

[0017] The source electrode 22 is p - n-type base region 3, n-type source region 4, p - shaped semiconductor region 5, and p - The source electrode 22 is provided on the p-type semiconductor region 6. - n-type base region 3, n-type source region 4, p - shaped semiconductor region 5, and p - The semiconductor region 6 is electrically connected to the semiconductor region 6 .

[0018] The first conductive portion 11 and the source electrode 22 are electrically isolated from each other by an insulating layer 11b. The second conductive portion 12 and the source electrode 22 are electrically isolated from each other by an insulating layer 12b. The first conductive portion 11 and the second conductive portion 12 are electrically connected to a gate pad 23.

[0019] As shown in Figures 2 and 3, - The n-type base region 3, the n-type source region 4, and the first conductive portion 11 are each provided in plurality in the X direction on the first portion 2a. - Shape base area 3, p - The semiconductor region 5, the first conductive portion 11, and the second conductive portion 12 extend in the Y direction. - The base regions 3 and the plurality of first conductive portions 11 are arranged alternately.

[0020] 3 shows the structure of one end side in the X direction of the semiconductor device 100. The structure of the other end side in the X direction of the semiconductor device 100 is substantially symmetrical to the structure shown in FIG. 3. That is, one second conductive part 12 is provided at one end side in the X direction of the semiconductor device 100, and another second conductive part 12 is provided at the other end side in the X direction of the semiconductor device 100. - The n-type base region 3, the plurality of n-type source regions 4, and the plurality of first conductive portions 11 are located between a pair of second conductive portions 12 spaced apart from each other in the X direction.

[0021] As shown in Figure 2, p - The base region 3 may include a contact region 3a with a high p-type impurity concentration. - The p-type semiconductor region 5 may include a contact region 5a having a high p-type impurity concentration. - The p-type semiconductor region 6 may include a contact region 6a having a high concentration of p-type impurities. The contact region 3a, the contact region 5a, and the contact region 6a are in contact with the source electrode 22.

[0022] As shown in Figure 2, one p -A plurality of contact regions 3a and a plurality of n-type source regions 4 are arranged alternately in the Y direction on the n-type base region 3. The length Ls of the n-type source region 4 in the Y direction is longer than the length Lb of the contact region 3a in the Y direction. The length Lb corresponds to the distance between adjacent n-type source regions 4 in the Y direction.

[0023] The operation of the semiconductor device 100 will be described. In a state where a positive voltage is applied to the drain electrode 21 with respect to the source electrode 22, a voltage equal to or higher than the threshold is applied to the first conductive section 11. As a result, p - A channel (inversion layer) is formed in the base region 3. Electrons pass through the channel and travel from the source electrode 22 to the n - Then, when the voltage applied to the first conductive portion 11 becomes lower than the threshold, the p - The channel in the base region 3 disappears, and the semiconductor device 100 enters an off state. The first conductive portion 11 functions as a gate electrode for controlling the flow of current in the semiconductor device 100.

[0024] p - On the n-type semiconductor region 5, there is no n-type semiconductor region electrically connected to the source electrode 22. Therefore, even when a voltage equal to or higher than the threshold is applied to the second conductive portion 12, the p - No current flows through the inversion layer of the semiconductor region 5.

[0025] When the semiconductor device 100 is turned off, n - The potential difference between the drift region 2 and the first conductive portion 11, and n - Due to the potential difference between the drift region 2 and the second conductive portion 12, impact ionization (avalanche breakdown) occurs near the bottom end of the first conductive portion 11 and near the bottom end of the second conductive portion 12. A large amount of carriers (electrons and holes) are generated by the impact ionization. The electrons are - The holes pass through the p-type drift region 2 and are discharged to the drain electrode 21. - Shape base area 3 and p - The electrons pass through the semiconductor region 5 and are discharged to the source electrode 22 .

[0026] An example of the material for each component is explained below. + shaped drain region 1, n - Shape drift region 2, p - n-type base region 3, n-type source region 4, p - shaped semiconductor region 5, and p - The semiconductor region 6 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The first conductive portion 11 and the second conductive portion 12 contain a conductive material such as polysilicon. The first insulating layer 11a, the insulating layer 11b, the second insulating layer 12a, and the insulating layer 12b contain an insulating material such as silicon oxide. The drain electrode 21, the source electrode 22, and the gate pad 23 contain a metal such as titanium, gold, or aluminum.

[0027] The preferred ranges of impurity concentrations in each semiconductor region are as follows: + The n-type impurity concentration in the n-type drain region 1 is 1.0×10 19 atom / cm 3 Over 1.0 x 10 21 atom / cm 3 The following is true: n - The n-type impurity concentration in the drift region 2 is 1.0×10 16 atom / cm 3 Over 1.0 x 10 18 atom / cm 3 The following is true: - Shape base area 3, p - shaped semiconductor region 5, and p - The n-type impurity concentration in the n-type semiconductor region 6 is 1.0×10 17 atom / cm 3 Over 1.0 x 10 19 atom / cm 3 The n-type impurity concentration in the n-type source region 4 is 5.0×10 18 atom / cm 3 Over 5.0 x 10 20 atom / cm 3The n-type impurity concentration in the contact region 3a, the contact region 5a, and the contact region 6a is 5.0×10 18 atom / cm 3 Over 5.0 x 10 20 atom / cm 3 The following is the result.

[0028] 4(a), 4(b), 5(a), and 5(b) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. An example of a manufacturing method for the semiconductor device 100 will be described. + shaped drain region 1 and n - A semiconductor substrate Sub including a shaped drift region 2 is prepared. As shown in FIG. - A plurality of openings OP1 are formed in the upper surface of the drift region 2. The plurality of openings OP1 are aligned in the X direction, and each opening OP1 extends in the Y direction.

[0029] The semiconductor substrate Sub is thermally oxidized. As a result, the inner surface of the opening OP1 and the n - An insulating layer 10a is formed on the upper surface of the drift region 2. A polysilicon layer is formed by chemical vapor deposition (CVD) to fill the opening OP1. The upper surface of the polysilicon layer is recessed by etching. As shown in FIG. 4(b), second conductive portions 12 are formed inside the openings OP1 located at the ends in the X direction. First conductive portions 11 are formed inside the other openings OP1.

[0030] P-type impurity and n-type impurity ions are implanted sequentially, and n - At the top of the drift region 2, p - n-type base region 3, n-type source region 4, p - shaped semiconductor region 5, and p - 5(a), an n-type source region 4, a p-type semiconductor region 6, and an insulating layer 10b covering the semiconductor region are formed by CVD. - shaped semiconductor region 5, and p - The insulating layer 10b and the insulating layer 10a are etched so that the top surface of the semiconductor region 6 is exposed.

[0031] A metal layer is formed by CVD, sputtering, etc. The metal layer is patterned to form a source electrode 22 and a gate pad 23 (not shown). + until the drain region 1 reaches a predetermined thickness. + The bottom surface of the drain region 1 is ground. As shown in FIG. 5(b), + A drain electrode 21 is formed by sputtering on the lower surface of the drain region 1. In this way, the semiconductor device 100 according to the embodiment is manufactured.

[0032] FIG. 6 is an enlarged cross-sectional view of a part of FIG. In the semiconductor device 100, the ratio of the distance d1 to the depth D1 is equal to or greater than 2.3 and less than 3. Also, the ratio of the distance d1 to the depth D2 is equal to or greater than 2.3 and less than 3. As shown in FIG. 6, the depth D1 (first depth) is the depth in the Z direction from the upper surface of the n-type source region 4 to the lower end of the first insulating layer 11a. The depth D2 (second depth) is the depth in the Z direction from the upper surface of the n-type source region 4 to the lower end of the second insulating layer 12a. The distance d1 is the distance from the upper surface of the n-type source region 4 to the lower end of the n + shaped drain region 1 and n - This is the distance in the Z direction to the boundary with the drift region 2.

[0033] FIG. 7 is a graph illustrating the profile of the n-type impurity concentration in the semiconductor device according to the embodiment. 7 shows the profile of the n-type impurity concentration along the line A1-A2 in FIG. 6. In FIG. 7, the horizontal axis represents the depth (position in the Z direction), and the vertical axis represents the n-type impurity concentration [atm / cm ] at each point in the Z direction. 3 ]. The horizontal axis represents n - An arbitrary position in the drift region 2 is set to 0 μm, and n + 1 represents the depth to the drain region 1.

[0034] n + shaped drain region 1 and n - The boundary between the drift region 2 and the n +The n-type impurity concentration in the n-type drain region 1 is determined as a reference. + At a position far enough away from the drain region 1, + The concentration C1 of the n-type impurity in the n-type drain region 1 is measured. The concentration C2 is calculated as 0.5 times the concentration C1. As shown in Figure 7, + Shape drain region 1 to n - The n-type impurity concentration decreases toward the n-type drift region 2. The point where the n-type impurity concentration is C2 is called the n + shaped drain region 1 and n - The boundary B between the drift region 2 and the ion beam is defined as B.

[0035] The advantages of the embodiment will be described. The semiconductor device 100 is - Shape drift region 2, p - The semiconductor device 100 includes a parasitic transistor consisting of a p-type base region 3 and an n-type source region 4. As described above, when the semiconductor device 100 is turned off, carriers are generated by impact ionization. At this time, p - If the potential of the base region 3 rises, a parasitic transistor may operate. If a large current flows through the semiconductor device 100 due to the operation of the parasitic transistor, the semiconductor device 100 may be destroyed. For this reason, it is desirable that the parasitic transistor is unlikely to operate.

[0036] The semiconductor device 100 is - Semiconductor region 5 and p - When impact ionization occurs near the bottom end of the second conductive portion 12, holes are mainly transported to the p - Semiconductor region 5 and p - flow into the semiconductor region 6. - Semiconductor region 5 and p - On the n-type semiconductor region 6, no n-type semiconductor region such as the n-type source region 4 is provided. - A part of the semiconductor region 5 and p - There is a part of the semiconductor region 6, i.e., p - Semiconductor region 5 and p- No parasitic transistor exists in the region where the semiconductor region 6 is provided. When impact ionization occurs more easily near the bottom end of the second conductive portion 12 than near the bottom end of the first conductive portion 11, p - Compared to the shape base region 3, p - Semiconductor region 5 or p - More holes flow into the semiconductor region 6. Therefore, in order to suppress the operation of the parasitic transistor, it is preferable that impact ionization occurs more easily near the bottom end of the second conductive portion 12 than near the bottom end of the first conductive portion 11.

[0037] 8(a) to 8(c) show simulation results showing the characteristics of the semiconductor device according to the embodiment. 8(a) to 8(c) show the hole current density at turn-off. The darker the color, the higher the current density. 8(a) to 8(c) show the simulation results when the depths D1 and D2 shown in FIG. 6 are constant and the distance d1 is changed.

[0038] Specifically, in the simulation, the depths D1 and D2 are set to 1.02 μm. - The thickness of the n-type base region 3 in the Z direction is set to 0.38 μm. The thickness of the n-type source region 4 in the Z direction is set to 0.45 μm. - Semiconductor region 5 and p - The thickness of each of the n-type source regions 4 and p-type semiconductor regions 6 in the Z direction is set to 0.8 μm. - shaped semiconductor region 5, and p - The positions in the Z direction of the top surfaces of the semiconductor regions 6 are the same. Under these conditions, the change in hole current density was investigated when the distance d1 was changed from 2.4 μm to 3.0 μm.

[0039] 8(a) shows the simulation results when the distance d1 is 2.4 μm. In the simulation results shown in FIG. 8(a), the current density near the bottom end of the first conductive part 11 is higher than the current density near the bottom end of the second conductive part 12.- The current density in the base region 3 is - Current density and p in the semiconductor region 5 - The current density in the semiconductor region 6 is higher than that in the p - The potential of the base region 3 is p - The potential and p - The potential of the semiconductor region 6 is more likely to rise than the potential of the semiconductor region 6.

[0040] 8(b) shows the simulation results when the distance d1 is 2.9 μm. In the simulation results shown in FIG. 8(b), the current density near the bottom end of the second conductive part 12 is higher than the current density near the bottom end of the first conductive part 11. - The current density in the semiconductor region 5 is p - The current density in the base region 3 is higher than that in the p - The potential rise of the base region 3 is - The increase in the potential of the semiconductor region 5 is suppressed.

[0041] 8(c) shows the simulation results when the distance d1 is 3.0 μm. In the simulation results shown in FIG. 8(c), similar to the simulation results shown in FIG. 8(b), the current density near the bottom end of the second conductive part 12 is higher than the current density near the bottom end of the first conductive part 11. Therefore, p - The potential rise of the base region 3 is suppressed.

[0042] 9 to 11 show other simulation results showing the characteristics of the semiconductor device according to the embodiment. FIG. 9 shows the simulation results of the ratio of hole current I1 to hole current I2 when depth D1, depth D2, and distance d1 are changed. In the simulation, distance d1 was changed from 2.2 μm to 3.2 μm, and depth D1 and depth D2 were changed from 0.95 μm to 1.2 μm. The other simulation conditions were the same as those used to obtain the results shown in FIGS. 8(a) to 8(c). In the subsequent simulations, depth D1 and depth D2 were set to the same value. Therefore, the simulation results for depth D1 can be interpreted as the simulation results for depth D2.

[0043] In FIG. 9, the vertical axis is p - The hole current I1 flowing through the semiconductor region 5 and the p - p adjacent to the semiconductor region 5 - The graph shows the ratio R1 (I1 / I2) of the hole current I1 flowing through the base region 3 to the hole current I2. The values ​​on the vertical axis are expressed in logarithm (log scale). Therefore, if the hole current I1 is larger than the hole current I2, the value on the vertical axis is positive. If the hole current I2 is larger than the hole current I1, the value on the vertical axis is negative.

[0044] From the simulation results shown in FIG. 9, when the depth D1 is 1.05 μm or more and the distance d1 is 2.8 μm or more, the ratio R1 is −0.5 or more. For example, when the depth D1 is 1.05 μm and the distance d1 is 2.9 μm, the ratio R1 is −0.43. This indicates that the hole current I2 is larger than the hole current I1, but is approximately the same as the hole current I1. Therefore, p - The potential rise in the base region 3 is suppressed.

[0045] In particular, when the depth D1 is greater than 1.05 μm and the distance d1 is greater than 2.8 μm, the ratio R1 is a positive value, i.e., the hole current I1 is greater than the hole current I2, and p - The potential rise in the base region 3 is effectively suppressed.

[0046] Although the details of why the hole current I1 can be increased as the depth D1 and depth D2 and the distance d1 are longer are unclear, it is presumed to be as follows. When the depths D1 and D2 are short and the distance D1 is short, the potential gradient between the drain electrode 21 and the lower end of the first conductive portion 11 and between the drain electrode 21 and the lower end of the second conductive portion 12 is large. In this case, as shown in the above simulation results, p - It was confirmed that more holes flow into the base region 3. On the other hand, when the depths D1 and D2 are long and the distance D1 is long, the potential gradient between the drain electrode 21 and the lower end of the first conductive portion 11 and between the drain electrode 21 and the lower end of the second conductive portion 12 becomes small. When holes are generated near the lower end of the first insulating layer 11a and near the lower end of the second insulating layer 12a, the acceleration of the holes in the Z direction becomes small. This can increase the distance that the holes move laterally. In addition, p - An n-type source region 4 is provided on the n-type base region 3, while a p-type - No n-type semiconductor region is provided on the n-type semiconductor region 5. - Shape drift region 2 and p - The electric field formed by the pn junction with the semiconductor region 5 is - Shape drift region 2 and p - The electric field formed by the pn junction with the base region 3 is stronger than that formed by the pn junction with the base region 3. - It is presumed that the electrons move more easily toward the semiconductor region 5, resulting in the hole current I1 being larger than the hole current I2.

[0047] For each simulation result shown in FIG. 9, the ratio R2 (d1 / D1) of the distance d1 to the depth D1 was calculated. The results are shown in FIG. 10. Comparing the simulation results shown in FIG. 9 with the ratios shown in FIG. 10, it can be seen that if the ratio R2 is 2.15 or more, the hole current I1 can be made sufficiently large. From the simulation results shown in FIGS. 9 and 10, if the depth D1 is 1.05 μm or more, the distance d1 is 2.8 μm or more, and the ratio R2 is 2.15 or more, the hole current I1 can be made sufficiently large, and p - The potential rise in the base region 3 is suppressed.

[0048] 9 and 10, when the depth D1 is 1.05 μm or more and the distance d1 is 2.8 μm or more, the ratio R1 of the hole current I1 to the hole current I2 increases as the ratio R2 of the distance d1 to the depth D1 increases. - The potential rise in the base region 3 is suppressed.

[0049] On the other hand, the longer the distance d1, the higher the on-resistance of the semiconductor device 100. Therefore, from the viewpoint of on-resistance, it is desirable that the distance d1 be short. The simulation results shown in FIG. 11 show the relationship between the depth D1, the distance d1, and the on-resistance RonA. The on-resistance RonA represents the electrical resistance per unit area when a voltage of 4.5 V is applied to the semiconductor device 100. The simulation results shown in FIG. 11 show that the on-resistance RonA increases as the distance d1 increases.

[0050] The simulation results shown in Fig. 11 reveal the following: When the depth D1 is 1.05 µm, if the distance d1 is 3.2 µm or less, the increase in the on-resistance RonA can be kept to less than 25% of the on-resistance RonA when the distance d1 is 2.8 µm. Similarly, when the depth D1 is 1.1 µm, 1.15 µm, and 1.2 µm, if the distance d1 is 3.2 µm or less, the increase in the on-resistance RonA can be kept to less than 25% of the on-resistance RonA when the distance d1 is 2.8 µm.

[0051] From the table shown in FIG. 10, when the distance d1 is 3.2 μm or less, the ratio R2 is 3.05 or less. That is, if the ratio R2 is 2.15 or more and 3.05 or less, the hole current I1 can be increased while suppressing an increase in the on-resistance RonA. More preferably, the ratio R2 is 2.95 or less. Even more preferably, the ratio R2 is 2.85 or less.

[0052] According to the embodiment, the depth D1 is set to 1.05 μm or more, the distance d1 is set to 2.8 μm or more, and the ratio of the distance d1 to the depth D1 and the ratio of the distance d1 to the depth D2 are set to 2.15 or more and 3.05 or less, thereby - This can suppress the flow of holes into the base region 3. As a result, the operation of the parasitic transistor can be suppressed, and the withstand capability of the semiconductor device 100 can be improved.

[0053] 12(a) to 12(f) show other simulation results showing the characteristics of the semiconductor device according to the embodiment. In order to reduce the on-resistance of the semiconductor device 100, it is preferable that the length Ls shown in FIG. 2 is longer than the length Lb. The larger the ratio of the length Ls to the length Lb, the lower the on-resistance. On the other hand, when the ratio of the length Lb is small, the p - The holes that have flowed into the base region 3 are less likely to be discharged to the source electrode 22. As a result, the return transistor operates more easily.

[0054] 12(a) to 12(f) show current-voltage characteristics when the ratio of length Ls to length Lb is changed. The horizontal axis shows the voltage Vd of the drain electrode 21 relative to the source electrode 22. The vertical axis shows the current Id flowing from the drain electrode 21 to the source electrode 22. In the simulation that produced the results of FIGS. 12(a) to 12(c), the distance d1 was set to 2.7 μm. The other simulation conditions were the same as those used in the simulation that produced the results of FIGS. 8(a) to 8(c) and 9. FIGS. 12(a) to 12(c) show simulation results when the ratio of length Ls to length Lb is 3, 5, and 7, respectively.

[0055] 12(a) to 12(c) show that when the ratio of length Ls to length Lb is 5 or more, the current Id changes significantly when the relative ratio of Vd is about 0.98, which indicates that a parasitic transistor is operating.

[0056] In the simulations that produced the results shown in Figures 12(d) to 12(f), the distance d1 was set to 3.1 μm. Figures 12(d) to 12(f) show simulation results when the ratio of length Ls to length Lb is 3, 5, and 7, respectively. The simulation results shown in Figures 12(d) to 12(f) show that the change in current Id is very small even when the ratio of length Ls to length Lb is 5 or more. This indicates that the operation of the parasitic transistor is sufficiently suppressed.

[0057] In order to sufficiently reduce the on-resistance of the semiconductor device 100, the ratio of the length Ls to the length Lb is preferably 5 or more. According to the embodiment, even when the ratio of the length Ls to the length Lb is 5 or more, the operation of the parasitic transistor can be suppressed by setting the ratio of the distance d1 to the depth D1 (or the depth D2) to be 2.25 or more and 3 or less. The on-resistance of the semiconductor device 100 can be reduced while suppressing the operation of the parasitic transistor.

[0058] On the other hand, if the ratio of length Ls to length Lb is excessively large, the operation of the parasitic transistor may not be sufficiently suppressed even if the ratio of distance d1 to depth D1 (or depth D2) is 2.25 to 3. For this reason, it is preferable that the ratio of length Ls to length Lb is 5 to 9. More preferably, the ratio of length Ls to length Lb is 5 to 7.

[0059] (Variation) FIG. 13 is a cross-sectional view showing a part of a semiconductor device according to a modified example of the embodiment. In the simulations described above, depth D1 and depth D2 are the same. In the semiconductor device 110 shown in FIG. 13, depth D2 is different from depth D1. Depth D1 and depth D2 may be different from each other as long as they are greater than 2.9 μm and less than 3.2 μm. For example, by making depth D2 greater than depth D1, impact ionization can be more easily generated near the lower end of the second conductive portion 12. This can further suppress the operation of the parasitic transistor in the semiconductor device 110.

[0060] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a first conductivity type, including a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region, the second semiconductor region being provided on the first semiconductor region and having a lower impurity concentration of the first conductivity type than the first semiconductor region; a third semiconductor region of the second conductivity type provided on the first portion; a fourth semiconductor region of the first conductivity type provided on the third semiconductor region; a first conductive portion facing the third semiconductor region via a first insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, the first conductive portion having a first depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the first insulating layer of 1.05 μm or more, a distance in the first direction from the upper surface of the fourth semiconductor region to a boundary between the first semiconductor region and the second semiconductor region of 2.8 μm or more, and a ratio of the distance to the first depth of 2.15 or more and 3.05 or less; a fifth semiconductor region of the second conductivity type provided on the second portion; a second conductive portion facing the fifth semiconductor region in the second direction via a second insulating layer, the second conductive portion having a second depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the second insulating layer of 1.05 μm or more, and a ratio of the distance to the second depth of 2.15 or more and 3.05 or less; a second electrode provided on the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; A semiconductor device comprising: (Feature 2) The third semiconductor region is a channel portion facing the first conductive portion in the second direction; a contact portion in contact with the second electrode; Including, the impurity concentration of the second conductivity type in the contact portion is higher than the impurity concentration of the second conductivity type in the channel portion; 2. The semiconductor device according to claim 1, wherein the contact portion is aligned with the fourth semiconductor region in a third direction perpendicular to the first direction and the second direction. (Feature 3) 3. The semiconductor device according to feature 2, wherein a ratio of a length of the fourth semiconductor region in the third direction to a length of the contact portion in the third direction is 5 or more and 9 or less. (Feature 4) 4. The semiconductor device according to feature 3, wherein the plurality of contact portions and the plurality of fourth semiconductor regions are arranged alternately in the third direction. (Feature 5) 2. The semiconductor device according to Feature 1, wherein the distance is 2.8 μm or more and 3.2 μm or less. (Feature 6) a ratio of the distance to the first depth is greater than or equal to 2.15 and less than 2.95; 2. The semiconductor device according to Feature 1, wherein the ratio of the distance to the second depth is greater than or equal to 2.15 and less than 2.95. (Feature 7) 7. The semiconductor device according to any one of Features 1 to 6, wherein a lower end of the second conductive portion is located lower than a lower end of the first conductive portion.

[0061] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS).

[0062] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0063] 1:n + Shaped drain region, 2:n - shaped drift region, 2a: first part, 2b: second part, 3:p - n-type base region, 3a: contact region, 4: n-type source region, 5: p - Semiconductor region, 5a: contact region, 6: p - Semiconductor region, 6a: contact region, 10a, 10b: insulating layer, 11: first conductive portion, 11a: first insulating layer, 11b: insulating layer, 12: second conductive portion, 12a: second insulating layer, 12b: insulating layer, 21: drain electrode, 22: source electrode, 23: gate pad, 100, 110: semiconductor device, D1, D2: depth, OP1: opening, Sub: semiconductor substrate

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a first conductivity type, including a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region, the second semiconductor region being provided on the first semiconductor region and having a lower impurity concentration of the first conductivity type than the first semiconductor region; a third semiconductor region of the second conductivity type provided on the first portion; a fourth semiconductor region of the first conductivity type provided on the third semiconductor region; a first conductive portion facing the third semiconductor region via a first insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, the first conductive portion having a first depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the first insulating layer of 1.05 μm or more, a distance in the first direction from the upper surface of the fourth semiconductor region to a boundary between the first semiconductor region and the second semiconductor region of 2.8 μm or more, and a ratio of the distance to the first depth of 2.15 or more and 3.05 or less; a fifth semiconductor region of the second conductivity type provided on the second portion; a second conductive portion facing the fifth semiconductor region in the second direction via a second insulating layer, the second conductive portion having a second depth in the first direction from an upper surface of the fourth semiconductor region to a lower end of the second insulating layer of 1.05 μm or more, and a ratio of the distance to the second depth of 2.15 or more and 3.05 or less; a second electrode provided on the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; A semiconductor device comprising:

2. The third semiconductor region is a channel portion facing the first conductive portion in the second direction; a contact portion in contact with the second electrode; Including, the impurity concentration of the second conductivity type in the contact portion is higher than the impurity concentration of the second conductivity type in the channel portion; The semiconductor device according to claim 1 , wherein the contact portion is aligned with the fourth semiconductor region in a third direction perpendicular to the first direction and the second direction.

3. 3 . The semiconductor device according to claim 2 , wherein a ratio of a length of said fourth semiconductor region in said third direction to a length of said contact portion in said third direction is 5 or more and 9 or less.

4. The semiconductor device according to claim 3 , wherein a plurality of said contact portions and a plurality of said fourth semiconductor regions are arranged alternately in said third direction.

5. 2. The semiconductor device according to claim 1, wherein the distance is not less than 2.8 [mu]m and not more than 3.2 [mu]m.

6. a ratio of the distance to the first depth is greater than or equal to 2.15 and less than 2.95; The semiconductor device according to claim 1 , wherein a ratio of the distance to the second depth is equal to or greater than 2.15 and less than 2.

95.

7. 7. The semiconductor device according to claim 1, wherein a lower end of said second conductive portion is located lower than a lower end of said first conductive portion.

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