Switching element

Abstract

To suppress the concentration of holes at avalanche driving.SOLUTION: An element region includes a plurality of first connection regions of a second conductivity type that are disposed in a part of a region between trenches and reach a first deep region by penetrating a source region and a body region from an upper surface of a semiconductor substrate. A peripheral region includes a second connection region of the second conductivity type that reaches a second deep region from the upper surface of the semiconductor substrate. An opening part of an interlayer insulating film includes a first opening region and a second opening region. The first opening region is a region including at least a part of the element region. The second opening region is a region disposed in a part of the peripheral region and surrounding the element region. On the upper surface of the semiconductor substrate in the opening part, an upper electrode is provided.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a switching element.

[0002] Patent Document 1 discloses a trench-gate switching element. In this switching element, multiple p-type deep layers are provided inside an n-type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is located below the bottom end of the trench. The switching element of Patent Document 1 also has multiple p-type connection regions. Each connection region connects each deep layer to a p-type body layer. In this way, by connecting each deep layer to the upper electrode via the body layer and the connection regions, it is possible to suppress the electric field applied to the gate insulating film covering the bottom end of the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-083790 Summary of the Invention [Problem to be solved by the invention]

[0004] A switching element may include an element region and a peripheral region surrounding the element region. The element region is a region in which a device structure is formed, and its upper surface is electrically connected to an upper electrode. The peripheral region is a region in which no device structure is formed, and at least a portion of its upper surface is insulated from the upper electrode. That is, the deep layer in the element region is connected to the upper electrode via a connection region, but the deep layer in the peripheral region is not connected to the upper electrode. When such a switching element is driven in avalanche mode, hot carriers (holes) are generated in each deep layer. Holes generated in the deep layer in the element region flow to the upper electrode via the connection region in the element region. On the other hand, holes generated in the deep layer in the peripheral region flow to the upper electrode via a nearby connection region in the element region. As a result, holes may concentrate in a connection region located near the boundary between the element region and the peripheral region among multiple connection regions arranged in the element region. As a result, there is a risk of damage due to heat generation. [Means for solving the problem]

[0005] The first switching element disclosed in this specification comprises a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) surrounding the element region; an interlayer insulating film (20) disposed on a portion of the upper surface of the semiconductor substrate and having an opening; an upper electrode (22) disposed on the upper surface of the semiconductor substrate within the opening; and a lower electrode (24) disposed on the lower surface of the semiconductor substrate. The element region of the semiconductor substrate comprises a plurality of trenches (14) disposed on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction. The element region comprises a gate insulating film (16) covering the inner surface of the trench. The element region comprises a gate electrode (18) disposed within the trench and insulated from the semiconductor substrate by the gate insulating film. The element region comprises a first conductivity type (n) source region (40) disposed in an inter-trench region, which is a region sandwiched between the plurality of trenches, and exposed on the upper surface of the semiconductor substrate. The element region is disposed in the inter-trench region and includes a body region (42) of a second conductivity type (p) disposed below the source region. The element region is disposed across the lower portions of the plurality of trenches and includes a first drift region (44A) of a first conductivity type (n) that is in contact with the lower surface of the body region and the lower portions of the trenches. The element region includes a plurality of first deep regions (50A) of the second conductivity type (p), which are disposed in an area surrounded by the first drift region, are spaced apart from the body region and disposed below the body region, and are disposed in an area including the lower end of the trench or below the lower end of the trench in the thickness direction of the semiconductor substrate. The element region is also provided with a plurality of first connection regions (52A) of the second conductivity type (p), which are disposed in a portion of the inter-trench region and extend from the upper surface of the semiconductor substrate through the source region and the body region to reach the first deep region. The peripheral region of the semiconductor substrate includes a second drift region (44B) of the first conductivity type (n), which is continuous with the first drift region arranged in the element region.The peripheral region includes a plurality of second deep regions (50B) of a second conductivity type (p), which are arranged in an area surrounded by the second drift region and are continuous with each of the plurality of first deep regions arranged in the element region. The peripheral region includes a second connection region (52B) of a second conductivity type (p), which reaches the second deep region from the upper surface of the semiconductor substrate. The opening in the interlayer insulating film includes a first opening region (AP1) and a second opening region (AP2). The first opening region is a region that includes at least a portion of the element region. The second opening region is a region that is arranged in a portion of the peripheral region and surrounds the periphery of the element region.

[0006] In the first switching element disclosed in this specification, the second connection region located within the second opening region among the second connection regions formed in the peripheral region can be electrically connected to the upper electrode. This allows the hole path from the second deep region to the upper electrode to be arranged so as to surround the periphery of the element region. Therefore, holes generated in the second deep region in the peripheral region during avalanche driving can be directly diverted to the upper electrode using the second connection region within the second opening region. This prevents holes from concentrating and flowing in the first connection region located near the boundary between the element region and the peripheral region. This makes it possible to prevent damage due to heat generation.

[0007] The second switching element disclosed in this specification includes a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) surrounding the element region, an upper electrode (22) provided on the upper surface of the semiconductor substrate, and a lower electrode (24) provided on the lower surface of the semiconductor substrate. The element region of the semiconductor substrate includes a plurality of trenches (14) arranged on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction. The element region includes a gate insulating film (16) covering the inner surface of the trench. The element region includes a gate electrode (18) arranged in the trench and insulated from the semiconductor substrate by the gate insulating film. The element region includes a first conductivity type (n) source region (40) arranged in an inter-trench region, which is a region sandwiched between the plurality of trenches, and exposed at the upper surface of the semiconductor substrate. The semiconductor device includes a body region (42) of a second conductivity type (p) that is disposed in the inter-trench region and below the source region. The element region includes a first drift region (44A) of a first conductivity type (n) that is distributed across the lower portions of the plurality of trenches and that is in contact with the lower surface of the body region and the lower portions of the trenches. The element region includes a plurality of first deep regions (50A) of the second conductivity type (p), that are disposed in an area surrounded by the first drift region, that are spaced apart from the body region and are disposed below the body region, and that are disposed in an area including the lower end of the trench or below the lower end of the trench in the thickness direction of the semiconductor substrate. The element region includes a plurality of first connection regions (52A) of the second conductivity type (p), that are disposed in a portion of the inter-trench region and that extend from the upper surface of the semiconductor substrate through the source region and the body region to reach the first deep region. The peripheral region of the semiconductor substrate includes a second drift region (44B) of the first conductivity type (n), which is continuous with the first drift region arranged in the element region.The peripheral region includes a plurality of second deep regions (50B) of a second conductivity type (p), which are arranged in an area surrounded by the second drift region and are continuous with each of the plurality of first deep regions arranged in the element region. The peripheral region includes a second connection region (52B) of a second conductivity type (p), which reaches the second deep region from the upper surface of the semiconductor substrate. When viewed vertically from above on the upper surface of the semiconductor substrate, the plurality of first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x). When viewed vertically from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern. The element region has a rectangular shape including a first element region side (10x) extending in the first direction and a second element region side (10y) extending in the second direction. The multiple intersections include a first boundary region group (BG1) adjacent to the second element region side and arranged in a line along the second direction, and an internal region group (IG) arranged more inward of the element region than the first boundary region group. A first connection region is arranged in at least one of the multiple intersections included in the first boundary region group, and the first connection region is arranged in some of the multiple intersections included in the internal region group. The proportion of first connection regions arranged in the first boundary region group is higher than the proportion of first connection regions arranged in the internal region group.

[0008] In the second switching element disclosed in this specification, the proportion of the first connection region disposed within the element region can be made higher at the boundary between the element region and the peripheral region than inside the element region. This allows holes generated in the second deep region within the peripheral region during avalanche driving to flow to the upper electrode via the first connection region, which has a higher proportion of the first connection region. This prevents the holes from concentrating and flowing, thereby preventing damage due to heat generation. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. [Figure 2] FIG. 2 is an enlarged top view of region R2 in FIG. 1. [Figure 3] FIG. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] 3 is a cross-sectional view taken along line VV in FIG. 2. [Figure 6] FIG. [Figure 7] FIG. 10 is a top view of a switching element 1001 of a comparative example. [Figure 8] FIG. 10 is a top view of a switching element 201 according to a second embodiment. [Figure 9] FIG. 10 is a top view of a switching element 301 according to a first modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0010] (Schematic structure of switching element 1) The semiconductor device of this embodiment will be described below with reference to the drawings. For clarity of illustration, only some of the repeatedly formed structures may be labeled with reference numerals. Hereinafter, a direction parallel to the upper surface 12 a of the semiconductor substrate 12 will be referred to as the x-direction, a direction parallel to the upper surface 12 a and perpendicular to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction.

[0011] The switching element 1 shown in FIG. 1 has a semiconductor substrate 12. The material of the semiconductor substrate 12 is not particularly limited, but may be, for example, silicon, silicon carbide, or a nitride semiconductor (e.g., GaN). In this embodiment, silicon carbide is used. The semiconductor substrate 12 has a semiconductor chip shape. The semiconductor substrate 12 has a rectangular shape including a first chip side 12x and a second chip side 12y. The first chip side 12x is a side extending in the x direction. The second chip side 12y is a side extending in the y direction.

[0012] The semiconductor substrate 12 includes an element region 10 and a peripheral region 11. The element region 10 is a region in which a device structure that performs a specific function is formed. The peripheral region 11 is a region provided around the element region 10. The device structure may be, for example, a MOSFET structure that performs a switching function, a diode structure that performs a rectifying function, or a reverse conducting IGBT structure that combines an IGBT structure and a diode structure.

[0013] The element region 10 has a rectangular shape with a first element region side 10x and a second element region side 10y. The first element region side 10x extends in the x direction. The second element region side 10y extends in the y direction.

[0014] An interlayer insulating film 20, two source electrodes 22, and a plurality of signal electrodes 26 are provided on the upper surface 12a of the semiconductor substrate 12. The interlayer insulating film 20 has two openings AP arranged within the region of the semiconductor substrate 12. The openings AP have a rectangular shape with a first opening side APx and a second opening side APy. The first opening side APx is a side extending in the x direction. The second opening side APy is a side extending in the y direction.

[0015] Each of the two source electrodes 22 is disposed so as to cover the two openings AP. That is, the source electrode 22 is provided on the upper surface 12a of the semiconductor substrate 12 within the openings AP. In the openings AP, the source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12. Note that instead of the two source electrodes 22, one source electrode 22 may be provided on the upper surface 12a of the semiconductor substrate 12.

[0016] Each of the plurality of signal electrodes 26 is an interface for inputting and outputting gate signals and various sensor signals.

[0017] There is a first distance D1 between the first chip side 12x and the first opening side APx. There is a second distance D2 between the second chip side 12y and the second opening side APy. There is a first width W1 between the first opening side APx and the first element region side 10x. There is a second width W2 between the second opening side APy and the second element region side 10y. When the first distance D1 is larger than the second distance D2, the first width W1 is made larger than the second width W2. On the other hand, when the second distance D2 is larger than the first distance D1, the second width W2 is made larger than the first width W1. In this embodiment, a case is described in which the first distance D1 is larger than the second distance D2 and the first width W1 is larger than the second width W2.

[0018] (Specific structure of switching element 1) FIG. 2 shows an enlarged top view of region R2 in FIG. 1. Region R2 is the region in the lower left corner of the element region 10. Region R2 includes the boundary between the element region 10 and the peripheral region 11. Note that in FIG. 2, the interlayer insulating film 20 and the source electrode 22 are omitted. The opening AP is indicated by a solid line, and the first opening region AP1 and the second opening region AP2 are indicated by a dashed-dotted line. The deep region 50 is indicated by dotted hatching, and the connection region 52 is indicated by diagonal hatching.

[0019] FIG. 3 shows a perspective view of the element region 10. In FIG. 3, a portion of the element region 10 is arbitrarily cut away. Note that in FIG. 3, the interlayer insulating film 20 and the source electrode 22 are omitted. FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 4 is a cross-sectional view in the xz plane including the boundary between the element region 10 and the peripheral region 11. FIG. 5 shows a cross-sectional view taken along line VV in FIG. 2. FIG. 5 is a cross-sectional view in the yz plane including the boundary between the element region 10 and the peripheral region 11.

[0020] A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the x direction on the upper surface 12a and is spaced apart in the y direction. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed within each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is disposed on the upper surface of each gate electrode 18.

[0021] Inter-trench regions TR are formed between adjacent trenches 14. The inter-trench regions TR are regions sandwiched between the trenches 14. Each inter-trench region TR extends linearly in the x direction on the upper surface 12a, and is arranged at intervals in the y direction.

[0022] The semiconductor substrate 12 has a source region 40, a body region 42, a drift region 44, and a drain region 46. The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is disposed in the inter-trench region TR. The source region 40 contacts the source electrode 22 in the inter-trench region TR. The source region 40 also contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench region TR.

[0023] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is disposed in the inter-trench region TR. The body region 42 is disposed in the inter-trench region TR and below the source region 40. The body region 42 is in contact with the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench region TR.

[0024] The drift region 44 is an n-type region with a low n-type impurity concentration. The drift region 44 includes a first drift region 44A and a second drift region 44B. The first drift region 44A is a region disposed in the element region 10. The second drift region 44B is a region disposed in the peripheral region 11. In other words, the first drift region 44A and the second drift region 44B are continuous with each other. Hereinafter, the first drift region 44A and the second drift region 44B may be collectively referred to as the "drift region 44."

[0025] In the element region 10, the first drift region 44A is distributed across the lower portions of multiple inter-trench regions TR. The upper end of the first drift region 44A extends into each inter-trench region TR. The first drift region 44A contacts the body region 42 from below within each inter-trench region TR. The first drift region 44A also contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of each inter-trench region TR.

[0026] The drain region 46 is an n-type region having a high n-type impurity concentration. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44. The drain region 46 contacts the drift region 44 from below. The drain region 46 contacts the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b.

[0027] The semiconductor substrate 12 has a plurality of p-type deep regions 50. Each deep region 50 is arranged in an area surrounded by the drift region 44. Each deep region 50 is arranged below the body region 42 with a gap therebetween. In addition, in the z direction, each deep region 50 is arranged below the lower end of the trench 14. The drift region 44 is distributed between each deep region 50 and the body region 42. In addition, when the semiconductor substrate 12 is viewed from above (+z direction), each deep region 50 extends linearly in the y direction and is arranged at intervals in the x direction.

[0028] The multiple deep regions 50 include a first deep region 50A and a second deep region 50B. The first deep region 50A is a region of the multiple deep regions 50 that is arranged in the element region 10. The second deep region 50B is a region of the multiple deep regions 50 that is arranged in the peripheral region 11. Therefore, when one deep region 50 extends in the y direction across the element region 10 and the peripheral region 11, the portion included in the element region 10 is the first deep region 50A, and the portion included in the peripheral region 11 is the second deep region 50B. In other words, the first deep region 50A and the second deep region 50B may be continuous.

[0029] The semiconductor substrate 12 has a plurality of connection regions 52. The connection regions 52 are p-type regions that extend from the upper surface 12a of the semiconductor substrate 12 to the deep region 50. The plurality of connection regions 52 include a first connection region 52A and a second connection region 52B. The first connection region 52A is a region of the plurality of connection regions 52 that is located in the element region 10. The second connection region 52B is a region of the plurality of connection regions 52 that is located in the peripheral region 11.

[0030] The first connection region 52A will be described. As shown in FIG. 2, in a vertical top view of the upper surface 12a, each inter-trench region TR extends linearly in the x direction, and the first deep region 50A extends linearly in the y direction. An intersection 60 is disposed at each of the intersections between the multiple inter-trench regions TR and the multiple first deep regions 50A. The multiple intersections 60 are disposed in a lattice pattern along the x direction and the y direction. The first connection region 52A is disposed in the inter-trench region TR so as to include some of the multiple intersections 60. As shown in FIGS. 3 and 5, the multiple first connection regions 52A extend from the upper surface 12a of the semiconductor substrate 12, penetrating the source region 40 and the body region 42, and reaching the first deep region 50A.

[0031] The second connection region 52B will now be described. As shown in Fig. 2, the second deep region 50B and the second connection region 52B are arranged over the entire peripheral region 11. This ensures the withstand voltage of the peripheral region 11. As shown in Figs. 4 and 5, the second connection region 52B extends from the upper surface 12a of the semiconductor substrate 12 to the second deep region 50B.

[0032] The interlayer insulating film 20 has an opening AP. As shown in FIG. 2, the opening AP includes a first opening region AP1 and a second opening region AP2. The first opening region AP1 is a region that includes at least a part of the element region 10. The second opening region AP2 is disposed in a part of the peripheral region 11 and is a region that surrounds the periphery of the element region 10. In the example of FIG. 2, the first opening region AP1 includes the entire element region 10 and has a rectangular shape. The second opening region AP2 is disposed so as to include the outer periphery of the element region 10 and has a rectangular ring shape.

[0033] The source electrode 22 is disposed in the opening AP and covers the upper surface 12a of the semiconductor substrate 12. The source electrode 22 in the first opening region AP1 contacts the upper surface 12a of the inter-trench region TR and is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 in the second opening region AP2 contacts the upper surface 12a of the semiconductor substrate 12 that forms the peripheral region 11. As a result, the first deep region 50A in the first opening region AP1 is connected to the source electrode 22 via the first connection region 52A. Furthermore, the second deep region 50B in the second opening region AP2 is connected to the source electrode 22 via the second connection region 52B.

[0034] (Operation of switching element 1) The switching element 1 of the first embodiment is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Normally, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42, and the source region 40 and the drift region 44 are connected by the inversion layer. This turns on the switching element 1, and a current flows from the drain electrode 24 to the source electrode 22.

[0035] Note that, among the multiple intersections 60, those intersections where the first connection regions 52A are located do not have source regions 40, and therefore almost no current flows. On the other hand, among the multiple intersections 60, those intersections where the first connection regions 52A are not located allow current to flow. Therefore, in the switching element 1 of Example 1, the first connection regions 52A are located only at some of the multiple intersections 60. That is, the first connection regions 52A are thinned out. Compared to when the first connection regions 52A are located at all intersections 60, the arrangement density of the first connection regions 52A can be reduced. Therefore, when the switching element 1 is turned on, a high density of current can flow through the semiconductor substrate 12, thereby reducing the on-resistance of the switching element 1.

[0036] When the potential of the gate electrode 18 is reduced to a potential lower than the gate threshold, the switching element 1 is turned off, and the current stops. When the switching element 1 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, causing a depletion layer to extend from the body region 42 to the drift region 44. Furthermore, because the first deep region 50A is connected to the body region 42 by the first connection region 52A, the potential of the first deep region 50A is substantially equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the first deep region 50A and the drift region 44, causing a depletion layer to extend from the first deep region 50A to the drift region 44. The depletion layer extending from the first deep region 50A prevents a high electric field from being applied to the gate insulating film 16 at the bottom end of each trench 14.

[0037] Moreover, an overvoltage may be applied to the switching element 1 in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. During such avalanche driving, hot carriers (holes) are generated in the multiple deep regions 50. The holes generated in the first deep region 50A in the element region 10 flow to the source electrode 22 via the first connection region 52A in the element region 10 (see arrow Y1 in FIG. 6).

[0038] As described above, the first connection region 52A is a path through which holes flow during avalanche driving, but does not allow on-current to easily flow. Therefore, by arranging the first connection regions 52A at some of the intersections 60 in the element region 10 (i.e., by thinning out the first connection regions 52A), it is possible to achieve both a reduction in on-resistance and an improvement in the withstand capability during avalanche driving.

[0039] (assignment) The problem will be explained using a switching element 1001 of a comparative example in Fig. 7. Fig. 7 is a top view at the same position as Fig. 2. In the switching element 1001 of the comparative example, the opening AP coincides with the outer circumferential contour of the element region 10. That is, the switching element 1001 of the comparative example differs from the switching element 1 of this embodiment in that the second opening region AP2 is not formed.

[0040] When the switching element 1001 of the comparative example performs the avalanche driving described above, holes are generated in the first deep region 50A and the second deep region 50B. The holes generated in the first deep region 50A in the element region 10 flow to the source electrode 22 via the first connection region 52A in the element region 10 (see arrow Y1 in FIG. 7). On the other hand, the holes generated in the second deep region 50B in the peripheral region 11 flow to the source electrode 22 via the nearby first connection region 52A in the element region 10 (see arrow Y2a in FIG. 7). As a result, holes may concentrate in the first connection region 52A located near the boundary between the element region 10 and the peripheral region 11, among the multiple first connection regions 52A located in the element region 10 (see region R11). As a result, there is a risk of breakdown due to heat generation.

[0041] (effect) The effects of this embodiment will be described using the switching element 1 (FIG. 6). In the switching element 1 of this embodiment, the second connection region 52B located in the second opening region AP2, among the second connection regions 52B formed in the peripheral region 11, can be electrically connected to the source electrode 22. This allows the second opening region AP2 to function as a hole flow path. That is, the hole flow path from the second deep region 50B to the source electrode 22 can be arranged to surround the periphery of the element region 10. Therefore, during avalanche driving, holes generated in the second deep region 50B in the peripheral region 11 can be directly directed to the source electrode 22 using the second connection region 52B in the second opening region AP2 (see arrow Y2 in FIG. 6). That is, since a ring-shaped hole flow path can be arranged to surround the periphery of the peripheral region 11, the concentrated flow of holes can be suppressed. This makes it possible to prevent damage due to heat generation.

[0042] As shown in FIG. 1, when the first distance D1 is greater than the second distance D2, the total area of ​​the second deep regions 50B located near the first opening side APx is greater than that of the second opening side APy. Therefore, the amount of holes generated during avalanche driving is greater near the first opening side APx than near the second opening side APy. Therefore, in the switching element 1 of this embodiment, the opening width of the second opening region AP2 is such that the first width W1 of the first opening side APx is greater than the second width W2 of the second opening side APy (see FIG. 2). This allows a hole flow path with a larger area to be located near a region where a larger amount of holes are generated. This makes it possible to suppress the concentration of hole flow. [Example]

[0043] Fig. 8 shows a switching element 201 according to the second embodiment. Fig. 8 is a diagram similar to Fig. 2. Components common to the first and second embodiments are given the same reference numerals, and descriptions thereof will be omitted.

[0044] The element region 10 has a first element region side 10x and a second element region side 10y. The opening AP in the interlayer insulating film 20 has a first opening side APx and a second opening side APy. The first opening side APx is located inside the element region 10 with respect to the first element region side 10x and adjacent to the first element region side 10x. The second opening side APy is located inside the element region 10 with respect to the second element region side 10y and adjacent to the second element region side 10y.

[0045] A plurality of intersections 60 are arranged in the element region 10. The plurality of intersections 60 are divided into a first boundary region group BG1, a second boundary region group BG2, and an internal region group IG. The first boundary region group BG1 is a group of intersections 60 adjacent to the second element region side 10y and arranged in a line along the y direction. The second boundary region group BG2 is a group of intersections 60 adjacent to the first element region side 10x and arranged in a line along the x direction. The internal region group IG is a group of intersections 60 arranged more inward in the element region 10 than the first boundary region group BG1 and the second boundary region group BG2.

[0046] A first connection region 52A is disposed at all of the intersections 60 included in the first boundary region group BG1. Similarly, a first connection region 52A is disposed at all of the intersections 60 included in the second boundary region group BG2. On the other hand, a first connection region 52A is disposed at only some of the intersections 60 included in the internal region group IG.

[0047] The effects will be explained. In the switching element 201 of Example 2, the proportion of the first connection regions 52A arranged in the first boundary region group BG1 and the second boundary region group BG2 can be made higher than the proportion of the first connection regions 52A arranged in the internal region group IG. This allows the ring-shaped hole flow path to be arranged so as to surround the periphery of the element region 10. Therefore, during avalanche driving, holes generated in the second deep region 50B in the peripheral region 11 can be flowed to the source electrode 22 using the ring-shaped hole flow path (see arrow Y201). Since the concentration of hole flow can be suppressed, it is possible to prevent breakdown due to heat generation.

[0048] (First Modification of the Second Embodiment) 9 shows a switching element 301 according to a first modified example of the second embodiment. FIG. 9 is a view similar to FIG.

[0049] Among the multiple intersections 60 included in the first boundary area group BG1, a first connection region 52A is disposed between the intersections 60 adjacent to each other in the y direction (see region R21 in FIG. 9). As a result, the first connection region 52A included in the first boundary area group BG1 extends continuously in a straight line in the y direction. The first connection region 52A is also continuously connected in the y direction to the top surface of the first deep region 50A located directly below it.

[0050] Similarly, among the multiple intersections 60 included in the second boundary area group BG2, first connection areas 52A are arranged between intersections 60 adjacent to each other in the x direction (see area R22 in FIG. 9). As a result, the first connection areas 52A included in the second boundary area group BG2 extend continuously and linearly in the x direction.

[0051] This increases the contact area between the first deep region 50A and the first connection region 52A, thereby increasing the ease of hole flow in the hole flow path from the first deep region 50A via the first connection region 52A to the source electrode 22. This makes it possible to prevent breakdown due to heat generation.

[0052] (Second Modification of Second Embodiment) As long as the proportion of first connection regions 52A arranged in the first boundary region group BG1 is higher than the proportion of first connection regions 52A arranged in the internal region group IG, the arrangement of the first connection regions 52A in the first boundary region group BG1 may be varied. For example, in the first boundary region group BG1, a first connection region 52A may be arranged at every other intersection 60. Similarly, the arrangement of the first connection regions 52A in the second boundary region group BG2 may also be varied.

[0053] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility.

[0054] (Variation) The technology of Example 1 (technology using the second opening region AP2) and the technology of Example 2 (technology increasing the proportion of first connection regions 52A arranged in the first boundary region group BG1 and the second boundary region group BG2) can also be used in combination.

[0055] In the above-described first and second embodiments, each deep region 50 is disposed below the lower end of the trench 14. However, each deep region 50 may be disposed at a depth that includes the lower end of the trench 14.

[0056] The configurations of the techniques disclosed in this specification are listed below. [Configuration 1] A switching element (1), a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) provided around the element region; an interlayer insulating film (20) disposed on a portion of the upper surface of the semiconductor substrate and having an opening; an upper electrode (22) provided on the upper surface of the semiconductor substrate within the opening; a lower electrode (24) provided on the lower surface of the semiconductor substrate; It is equipped with The element region of the semiconductor substrate is A plurality of trenches (14) are arranged on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; a source region (40) of a first conductivity type (n) that is disposed in an inter-trench region that is a region sandwiched between the plurality of trenches and that is exposed on the upper surface of the semiconductor substrate; a body region (42) of a second conductivity type (p) disposed in the inter-trench region and below the source region; a first drift region (44A) of a first conductivity type (n) that is distributed across the lower portions of the plurality of trenches and is in contact with a lower surface of the body region and the lower portions of the trenches; a plurality of first deep regions (50A) of a second conductivity type (p), the first deep regions being arranged in a range surrounded by the first drift region, spaced apart from the body region and located below the body region, and being arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of first connection regions (52A) of a second conductivity type (p), the first connection regions being arranged in a portion of the inter-trench region and extending from the top surface of the semiconductor substrate through the source region and the body region to reach the first deep region; It is equipped with The peripheral region of the semiconductor substrate is a second drift region (44B) of the first conductivity type (n), the second drift region being continuous with the first drift region arranged in the element region; a plurality of second deep regions (50B) of a second conductivity type (p), the second deep regions being arranged in an area surrounded by the second drift region and being continuous with each of the plurality of first deep regions arranged in the element region; a second connection region (52B) of a second conductivity type (p) that extends from the top surface of the semiconductor substrate to the second deep region; It is equipped with the opening in the interlayer insulating film includes a first opening region (AP1) and a second opening region (AP2); the first opening region is a region that includes at least a part of the element region, the second opening region is a region disposed in a part of the peripheral region and surrounding the periphery of the element region; Switching element. [Configuration 2] A switching element as described in configuration 1, wherein, when viewed vertically from above on the top surface of the semiconductor substrate, the multiple first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x). [Configuration 3] When viewed vertically from above on the top surface of the semiconductor substrate, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern; 3. The switching element according to configuration 1 or 2, wherein the first connection region is disposed at some of the plurality of intersections. [Configuration 4] The switching element is formed on a semiconductor chip, The semiconductor chip has a rectangular shape including a first chip side (12x) extending in the first direction (x) and a second chip side (12y) extending in the second direction (y), the opening is disposed within the region of the semiconductor chip and has a rectangular shape including a first opening side (APx) extending in the first direction (x) and a second opening side (APy) extending in the second direction (y); the element region is disposed within the region of the opening, and has a rectangular shape including a first element region side (10x) extending in the first direction (x) and a second element region side (10y) extending in the second direction (y), a first distance between the first chip side and the first opening side; a first width is provided between the first opening side and the first element region side; a second distance between the second chip side and the second opening side; a second width is provided between the second opening side and the second element region side; When the first distance is greater than the second distance, the first width is greater than the second width, The switching element according to any one of configurations 1-3, wherein when the second distance is greater than the first distance, the second width is greater than the first width. [Configuration 5] A switching element, a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) provided around the element region; an upper electrode (22) provided on the upper surface of the semiconductor substrate; a lower electrode (24) provided on the lower surface of the semiconductor substrate; It is equipped with The element region of the semiconductor substrate is A plurality of trenches (14) are arranged on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; a source region (40) of a first conductivity type (n) that is disposed in an inter-trench region that is a region sandwiched between the plurality of trenches and that is exposed on the upper surface of the semiconductor substrate; a body region (42) of a second conductivity type (p) disposed in the inter-trench region and below the source region; a first drift region (44A) of a first conductivity type (n) that is distributed across the lower portions of the plurality of trenches and is in contact with a lower surface of the body region and the lower portions of the trenches; a plurality of first deep regions (50A) of a second conductivity type (p), the first deep regions being arranged in a range surrounded by the first drift region, spaced apart from the body region and located below the body region, and being arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of first connection regions (52A) of a second conductivity type (p), the first connection regions being arranged in a portion of the inter-trench region and extending from the top surface of the semiconductor substrate through the source region and the body region to reach the first deep region; It is equipped with The peripheral region of the semiconductor substrate is a second drift region (44B) of the first conductivity type (n), the second drift region being continuous with the first drift region arranged in the element region; a plurality of second deep regions (50B) of a second conductivity type (p), the second deep regions being arranged in an area surrounded by the second drift region and being continuous with each of the plurality of first deep regions arranged in the element region; a second connection region (52B) of a second conductivity type (p) that extends from the top surface of the semiconductor substrate to the second deep region; It is equipped with When viewed vertically from above on the top surface of the semiconductor substrate, the first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x), When viewed vertically from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern, the element region has a rectangular shape including a first element region side (10x) extending in the first direction and a second element region side (10y) extending in the second direction, the plurality of intersections include a first boundary region group (BG1) adjacent to the second element region side and arranged in a line along the second direction, and an internal region group (IG) arranged inside the element region with respect to the first boundary region group, the first connection region is disposed at at least one of the plurality of intersections included in the first boundary region group, and the first connection region is disposed at some of the plurality of intersections included in the internal region group, a ratio of the first connection regions arranged in the first boundary region group being higher than a ratio of the first connection regions arranged in the internal region group; Switching element. [Configuration 6] 6. The switching element according to configuration 5, wherein the first connection region is disposed at all of the plurality of intersections included in the first boundary region group. [Configuration 7] 7. The switching element according to configuration 5 or 6, wherein the first connection region is disposed between adjacent intersections in the plurality of intersections included in the first boundary region group. [Configuration 8] A switching element described in any one of configurations 5-7, wherein the first connection regions arranged at all of the multiple intersections included in the first boundary region group extend continuously in a straight line along the second direction (y). [Configuration 9] the plurality of intersections further include a second boundary region group (BG2) adjacent to the first element region side and arranged in a line along the first direction, the first connection region is disposed in at least a portion of the second boundary region group; A switching element described in any one of configurations 5-8, wherein the proportion of the first connection regions arranged in the second boundary area group is higher than the proportion of the first connection regions arranged in the internal area group. [Configuration 10] A switching element as described in configuration 5, wherein, when viewed vertically from above on the top surface of the semiconductor substrate, the multiple first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x). [Configuration 11] When viewed vertically from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern, The switching element according to any one of configurations 5-10, wherein the first connection region is disposed at some of the plurality of intersections. [Explanation of symbols]

[0057] 1: Switching element 10: Element region 11: Peripheral region 12: Semiconductor substrate 14: Trench 16: Gate insulating film 18: Gate electrode 20: Interlayer insulating film 22: Source electrode 24: Drain electrode 40: Source region 42: Body region 44A: First drift region 44B: Second drift region 50A: First deep region 50B: Second deep region 52A: First connection region 52B: Second connection region 60: Intersection AP1: First opening region AP2: Second opening region

Claims

1. A switching element (1), a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) provided around the element region; an interlayer insulating film (20) disposed on a portion of the upper surface of the semiconductor substrate and having an opening; an upper electrode (22) provided on the upper surface of the semiconductor substrate within the opening; a lower electrode (24) provided on the lower surface of the semiconductor substrate; It is equipped with The element region of the semiconductor substrate is A plurality of trenches (14) arranged on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; a source region (40) of a first conductivity type (n) that is disposed in an inter-trench region that is a region sandwiched between the plurality of trenches and that is exposed on the upper surface of the semiconductor substrate; a body region (42) of a second conductivity type (p) disposed in the inter-trench region and below the source region; a first drift region (44A) of a first conductivity type (n) that is distributed across the lower portions of the plurality of trenches and is in contact with a lower surface of the body region and the lower portions of the trenches; a plurality of first deep regions (50A) of a second conductivity type (p), the first deep regions being arranged in a range surrounded by the first drift region, spaced apart from the body region and located below the body region, and being arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of first connection regions (52A) of a second conductivity type (p), the first connection regions being arranged in a portion of the inter-trench region and extending from the top surface of the semiconductor substrate through the source region and the body region to reach the first deep region; It is equipped with The peripheral region of the semiconductor substrate is a second drift region (44B) of the first conductivity type (n), the second drift region being continuous with the first drift region arranged in the element region; a plurality of second deep regions (50B) of a second conductivity type (p), the second deep regions being arranged in an area surrounded by the second drift region and being continuous with each of the plurality of first deep regions arranged in the element region; a second connection region (52B) of a second conductivity type (p), the second connection region extending from the top surface of the semiconductor substrate to the second deep region; It is equipped with the opening in the interlayer insulating film includes a first opening region (AP1) and a second opening region (AP2); the first opening region is a region including at least a part of the element region, the second opening region is a region disposed in a part of the peripheral region and surrounding the periphery of the element region; Switching element.

2. 2. The switching element of claim 1, wherein, when viewed vertically from above on the top surface of the semiconductor substrate, the first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x).

3. When viewed from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern, The switching element according to claim 2 , wherein the first connection region is disposed at some of the plurality of intersections.

4. The switching element is formed on a semiconductor chip, The semiconductor chip has a rectangular shape including a first chip side (12x) extending in the first direction (x) and a second chip side (12y) extending in the second direction (y), the opening is disposed within the semiconductor chip region and has a rectangular shape including a first opening side (APx) extending in the first direction (x) and a second opening side (APy) extending in the second direction (y); the element region is disposed within the opening region and has a rectangular shape including a first element region side (10x) extending in the first direction (x) and a second element region side (10y) extending in the second direction (y); a first distance between the first chip side and the first opening side; a first width is provided between the first opening side and the first element region side; a second distance between the second chip side and the second opening side; a second width is provided between the second opening side and the second element region side; When the first distance is greater than the second distance, the first width is greater than the second width, 4. The switching element according to claim 1, wherein when the second distance is greater than the first distance, the second width is greater than the first width.

5. A switching element, a semiconductor substrate (12) having an element region (10) in which a device structure is formed and a peripheral region (11) provided around the element region; an upper electrode (22) provided on the upper surface of the semiconductor substrate; a lower electrode (24) provided on the lower surface of the semiconductor substrate; It is equipped with The element region of the semiconductor substrate is A plurality of trenches (14) arranged on the upper surface of the semiconductor substrate, the trenches extending linearly in a first direction (x) and spaced apart in a second direction (y) intersecting the first direction; a gate insulating film (16) covering the inner surface of the trench; a gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; a source region (40) of a first conductivity type (n) that is disposed in an inter-trench region that is a region sandwiched between the plurality of trenches and that is exposed on the upper surface of the semiconductor substrate; a body region (42) of a second conductivity type (p) disposed in the inter-trench region and below the source region; a first drift region (44A) of a first conductivity type (n) that is distributed across the lower portions of the plurality of trenches and is in contact with a lower surface of the body region and the lower portions of the trenches; a plurality of first deep regions (50A) of a second conductivity type (p), the first deep regions being arranged in a range surrounded by the first drift region, spaced apart from the body region and located below the body region, and being arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of first connection regions (52A) of a second conductivity type (p), the first connection regions being arranged in a portion of the inter-trench region and extending from the top surface of the semiconductor substrate through the source region and the body region to reach the first deep region; It is equipped with The peripheral region of the semiconductor substrate is a second drift region (44B) of the first conductivity type (n), the second drift region being continuous with the first drift region arranged in the element region; a plurality of second deep regions (50B) of a second conductivity type (p), the second deep regions being arranged in an area surrounded by the second drift region and being continuous with each of the plurality of first deep regions arranged in the element region; a second connection region (52B) of a second conductivity type (p), the second connection region extending from the top surface of the semiconductor substrate to the second deep region; It is equipped with When viewed vertically from above on the top surface of the semiconductor substrate, the first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x), When viewed from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern, The element region has a rectangular shape including a first element region side (10x) extending in the first direction and a second element region side (10y) extending in the second direction, the plurality of intersections include a first boundary region group (BG1) adjacent to the second element region side and arranged in a line along the second direction, and an internal region group (IG) arranged more inward than the first boundary region group in the element region, the first connection region is disposed at at least one of the plurality of intersections included in the first boundary region group, and the first connection region is disposed at some of the plurality of intersections included in the internal region group, a ratio of the first connection regions arranged in the first boundary region group being higher than a ratio of the first connection regions arranged in the internal region group; Switching element.

6. The switching element according to claim 5 , wherein the first connection region is disposed at all of the plurality of intersections included in the first boundary region group.

7. The switching element according to claim 6 , wherein the first connection region is disposed between adjacent ones of the plurality of intersections included in the first boundary region group.

8. 8. The switching element according to claim 7, wherein the first connection regions arranged at all of the plurality of intersections included in the first boundary region group extend continuously in a straight line along the second direction (y).

9. the plurality of intersections further include a second boundary region group (BG2) adjacent to the first element region side and arranged in a line along the first direction, the first connection region is disposed in at least a portion of the second boundary region group; A switching element according to any one of claims 5 to 8, wherein the proportion of the first connection regions arranged in the second boundary region group is higher than the proportion of the first connection regions arranged in the internal region group.

10. 6. The switching element of claim 5, wherein, when viewed vertically from above on the top surface of the semiconductor substrate, the first deep regions extend linearly along the second direction (y) and are arranged at intervals in the first direction (x).

11. When viewed from above, a plurality of intersections (60) between the plurality of inter-trench regions and the plurality of first deep regions are arranged in a lattice pattern, The switching element according to claim 10 , wherein the first connection region is disposed at some of the plurality of intersections.

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