Semiconductor device

Abstract

To provide a semiconductor device in which the electric resistance of a gate wire can be reduced.SOLUTION: A semiconductor device in an embodiment includes a semiconductor layer including a plurality of first trenches and a plurality of second trenches extending in a first direction, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate wire including a first upper metal layer and a first lower metal layer and electrically connected to the first gate electrode, and a second gate wire including a second upper metal layer and a second lower metal layer and electrically connected to the second gate electrode. At a first intersection part where a first gate wire and a second gate wire intersect, the first lower metal layer and the second upper metal layer do not exist or the first upper metal layer and the second lower metal layer do not exist.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An example of a power semiconductor device is an insulated gate bipolar transistor (IGBT). An IGBT has, for example, a p-type collector region, an n-type drift region, and a p-type base region provided on a collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film sandwiched between them. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In an IGBT, a channel is formed in the p-type base region when a positive voltage equal to or greater than the threshold voltage is applied to the gate electrode. Electrons are then injected from the n-type emitter region into the n-type drift region, and simultaneously holes are injected from the collector region into the n-type drift region. This causes a current to flow between the collector electrode and the emitter electrode, with the electrons and holes as carriers.

[0004] It is desirable to reduce both the on-resistance and the switching loss of an IGBT. To achieve both, an IGBT with multiple gates driven independently has been proposed. By changing the drive timing of the multiple gates, the switching time of the IGBT can be shortened, and the switching loss of the IGBT can be reduced.

[0005] In an IGBT that drives multiple gates independently, multiple gate wirings are provided that are connected to multiple gate electrode pads. Each of the multiple gate wirings is connected to the gate electrodes of different gates. High electrical resistance in the gate wirings causes signal wiring delays, making it difficult to increase the speed of IGBT operation, for example. Therefore, it is desirable to reduce the electrical resistance of the gate wirings. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2022-146579 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device capable of reducing the electrical resistance of gate wiring. [Means for solving the problem]

[0008] The semiconductor device of the embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, including a plurality of first trenches provided on the first surface side and extending in a first direction parallel to the first surface, and a plurality of second trenches provided on the first surface side and extending in the first direction, a first electrode provided on the first surface side of the semiconductor layer, a second electrode provided on the second surface side of the semiconductor layer, a first gate electrode provided in the first trench, and a second electrode provided on the second surface side of the semiconductor layer. a first gate wiring provided on the first surface side of the semiconductor layer, the first gate wiring including a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, the first gate wiring including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode between the first portion and the second portion, the first gate wiring being electrically connected to the first gate electrode; a second gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate wiring, the first gate electrode pad being provided on the first surface side of the semiconductor layer, the second gate electrode pad being electrically connected to the second gate wiring, the first gate electrode pad being provided on the first surface side of the semiconductor layer, the first gate electrode being provided between the third portion and the first electrode, the second portion being provided between the fourth portion and the first electrode, the first gate electrode and the second gate wiring intersecting at a first intersection, and at the first intersection, the first lower metal layer and the second upper metal layer are not present, or the first upper metal layer and the second lower metal layer are not present. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2]1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 1 is a schematic diagram of a part of a semiconductor device according to a first embodiment. [Figure 5] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 7] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 8] FIG. 10 is a schematic diagram of a semiconductor device according to a comparative example. [Figure 9] FIG. 3 is a schematic diagram of a semiconductor device according to a first modified example of the first embodiment. [Figure 10] FIG. 4 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 11] FIG. 4 is a schematic diagram of a semiconductor device according to a second modified example of the first embodiment. [Figure 12] FIG. 4 is a schematic diagram of a semiconductor device according to a second modified example of the first embodiment. [Figure 13] FIG. 10 is a schematic diagram of a semiconductor device according to a third modified example of the first embodiment. [Figure 14] FIG. 10 is a schematic diagram of a semiconductor device according to a third modified example of the first embodiment. [Figure 15] FIG. 4 is a schematic diagram of a semiconductor device according to a second embodiment. [Figure 16] FIG. 6 is a schematic diagram of a part of a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 18] FIG. 4 is a schematic diagram of a semiconductor device according to a second embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0011] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the concentration of n-type impurities decreases in the order of p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0012] (First embodiment) A semiconductor device according to a first embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a plurality of first trenches provided on the first surface side and extending in a first direction parallel to the first surface, and a plurality of second trenches provided on the first surface side and extending in the first direction, a first electrode provided on the first surface side of the semiconductor layer, a second electrode provided on the second surface side of the semiconductor layer, a first gate electrode provided in the first trench, a second gate electrode provided in the second trench, a first upper metal layer provided on the first surface side of the semiconductor layer, and a first lower metal layer provided between the first upper metal layer and the first surface, and a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction. a first gate wiring including a third portion extending in the second direction and a second portion having a first electrode provided between the first portion and the first gate electrode, the second gate wiring being electrically connected to the first gate electrode, a second upper metal layer provided on the first surface side of the semiconductor layer and a second lower metal layer provided between the second upper metal layer and the first surface, the second gate wiring including a third portion extending in the second direction and a fourth portion extending in the second direction and having a first electrode provided between the third portion and the second gate electrode, a first gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate wiring, and a second gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate wiring. The first portion is provided between the third portion and the first electrode, and the second portion is provided between the fourth portion and the first electrode. The first gate wiring and the second gate wiring intersect at a first intersection, and at the first intersection, the first lower metal layer and the second upper metal layer are not present, or the first upper metal layer and the second lower metal layer are not present.

[0013] The semiconductor device of the first embodiment is a trench-gate IGBT 100 having a gate electrode in a trench formed in a semiconductor layer. The IGBT 100 has three independently controllable gates and is capable of triple-gate drive.

[0014] The IGBT 100 of the first embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first contact portion 16, a second contact portion 17, a third contact portion 18, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a first interlayer insulating layer 36, a second interlayer insulating layer 37 (insulating layer), a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103.

[0015] The first gate wiring 11 includes a first portion 11a and a second portion 11b, a first lower metal layer 11x, and a first upper metal layer 11y.

[0016] The second gate wiring 12 includes a third portion 12a and a fourth portion 12b. The second gate wiring 12 includes a second lower metal layer 12x and a second upper metal layer 12y.

[0017] The third gate wiring 13 includes a fifth portion 13a and a sixth portion 13b. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y.

[0018] The emitter electrode 21 includes a fourth lower metal layer 21x and a fourth upper metal layer 21y.

[0019] Within the semiconductor layer 10, a first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a collector region 51, a drift region 52, a base region 53, an emitter region 54, and a contact region 55 are provided.

[0020] 1(a) and 1(b) are schematic diagrams of a semiconductor device according to a first embodiment. Fig. 1(a) shows a layout pattern of a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first gate electrode pad 101, a second gate electrode pad 102, a third gate electrode pad 103, and an emitter electrode 21. Fig. 1(b) shows a layout pattern of a first gate trench 41, a second gate trench 42, and a third gate trench 43.

[0021] As shown in FIG. 1(a), the first gate wiring 11 is connected to the first gate electrode pad 101. The first gate wiring 11 is electrically and physically connected to the first gate electrode pad 101. A first portion 11a of the first gate wiring extends in a second direction. A second portion 11b of the first gate wiring extends in the second direction. An emitter electrode 21 is provided between the first portion 11a and the second portion 11b. The first gate wiring 11 surrounds the emitter electrode 21.

[0022] As shown in FIG. 1(a), the second gate wiring 12 is connected to the second gate electrode pad 102. The second gate wiring 12 is electrically and physically connected to the second gate electrode pad 102. A third portion 12a of the second gate wiring extends in the second direction. A fourth portion 12b of the second gate wiring extends in the second direction. An emitter electrode 21 is provided between the third portion 12a and the fourth portion 12b. The second gate wiring 12 surrounds the emitter electrode 21.

[0023] The first portion 11a of the first gate wiring is provided between the third portion 12a of the second gate wiring and the emitter electrode 21. The second portion 11b of the first gate wiring is provided between the fourth portion 12b of the second gate wiring and the emitter electrode 21.

[0024] As shown in FIG. 1(a), the third gate wiring 13 is connected to the third gate electrode pad 103. The third gate wiring 13 is electrically and physically connected to the third gate electrode pad 103. A fifth portion 13a of the third gate wiring extends in the second direction. A sixth portion 13b of the third gate wiring extends in the second direction. An emitter electrode 21 is provided between the fifth portion 13a and the sixth portion 13b. The third gate wiring 13 surrounds the emitter electrode 21.

[0025] The third portion 12a of the second gate wiring is provided between the fifth portion 13a of the third gate wiring and the emitter electrode 21. The fourth portion 12b of the second gate wiring is provided between the sixth portion 13b of the third gate wiring and the emitter electrode 21.

[0026] The first gate line 11 and the second gate line 12 intersect at a first intersection J1. The first gate line 11 and the third gate line 13 intersect at a second intersection J2. The second gate line 12 and the third gate line 13 intersect at a third intersection J3.

[0027] As shown in FIG. 1(b), the first gate trench 41, the second gate trench 42, and the third gate trench 43 extend in a first direction.

[0028] Fig. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 2 is a cross-section taken along line AA' in Fig. 1(a). Fig. 2 is a cross-section including the emitter electrode 21.

[0029] Fig. 3 is a schematic top view of the semiconductor device of the first embodiment, Fig. 3 is a top view on the first face F1, Fig. 2 is a cross section taken along line AA' in Fig. 3.

[0030] The semiconductor layer 10 has a first face F1 and a second face F2 opposite to the first face F1. The semiconductor layer 10 is, for example, single crystal silicon.

[0031] In this specification, a direction parallel to the first surface F1 is referred to as a "first direction," a direction parallel to the first surface F1 and perpendicular to the first direction is referred to as a "second direction," and a normal direction to the first surface F1 is referred to as a "third direction."

[0032] The emitter electrode 21 is provided on the first face F1 side of the semiconductor layer 10. At least a portion of the emitter electrode 21 contacts the first face F1 of the semiconductor layer 10.

[0033] The emitter electrode 21 is made of metal. The emitter electrode 21 includes a fourth lower metal layer 21x and a fourth upper metal layer 21y. The fourth lower metal layer 21x is provided between the fourth upper metal layer 21y and the first face F1.

[0034] The fourth lower metal layer 21x is formed of a first material, which is a metal. The fourth upper metal layer 21y is formed of a second material, which is a metal.

[0035] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0036] The fourth lower metal layer 21x is, for example, a stacked film of titanium, titanium nitride, and tungsten, and the fourth upper metal layer 21y is, for example, a stacked film of titanium, titanium nitride, and aluminum.

[0037] The fourth lower metal layer 21x and the fourth upper metal layer 21y are electrically and physically connected to each other. An insulating layer may be provided between the fourth lower metal layer 21x and the fourth upper metal layer 21y.

[0038] The emitter electrode 21 is electrically connected to the emitter region 54 and the contact region 55. An emitter voltage is applied to the emitter electrode 21. The emitter voltage is, for example, 0V.

[0039] The collector electrode 22 is provided on the second face F2 side of the semiconductor layer 10. At least a portion of the collector electrode 22 contacts the second face F2 of the semiconductor layer 10. The collector electrode 22 is, for example, a metal.

[0040] The collector electrode 22 is electrically connected to the p-type collector region 51. A collector voltage is applied to the collector electrode 22. The collector voltage is, for example, 200V or more and 6500V or less.

[0041] The collector region 51 is a p-type semiconductor region. The collector region 51 is electrically connected to the collector electrode 22. The collector region 51 is in contact with the collector electrode 22. The collector region 51 serves as a supply source of holes when the IGBT 100 is in the on state.

[0042] The drift region 52 is n - The drift region 52 is a semiconductor region having a shape similar to that of the collector region 51. The drift region 52 is provided between the collector region 51 and the first face F1. The drift region 52 serves as a path for an on-current when the IGBT 100 is in an on-state. The drift region 52 is depleted when the IGBT 100 is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT 100.

[0043] The base region 53 is a p-type semiconductor region. The base region 53 is provided between the drift region 52 and the first face F1. The base region 53 functions as a channel region of the transistor.

[0044] The emitter region 54 is n + The emitter region 54 is a semiconductor region having a shape similar to that of the base region 53. The emitter region 54 is provided between the base region 53 and the first face F1. The emitter region 54 is electrically connected to the emitter electrode 21. The emitter region 54 contacts the emitter electrode 21. The emitter region 54 serves as a source of electrons when the transistor is in an on-state.

[0045] The contact region 55 is p +The contact region 55 is a semiconductor region having a shape similar to that of the emitter electrode 21. The contact region 55 is provided between the base region 53 and the first face F1. The contact region 55 is provided adjacent to or spaced apart from the emitter region 54. The contact region 55 is electrically connected to the emitter electrode 21.

[0046] A plurality of first gate trenches 41 are provided on the first face F1 side of the semiconductor layer 10. As shown in FIG. 3 , the first gate trenches 41 extend in the first face F1 in a first direction parallel to the first face F1. The first gate trenches 41 have a stripe shape. The plurality of first gate trenches 41 are repeatedly arranged in a second direction perpendicular to the first direction. The first gate trenches 41 penetrate the base region 53 and reach the drift region 52.

[0047] A plurality of second gate trenches 42 are provided on the first face F1 side of the semiconductor layer 10. As shown in FIG. 3 , the second gate trenches 42 extend in a first direction on the first face F1. The second gate trenches 42 have a stripe shape. The second gate trenches 42 are repeatedly arranged in the second direction. The second gate trenches 42 penetrate the base region 53 and reach the drift region 52.

[0048] A plurality of third gate trenches 43 are provided on the first face F1 side of the semiconductor layer 10. As shown in FIG. 3 , the third gate trenches 43 extend in a first direction on the first face F1. The third gate trenches 43 have a stripe shape. The third gate trenches 43 are repeatedly arranged in the second direction. The third gate trenches 43 penetrate the base region 53 and reach the drift region 52.

[0049] The first gate electrode 31 is provided in the first gate trench 41. The first gate electrode 31 is, for example, a semiconductor or a metal. The first gate electrode 31 is, for example, polycrystalline silicon containing conductive impurities. The first gate electrode 31 is electrically connected to the first gate wiring 11 and the first gate electrode pad 101.

[0050] The second gate electrode 32 is provided in the second gate trench 42. The second gate electrode 32 is, for example, a semiconductor or a metal. The second gate electrode 32 is, for example, polycrystalline silicon containing conductive impurities. The second gate electrode 32 is electrically connected to the second gate wiring 12 and the second gate electrode pad 102.

[0051] The third gate electrode 33 is provided in the third gate trench 43. The third gate electrode 33 is, for example, a semiconductor or a metal. The third gate electrode 33 is, for example, polycrystalline silicon containing conductive impurities. The third gate electrode 33 is electrically connected to the third gate wiring 13 and the third gate electrode pad 103.

[0052] The gate insulating film 23 is provided between the first gate electrode 31 and the semiconductor layer 10. The gate insulating film 23 is provided between the second gate electrode 32 and the semiconductor layer 10. The gate insulating film 23 is provided between the third gate electrode 33 and the semiconductor layer 10. The gate insulating film 23 is made of, for example, silicon oxide.

[0053] The first interlayer insulating layer 36 is provided between the first gate electrode 31 and the emitter electrode 21. The first interlayer insulating layer 36 electrically separates the first gate electrode 31 and the emitter electrode 21.

[0054] The first interlayer insulating layer 36 is provided between the second gate electrode 32 and the emitter electrode 21. The first interlayer insulating layer 36 electrically separates the second gate electrode 32 and the emitter electrode 21 from each other.

[0055] The first interlayer insulating layer 36 is provided between the third gate electrode 33 and the emitter electrode 21. The first interlayer insulating layer 36 electrically isolates the third gate electrode 33 from the emitter electrode 21.

[0056] The first interlayer insulating layer 36 is, for example, silicon oxide.

[0057] 4(a) and 4(b) are schematic diagrams of a portion of the semiconductor device of the first embodiment. Fig. 4(a) is an enlarged view of a first region R1 shown in Fig. 1(a). Fig. 4(b) is an enlarged view of a second region R2 shown in Fig. 1(a).

[0058] 4(a) and 4(b) show layout patterns of the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, the first contact portion 16, the second contact portion 17, the third contact portion 18, and the emitter electrode 21.

[0059] 4(a), a first contact portion 16 is provided at a portion where a first portion 11a of the first gate wiring intersects with the first gate trench 41. In the first contact portion 16, the first portion 11a is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0060] 4(a), a second contact portion 17 is provided at a portion where the third portion 12a of the second gate wiring intersects with the second gate trench 42. In the second contact portion 17, the third portion 12a is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0061] 4(a), a third contact portion 18 is provided at a portion where a fifth portion 13a of the third gate wiring intersects with the third gate trench 43. In the third contact portion 18, the fifth portion 13a is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0062] 4(b), a first contact portion 16 is provided at a portion where the second portion 11b of the first gate wiring intersects with the first gate trench 41. In the first contact portion 16, the second portion 11b is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0063] 4(b), a second contact portion 17 is provided at a portion where the fourth portion 12b of the second gate wiring intersects with the second gate trench 42. In the second contact portion 17, the fourth portion 12b is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0064] 4(b), a third contact portion 18 is provided at a portion where the sixth portion 13b of the third gate wiring intersects with the third gate trench 43. In the third contact portion 18, the sixth portion 13b is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0065] 5 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line BB' in FIG.

[0066] The first gate wiring 11 is made of metal. The first gate wiring 11 includes a first lower metal layer 11x and a first upper metal layer 11y. The first lower metal layer 11x is provided between the first upper metal layer 11y and the first face F1.

[0067] The second gate wiring 12 is made of metal. The second gate wiring 12 includes a second lower metal layer 12x and a second upper metal layer 12y. The second lower metal layer 12x is provided between the second upper metal layer 12y and the first face F1.

[0068] The third gate wiring 13 is made of metal. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y. The third lower metal layer 13x is provided between the third upper metal layer 13y and the first face F1.

[0069] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0070] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are formed of a second material. The second material is a metal. The second material of the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y is the same as the second material of the fourth upper metal layer 21y of the emitter electrode 21.

[0071] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0072] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are, for example, stacked films of titanium, titanium nitride, and tungsten.

[0073] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0074] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are electrically and physically connected to the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y, respectively.

[0075] Each of the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 has a laminated structure of two different metal layers.

[0076] 5, the second interlayer insulating layer 37 is provided, for example, between a portion of the first lower metal layer 11x and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second lower metal layer 12x and a portion of the second upper metal layer 12y. The second interlayer insulating layer 37 is provided, for example, between a portion of the third lower metal layer 13x and a portion of the third upper metal layer 13y.

[0077] As shown in FIG. 5, the first lower metal layer 11x of the first gate wiring is connected to the first gate electrode 31 at the first contact portion 16.

[0078] 6(a) and 6(b) are schematic diagrams of the semiconductor device of the first embodiment. Fig. 6(a) shows a layout pattern of a first lower metal layer 11x of the first gate wiring, a second lower metal layer 12x of the second gate wiring, a third lower metal layer 13x of the third gate wiring, and a fourth lower metal layer 21x of the emitter electrode. Fig. 6(b) shows a layout pattern of a first upper metal layer 11y of the first gate wiring, a second upper metal layer 12y of the second gate wiring, a third upper metal layer 13y of the third gate wiring, and a fourth upper metal layer 21y of the emitter electrode.

[0079] Note that Figure 6(b) also shows layout patterns of the first gate electrode pad 101, the second gate electrode pad 102, and the third gate electrode pad 103, which are formed from the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0080] 6(a), the first lower metal layer 11x surrounds the fourth lower metal layer 21x. The first lower metal layer 11x surrounds the emitter electrode 21. The first lower metal layer 11x is annular in a plane parallel to the first face F1.

[0081] 6(a), the second lower metal layer 12x surrounds the fourth lower metal layer 21x. The second lower metal layer 12x surrounds the emitter electrode 21. The second lower metal layer 12x surrounds the first lower metal layer 11x. The second lower metal layer 12x is annular in a plane parallel to the first face F1.

[0082] 6(a), the third lower metal layer 13x surrounds the fourth lower metal layer 21x. The third lower metal layer 13x surrounds the emitter electrode 21. The third lower metal layer 13x surrounds the second lower metal layer 12x. The third lower metal layer 13x is annular in a plane parallel to the first face F1.

[0083] As shown in Fig. 6(a), the first lower metal layer 11x of the first gate wiring is not present at the first intersection J1 between the first gate wiring 11 and the second gate wiring 12. Also, as shown in Fig. 6(b), the second upper metal layer 12y of the second gate wiring is not present at the first intersection J1.

[0084] Fig. 7 is a schematic cross-sectional view of a portion of the semiconductor device of the first embodiment. Fig. 7 shows a cross section of a first intersection J1. Fig. 7 shows a cross section parallel to the first direction and perpendicular to the second direction.

[0085] 7, at the first intersection J1, only the second lower metal layer 12x of the second gate wiring 12 is continuous in the first direction, and at the first intersection J1, only the first upper metal layer 11y of the first gate wiring 11 is continuous in the second direction perpendicular to the paper surface.

[0086] At the first intersection J1, the first gate line 11 and the second gate line 12 are separated from each other by the second interlayer insulating layer 37. Therefore, at the first intersection J1, the first gate line 11 and the second gate line 12 are not short-circuited.

[0087] As shown in Fig. 6(a), the first lower metal layer 11x of the first gate line is not present at the second intersection J2 between the first gate line 11 and the third gate line 13. Also, as shown in Fig. 6(b), the second upper metal layer 12y of the second gate line is not present at the second intersection J2. Therefore, the first gate line 11 and the third gate line 13 are not short-circuited at the second intersection J2.

[0088] As shown in Fig. 6(a), the second lower metal layer 12x of the second gate line is not present at the third intersection J3 between the second gate line 12 and the third gate line 13. Also, as shown in Fig. 6(b), the third upper metal layer 13y of the third gate line is not present at the third intersection J3. Therefore, the second gate line 12 and the third gate line 13 are not short-circuited at the third intersection J3.

[0089] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0090] The IGBT 100 of the first embodiment includes a first gate electrode 31 to which a first gate voltage (Vg1) is applied, a second gate electrode 32 to which a second gate voltage (Vg2) is applied, and a third gate electrode 33 to which a third gate voltage (Vg3) is applied. The IGBT 100 of the first embodiment includes a first transistor controlled by the first gate electrode 31, a second transistor controlled by the second gate electrode 32, and a third transistor controlled by the third gate electrode 33. For example, the area surrounded by dashed line T1 in FIG. 2 corresponds to the first transistor. Also, for example, the area surrounded by dashed line T2 in FIG. 2 corresponds to the second transistor. Also, for example, the area surrounded by dashed line T3 in FIG. 2 corresponds to the third transistor. Triple gate drive of the IGBT 100 can be achieved by providing independent gate signals to the first transistor, the second transistor, and the third transistor. The triple gate drive of the IGBT 100 makes it possible to achieve, for example, both a reduction in on-resistance and a reduction in switching loss.

[0091] To perform triple gate drive, three gate electrode pads are required to apply three different gate voltages, and three gate wiring lines are required to connect each gate electrode pad to the gate electrode.

[0092] Fig. 8 is a schematic diagram of a semiconductor device of a comparative embodiment, which corresponds to Fig. 1(a) of the first embodiment.

[0093] The semiconductor device of the comparative example is an IGBT 900 capable of triple gate drive. The IGBT 100 of the comparative example differs from the IGBT 100 of the first embodiment in that the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 are formed of a single metal layer.

[0094] For example, in FIG. 8, the wiring length from the terminal end (P1 in FIG. 8) of the second gate wiring 12 to the second gate electrode pad 102 becomes extremely long because the second gate wiring 12 wraps around the emitter electrode 21. The wiring length from the second gate electrode pad 102 to the gate electrode connected to the second gate wiring 12 at the terminal end P1 becomes long. This increases the electrical resistance of the second gate wiring 12 up to the terminal end P1. This increases the wiring delay to the gate electrode connected to the second gate wiring 12 at the terminal end P1. This makes it difficult to increase the operating speed of the IGBT 900, for example.

[0095] Furthermore, in the comparative IGBT 900, the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 are formed of a single metal layer, so the electrical resistance per unit length of the gate wiring is also large.

[0096] In the IGBT 100 of the first embodiment, the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 are each formed with a stacked structure of a first lower metal layer 11x and a first upper metal layer 11y, a second lower metal layer 12x and a second upper metal layer 12y, and a third lower metal layer 13x and a third upper metal layer 13y, respectively, thereby reducing the electrical resistance per unit length of the gate wiring.

[0097] Furthermore, by forming the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 in a stacked structure, it becomes possible to cross each other. Therefore, the wiring length of the gate wiring from the electrode pad to the gate electrode can be shortened. Therefore, the electrical resistance of the gate wiring can be reduced.

[0098] According to the IGBT 100 of the first embodiment, by reducing the electrical resistance of the gate wiring, it is possible to increase the operating speed of the IGBT 100, for example.

[0099] Furthermore, according to the IGBT 100 of the first embodiment, the gate wirings can be crossed, which increases the degree of freedom in designing the layout pattern of the gate wirings, and therefore, for example, makes it possible to reduce the chip size of the IGBT 100.

[0100] Furthermore, the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x can be formed simultaneously with the fourth lower metal layer 21x of the emitter electrode 21. Furthermore, the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y can be formed simultaneously with the fourth upper metal layer 21y of the emitter electrode 21. Therefore, an additional manufacturing process for forming a stacked structure of the gate wiring is not required, and an increase in the manufacturing cost of the IGBT 100 can be suppressed.

[0101] (First Modification) The semiconductor device of the first variant of the first embodiment differs from the semiconductor device of the first embodiment in that the first upper metal layer of the second gate wiring surrounds the first electrode, and the third upper metal layer of the third gate wiring surrounds the first electrode.

[0102] The semiconductor device of the first modification of the first embodiment is an IGBT 110.

[0103] 9(a) and 9(b) are schematic diagrams of a semiconductor device according to a first modified example of the first embodiment, and correspond to FIGS. 6(a) and 6(b) of the first embodiment.

[0104] 9(a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. FIG. 9(b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0105] Note that Figure 9(a) also shows layout patterns of a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103, which are formed from the same first material as the first lower metal layer 11x, the second lower metal layer 12x, the third lower metal layer 13x, and the fourth lower metal layer 21x.

[0106] FIG. 9(b) also shows layout patterns of a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103 formed from the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0107] 9(b), the first upper metal layer 11y surrounds the fourth upper metal layer 21y. The first upper metal layer 11y surrounds the emitter electrode 21. The first upper metal layer 11y is annular in a plane parallel to the first face F1.

[0108] 9(b), the second upper metal layer 12y surrounds the fourth upper metal layer 21y. The second upper metal layer 12y surrounds the emitter electrode 21. The second upper metal layer 12y surrounds the first upper metal layer 11y. The second upper metal layer 12y is annular in a plane parallel to the first face F1.

[0109] 9(b), the third upper metal layer 13y surrounds the fourth upper metal layer 21y. The third upper metal layer 13y surrounds the emitter electrode 21. The third upper metal layer 13y surrounds the second upper metal layer 12y. The third upper metal layer 13y is annular in a plane parallel to the first plane F1.

[0110] 9(a), the second lower metal layer 12x of the second gate wiring is not present at the first intersection J1 between the first gate wiring 11 and the second gate wiring 12. Also, as shown in FIG. 9(b), the first upper metal layer 11y of the first gate wiring is not present at the first intersection J1.

[0111] Fig. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a first modification of the first embodiment. Fig. 10 shows a cross section of a first intersection J1. Fig. 10 shows a cross section parallel to the first direction and perpendicular to the second direction.

[0112] 10, at the first intersection J1, only the first lower metal layer 11x of the first gate wiring 11 is continuous in the second direction perpendicular to the paper surface, and at the first intersection J1, only the second upper metal layer 12y of the second gate wiring 12 is continuous in the first direction.

[0113] At the first intersection J1, the first gate line 11 and the second gate line 12 are separated from each other by the second interlayer insulating layer 37. Therefore, at the first intersection J1, the first gate line 11 and the second gate line 12 are not short-circuited.

[0114] As shown in Fig. 9(a), the third lower metal layer 13x of the third gate wiring is not present at the second intersection J2 between the first gate wiring 11 and the third gate wiring 13. Also, as shown in Fig. 9(b), the first upper metal layer 11y of the first gate wiring is not present at the second intersection J2. Therefore, the first gate wiring 11 and the third gate wiring 13 are not short-circuited at the second intersection J2.

[0115] As shown in Fig. 9(a), the third lower metal layer 13x of the third gate line is not present at the third intersection J3 between the second gate line 12 and the third gate line 13. Also, as shown in Fig. 9(b), the second upper metal layer 12y of the second gate line is not present at the third intersection J3. Therefore, the second gate line 12 and the third gate line 13 are not short-circuited at the third intersection J3.

[0116] According to the IGBT 110 of the first modification of the first embodiment, the electrical resistance of the gate wiring can be reduced, similarly to the IGBT 100 of the first embodiment.

[0117] (Second Modification) The semiconductor device of the second variant of the first embodiment differs from the semiconductor device of the first embodiment in that the first gate wiring includes a seventh portion that is provided between the first portion and the second portion and extends in the second direction, the second gate wiring includes an eighth portion that is provided between the third portion and the fourth portion and extends in the second direction, and the third gate wiring includes a ninth portion that is provided between the fifth portion and the sixth portion and extends in the second direction.

[0118] The semiconductor device of the second modification of the first embodiment is an IGBT 120.

[0119] Figures 11(a) and 11(b) are schematic diagrams of a semiconductor device according to a second modified example of the first embodiment, and correspond to Figures 1(a) and 1(b) of the first embodiment.

[0120] The first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 include a seventh portion 11c, an eighth portion 12c, and a ninth portion 13c, respectively.

[0121] The emitter electrode 21 is divided in the second direction and includes a first region 21a and a second region 21b.

[0122] The seventh portion 11c of the first gate wiring 11 is provided between the first portion 11a and the second portion 11b. The seventh portion 11c of the first gate wiring 11 extends in the second direction. A first region 21a of the emitter electrode 21 is provided between the first portion 11a and the seventh portion 11c. A second region 21b of the emitter electrode 21 is provided between the second portion 11b and the seventh portion 11c.

[0123] The eighth portion 12c of the second gate wiring 12 is provided between the third portion 12a and the fourth portion 12b. The eighth portion 12c of the second gate wiring 12 extends in the second direction. The first region 21a of the emitter electrode 21 is provided between the third portion 12a and the eighth portion 21c. The second region 21b of the emitter electrode 21 is provided between the fourth portion 12b and the eighth portion 12c.

[0124] The ninth portion 13c of the third gate wiring 13 is provided between the fifth portion 13a and the sixth portion 13b. The ninth portion 13c of the third gate wiring 13 extends in the second direction. A first region 21a of the emitter electrode 21 is provided between the fifth portion 13a and the ninth portion 13c. A second region 21b of the emitter electrode 21 is provided between the sixth portion 13b and the ninth portion 13c.

[0125] The seventh portion 11c of the first gate wiring 11, the eighth portion 12c of the second gate wiring 12, and the ninth portion 13c of the third gate wiring 13 are so-called gate fingers.

[0126] Figures 12(a) and 12(b) are schematic diagrams of a semiconductor device according to a second modified example of the first embodiment, and correspond to Figures 6(a) and 6(b) of the first embodiment.

[0127] 12(a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. FIG. 12(b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0128] Note that Figure 12(b) also shows layout patterns of the first gate electrode pad 101, the second gate electrode pad 102, and the third gate electrode pad 103, which are formed from the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0129] According to the IGBT 120 of the second modification of the first embodiment, even if the gate wiring includes gate fingers, the electrical resistance of the gate wiring can be reduced, similar to the IGBT 100 of the first embodiment.

[0130] (Third Modification) The semiconductor device of the third modified example of the first embodiment differs from the semiconductor device of the first embodiment in that the first gate wiring does not surround the first electrode, and the second gate wiring does not surround the first electrode.

[0131] The semiconductor device of the third modified example of the first embodiment is an IGBT 130.

[0132] Figures 13(a) and 13(b) are schematic diagrams of a semiconductor device according to a third modified example of the first embodiment, and correspond to Figures 1(a) and 1(b) of the first embodiment.

[0133] The first gate wiring 11 does not surround the emitter electrode 21. The second gate wiring 12 does not surround the emitter electrode 21. The third gate wiring 13 does not surround the emitter electrode 21.

[0134] Figures 14(a) and 14(b) are schematic diagrams of a semiconductor device according to a third modification of the first embodiment. Figures 13(a) and 13(b) correspond to Figures 6(a) and 6(b) of the first embodiment.

[0135] 14(a) shows a layout pattern of the first lower metal layer 11x of the first gate wiring, the second lower metal layer 12x of the second gate wiring, the third lower metal layer 13x of the third gate wiring, and the fourth lower metal layer 21x of the emitter electrode. FIG. 14(b) shows a layout pattern of the first upper metal layer 11y of the first gate wiring, the second upper metal layer 12y of the second gate wiring, the third upper metal layer 13y of the third gate wiring, and the fourth upper metal layer 21y of the emitter electrode.

[0136] Note that Figure 14(b) also shows layout patterns of the first gate electrode pad 101, the second gate electrode pad 102, and the third gate electrode pad 103, which are formed from the same second material as the first upper metal layer 11y, the second upper metal layer 12y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0137] According to the IGBT 130 of the third modified example of the first embodiment, the electrical resistance of the gate wiring can be reduced, similarly to the IGBT 100 of the first embodiment.

[0138] As described above, according to the first embodiment and the modified examples, a semiconductor device capable of reducing the electrical resistance of the gate wiring can be provided.

[0139] (Second embodiment) The semiconductor device of the second embodiment has a first surface and a second surface opposite to the first surface, and includes a semiconductor layer including a plurality of first trenches provided on the first surface side and extending in a first direction parallel to the first surface, a plurality of second trenches provided on the first surface side and extending in the first direction, and a plurality of third trenches provided on the first surface side and extending in the first direction; a first electrode provided on the first surface side of the semiconductor layer; a second electrode provided on the second surface side of the semiconductor layer; a first gate electrode provided in the trench, a second gate electrode provided in the second trench, a third gate electrode provided in the third trench, a first upper metal layer provided on the first surface side of the semiconductor layer, and a first lower metal layer provided between the first upper metal layer and the first surface; a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having a first electrode provided between the first portion; a first gate wiring electrically connected to the gate electrode; a second gate wiring provided on the first surface side of the semiconductor layer and including a third portion extending in the second direction and a fourth portion extending in the second direction and having a first electrode provided between the third portion, and electrically connected to the second gate electrode; a third gate wiring provided on the first surface side of the semiconductor layer and including a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, and including a fifth portion extending in the second direction and a sixth portion extending in the second direction and having a first electrode provided between the fifth portion, and electrically connected to the third gate electrode; a first gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate wiring; a second gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate wiring; and a third gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate wiring. A first portion is provided between the third portion and the first electrode, and a third portion is provided between the fifth portion and the first electrode. A first distance in a first direction between the first upper metal layer of the first portion and the third upper metal layer of the fifth portion is smaller than a first width in the first direction of the third portion.The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that a first distance in a first direction between an upper metal layer of a first portion of a first gate wiring and an upper metal layer of a first portion of a third gate wiring is smaller than a first width in the first direction of the first portion of a second gate wiring. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0140] The semiconductor device of the second embodiment is a trench-gate IGBT 200 having a gate electrode in a trench formed in a semiconductor layer. The IGBT 200 has three independently controllable gates and is capable of triple-gate drive.

[0141] The IGBT 200 of the second embodiment includes a semiconductor layer 10, a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first contact portion 16, a second contact portion 17, a third contact portion 18, an emitter electrode 21 (first electrode), a collector electrode 22 (second electrode), a gate insulating film 23, a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a first interlayer insulating layer 36, a second interlayer insulating layer 37, a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103.

[0142] The first gate wiring 11 includes a first portion 11a and a second portion 11b, a first lower metal layer 11x, and a first upper metal layer 11y.

[0143] The second gate line 12 includes a third portion 12a and a fourth portion 12b.

[0144] The third gate wiring 13 includes a fifth portion 13a and a sixth portion 13b. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y.

[0145] The emitter electrode 21 includes a fourth lower metal layer 21x and a fourth upper metal layer 21y.

[0146] Within the semiconductor layer 10, a first gate trench 41 (first trench), a second gate trench 42 (second trench), a third gate trench 43 (third trench), a collector region 51, a drift region 52, a base region 53, an emitter region 54, and a contact region 55 are provided.

[0147] 15(a) and 15(b) are schematic diagrams of a semiconductor device according to the second embodiment. Fig. 15(a) shows a layout pattern of a first gate wiring 11, a second gate wiring 12, a third gate wiring 13, a first gate electrode pad 101, a second gate electrode pad 102, a third gate electrode pad 103, and an emitter electrode 21. Fig. 15(b) shows a layout pattern of a first gate trench 41, a second gate trench 42, and a third gate trench 43.

[0148] As shown in FIG. 15(a), the first gate wiring 11 is connected to the first gate electrode pad 101. The first gate wiring 11 is electrically and physically connected to the first gate electrode pad 101. A first portion 11a of the first gate wiring extends in the second direction. A second portion 11b of the first gate wiring extends in the second direction. An emitter electrode 21 is provided between the first portion 11a and the second portion 11b. The first gate wiring 11 surrounds the emitter electrode 21.

[0149] As shown in FIG. 15(a), the second gate wiring 12 is connected to the second gate electrode pad 102. The second gate wiring 12 is electrically and physically connected to the second gate electrode pad 102. A third portion 12a of the second gate wiring extends in the second direction. A fourth portion 12b of the second gate wiring extends in the second direction. An emitter electrode 21 is provided between the third portion 12a and the fourth portion 12b. The second gate wiring 12 surrounds the emitter electrode 21.

[0150] The first portion 11a of the first gate wiring is provided between the third portion 12a of the second gate wiring and the emitter electrode 21. The second portion 11b of the first gate wiring is provided between the fourth portion 12b of the second gate wiring and the emitter electrode 21.

[0151] As shown in FIG. 15(a), the third gate wiring 13 is connected to the third gate electrode pad 103. The third gate wiring 13 is electrically and physically connected to the third gate electrode pad 103. A fifth portion 13a of the third gate wiring extends in the second direction. A sixth portion 13b of the third gate wiring extends in the second direction. An emitter electrode 21 is provided between the fifth portion 13a and the sixth portion 13b.

[0152] The third portion 12a of the third gate wiring is provided between the fifth portion 13a of the third gate wiring and the emitter electrode 21. The fourth portion 12b of the second gate wiring is provided between the sixth portion 13b of the third gate wiring and the emitter electrode 21.

[0153] The first gate wiring 11 and the second gate wiring 12 partially overlap each other, and the second gate wiring 12 and the third gate wiring 13 partially overlap each other.

[0154] As shown in FIG. 15(b), the first gate trench 41, the second gate trench 42, and the third gate trench 43 extend in a first direction.

[0155] 16(a) and 16(b) are schematic diagrams of a portion of the semiconductor device of the second embodiment. Fig. 16(a) is an enlarged view of the first region R1 shown in Fig. 15(a). Fig. 16(b) is an enlarged view of the second region R2 shown in Fig. 15(a).

[0156] 16(a) and 16(b) show layout patterns of the first gate wiring 11, the second gate wiring 12, the third gate wiring 13, the first contact portion 16, the second contact portion 17, the third contact portion 18, and the emitter electrode 21.

[0157] 16(a), a first contact portion 16 is provided at a portion where a first portion 11a of the first gate wiring intersects with the first gate trench 41. In the first contact portion 16, the first portion 11a is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0158] 16(a), a second contact portion 17 is provided at a portion where the third portion 12a of the second gate wiring intersects with the second gate trench 42. In the second contact portion 17, the third portion 12a is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0159] 16(a), a third contact portion 18 is provided at a portion where a fifth portion 13a of the third gate wiring intersects with the third gate trench 43. In the third contact portion 18, the fifth portion 13a is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0160] 16(b), a first contact portion 16 is provided at a portion where the second portion 11b of the first gate wiring intersects with the first gate trench 41. In the first contact portion 16, the second portion 11b is electrically and physically connected to the first gate electrode 31 provided in the first gate trench 41.

[0161] 16(b), a second contact portion 17 is provided at a portion where the fourth portion 12b of the second gate wiring intersects with the second gate trench 42. In the second contact portion 17, the fourth portion 12b is electrically and physically connected to the second gate electrode 32 provided in the second gate trench 42.

[0162] 16(b), a third contact portion 18 is provided at a portion where the sixth portion 13b of the third gate wiring intersects with the third gate trench 43. In the third contact portion 18, the sixth portion 13b is electrically and physically connected to the third gate electrode 33 provided in the third gate trench 43.

[0163] 17 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, taken along the line CC' in FIG.

[0164] The first gate wiring 11 is made of metal. The first gate wiring 11 includes a first lower metal layer 11x and a first upper metal layer 11y. The first lower metal layer 11x is provided between the first upper metal layer 11y and the first face F1.

[0165] The second gate wiring 12 is made of metal.

[0166] The third gate wiring 13 is made of metal. The third gate wiring 13 includes a third lower metal layer 13x and a third upper metal layer 13y. The third lower metal layer 13x is provided between the third upper metal layer 13y and the first face F1.

[0167] The first lower metal layer 11x, the second gate wiring 12, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second gate wiring 12, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0168] The first upper metal layer 11y and the second upper metal layer 12y are formed of a second material, which is a metal. The second material of the first upper metal layer 11y and the third upper metal layer 13y is the same as the second material of the fourth upper metal layer 21y of the emitter electrode 21.

[0169] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0170] The first lower metal layer 11x, the second gate wiring 12, and the third lower metal layer 13x are, for example, a stacked film of titanium, titanium nitride, and tungsten.

[0171] The first upper metal layer 11y and the third upper metal layer 13y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0172] The first lower metal layer 11x and the third lower metal layer 13x are electrically and physically connected to the first upper metal layer 11y and the third upper metal layer 13y, respectively.

[0173] The first gate line 11 and the third gate line 13 each have a laminated structure of two different metal layers.

[0174] 17, the second interlayer insulating layer 37 is provided, for example, between a portion of the first lower metal layer 11x and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second gate wiring 12 and a portion of the first upper metal layer 11y. The second interlayer insulating layer 37 is provided, for example, between a portion of the second gate wiring 12 and a portion of the third upper metal layer 13y. The second interlayer insulating layer 37 is provided, for example, between a portion of the third lower metal layer 13x and a portion of the third upper metal layer 13y.

[0175] As shown in FIG. 17, the first lower metal layer 11x of the first gate wiring is connected to the first gate electrode 31 at the first contact portion 16.

[0176] As shown in FIG. 17, the first distance in the first direction (d1 in FIG. 17) between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring is smaller than the first width in the first direction (w1 in FIG. 17) of the third portion 12a of the second gate wiring.

[0177] 17, the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third portion 12a of the second gate wiring overlap in the third direction. Also, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring and the third portion 12a of the second gate wiring overlap in the third direction.

[0178] 17, the first width w1 in the first direction of the third portion 12a of the second gate wiring is wider than the second width (w2 in FIG. 17) in the first direction of the first lower metal layer 11x of the first portion 11a of the first gate wiring. Also, the first width w1 is wider than the third width (w3 in FIG. 17) in the first direction of the third lower metal layer 13x of the fifth portion 13a of the third gate wiring.

[0179] 17, the fourth width in the first direction (w4 in FIG. 17) of the first upper metal layer 11y of the first portion 11a of the first gate wiring is wider than the second width in the first direction w2 of the first lower metal layer 11x of the first portion 11a. Also, the fifth width in the first direction (w5 in FIG. 17) of the third upper metal layer 13y of the fifth portion 13a of the third gate wiring is wider than the third width in the first direction w3 of the third lower metal layer 13x of the fifth portion 13a.

[0180] Figures 18(a) and 18(b) are schematic diagrams of a semiconductor device according to the second embodiment, which correspond to Figures 6(a) and 6(b) of the first embodiment.

[0181] 18(a) shows a layout pattern of the first lower metal layer 11x, the second gate wiring 12, the third lower metal layer 13x, and the fourth lower metal layer 21x. FIG. 18(b) shows a layout pattern of the first upper metal layer 11y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0182] In addition, Figure 18(a) also shows the layout pattern of the second gate electrode pad 102 formed from the same first material as the first lower metal layer 11x, the second gate wiring 12, the third lower metal layer 13x, and the fourth lower metal layer 21x.

[0183] FIG. 18(b) also shows layout patterns of a first gate electrode pad 101, a second gate electrode pad 102, and a third gate electrode pad 103 formed from the same second material as the first upper metal layer 11y, the third upper metal layer 13y, and the fourth upper metal layer 21y.

[0184] 18(a), the second gate wiring 12 surrounds the fourth lower metal layer 21x of the emitter electrode. The second gate wiring 12 surrounds the emitter electrode 21. The second gate wiring 12 is annular in a plane parallel to the first plane F1.

[0185] 18(b), the first upper metal layer 11y surrounds the fourth upper metal layer 21y. The first upper metal layer 11y surrounds the emitter electrode 21. The first upper metal layer 11y is annular in a plane parallel to the first face F1.

[0186] Next, the operation and effects of the semiconductor device of the second embodiment will be described.

[0187] The IGBT 200 of the second embodiment can achieve both a reduction in on-resistance and a reduction in switching loss by using triple gate driving, for example.

[0188] In the IGBT 200 of the second embodiment, at least a portion of the first gate wiring 11 is formed of a stacked structure of a first lower metal layer 11x and a first upper metal layer 11y. Also, at least a portion of the third gate wiring 13 is formed of a stacked structure of a third lower metal layer 13x and a third upper metal layer 13y. Therefore, the electrical resistance per unit length of the gate wiring can be reduced.

[0189] According to the IGBT 200 of the second embodiment, by reducing the electrical resistance of the gate wiring, for example, it becomes difficult to increase the operating speed of the IGBT 200.

[0190] In the IGBT 200 of the second embodiment, as shown in FIG. 17, the first distance in the first direction (d1 in FIG. 17) between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring is smaller than the first width in the first direction (w1 in FIG. 17) of the third portion 12a of the second gate wiring. Therefore, the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third portion 12a of the second gate wiring overlap in the third direction. Furthermore, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring and the third portion 12a of the second gate wiring overlap in the third direction.

[0191] By arranging three gate wirings extending in the second direction so as to overlap each other, the width of the region in which the gate wirings are provided in the first direction can be reduced, which makes it possible to reduce the chip size of the IGBT 200, for example.

[0192] (First Modification) The semiconductor device of the first modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the second gate wiring includes a lower metal layer and an upper metal layer.

[0193] 19 is a schematic cross-sectional view of a part of a semiconductor device according to a first modification of the second embodiment, which corresponds to FIG.

[0194] The second gate wiring 12 includes a second lower metal layer 12x and a second upper metal layer 12y. The second lower metal layer 12x is provided between the second upper metal layer 12y and the first face F1.

[0195] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are formed of a first material. The first material is a metal. The first material of the first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x is the same as the first material of the fourth lower metal layer 21x of the emitter electrode 21.

[0196] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are formed of a second material. The second material is a metal. The second material of the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y is the same as the second material of the fourth upper metal layer 21y of the emitter electrode 21.

[0197] The first material and the second material are different metals. The first material includes, for example, tungsten (W), molybdenum (Mo), or tantalum (Ta). The second material includes, for example, aluminum (Al) or copper (Cu).

[0198] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are, for example, stacked films of titanium, titanium nitride, and tungsten.

[0199] The first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y are, for example, stacked films of titanium, titanium nitride, and aluminum.

[0200] The first lower metal layer 11x, the second lower metal layer 12x, and the third lower metal layer 13x are electrically and physically connected to the first upper metal layer 11y, the second upper metal layer 12y, and the third upper metal layer 13y, respectively.

[0201] Each of the first gate wiring 11, the second gate wiring 12, and the third gate wiring 13 has a laminated structure of two different metal layers.

[0202] As shown in Figure 19, the first distance in the first direction (d1 in Figure 19) between the first upper metal layer 11y of the first portion 11a of the first gate wiring and the third upper metal layer 13y of the fifth portion 13a of the third gate wiring is smaller than the first width in the first direction (w1 in Figure 19) of the second lower metal layer 12x of the third portion 12a of the second gate wiring.

[0203] 19, the first upper metal layer 11y of the first portion 11a of the first gate wiring and the second lower metal layer 12x of the third portion 12a of the second gate wiring overlap in the third direction. Also, the third upper metal layer 13y of the fifth portion 13a of the third gate wiring and the second lower metal layer 12x of the third portion 12a of the second gate wiring overlap in the third direction.

[0204] 19, the first width w1 in the first direction of the second lower metal layer 12x of the third portion 12a of the second gate wiring is wider than the second width (w2 in FIG. 19) in the first direction of the first lower metal layer 11x of the first portion 11a of the first gate wiring. Also, the first width w1 is wider than the third width (w3 in FIG. 19) in the first direction of the third lower metal layer 13x of the fifth portion 13a of the third gate wiring.

[0205] 19, the fourth width in the first direction (w4 in FIG. 19) of the first upper metal layer 11y of the first portion 11a of the first gate wiring is wider than the second width in the first direction w2 of the first lower metal layer 11x of the first portion 11a. Also, the fifth width in the first direction (w5 in FIG. 19) of the third upper metal layer 13y of the fifth portion 13a of the third gate wiring is wider than the third width in the first direction w3 of the third lower metal layer 13x of the fifth portion 13a.

[0206] According to the IGBT of the second modified example of the second embodiment, the electrical resistance of the gate wiring can be reduced, similarly to the IGBT 200 of the second embodiment. In particular, by forming the second gate wiring into a stacked structure, the electrical resistance of the second gate wiring can be reduced.

[0207] As described above, according to the second embodiment and the modified example, a semiconductor device capable of reducing the electrical resistance of the gate wiring can be provided.

[0208] In the first and second embodiments, an IGBT having three independently controllable gates has been described as an example. However, the IGBT may also be configured to have two independently controllable gates. In this case, the number of gate wirings is two. In this case, for example, the third gate wiring is removed from the semiconductor device of the first embodiment. The IGBT may also be configured to have four or more independently controllable gates. In this case, the number of gate wirings is four or more. In this case, for example, the fourth gate wiring is provided outside the third gate wiring in the semiconductor device of the first embodiment.

[0209] In the first or second embodiment, the arrangement order of each trench and the ratio of the number of each trench are arbitrary and are not necessarily limited to the arrangement order and ratio of the number of each trench in the first or second embodiment.

[0210] The semiconductor device may be provided with a trench in which the conductive layer in the trench is not electrically connected to the gate wiring, or may be provided with a trench in which the conductive layer in the trench is electrically connected to the emitter electrode, for example.

[0211] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0212] 10 Semiconductor layer 11 First gate wiring 11a First Section 11b Second Part 11c Seventh Section 11x 1st bottom metal layer 11y First top metal layer 12 Second gate wiring 12a Third Section 12b Fourth Section 12c Eighth Section 12x second bottom metal layer 12y Second top metal layer 13 Third gate wiring 13a Fifth Section 13b Sixth Section 13c Ninth Section 13x 3rd bottom metal layer 13y Third top metal layer 21 Emitter electrode (first electrode) 21x 4th bottom metal layer 21y 4th top metal layer 22 Collector electrode (second electrode) 31 first gate electrode 32 second gate electrode 33 Third gate electrode 37 Second interlayer insulating layer (insulating layer) 41 First gate trench (first trench) 42 Second gate trench (second trench) 43 Third gate trench (third trench) 100 IGBT (semiconductor device) 101 first gate electrode pad 102 second gate electrode pad 103 Third gate electrode pad 200 IGBT (semiconductor device) F1 First Side F2 Second side J1 First Intersection J2 Second Intersection J3 Third Intersection d1 First distance w1 First width w2 Second width w3 Third width w4 Fourth width w5 Fifth width

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including: a plurality of first trenches provided on the first surface side and extending in a first direction parallel to the first surface; and a plurality of second trenches provided on the first surface side and extending in the first direction; a first electrode provided on the first surface side of the semiconductor layer; a second electrode provided on the second surface side of the semiconductor layer; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a first gate wiring provided on the first surface side of the semiconductor layer, the first gate wiring including a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, the first gate wiring including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided between the first portion; a second gate wiring provided on the first surface side of the semiconductor layer, including a second upper metal layer and a second lower metal layer provided between the second upper metal layer and the first surface, including a third portion extending in the second direction and a fourth portion extending in the second direction and having the first electrode provided between the third portion, and electrically connected to the second gate electrode; a first gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate wiring; a second gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate wiring; Equipped with the first portion is provided between the third portion and the first electrode; the second portion is provided between the fourth portion and the first electrode; The first gate wiring and the second gate wiring intersect at a first intersection, and at the first intersection, the first lower metal layer and the second upper metal layer are absent, or The semiconductor device is free of the first upper metal layer and the second lower metal layer.

2. the first portion is connected to the first gate electrode at a portion where the first portion intersects with the first trench; the second portion is connected to the first gate electrode at a portion where the second portion intersects with the first trench; the third portion is connected to the second gate electrode at a portion where the third portion intersects with the second trench; 2. The semiconductor device according to claim 1, wherein said fourth portion is connected to said second gate electrode at a portion where said fourth portion intersects with said second trench.

3. the first gate wiring surrounds the first electrode; 2. The semiconductor device according to claim 1, wherein said second gate wiring surrounds said first electrode.

4. the first lower metal layer surrounds the first electrode; 2. The semiconductor device according to claim 1, wherein said second lower metal layer surrounds said first electrode.

5. the semiconductor layer further includes a plurality of third trenches provided on the first surface side and extending in the first direction; a third gate electrode disposed in the third trench; a third gate wiring provided on the first surface side of the semiconductor layer, including a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, including a fifth portion extending in the second direction and a sixth portion extending in the second direction and having the first electrode provided between the fifth portion, and electrically connected to the third gate electrode; a third gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate wiring; Further provided with The first gate wiring and the third gate wiring intersect at a second intersection, and at the second intersection, the first lower metal layer and the third upper metal layer are absent, or 2. The semiconductor device of claim 1, wherein said first upper metal layer and said third lower metal layer are absent.

6. the fifth portion is connected to the third gate electrode at a portion where the fifth portion intersects with the third trench; 6. The semiconductor device according to claim 5, wherein said sixth portion is connected to said third gate electrode at a portion where said sixth portion intersects with said third trench.

7. The second gate wiring and the third gate wiring intersect at a third intersection, and at the third intersection, the second lower metal layer and the third upper metal layer are absent, or 6. The semiconductor device according to claim 5, wherein said second upper metal layer and said third lower metal layer are absent.

8. the first lower metal layer and the second lower metal layer comprise tungsten; 2. The semiconductor device of claim 1, wherein said first upper metal layer and said second upper metal layer comprise aluminum.

9. 2. The semiconductor device according to claim 1, wherein an insulating layer is provided between said first gate wiring and said second gate wiring at said first intersection.

10. the first electrode includes a fourth upper metal layer and a fourth lower metal layer provided between the fourth upper metal layer and the first surface; the fourth lower metal layer, the first lower metal layer, and the second lower metal layer are made of the same material; 2. The semiconductor device according to claim 1, wherein said fourth upper metal layer, said first upper metal layer and said second upper metal layer are made of the same material.

11. a first surface and a second surface opposite to the first surface, the first surface including a plurality of first trenches provided on the first surface side and extending in a first direction parallel to the first surface, a plurality of second trenches provided on the first surface side and extending in the first direction, and a plurality of third trenches provided on the first surface side and extending in the first direction; a semiconductor layer comprising: a first electrode provided on the first surface side of the semiconductor layer; a second electrode provided on the second surface side of the semiconductor layer; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a third gate electrode disposed in the third trench; a first gate wiring provided on the first surface side of the semiconductor layer, the first gate wiring including a first upper metal layer and a first lower metal layer provided between the first upper metal layer and the first surface, the first gate wiring including a first portion extending in a second direction parallel to the first surface and perpendicular to the first direction, and a second portion extending in the second direction and having the first electrode provided between the first portion; a second gate wiring provided on the first surface side of the semiconductor layer, including a third portion extending in the second direction and a fourth portion extending in the second direction and having the first electrode provided between the third portion, and electrically connected to the second gate electrode; a third gate wiring provided on the first surface side of the semiconductor layer, including a third upper metal layer and a third lower metal layer provided between the third upper metal layer and the first surface, including a fifth portion extending in the second direction and a sixth portion extending in the second direction and having the first electrode provided between the fifth portion, and electrically connected to the third gate electrode; a first gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate wiring; a second gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate wiring; a third gate electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate wiring; Equipped with the first portion is provided between the third portion and the first electrode; the third portion is provided between the fifth portion and the first electrode, a first distance in the first direction between the first upper metal layer of the first portion and the third upper metal layer of the fifth portion; the width of the third portion in the first direction is smaller than the first width of the third portion.

12. The semiconductor device according to claim 11 , wherein the second gate wiring surrounds the first electrode.

13. the first width is greater than a second width in the first direction of the first lower metal layer in the first portion; 12. The semiconductor device according to claim 11, wherein the first width is greater than a third width in the first direction of the third lower metal layer in the fifth portion.

14. a fourth width in the first direction of the first upper metal layer in the first portion is wider than a second width in the first direction of the first lower metal layer in the first portion; 12. The semiconductor device according to claim 11, wherein a fifth width in the first direction of the third upper metal layer in the fifth portion is wider than a third width in the first direction of the third lower metal layer in the fifth portion.

15. the first lower metal layer and the third lower metal layer comprise tungsten; the first upper metal layer and the third upper metal layer comprise aluminum; The semiconductor device according to claim 11 , wherein the second gate wiring includes tungsten.

16. 12. The semiconductor device according to claim 11, wherein said second gate wiring further includes a second upper metal layer and a second lower metal layer provided between said second upper metal layer and said first surface.

17. the first electrode includes a fourth upper metal layer and a fourth lower metal layer provided between the fourth upper metal layer and the first surface; the fourth lower metal layer, the first lower metal layer, and the third lower metal layer are made of the same material; 12. The semiconductor device according to claim 11, wherein the fourth upper metal layer, the first upper metal layer, and the third upper metal layer are made of the same material.

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