Semiconductor device

Abstract

To provide a semiconductor device capable of further reducing on-resistance.SOLUTION: A semiconductor device includes a gate electrode, a contact region of a first conductivity type, and a drift layer having a super-junction structure. The drift layer has a first stripe pattern in which a first column layer of the first conductivity type and a second column layer of a second conductivity type extending in a first direction are alternately arranged in a second direction. The gate electrode has a second stripe pattern in which a plurality of trench gates extending in the second direction are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect each other in a plan view. When a repetition period of the first column layer or the second column layer is a first period and that of the trench gate is a second period, the second period is shorter than the first period. The contact region has higher concentration of the first conductivity type than the first column layer and a larger width in the second direction than the first column layer.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A super-junction semiconductor element is known that has a parallel pn junction layer configured by alternately and repeatedly joining a plurality of drift layers made of a first conductivity type semiconductor extending from a first main surface side toward a second main surface side of a semiconductor substrate and a plurality of partition regions made of a second conductivity type semiconductor extending in the same manner as the drift layers in a direction intersecting the direction in which the drift layers extend, and that allows a current to flow through the parallel pn junction layer when it is in an on state and is depleted when it is in an off state (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-76339 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices having a super junction (hereinafter also referred to as SJ) structure, further reduction in on-resistance is desired.

[0005] The present disclosure has been made in light of the above-mentioned problems, and has an object to provide a semiconductor device that can further reduce the on-resistance. [Means for solving the problem]

[0006] To solve the above problems, a semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer, a gate electrode provided on a first surface side of the semiconductor layer, a first conductivity type contact region provided in the semiconductor layer, and a drift layer with a super-junction structure provided in the semiconductor layer. The drift layer includes a plurality of first column layers of a first conductivity type extending in a first direction and a plurality of second column layers of a second conductivity type extending in the first direction, and has a first stripe pattern in which the first column layers and the second column layers are alternately arranged in a second direction intersecting the first direction. The gate electrode includes a plurality of trench gates extending in the second direction and has a second stripe pattern in which the plurality of trench gates are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect in a plan view. A first period is a period in which the first column layers or the second column layers are repeated in the second direction in the first stripe pattern, and a second period is a period in which the trench gates are repeated in the first direction in the second stripe pattern. The second period is shorter than the first period. The contact region has a higher concentration of the first conductivity type than the first column layer and is wider in the second direction than the first column layer.

[0007] A semiconductor device according to another aspect of the present disclosure includes a semiconductor layer, a gate electrode provided on a first surface side of the semiconductor layer, a first conductivity type contact region provided in the semiconductor layer, and a drift layer with a super-junction structure provided in the semiconductor layer. The drift layer includes a plurality of first column layers of a first conductivity type extending in a first direction and a plurality of second column layers of a second conductivity type extending in the first direction, and has a first stripe pattern in which the first column layers and the second column layers are alternately arranged in a second direction intersecting the first direction. The gate electrode includes a plurality of trench gates extending in the second direction and has a second stripe pattern in which the plurality of trench gates are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect in a plan view. A first period is a period in which the first column layers or the second column layers are repeated in the second direction in the first stripe pattern, and a second period is a period in which the trench gates are repeated in the first direction in the second stripe pattern. The second period is shorter than the first period. The contact region has a higher concentration of the first conductivity type than the first column layer. The drift layer further includes a third column layer provided in the semiconductor layer and located below the contact region. The conductivity type of the third column layer is the first conductivity type with a lower concentration than the first column layer, or the second conductivity type with a lower concentration than the second column layer. The third column layer extends in the first direction and is wider in the second direction than the first column layer. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a semiconductor device that can further reduce the on-resistance. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a configuration example of an insulated gate semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 3]FIG. 3 is a plan view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a perspective view illustrating a configuration example of an insulated gate semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to a modified example of the first embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view showing a configuration example of an insulated gate semiconductor device according to a modified example of the first embodiment of the present disclosure. [Figure 11] FIG. 11 is a plan view illustrating a configuration example of an insulated gate semiconductor device according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a cross-sectional view illustrating a configuration example of an insulated gate semiconductor device according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a cross-sectional view illustrating a configuration example of an insulated gate semiconductor device according to the second embodiment of the present disclosure. [Figure 14] FIG. 14 is a graph showing the results of an experiment conducted by the present inventors, illustrating the relationship between trench pitch and on-resistance RonA. [Figure 15] FIG. 15 is a graph created based on the graph of FIG. 14, and shows the relationship between the trench pitch and the reduction rate of RonA from non-SJ. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of the present disclosure will be described below. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device or component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0011] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0012] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and Y-axis direction are directions parallel to the surface 10a of the GaN layer 10. The Z-axis direction is the normal direction to the surface 10a of the GaN layer 10 and is also the thickness direction of the GaN layer 10. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0013] In the following description, a plan view means a view from the normal direction of the surface 10a of the GaN layer 10 (for example, the Z-axis direction).

[0014] In the following explanation, an example will be given in which the first conductivity type is P type and the second conductivity type is N type. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being N type and the second conductivity type being P type. Furthermore, + or - attached to P or N means that the semiconductor region has a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without + or - attached. However, even if semiconductor regions are attached with the same P and P (or the same N and N), this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0015] <Embodiment 1> (Configuration example of an insulated gate semiconductor device) 1 to 3 are plan views showing a configuration example of an insulated gate semiconductor device 1 (an example of a "semiconductor device" of the present disclosure) according to a first embodiment of the present disclosure. FIG. 2 is a view in which the gate electrode GE is removed from the plan view shown in FIG. 1. FIG. 3 is a view in which the source region 13 and the source lead region 131 are removed from the plan view shown in FIG. 2. FIGS. 4 to 7 are cross-sectional views showing a configuration example of an insulated gate semiconductor device 1 according to a first embodiment of the present disclosure. FIG. 4 shows a cross section taken along line A1-A1' in the plan view shown in FIG. 1. FIG. 5 shows a cross section taken along line B1-B1' in the plan view shown in FIG. 1. FIG. 6 shows a cross section taken along line C1-C1' in the plan view shown in FIG. 1. FIG. 7 shows a cross section taken along line D1-D1' in the plan view shown in FIG. 1.

[0016] 8 is a perspective view showing a configuration example of an insulated gate semiconductor device 1 according to the first embodiment of the present disclosure. In Fig. 8, the gate insulating film 21, the gate electrode GE, the insulating film 41, and the source electrode SE are omitted in order to clearly show the configurations of the P-type first column layer CL1, the N-type second column layer CL2, the well region 12, the source region 13, and the source lead region 131 shown in Figs. 1 to 7.

[0017] 1 to 3 illustrate an example in which the number of first column layers CL1 present in a region sandwiched between the P+ type contact regions 14 in a plan view (hereinafter also referred to as an active region) is three. Also, FIG. 8 illustrates an example in which the number of first column layers CL1 present in one active region is four.

[0018] 1 to 8, insulated gate semiconductor device 1 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate structure. For example, insulated gate semiconductor device 1 includes an N+ type gallium nitride substrate (hereinafter referred to as GaN substrate) 2 and an N-type gallium nitride layer 10 (hereinafter referred to as GaN layer 10; an example of a "semiconductor layer" in the present disclosure) provided on a surface 2a of GaN substrate 2. GaN layer 10 includes a drift layer 11 with a superjunction structure (i.e., SJ structure), a P-type well region 12, an N+ type source region 13, an N+ type source lead region 131, and a P+ type contact region 14.

[0019] Insulated gate semiconductor device 1 also includes a plurality of trenches H provided in GaN layer 10, gate insulating films 21 provided in trenches H, a gate electrode GE provided on front surface 10a (an example of the "first surface" of the present disclosure) of GaN layer 10, a source electrode SE provided on front surface 10a of GaN layer 10, and an insulating film 41 provided on front surface 10a of GaN layer 10 and positioned between gate electrode GE and source electrode SE. Insulated gate semiconductor device 1 also includes a drain electrode DE provided on back surface 2b of GaN substrate 2. Each component of insulated gate semiconductor device 1 will be described in detail below.

[0020] The GaN substrate 2 is a GaN single crystal substrate. The GaN substrate 2 is an N-type substrate, for example, an N+ type substrate. The N-type impurities contained in the GaN substrate 2 are one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium). For example, the N-type impurities contained in the GaN substrate 2 are Si or O, and the impurity concentration of Si or O in the GaN substrate 2 is 2×10 18cm -3 That's all.

[0021] The GaN substrate 2 may be a low-dislocation freestanding substrate with a dislocation density of less than 1×107 cm-2. When the GaN substrate 2 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 10 formed on the GaN substrate 2 is also low. Furthermore, by using a low-dislocation substrate for the GaN substrate 2, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 2. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during heat treatment.

[0022] The GaN layer 10 is provided on the surface 2a of the GaN substrate 2. The GaN layer 10 is a GaN single crystal layer that is epitaxially formed on the surface of the GaN substrate 2. The GaN layer 10 is formed by doping with N-type impurities during the epitaxial growth process.

[0023] The drift layer 11 of the SJ structure includes a plurality of P-type first column layers CL1 extending in the Y-axis direction and a plurality of N-type second column layers CL2 extending in the Y-axis direction. The first column layers CL1 and the second column layers CL2 are arranged alternately in the X-axis direction in a first stripe pattern SP1 (for example, a vertical stripe pattern in FIG. 1).

[0024] The first column layer CL1 has the same or almost the same P-type impurity concentration as the well region 12. The second column layer CL2 has a lower N-type impurity concentration than the source region 13. The first column layer CL1 and the second column layer CL2 are located below the well region 12 and are in contact with the well region 12. The second column layer CL2 functions as a current path between the GaN substrate 2 and the well region 12.

[0025] As shown in FIGS. 6 to 8, the drift layer 11 of the SJ structure is provided on the gallium nitride layer 10 and has a P- type third column layer CL3 located below the P+ type contact region 14. The third column layer CL3 also extends in the Y-axis direction and is arranged parallel to the first stripe SP1 of the SJ structure. The third column layer CL3 has a lower P-type impurity concentration than the first column layer CL1. The third column layer CL3 is also wider in the X-axis direction than the first column layer CL1. If the width of the first column layer CL1 in the X-axis direction is WCL1 and the width of the third column layer CL3 in the X-axis direction is WCL3, then WCL1 <WCL3である。

[0026] Well region 12 is formed by doping with P-type impurities during the epitaxial growth process that forms GaN layer 10. Alternatively, well region 12 may be formed by ion-implanting P-type impurities to a predetermined depth from surface 10a of GaN layer 10, followed by heat treatment. The P-type impurity is, for example, Mg. A channel of the vertical MOSFET is formed in well region 12 at a portion that contacts gate insulating film 21 and in the vicinity thereof.

[0027] In the insulated gate semiconductor device 1, a channel and a source region 13 adjacent to the channel are repeatedly arranged at regular intervals in one direction (e.g., the Y-axis direction). In the embodiment of the present disclosure, a unit structure of the channel and source region 13 repeatedly arranged at regular intervals in the Y-axis direction is referred to as a channel cell CS.

[0028] The channel cell CS is provided in the GaN layer 10 and has a P-type well region 12 and an N+-type source region 13 in contact with the well region 12. The channel cells CS each extend in the X-axis direction. The channel cells CS are also arranged side by side at regular intervals in the Y-axis direction, which is the direction of the channel width of the vertical MOSFET. The channel cell CS is located between one trench gate 31 and the other trench gate 31 adjacent to each other in the Y-axis direction, i.e., between one trench H and the other trench H adjacent to each other in the Y-axis direction.

[0029] The trenches H are recesses formed by etching the GaN substrate 10 from the front surface 10a side. The channel cells CS are protruding semiconductor portions, or mesa portions, sandwiched between the trenches H. The width WCS of the channel cells CS (i.e., the mesa portion) in the Y-axis direction is, for example, not less than 20 nm and not more than 1 μm.

[0030] The source region 13 and the source leading region 131 are provided on and in the vicinity of the surface 10a of the GaN layer 10. The source region 13 and the source leading region 131 are formed by ion-implanting N-type impurities to a predetermined depth from the surface 10a of the GaN layer 10 and performing heat treatment. The source region 13 and the source leading region 131 are located on the well region 12 and are in contact with the well region 12.

[0031] The source region 13 extends in the X-axis direction. The source lead-out region 131 extends in the Y-axis direction. The end of the source region 13 in the X-axis direction is connected to the source lead-out region 131. The source region 13 overlaps with the gate electrode GE in a planar view. The source lead-out region 131 does not overlap with the gate electrode GE in a planar view.

[0032] The P+ type contact region 14 is provided on and near the surface 10a of the GaN layer 10. The contact region 14 is formed by ion-implanting P-type impurities to a predetermined depth from the surface 10a of the GaN layer 10 and performing heat treatment. The contact region 14 has a higher P-type concentration (i.e., a value obtained by offsetting the N-type impurity concentration from the P-type impurity concentration) than the P-type well region 12 that constitutes the channel cell CS. Similarly, the contact region 14 has a higher P-type impurity concentration than the P-type first column layer CL1.

[0033] In the insulated gate semiconductor device 1, one channel cell CS group arranged in the Y-axis direction and another channel cell CS group arranged in the Y-axis direction are adjacent to each other in the X-axis direction. The contact region 14 is located between one channel cell CS group and another channel cell CS group adjacent to each other in the X-axis direction. The contact region 14 extends in the Y-axis direction and is arranged in parallel with the first stripe SP1 of the SJ structure.

[0034] The contact region 14 is in contact with the well region 12 and the source extraction region 131 of one channel cell CS group and the well region 12 and the source extraction region 131 of another channel cell CS group, respectively. Also, the depth from the surface 10a side of the contact region 14 is deeper than the depth from the surface 10a side of the well region 12. Thereby, the contact region 14 is also in contact with the P-type third column layer CL3 constituting the drift layer 11 of the SJ structure.

[0035] As shown in FIGS. 6 and 7, when the width of the contact region 14 in the X-axis direction is W14, the width W14 of the contact region 14 is narrower than the width WCL3 of the third column layer CL3. W14 < WCL3. Thereby, the contact region 14 is in contact only with the P-type third column layer CL3 without contacting the N-type second column layer CL2 in the drift layer 11 of the SJ structure. As shown in FIG. 8, the contact region 14 is also connected to the P-type first column layer CL1 through the P-type well region 12.

[0036] The contact region 14 and the source extraction region 131 are in contact with the source electrode SE at the source contact region CA. The source contact region CA is provided at a position away from the columns of a plurality of channel cells CS arranged in the Y-axis direction. For example, the source contact region CA is located between one channel cell CS group and another channel cell CS group adjacent to each other in the X-axis direction. The source contact region CA is provided with contact holes having the contact region 14 and the source extraction region 131 as the bottom surfaces. Through this contact hole, the source electrode SE is in contact with the contact region 14 and the source extraction region 131.

[0037] The width WCA of the source contact region CA in the X-axis direction is, for example, 1 μm or more and 5 μm or less, and the arrangement interval PCA of the source contact regions CA in the X-axis direction is, for example, 2 μm or more and 10 μm or less.

[0038] The trenches H extend in the X-axis direction and are arranged side by side at regular intervals in the Y-axis direction. The trenches H open to the surface 10a side of the GaN layer 10. The trenches H are located between the channel cells CS. For example, the trenches H are arranged between two channel cells CS adjacent to each other in the Y-axis direction. That is, the trenches H are arranged so as to sandwich the channel cell CS from both sides in the Y-axis direction. The width WH of the trenches H in the Y-axis direction is, for example, 0.1 μm or more and 1 μm or less.

[0039] The gate insulating film 21 is provided on the side surface of the trench H. The gate insulating film 21 is, for example, a silicon oxide film (SiO2 film) or an aluminum oxide (Al2O3) film. The insulating film 22 is provided on the bottom surface of the trench H. The insulating film 22 is, for example, a SiO2 film or an Al2O3 film. The gate insulating film 21 and the insulating film 22 are in contact with each other inside the trench H. For example, the insulating film 22 is thicker than the gate insulating film 21.

[0040] The gate electrode GE has an electrode portion (hereinafter referred to as a trench gate) 31 disposed in the trench H via a gate insulating film 21 or an insulating film 22, and a wiring portion 32 extending in the Y-axis direction so as to straddle a plurality of channel cells CS. Like the trenches H, a plurality of trench gates 31 are also provided, each extending in the X-axis direction. The trench gates 31 and the wiring portion 32 are connected to each other. The trench gates 31 are adjacent to the channel cells CS via the gate insulating film 21. The gate electrode GE is made of polysilicon doped with impurities. An insulating film 41 is provided on the gate electrode GE. The insulating film 41 is, for example, a SiO2 film or an Al2O3 film.

[0041] As shown in FIG. 1, a second stripe pattern SP2 is formed in which multiple trench gates 31 are arranged in the Y-axis direction. The first stripe pattern SP1 and the second stripe pattern SP2 intersect in a plan view. If the repetition period of the first column layer CL1 or the second column layer CL2 in the X-axis direction of the first stripe pattern SP1 is defined as a super junction period PSJ (an example of the "first period" in the present disclosure), and the repetition period of the trench gates 31 in the Y-axis direction of the second stripe pattern SP2 is defined as a trench gate period P31 (an example of the "second period" in the present disclosure), the trench gate period P31 is shorter than the super junction period PSJ. P31 <PSJとなっている。

[0042] The source electrode SE is provided on the insulating film 41. The source electrode SE is in contact with the source lead region 131 and the contact region 14 through a contact hole provided in the insulating film 41. As a result, the on-current of the vertical MOSFET flows through the source region 13 and the source lead region 131 to the source electrode SE. In addition, the potential of the well region 12 is fixed to the potential of the source electrode SE via the contact region 14.

[0043] The source electrode SE is made of Al or an Al-Si alloy. The source electrode 53 may have a barrier metal layer between it and the surface 10a of the GaN layer 10. For example, the barrier metal layer disposed between the source electrode SE and the N+ type source extraction region 131 may be made of titanium (Ti). The barrier metal layer disposed between the source electrode SE and the P+ type contact region 14 may be made of nickel (Ni) or a laminated film of Ni / gold (Au). In this way, barrier metals made of different materials may be used for the P+ type region and the N+ type region.

[0044] That is, the source electrode 53 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al-Si alloy layer, on the N+ type region. The source electrode 53 may be a laminate of a Ni layer and an Al layer, or a laminate of a Ni layer and an Al-Si alloy layer, on the P+ type region. Alternatively, the source electrode 53 may be a laminate of a Ni / Au and Al layer, or a laminate of a Ni / Au and an Al-Si alloy layer, on the P+ type region. The source electrode SE may also serve as a source pad (not shown), or may be an electrode provided separately from the source pad.

[0045] (Effects of the First Embodiment) As described above, the insulated gate semiconductor device 1 according to the first embodiment of the present disclosure includes a GaN layer 10, a gate electrode GE provided on the first surface side of the GaN layer 10, a P-type contact region 14 provided in the GaN layer 10, and a drift layer 11 with an SJ structure provided in the GaN layer 10. The drift layer 11 includes a plurality of P-type first column layers CL1 extending in the Y-axis direction and a plurality of N-type second column layers CL2 extending in the Y-axis direction, and has a first stripe pattern SP1 in which the first column layers CL1 and the second column layers CL2 are alternately arranged in the X-axis direction intersecting the Y-axis direction. The gate electrode GE includes a plurality of trench gates 31 extending in the X-axis direction and has a second stripe pattern SP2 in which the plurality of trench gates 31 are arranged in the Y-axis direction. The first stripe pattern SP1 and the second stripe pattern SP2 intersect in a plan view. If the repeating period of the first column layer CL1 or the second column layer CL2 in the X-axis direction of the first stripe pattern SP1 is defined as a super junction period PSJ, and the repeating period of the trench gates 31 in the Y-axis direction of the second stripe pattern SP2 is defined as a trench gate period P31, the trench gate period P31 is shorter than the super junction period PSJ. The contact region 14 has a higher P-type concentration than the first column layer CL1 and is wider in the X-axis direction than the first column layer CL1.

[0046] According to this, since the insulated gate semiconductor device 1 includes the drift layer 11 of the SJ structure, it is possible to increase the impurity concentration of the drift layer 11 while suppressing the reduction of the breakdown voltage, and it is possible to reduce the on-resistance of the vertical MOSFET. Further, the extending direction of the first stripe pattern SP1 in which the first column layer CL1 and the second column layer CL2 are alternately arranged intersects with the extending direction of the second stripe pattern SP2 in which the plurality of trench gates 31 are arranged. Thereby, the pitch of the first stripe pattern SP1 (superjunction period PSJ) and the pitch of the second stripe pattern SP2 (trench gate period P31) can be set independently of each other.

[0047] In the insulated gate semiconductor device 1, the trench gate period P31 is set to a narrower pitch than the superjunction period PSJ (P31 < PSJ). Thereby, the channel width of the vertical MOSFET can be increased, and the on-resistance of the vertical MOSFET can be further reduced. In a vertical MOSFET in which the drift layer is made of a low-resistance material such as GaN, since the proportion of the channel resistance in the resistance of the element is relatively large, the expansion of the channel width is particularly effective in reducing the on-resistance.

[0048] The contact region 14 has a higher P-type concentration than the first column layer CL1 and a wider width in the X-axis direction than the first column layer CL1. Thereby, the junction area between the contact region 14 and the source electrode SE can be widened, so that the resistance of the junction between the contact region 14 and the source electrode SE (that is, the source contact) can be reduced.

[0049] The drift layer 11 is provided in the GaN layer 10 and further has a third column layer CL3 located under the contact region 14. The conductivity type of the third column layer CL3 is a P-type with a lower concentration than the first column layer CL1. The third column layer CL3 extends in the Y-axis direction and has a wider width in the X-axis direction than the first column layer CL1. <\

[0050] This makes it possible to reduce the junction capacitance formed in the contact region 14 compared to when the second column layer CL2 is disposed below the contact region 14. Furthermore, when a drain voltage is applied, the depletion layer can be extended widely from the PN junction interface between the second column layer CL2 and the third column layer CL3 toward the third column layer CL3 side, thereby suppressing a decrease in the breakdown voltage of the insulated gate semiconductor device 1.

[0051] The contact region 14 extends in the Y-axis direction and is provided near the end of the trench gate 31 in the X-axis direction. This eliminates the need for source contacts above the channel cells CS or between adjacent channel cells CS in the Y-axis direction, allowing the arrangement interval PCS (see FIG. 5) of the channel cells CS in the Y-axis direction to be narrowed. This is advantageous for narrowing the trench gate period P31.

[0052] Furthermore, since there is no need to make source contacts above the channel cell CS or between adjacent channel cells CS in the Y-axis direction, even if the placement interval PCS of the channel cells CS in the Y-axis direction is narrowed, short-circuit defects between the gate and source do not occur. This makes it possible to suppress yield reductions due to the fabrication process even when miniaturization is achieved. The SJ structure and the fine trench MOS structure can be fabricated simultaneously.

[0053] (Modification of the first embodiment) In the above-described first embodiment, the third column layer CL3 is described as being of P-type. However, in the first embodiment of the present disclosure, the conductivity type of the third column layer CL3 is not limited to P-type. The conductivity type of the third column layer CL3 may be N-type, which has a lower concentration than the N-type second column layer CL2.

[0054] 9 and 10 are cross-sectional views showing an example configuration of an insulated gate semiconductor device 1A (an example of a "semiconductor device" of the present disclosure) according to a modification of the first embodiment of the present disclosure. FIG. 9 corresponds to a cross section taken along line A1-A1' in the plan view shown in FIG. 1. FIG. 10 corresponds to a cross section taken along line B1-B1' in the plan view shown in FIG. 1.

[0055] As shown in FIGS. 9 and 10, an insulated gate semiconductor device 1A according to a modification of the first embodiment includes an N-type third column layer CL3 having a lower concentration than the N-type second column layer CL2, instead of the P-type third column layer CL3 shown in FIGS. 6 and 7.

[0056] Even in this embodiment, the same effects as those of the above-described embodiment 1 can be achieved. Furthermore, by replacing the third column layer CL3 from P-type to N-type, there is no longer at least one P-type region having a concentration different from that of other regions, which may reduce the number of manufacturing steps and the manufacturing cost.

[0057] <Embodiment 2> FIG. 11 is a plan view showing a configuration example of an insulated gate semiconductor device 1B (an example of a "semiconductor device" of the present disclosure) according to a second embodiment of the present disclosure. FIGS. 12 and 13 are cross-sectional views showing a configuration example of an insulated gate semiconductor device 1B according to the second embodiment of the present disclosure. FIG. 12 shows a cross section taken along line A2-A2' in the plan view shown in FIG. 11. FIG. 13 shows a cross section taken along line B2-B2' in the plan view shown in FIG. 1.

[0058] As shown in FIGS. 11 to 13, the insulated gate semiconductor device 1B according to the second embodiment further includes a P+ type heavily doped layer 16 provided in the GaN layer 10 and having a higher P-type concentration than the P-type first column layer CL1.

[0059] 11, the P+ type high-concentration layer 16 is connected to the P+ type contact region 14. Furthermore, as shown in Figures 12 and 13, the P+ type high-concentration layer 16 is connected to the P type first column layer CL1 and the N type second column layer CL2, respectively. The presence of the P+ type high-concentration layer 16 reduces the resistance of the entire P type layer in the drift layer 11.

[0060] The P+ type high concentration layer 16 is located between one trench gate 31 and the other trench gate 31 adjacent to each other in the Y-axis direction. As shown in Figures 12 and 13, the P+ type high concentration layer 16 extends from a position between the trench gates 31 to below the trench gate 31 via the first column layer CL1 or the second column layer CL2. As shown in Figure 13, the width (i.e., the width of the current path) of the N type second column layer CL2, which functions as a current path between the GaN substrate 2 and the well region 12, is narrowed by the P+ type high concentration layer 16 extending to below the trench gate 31.

[0061] Other than this, the configuration of insulated gate semiconductor device 1B is the same as that of insulated gate semiconductor device 1 according to embodiment 1. As a result, insulated gate semiconductor device 1B according to embodiment 2 achieves the same effects as those of embodiment 1 described above.

[0062] Furthermore, the insulated gate semiconductor device 1B can improve short-circuit resistance. If the channel of a vertical MOSFET is formed finely, the current during a short circuit becomes excessive, resulting in a large short-circuit current and a decrease in short-circuit resistance. However, as shown in Figures 11 to 13, by providing a P+ type heavily doped layer 16 (i.e., a buried JFET structure), the short-circuit current can be kept low, and short-circuit resistance can be ensured.

[0063] (Experiment and results) The present inventors conducted an experiment to investigate the relationship between the ratio of the trench pitch to the SJ pitch and the on-resistance RonA.

[0064] 14 is a graph showing the relationship between the trench gate period (hereinafter also referred to as trench pitch) and on-resistance RonA, based on the results of an experiment conducted by the present inventors. In Fig. 14, the horizontal axis represents trench pitch (μm) and the vertical axis represents on-resistance RonA.

[0065] In the graph of FIG. 14, SJ is an insulated gate semiconductor device having a drift layer 11 with an SJ structure as shown in FIGS. 6 to 8. NonS-SJ is an insulated gate semiconductor device having a drift region composed only of an N-type region without an SJ structure. The structural difference between SJ and NonS-SJ is only the presence or absence of the SJ structure, and the others are the same. Each data of SJ and NonS-SJ shown in FIG. 14 is data with a drain-source voltage of 1400V and a mobility of 75 cm 2 / Vs. Also, the superjunction period of SJ (hereinafter also referred to as SJ pitch) was set to 2 μm.

[0066] Regarding SJ in FIG. 14, when the trench pitch is 2 μm, the trench pitch = SJ pitch. Also, when the trench pitch is less than 2 μm, the trench pitch < SJ pitch. In SJ of FIG. 14, the range where the trench pitch is less than 2 μm is an embodiment of the present disclosure.

[0067] As can be seen by comparing SJ and NonS-SJ in FIG. 14, it was confirmed that the on-resistance RonA can be reduced by having a drift layer with an SJ structure. Also, in SJ of FIG. 14, it was confirmed that the on-resistance RonA tends to decrease as the trench pitch becomes smaller with respect to the SJ pitch.

[0068] As shown in FIG. 14, in Non-SJ, even when the trench pitch was refined to 0.1 μm or less, the on-resistance RonA could only be reduced by about half. In contrast, in SJ, by refining the trench pitch to 0.1 μm or less, the on-resistance RonA could be reduced to 1 / 5 or less. It was confirmed that SJ has a greater effect of reducing the on-resistance RonA by refining the trench pitch compared to Non-SJ.

[0069] FIG. 15 is a graph created based on the graph in FIG. 14, showing the relationship between trench pitch and the reduction rate of RonA. In FIG. 15, the horizontal axis represents trench pitch (μm), and the vertical axis represents the reduction rate (%) of on-resistance RonA from non-SJ. As shown in FIG. 15, when the trench pitch is 0.1 μm or less (i.e., the ratio of trench pitch to SJ pitch is 0.05 or less), the reduction rate of on-resistance RonA from non-SJ is approximately 20%.

[0070] From these results, it was found that the ratio of the trench pitch to the SJ pitch (i.e., the ratio of the trench gate period P31 to the superjunction period PSJ) is preferably 0.5 or less, and more preferably 0.05 or less, which can further reduce the on-resistance RonA.

[0071] <Other embodiments> As described above, the present disclosure has been described with reference to Embodiments 1 and 2. However, the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0072] For example, the semiconductor layer of the present disclosure is not limited to a GaN layer and may be a silicon carbide (SiC) layer. In a vertical MOSFET in which the drift layer is made of a low-resistance material such as SiC, the channel resistance is relatively large, so increasing the channel width is particularly effective in reducing the on-resistance. Furthermore, the semiconductor layer of the present disclosure is not limited to a GaN layer or a SiC layer and may be a Si layer.

[0073] As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described first and second embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0074] The present disclosure can also be configured as follows. (1) a semiconductor layer; a gate electrode provided on the first surface side of the semiconductor layer; a first conductivity type contact region provided in the semiconductor layer; a drift layer having a super-junction structure provided in the semiconductor layer, The drift layer is a first column layer of a first conductivity type extending in a first direction and a second column layer of a second conductivity type extending in the first direction, the first column layer and the second column layer having a first stripe pattern alternately arranged in a second direction intersecting the first direction; The gate electrode is a plurality of trench gates extending in the second direction, the plurality of trench gates having a second stripe pattern aligned in the first direction; the first stripe pattern and the second stripe pattern intersect in a plan view, a repeating period of the first column layer or the second column layer in the second direction of the first stripe pattern is defined as a first period, and a repeating period of the trench gate in the first direction of the second stripe pattern is defined as a second period, the second period being shorter than the first period; The contact region has a higher concentration of the first conductivity type than the first column layer and is wider in the second direction than the first column layer. (2) The drift layer is a third column layer provided in the semiconductor layer and positioned below the contact region; a conductivity type of the third column layer is a first conductivity type having a lower concentration than the first column layer, or a second conductivity type having a lower concentration than the second column layer; The semiconductor device according to (1), wherein the third column layer extends in the first direction and has a width in the second direction greater than that of the first column layer. (3) a semiconductor layer; a gate electrode provided on the first surface side of the semiconductor layer; a first conductivity type contact region provided in the semiconductor layer; a drift layer having a super-junction structure provided in the semiconductor layer, The drift layer is a first column layer of a first conductivity type extending in a first direction and a second column layer of a second conductivity type extending in the first direction, the first column layer and the second column layer having a first stripe pattern alternately arranged in a second direction intersecting the first direction; The gate electrode is a plurality of trench gates extending in the second direction, the plurality of trench gates having a second stripe pattern aligned in the first direction; the first stripe pattern and the second stripe pattern intersect in a plan view, a repeating period of the first column layer or the second column layer in the second direction of the first stripe pattern is defined as a first period, and a repeating period of the trench gate in the first direction of the second stripe pattern is defined as a second period, the second period being shorter than the first period; the contact region has a higher concentration of the first conductivity type than the first column layer; The drift layer is a third column layer provided in the semiconductor layer and positioned below the contact region; a conductivity type of the third column layer is a first conductivity type having a lower concentration than the first column layer, or a second conductivity type having a lower concentration than the second column layer; The third column layer extends in the first direction and has a width in the second direction greater than that of the first column layer. (4) The contact region is The semiconductor device according to any one of (1) to (3), wherein the first electrode extends in the first direction and is provided near an end of the trench gate in the second direction. (5) a first conductivity type high concentration layer provided in the semiconductor layer and having a first conductivity type concentration higher than that of the first column layer; The high concentration layer is The semiconductor device according to any one of (1) to (4), wherein the first column layer is located between one of the trench gates and the other of the trench gates adjacent to each other in the first direction, and extends from the position between the two trench gates via the first column layer to below the trench gates. (6) The semiconductor device according to (5), wherein the high concentration layer is connected to the contact region. (7) The semiconductor device according to (5) or (6), wherein the high concentration layer is connected to the first column layer. (8) a channel cell provided in the semiconductor layer and positioned between one of the trench gates and the other of the trench gates adjacent to each other in the first direction; The channel cell is The semiconductor device according to any one of (1) to (7), further comprising a well region of a first conductivity type and a source region of a second conductivity type in contact with the well region. (9) a second conductivity type source leading region provided in the semiconductor layer and leading the source region to the outside of the channel cell; The semiconductor device according to (8), wherein the source lead region is in contact with the contact region. (10) a source electrode provided on the first main surface side of the semiconductor layer, The semiconductor device according to claim 9, wherein the source electrode is in contact with the source extraction region and the contact region. (11) The semiconductor device according to any one of (1) to (10), wherein a ratio of the second period to the first period is 0.5 or less. (12) The semiconductor device according to any one of (1) to (10), wherein a ratio of the second period to the first period is 0.05 or less. (13) The semiconductor device according to any one of (1) to (12), wherein the semiconductor layer is a GaN layer or a SiC layer. [Explanation of symbols]

[0075] 1, 1A, 1B Insulated gate semiconductor device 2. GaN substrate 2a, 10a surface 2b Back side 10 GaN layers 11 Drift layer 12 well area 13 Source Region 14 Contact Area 16 High concentration layer 21 Gate insulating film 22 insulating film 31 Trench Gate 32 Wiring section 41 insulating film 53 Source electrode 131 Source Drawer Area CA Source Contact Area CL1 First column layer CL2 Second column layer CL3 Third column layer CS channel cell DE drain electrode GE gate electrode H Trench P31 Trench gate period PCA, PCS placement interval PSJ superjunction period SE source electrode SP1 First stripe pattern SP2 Second stripe pattern W14, WCA width WCL3 width

Claims

1. a semiconductor layer; a gate electrode provided on the first surface side of the semiconductor layer; a first conductivity type contact region provided in the semiconductor layer; a drift layer having a super-junction structure provided in the semiconductor layer, The drift layer is a first column layer of a first conductivity type extending in a first direction and a second column layer of a second conductivity type extending in the first direction, the first column layer and the second column layer having a first stripe pattern alternately arranged in a second direction intersecting the first direction; The gate electrode is a plurality of trench gates extending in the second direction, the plurality of trench gates having a second stripe pattern aligned in the first direction; the first stripe pattern and the second stripe pattern intersect in a plan view, a repeating period of the first column layer or the second column layer in the second direction of the first stripe pattern is defined as a first period, and a repeating period of the trench gate in the first direction of the second stripe pattern is defined as a second period, the second period being shorter than the first period; the contact region has a higher concentration of the first conductivity type than the first column layer and is wider in the second direction than the first column layer.

2. The drift layer is a third column layer provided in the semiconductor layer and positioned below the contact region; a conductivity type of the third column layer is a first conductivity type having a lower concentration than that of the first column layer, or a second conductivity type having a lower concentration than that of the second column layer, 2. The semiconductor device according to claim 1, wherein said third column layer extends in said first direction and has a width in said second direction greater than that of said first column layer.

3. a semiconductor layer; a gate electrode provided on the first surface side of the semiconductor layer; a first conductivity type contact region provided in the semiconductor layer; a drift layer having a super-junction structure provided in the semiconductor layer, The drift layer is a first column layer of a first conductivity type extending in a first direction and a second column layer of a second conductivity type extending in the first direction, the first column layer and the second column layer having a first stripe pattern alternately arranged in a second direction intersecting the first direction; The gate electrode is a plurality of trench gates extending in the second direction, the plurality of trench gates having a second stripe pattern aligned in the first direction; the first stripe pattern and the second stripe pattern intersect in a plan view, a repeating period of the first column layer or the second column layer in the second direction of the first stripe pattern is defined as a first period, and a repeating period of the trench gate in the first direction of the second stripe pattern is defined as a second period, the second period being shorter than the first period; the contact region has a higher concentration of the first conductivity type than the first column layer; The drift layer is a third column layer provided in the semiconductor layer and positioned below the contact region; a conductivity type of the third column layer is a first conductivity type having a lower concentration than that of the first column layer, or a second conductivity type having a lower concentration than that of the second column layer, the third column layer extends in the first direction and has a width in the second direction greater than that of the first column layer.

4. The contact region is 4. The semiconductor device according to claim 1, wherein the second insulating film extends in the first direction and is provided near an end of the trench gate in the second direction.

5. a high concentration layer of a first conductivity type provided in the semiconductor layer and having a higher concentration of the first conductivity type than the first column layer; The high concentration layer is 4. The semiconductor device according to claim 1, wherein the first column layer is located between one of the trench gates and the other of the trench gates adjacent to each other in the first direction, and extends from the position between the two trench gates via the first column layer to below the trench gates.

6. The semiconductor device according to claim 5 , wherein said high concentration layer is connected to said contact region.

7. 6. The semiconductor device according to claim 5, wherein said heavily doped layer is connected to said first column layer.

8. a channel cell provided in the semiconductor layer and positioned between one of the trench gates and the other of the trench gates adjacent to each other in the first direction; The channel cell is 4. The semiconductor device according to claim 1, further comprising: a well region of a first conductivity type; and a source region of a second conductivity type in contact with said well region.

9. a second conductivity type source leading region provided in the semiconductor layer and leading the source region to an outside of the channel cell; 9. The semiconductor device according to claim 8, wherein said source lead region is in contact with said contact region.

10. a source electrode provided on the first main surface side of the semiconductor layer, 10. The semiconductor device according to claim 9, wherein said source electrode is in contact with said source lead region and said contact region.

11. 4. The semiconductor device according to claim 1, wherein a ratio of the second period to the first period is 0.5 or less.

12. 4. The semiconductor device according to claim 1, wherein a ratio of the second period to the first period is 0.05 or less.

13. 4. The semiconductor device according to claim 1, wherein the semiconductor layer is a SiC layer or a GaN layer.

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