Semiconductor device

Abstract

To provide a semiconductor device whose avalanche resistance is improved.SOLUTION: A semiconductor device in an embodiment includes a semiconductor layer having a first surface and a second surface, a first gate electrode extending in a first direction parallel to the first surface on the first surface side, a second gate electrode extending in the first direction and provided in a second direction perpendicular to the first direction and parallel to the first surface with respect to the first gate electrode, a first electrode on the first surface side, and a second electrode on the second surface side. The first electrode includes a first part and a second part. The first part and the second part are provided between the first gate electrode and the second gate electrode. The first part and the second part are in contact with the semiconductor layer. The second part is provided in the first direction of the first part. The first part and the second part are held in the semiconductor layer in the second direction. A second width of the second part in the second direction is larger than a first width of the first part in the second direction, or a second depth of the second part is larger than a first depth of the first part.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An example of a power semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET), and it is desirable to improve the avalanche resistance of the MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-113710 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device with improved avalanche resistance. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a first gate electrode provided on the first surface side of the semiconductor layer and extending in a first direction parallel to the first surface; a second gate electrode provided on the first surface side of the semiconductor layer and extending in the first direction, and provided in a second direction relative to the first gate electrode that is parallel to the first surface and perpendicular to the first direction; a first gate insulating layer provided between the first gate electrode and the semiconductor layer; a second gate insulating layer provided between the second gate electrode and the semiconductor layer; a first electrode provided on the side of the first surface of the semiconductor layer and electrically connected to the third semiconductor region; and a second electrode provided on the side of the second surface of the semiconductor layer and electrically connected to the first semiconductor region, wherein the first electrode includes a first portion and a second portion, the first portion and the second portion are provided between the first gate electrode and the second gate electrode, the first portion and the second portion are in contact with the second semiconductor region, the second portion is provided in the first direction of the first portion, the first portion is sandwiched between one portion and another portion of the semiconductor layer in the second direction, the second portion is sandwiched between one portion and another portion of the semiconductor layer in the second direction, a second width of the second portion in the second direction is wider than the first width of the first portion in the second direction, or a second depth of the second portion is deeper than the first depth of the first portion. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4]FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a portion of a semiconductor device according to a comparative example. [Figure 6] FIG. 10 is a schematic top view of a part of a semiconductor device according to a comparative example. [Figure 7] FIG. 4 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 8] FIG. 3 is a schematic top view of a part of a semiconductor device according to a first modified example of the first embodiment. [Figure 9] FIG. 10 is a schematic top view of a part of a semiconductor device according to a second modified example of the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third modified example of the first embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fourth modified example of the first embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a schematic top view of a part of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 18] FIG. 10 is a schematic top view of a part of a semiconductor device according to a first modified example of the second embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment. [Figure 20] FIG. 10 is a schematic diagram of a semiconductor device according to a third embodiment. [Figure 21] FIG. 10 is a schematic top view of a part of the third embodiment. [Figure 22] FIG. 10 is a schematic top view of a part of a semiconductor device according to a third embodiment. [Figure 23] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third embodiment. [Figure 24] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third embodiment. [Figure 25] FIG. 13 is a schematic top view of a part of a semiconductor device according to a first modified example of the third embodiment. [Figure 26] FIG. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the third embodiment. [Figure 27] FIG. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the third embodiment. [Figure 28] FIG. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the third embodiment. [Figure 29] FIG. 10 is a schematic diagram of a semiconductor device according to a fourth embodiment. [Figure 30] FIG. 10 is a schematic top view of a part of the fourth embodiment. [Figure 31] FIG. 10 is a schematic top view of a part of a semiconductor device according to a fourth embodiment. [Figure 32] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fourth embodiment. [Figure 33] FIG. 13 is a schematic top view of a part of a semiconductor device according to a first modified example of the fourth embodiment. [Figure 34] FIG. 13 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0008] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of the p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of the type.

[0009] The impurity concentration of a semiconductor device can be measured by, for example, secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration of a semiconductor device can also be determined from the level of the carrier concentration determined by, for example, scanning capacitance microscopy (SCM). Distances such as the width and depth of an impurity region of a semiconductor device can be determined by, for example, SIMS. Distances such as the width and depth of an impurity region of a semiconductor device can also be determined from, for example, an SCM image.

[0010] Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor device herein can be performed by, for example, SIMS, energy dispersive X-ray spectroscopy (EDX), or Rutherford backscattering spectroscopy (RBS). Furthermore, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) can be used to measure the thickness of the components constituting the semiconductor device, the distance between the components, and the like.

[0011] (First embodiment) The semiconductor device of the first embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a first gate electrode provided on the first surface side of the semiconductor layer and extending in a first direction parallel to the first surface; The semiconductor device includes a second gate electrode extending in a first direction and provided in a second direction that is parallel to the first surface and perpendicular to the first direction relative to the first gate electrode, a first gate insulating layer provided between the first gate electrode and the semiconductor layer, a second gate insulating layer provided between the second gate electrode and the semiconductor layer, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to a third semiconductor region, and a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region. The first electrode includes a first portion and a second portion, the first portion and the second portion being provided between the first gate electrode and the second gate electrode, the first portion and the second portion being in contact with the second semiconductor region, the second portion being provided in a first direction of the first portion, the first portion being sandwiched between one part and another part of the semiconductor layer in the second direction, the second portion being sandwiched between one part and another part of the semiconductor layer in the second direction, and the second width of the second portion in the second direction being wider than the first width of the first portion in the second direction.

[0012] The semiconductor layer further includes a first trench provided on the first surface side and extending in a first direction, and a second trench provided on the first surface side and extending in the first direction, The first gate electrode is provided in the first trench, and the second gate electrode is provided in the second trench.

[0013] Moreover, the semiconductor device of the first embodiment further includes a first field plate electrode provided in the first trench and between the first gate electrode and the second surface, a second field plate electrode provided in the second trench and between the second gate electrode and the second surface, a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer, a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer, a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode, and a second inter-electrode insulating layer provided between the second gate electrode and the second field plate electrode.

[0014] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type, that is, an n-channel MOSFET in which electrons are carriers.

[0015] The semiconductor device of the first embodiment is a MOSFET 100. The MOSFET 100 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0016] In this specification, a trench is a groove-type or recessed structure that the semiconductor layer itself has, and a structure other than the semiconductor layer can be provided inside the trench. The trench is a part of the semiconductor layer.

[0017] 1(a) and 1(b) are schematic diagrams of a semiconductor device according to a first embodiment. Fig. 1(a) shows the front surface of a MOSFET 100. Fig. 1(b) shows the back surface of the MOSFET 100.

[0018] 1(a), a source electrode 10, a gate electrode pad 12, and a gate electrode wiring 12x are provided on the surface side of the MOSFET 100. The gate electrode wiring 12x is connected to the gate electrode pad 12.

[0019] As shown in FIG. 1(b), a drain electrode 20 is provided on the back surface side of the MOSFET 100.

[0020] A plurality of transistors are provided below the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 12 to control the switching operation of the transistors.

[0021] 1(a), the MOSFET 100 includes an element region 101 and a termination region 102. The termination region 102 surrounds the element region 101. In FIG. 1(a), the hatched region is the element region 101, and the outer periphery of the element region 101 is the termination region 102.

[0022] The element region 101 includes a transistor. The element region 101 includes a source region 36 of the transistor. The termination region 102 does not include a transistor. The termination region 102 does not include a source region 36.

[0023] Termination region 102 includes, for example, a termination structure for improving the breakdown voltage of MOSFET 100. The termination structure is, for example, a resurf structure or a guard ring structure.

[0024] 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line AA' in FIGS.

[0025] Fig. 3 is a schematic top view of a portion of the semiconductor device of the first embodiment. Fig. 3 is a top view of a portion corresponding to Fig. 2. Fig. 3 is a view of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 3 is a view excluding components above the first face F1.

[0026] 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line BB' in FIG.

[0027] The MOSFET 100 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a first gate electrode 40a, a second gate electrode 40b, a third gate electrode 40c, a first gate insulating layer 45a, a second gate insulating layer 45b, a third gate insulating layer 45c, a first field plate electrode 50a, a second field plate electrode 50b, a third field plate electrode 50c, a first field plate insulating layer 55a, a second field plate insulating layer 55b, a third field plate insulating layer 55c, a first inter-electrode insulating layer 60a, a second inter-electrode insulating layer 60b, a third inter-electrode insulating layer 60c, and an interlayer insulating layer 70.

[0028] Hereinafter, the first gate electrode 40a, the second gate electrode 40b, and the third gate electrode 40c may be individually or collectively referred to simply as gate electrodes 40. Furthermore, the first gate insulating layer 45a, the second gate insulating layer 45b, and the third gate insulating layer 45c may be individually or collectively referred to simply as gate insulating layers 45. Furthermore, the first field plate electrode 50a, the second field plate electrode 50b, and the third field plate electrode 50c may be individually or collectively referred to simply as field plate electrodes 50. Furthermore, the first field plate insulating layer 55a, the second field plate insulating layer 55b, and the third field plate insulating layer 55c may be individually or collectively referred to simply as field plate insulating layers 55. Furthermore, the first interelectrode insulating layer 60a, the second interelectrode insulating layer 60b, and the third interelectrode insulating layer 60c may be individually or collectively referred to simply as interelectrode insulating layer 60.

[0029] The source electrode 10 includes a first contact portion 10a (first portion), a second contact portion 10b (second portion), and a surface layer portion 10c.

[0030] The semiconductor layer 30 includes a first trench 31a, a second trench 31b, a third trench 31c, and a + shaped drain region 33, n -a p-type drift region 34 (first semiconductor region), a p-type body region 35 (second semiconductor region), and an n-type + The source region 36 (third semiconductor region) is of a crystalline form.

[0031] Hereinafter, the first trench 31a, the second trench 31b, and the third trench 31c may be referred to simply as trenches 31 individually or collectively.

[0032] The body region 35 includes a low-concentration region 35a (first region) and a high-concentration region 35b (second region).

[0033] The semiconductor layer 30 is provided between the source electrode 10 and the drain electrode 20. The semiconductor layer 30 has a first surface ("F1" in FIG. 2) and a second surface ("F2" in FIG. 2). The second surface F2 faces the first surface F1.

[0034] The first face F1 faces the source electrode 10. The second face F2 faces the drain electrode 20.

[0035] The first direction and the second direction are parallel to the first face F1. The second direction is perpendicular to the first direction. The third direction is perpendicular to the first face F1. The third direction is perpendicular to the first direction and the second direction.

[0036] Hereinafter, the term "depth" refers to the depth based on the first plane F1, that is, the distance in the third direction based on the first plane F1.

[0037] The semiconductor layer 30 is, for example, single-crystal silicon (Si). When the semiconductor layer 30 is single-crystal silicon, the surface of the semiconductor layer 30 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (100) plane.

[0038] n +A drain region 33 having a shape is provided in the semiconductor layer 30. The drain region 33 is in contact with the second face F2. The drain region 33 is in contact with the drain electrode 20. The drain region 33 is electrically connected to the drain electrode 20.

[0039] The drain region 33 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0040] n - A drift region 34 having a shape similar to that of the semiconductor layer 30 is provided in the semiconductor layer 30. The drift region 34 is provided between the drain region 33 and the first face F1. The drift region 34 is provided on the drain region 33. The drift region 34 is electrically connected to the drain electrode 20. The drift region 34 functions as a current path when the MOSFET 100 is in an on-state.

[0041] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The following is the result.

[0042] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 15 μm.

[0043] A p-type body region 35 is provided in the semiconductor layer 30. The body region 35 is provided between the drift region 34 and the first face F1.

[0044] The body region 35 is provided between two adjacent trenches 31. The body region 35 is provided, for example, between the first trench 31a and the second trench 31b.

[0045] The body region 35 is in contact with, for example, the source electrode 10. The body region 35 is electrically connected to, for example, the source electrode 10.

[0046] When the MOSFET 100 is turned on, an inversion layer channel is formed in the body region 35 facing the gate electrode 40 .

[0047] The body region 35 includes a low concentration region 35a and a high concentration region 35b. The high concentration region 35b has a higher p-type impurity concentration than the low concentration region 35a.

[0048] The high concentration region 35b is provided between the low concentration region 35a and the first face F1. The high concentration region 35b is provided between the low concentration region 35a and the source electrode 10.

[0049] The high concentration region 35b is provided between the low concentration region 35a and the first contact portion 10a. The high concentration region 35b is provided between the low concentration region 35a and the second contact portion 10b.

[0050] The body region 35 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The following is the result.

[0051] The p-type impurity concentration of the low concentration region 35a is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The p-type impurity concentration of the high concentration region 35b is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0052] n + A source region 36 having a shape similar to that of the body region 35 is provided in the semiconductor layer 30. The source region 36 is provided between the body region 35 and the first face F1.

[0053] The source region 36 is in contact with the first face F1. The source region 36 is in contact with the source electrode 10. The source region 36 is electrically connected to the source electrode 10.

[0054] The source region 36 is provided between two adjacent trenches 31. The source region 36 is provided, for example, between the first trench 31a and the second trench 31b.

[0055] The source region 36 is provided between the first contact portion 10a and the trench 31. The source region 36 is not provided between the second contact portion 10b and the trench 31. A body region 35 is provided between the second contact portion 10b and the trench 31.

[0056] The source region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0057] The trench 31 exists in the semiconductor layer 30. The trench 31 is located on the first face F1 side of the semiconductor layer 30. The trench 31 is a groove formed in the semiconductor layer 30.

[0058] The trench 31 extends in a first direction. The plurality of trenches 31 are repeatedly arranged in a second direction. For example, the plurality of trenches 31 are repeatedly arranged in the second direction at a constant pitch.

[0059] The trench 31 penetrates the body region 35 and reaches the drift region 34. The depth of the trench 31 is, for example, not less than 1 μm and not more than 5 μm. The width of the trench 31 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm.

[0060] The gate electrode 40 is provided in the trench 31. The gate electrode 40 is electrically connected to the gate electrode wiring 12x and the gate electrode pad 12 by using, for example, a contact structure (not shown).

[0061] The gate electrode 40 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0062] The gate insulating layer 45 is provided between the gate electrode 40 and the semiconductor layer 30. The gate insulating layer 45 is provided between the gate electrode 40 and the body region 35. The gate insulating layer 45 is provided between the gate electrode 40 and the drift region 34. The gate insulating layer 45 is provided between the gate electrode 40 and the source region 36. The gate insulating layer 45 is made of, for example, silicon oxide.

[0063] The field plate electrode 50 is provided in the trench 31. The field plate electrode 50 is provided between the gate electrode 40 and the second face F2 in the third direction. The field plate electrode 50 extends in the first direction.

[0064] The field plate electrode 50 has the function of changing the electric field distribution in the drift region 34 when the MOSFET 100 is in an off state, thereby improving the breakdown voltage of the MOSFET 100.

[0065] The field plate electrode 50 is electrically connected to the source electrode 10 using, for example, a contact structure (not shown).

[0066] The field plate electrode 50 is a conductor and is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0067] The field plate insulating layer 55 is provided between the field plate electrode 50 and the semiconductor layer 30. The field plate insulating layer 55 is provided between the field plate electrode 50 and the drift region 34. The field plate insulating layer 55 is made of, for example, silicon oxide.

[0068] The thickness of the field plate insulating layer 55 is, for example, thicker than the thickness of the gate insulating layer 45. The thickness of the field plate insulating layer 55 is, for example, 3 times or more and 30 times or less the thickness of the gate insulating layer 45.

[0069] The inter-electrode insulating layer 60 is provided between the gate electrode 40 and the field plate electrode 50. The inter-electrode insulating layer 60 is made of, for example, silicon oxide.

[0070] The thickness of the inter-electrode insulating layer 60 is greater than the thickness of the gate insulating layer 45, for example.

[0071] The interlayer insulating layer 70 is provided between the gate electrode 40 and the source electrode 10. The interlayer insulating layer 70 has a function of electrically isolating the gate electrode 40 and the source electrode 10. The interlayer insulating layer 70 is made of, for example, silicon oxide.

[0072] The source electrode 10 is provided on the first face F1 side of the semiconductor layer 30. The source electrode 10 is provided on the first face F1 of the semiconductor layer 30. The source electrode 10 is electrically connected to the source region 36 and the body region 35.

[0073] The source electrode 10 includes a first contact portion 10a, a second contact portion 10b, and a surface portion 10c.

[0074] The first contact portion 10a is provided between the semiconductor layer 30 and the surface portion 10c. The first contact portion 10a is provided between two gate electrodes 40 adjacent to each other in the second direction. The first contact portion 10a is provided, for example, between the first gate electrode 40a and the second gate electrode 40b. The first contact portion 10a is provided, for example, between the second gate electrode 40b and the third gate electrode 40c.

[0075] The first contact portion 10a is in contact with the semiconductor layer 30. The first contact portion 10a is in contact with the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the body region 35. The first contact portion 10a is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the high-concentration region 35b of the body region 35.

[0076] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0077] A portion of the first contact portion 10a fills a recess provided in the semiconductor layer 30. A portion of the first contact portion 10a is provided in the recess provided in the semiconductor layer 30. The recess extends in a first direction.

[0078] The first contact portion 10a is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the first contact portion 10a is sandwiched between the source regions 36 in the second direction.

[0079] The width of the first contact portion 10a in the second direction is a first width (w1 in FIG. 2). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0080] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 2). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0081] The length of the first contact portion 10a in the first direction is a first length (L1 in FIG. 3). The first length L1 of the first contact portion 10a in the first direction is, for example, the length of the first contact portion 10a in the first direction at the position of the first face F1.

[0082] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0083] The second contact portion 10b is provided between the semiconductor layer 30 and the surface layer portion 10c. The second contact portion 10b is provided between two gate electrodes 40 adjacent to each other in the second direction. The second contact portion 10b is provided, for example, between the first gate electrode 40a and the second gate electrode 40b. The second contact portion 10b is provided, for example, between the second gate electrode 40b and the third gate electrode 40c.

[0084] The second contact portion 10b is provided in a first direction of the first contact portion 10a.

[0085] The second contact portion 10b is in contact with the semiconductor layer 30. The second contact portion 10b is in contact with the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the body region 35. The second contact portion 10b is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the high-concentration region 35b of the body region 35.

[0086] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0087] A portion of the second contact portion 10b fills a recess provided in the semiconductor layer 30. A portion of the second contact portion 10b is provided in the recess provided in the semiconductor layer 30. The recess extends in the first direction. A portion of the second contact portion 10b is provided in the same recess as a portion of the first contact portion 10a.

[0088] The second contact portion 10b is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the second contact portion 10b is sandwiched between the body regions 35 in the second direction.

[0089] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 2). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first surface F1 of the second contact portion 10b.

[0090] The second width w2 of the second contact portion 10b is greater than the first width w1 of the first contact portion 10a, and is, for example, 1.2 to 3 times the first width w1.

[0091] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 2). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0092] The second depth d2 of the second contact portion 10b is, for example, deeper than the depth of the source region .

[0093] The second depth d2 of the second contact portion 10b is, for example, substantially the same as the first depth d1 of the first contact portion 10a.

[0094] The length of the second contact portion 10b in the first direction is the second length (L2 in FIG. 3). The second length L2 of the second contact portion 10b in the first direction is, for example, the length of the second contact portion 10b in the first direction at the position of the first face F1.

[0095] The first length L1 of the first contact portion 10a is, for example, longer than the second length L2 of the second contact portion 10b, and is, for example, two to ten times the second length L2 of the second contact portion 10b.

[0096] 3, a plurality of first contact portions 10a and a plurality of second contact portions 10b are alternately and repeatedly provided in the first direction between two gate electrodes 40 adjacent to each other in the second direction. The width of the contact portions including the first contact portions 10a and the second contact portions 10b in the second direction repeatedly widens and narrows along the first direction.

[0097] 3, the repeated pattern of the first contact portion 10a and the second contact portion 10b is shifted in the first direction between the first gate electrode 40a and the second gate electrode 40b and between the second gate electrode 40b and the third gate electrode 40c. In the second direction of the second contact portion 10b between the first gate electrode 40a and the second gate electrode 40b, the first contact portion 10a between the second gate electrode 40b and the third gate electrode 40c is provided.

[0098] The surface layer portion 10c is provided on the plurality of first contact portions 10a and the plurality of second contact portions 10b, and electrically connects the plurality of first contact portions 10a and the plurality of second contact portions 10b.

[0099] The surface layer portion 10c is a region to which, for example, a bonding wire is connected when the MOSFET 100 is mounted.

[0100] The source electrode 10 is a conductor. The source electrode 10 is, for example, a metal. The first contact portion 10a, the second contact portion 10b, and the surface layer portion 10c may be formed of the same material or different materials.

[0101] The first contact portion 10a and the second contact portion 10b have a laminated structure of, for example, titanium, titanium nitride, and tungsten, and the surface layer portion 10c has a laminated structure of, for example, titanium nitride and aluminum.

[0102] The drain electrode 20 is provided on the second face F2 side of the semiconductor layer 30. The drain electrode 20 is provided on the second face F2 of the semiconductor layer 30. The drain electrode 20 is electrically connected to the drain region 33. The drain electrode 20 contacts the drain region 33. The drain electrode 20 is electrically connected to the drift region 34.

[0103] The drain electrode 20 is made of a metal and has a laminated structure of a material selected from, for example, titanium, aluminum, nickel, copper, silver, and gold.

[0104] The gate electrode pad 12 is provided on the first face F1 side of the semiconductor layer 30. The gate electrode pad 12 is provided on the first face F1 of the semiconductor layer 30. The gate electrode pad 12 and the gate electrode wiring 12x surround, for example, the source electrode 10, as shown in FIG. 1(a).

[0105] The gate electrode pad 12 is electrically connected to the gate electrode 40. When the MOSFET 100 is mounted, the gate electrode pad 12 is a region to which, for example, a bonding wire is connected.

[0106] The gate electrode pad 12 is made of metal. The gate electrode pad 12 has, for example, a laminated structure of titanium nitride and aluminum. The material of the gate electrode pad 12 is, for example, the same as the material of the source electrode 10.

[0107] The gate electrode wiring 12x is electrically connected to the gate electrode 40. The gate electrode pad 12 and the gate electrode 40 are electrically connected to each other using the gate electrode wiring 12x.

[0108] The gate electrode wiring 12x is made of metal. The gate electrode wiring 12x has, for example, a laminated structure of titanium nitride and aluminum. The material of the gate electrode wiring 12x is, for example, the same as the material of the source electrode 10 and the material of the gate electrode pad 12.

[0109] The MOSFET 100 of the first embodiment can be manufactured, for example, by patterning the interlayer insulating layer 70 to form openings for providing the first contact portion 10a and the second contact portion 10b so that the width of the opening corresponding to the second contact portion 10b is larger than the width of the opening corresponding to the first contact portion 10a.

[0110] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0111] Fig. 5 is a schematic cross-sectional view of a part of a semiconductor device of a comparative embodiment, which is a cross-section taken along CC' in Fig. 6. Fig. 5 is a view corresponding to Fig. 2 of the first embodiment.

[0112] Fig. 6 is a schematic top view of a part of a semiconductor device of a comparative embodiment Fig. 5 is a view corresponding to Fig. 3 of the first embodiment.

[0113] The semiconductor device of the comparative embodiment is a MOSFET 900. The MOSFET 900 differs from the MOSFET 100 of the first embodiment in that the width of the contact portion of the source electrode is constant.

[0114] The source electrode 10 of the MOSFET 900 includes a contact portion 10x. The contact portion 10x has a structure similar to that of the first contact portion 10a of the MOSFET 100 of the first embodiment. In the MOSFET 900, the contact portion 10x is provided continuously in the first direction between two gate electrodes 40 adjacent to each other in the second direction.

[0115] In the MOSFET 900, for example, the avalanche resistance may be reduced. For example, if avalanche breakdown occurs during the turn-off operation of the MOSFET 900, holes are discharged from the contact portion 10x to the source electrode 10 in the body region 35. If the holes are not sufficiently discharged from the contact portion 10x, the parasitic NPN transistor turns on, causing a large current to flow and destroying the MOSFET 900. If the holes are not sufficiently discharged from the contact portion 10x, the parasitic NPN transistor turns on prematurely, reducing the avalanche resistance of the MOSFET 900.

[0116] In order to promote the discharge of holes from the contact portion 10x, for example, it is possible to increase the width of the contact portion 10x in the second direction. By increasing the width of the contact portion 10x in the second direction, the discharge of holes from the contact portion 10x is promoted, making it difficult for the parasitic NPN transistor to turn on.

[0117] However, for example, increasing the width of the contact portion 10x may increase the threshold voltage of the transistor due to the influence of the p-type high-concentration regions 35b provided on the side and bottom of the contact portion 10x. An increase in the threshold voltage of the transistor is undesirable because it reduces the on-current of the MOSFET 900.

[0118] In the MOSFET 100 of the first embodiment, the second width w2 of the second contact portion 10b is wider than the first width w1 of the first contact portion 10a. By widening the second width w2 of the second contact portion 10b, the discharge of holes from the second contact portion 10b is promoted. Therefore, the avalanche resistance of the MOSFET 100 is improved.

[0119] Furthermore, in the MOSFET 100, the second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b. Therefore, the contact area between the second contact portion 10b and the body region 35 is increased compared to when the second contact portion 10b contacts the source region 36. This further improves the avalanche resistance of the MOSFET 100.

[0120] Furthermore, because the second contact portion 10b does not contact the source region 36, the region below the second contact portion 10b does not function as a transistor. This prevents a parasitic transistor with a high threshold voltage from forming below the second contact portion 10b. This, for example, reduces variations in the on-current of the MOSFET 100.

[0121] In the MOSFET 100 of the first embodiment, the first width w1 of the first contact portion 10a is smaller than the second width w2 of the second contact portion 10b. Therefore, the p-type high-concentration regions 35b provided on the side and bottom of the contact portion 10x prevent the transistor threshold voltage from increasing. Therefore, the on-current of the MOSFET 100 is prevented from decreasing.

[0122] Furthermore, the MOSFET 100 of the first embodiment includes a field plate electrode 50. The second contact portion 10b improves the avalanche resistance, making it possible to increase the n-type impurity concentration in the drift region 34 between the trenches 31. Therefore, by providing the second contact portion 10b, the electrical resistance of the drift region 34 is reduced, and the on-current of the MOSFET 100 can be increased.

[0123] According to the MOSFET 100 of the first embodiment, a MOSFET with improved avalanche resistance can be realized.

[0124] From the viewpoint of improving the avalanche resistance of the MOSFET 100, the second width w2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first width w1 of the first contact portion 10a.

[0125] From the viewpoint of suppressing a decrease in the on-current of the MOSFET 100, it is preferable that the first length L1 of the first contact portion 10a be longer than the second length L2 of the second contact portion 10b. Furthermore, from the viewpoint of suppressing a decrease in the on-current of the MOSFET 100, it is more preferable that the first length L1 of the first contact portion 10a be at least twice the second length L2 of the second contact portion 10b, and even more preferably at least five times the second length L2 of the second contact portion 10b.

[0126] (First Modification) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the second portion is in contact with the third semiconductor region.

[0127] The semiconductor device according to the first modification of the first embodiment is a MOSFET 110. The MOSFET 110 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0128] Fig. 7 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the first embodiment. Fig. 7 is a cross-section taken along line DD' in Fig. 8. Fig. 7 is a view corresponding to Fig. 2 of the first embodiment.

[0129] Fig. 8 is a schematic top view of a part of a semiconductor device according to a first modification of the first embodiment, and corresponds to Fig. 3 of the first embodiment.

[0130] In the MOSFET 110 according to the first modification of the first embodiment, the second contact portion 10b is in contact with the source region 36. In the MOSFET 110, the source region 36 is provided in the semiconductor layer 30 around the second contact portion 10b.

[0131] According to the MOSFET 110 of the first modification of the first embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 100 of the first embodiment.

[0132] (Second Modification) The semiconductor device of the second variant of the first embodiment differs from the semiconductor device of the first embodiment in that the repeating pattern of the first contact portion and the second contact portion is not shifted in the first direction between the first gate electrode and the second gate electrode and between the second gate electrode and the third gate electrode.

[0133] The semiconductor device according to the second modification of the first embodiment is a MOSFET 120. The MOSFET 120 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0134] Fig. 9 is a schematic top view of a part of a semiconductor device according to a second modification of the first embodiment, which corresponds to Fig. 3 of the first embodiment.

[0135] The repeated pattern of the first contact portion 10a and the second contact portion 10b is not shifted in the first direction between the first gate electrode 40a and the second gate electrode 40b and between the second gate electrode 40b and the third gate electrode 40c. The first contact portion 10a is provided in the second direction of the first contact portion 10a. The second contact portion 10b is provided in the second direction of the second contact portion 10b.

[0136] According to the MOSFET 120 of the second modification of the first embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 100 of the first embodiment.

[0137] (Third Modification) The semiconductor device of the third modified example of the first embodiment differs from the semiconductor device of the first embodiment in that it does not include a field plate electrode.

[0138] The semiconductor device according to the third modification of the first embodiment is a MOSFET 130. The MOSFET 130 is a vertical trench gate MOSFET in which a gate electrode is provided in a trench.

[0139] Fig. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third modification of the first embodiment, and corresponds to Fig. 2 of the first embodiment.

[0140] The MOSFET 130 according to the third modification of the first embodiment does not include the field plate electrode 50 .

[0141] According to the MOSFET 130 of the third modification of the first embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 100 of the first embodiment.

[0142] (Fourth Modification) The semiconductor device of the fourth modification of the first embodiment differs from the semiconductor device of the first embodiment in that it does not include a trench.

[0143] The semiconductor device according to the fourth modification of the first embodiment is a MOSFET 140. The MOSFET 140 is a vertical planar gate MOSFET in which a gate electrode is provided on the surface of a semiconductor layer.

[0144] Fig. 11 is a schematic cross-sectional view of a part of a semiconductor device according to a fourth modification of the first embodiment, and corresponds to Fig. 2 of the first embodiment.

[0145] The MOSFET 140 of the fourth modification of the first embodiment does not include the trench 31. The MOSFET 140 of the fourth modification is a planar gate MOSFET.

[0146] According to the MOSFET 140 of the fourth modification of the first embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 100 of the first embodiment.

[0147] (Fifth Modification) The semiconductor device of the fifth modification of the first embodiment differs from the semiconductor device of the first embodiment in that the gate electrode is divided into two parts in the second direction.

[0148] The semiconductor device according to the fifth modification of the first embodiment is a MOSFET 150. The MOSFET 150 is a vertical trench-gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0149] Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device according to a fifth modified example of the first embodiment, and corresponds to Fig. 2 of the first embodiment.

[0150] In the MOSFET 150 according to the fifth modification of the first embodiment, the gate electrode 40 is divided into two parts in the second direction.

[0151] According to the MOSFET 150 of the fifth modification of the first embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 100 of the first embodiment.

[0152] As described above, according to the first embodiment and the modified example, a semiconductor device with improved avalanche resistance can be realized.

[0153] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the second depth of the second portion is deeper than the first depth of the first portion. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0154] The semiconductor device of the second embodiment is a MOSFET 200. The MOSFET 200 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0155] 13 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, taken along the line EE' of FIG.

[0156] Fig. 14 is a schematic top view of a portion of the semiconductor device of the second embodiment. Fig. 14 is a top view of a portion corresponding to Fig. 13. Fig. 14 is a view of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 14 is a view excluding components above the first face F1.

[0157] 15 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, taken along the line FF' in FIG.

[0158] 16 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, taken along line GG' in FIG.

[0159] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0160] The width of the first contact portion 10a in the second direction is the first width (w1 in FIG. 13). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0161] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 13). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0162] The length of the first contact portion 10a in the first direction is a first length (L1 in FIG. 14). The first length L1 of the first contact portion 10a in the first direction is, for example, the length of the first contact portion 10a in the first direction at the position of the first face F1.

[0163] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0164] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0165] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 13). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first surface F1 of the second contact portion 10b.

[0166] The second width w2 of the second contact portion 10b is, for example, substantially the same as the first width w1 of the first contact portion 10a.

[0167] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 13). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0168] The second depth d2 of the second contact portion 10b is, for example, deeper than the depth of the source region .

[0169] The second depth d2 of the second contact portion 10b is deeper than the first depth d1 of the first contact portion 10a, and is, for example, 1.2 to 2 times the first depth d1 of the first contact portion 10a.

[0170] The length of the second contact portion 10b in the first direction is the second length (L2 in FIG. 14). The second length L2 of the second contact portion 10b in the first direction is, for example, the length of the second contact portion 10b in the first direction at the position of the first face F1.

[0171] The first length L1 of the first contact portion 10a is, for example, longer than the second length L2 of the second contact portion 10b, and is, for example, two to ten times the second length L2 of the second contact portion 10b.

[0172] Between two gate electrodes 40 adjacent to each other in the second direction, for example, a plurality of first contact portions 10a and a plurality of second contact portions 10b are provided alternately and repeatedly in the first direction, as shown in Fig. 14. As shown in Fig. 16, the depth in the third direction of the contact portions including the first contact portions 10a and the second contact portions 10b alternates between becoming deeper and shallower along the first direction.

[0173] 14, the repeated pattern of the first contact portion 10a and the second contact portion 10b is shifted in the first direction between the first gate electrode 40a and the second gate electrode 40b and between the second gate electrode 40b and the third gate electrode 40c. In the second direction of the second contact portion 10b between the first gate electrode 40a and the second gate electrode 40b, the first contact portion 10a between the second gate electrode 40b and the third gate electrode 40c is provided.

[0174] The MOSFET 200 of the second embodiment can be manufactured, for example, by performing two etching steps to form recesses in the semiconductor layer 30 for providing the first contact portion 10a and the second contact portion 10b, and patterning the recesses so that the depth of the recess corresponding to the second contact portion 10b is deeper than the depth of the recess corresponding to the first contact portion 10a.

[0175] Next, the operation and effects of the semiconductor device of the second embodiment will be described.

[0176] 5 and 6 of the first embodiment, in order to promote the discharge of holes from the contact portion 10x, it is possible to consider, for example, increasing the depth of the contact portion 10x in the third direction. By increasing the depth of the contact portion 10x in the third direction, the discharge of holes from the contact portion 10x is promoted, and the parasitic NPN transistor becomes less likely to be turned on.

[0177] However, for example, increasing the depth of the contact portion 10x may increase the threshold voltage of the transistor due to the influence of the p-type high concentration regions 35b provided on the side and bottom of the contact portion 10x. An increase in the threshold voltage of the transistor is undesirable because it reduces the on-current of the MOSFET 900.

[0178] In the MOSFET 200 of the second embodiment, the second depth d2 of the second contact portion 10b is deeper than the first depth d1 of the first contact portion 10a. By increasing the second depth d2 of the second contact portion 10b, the discharge of holes from the second contact portion 10b is promoted. Therefore, the avalanche resistance of the MOSFET 200 is improved.

[0179] Furthermore, in the MOSFET 200, the second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b. Therefore, the contact area between the second contact portion 10b and the body region 35 is increased compared to when the second contact portion 10b contacts the source region 36. This further improves the avalanche resistance of the MOSFET 200.

[0180] Furthermore, because the second contact portion 10b does not contact the source region 36, the region below the second contact portion 10b does not function as a transistor. This prevents a parasitic transistor with a high threshold voltage from forming below the second contact portion 10b. This, for example, reduces variations in the on-current of the MOSFET 200.

[0181] In the MOSFET 200 of the second embodiment, the first depth d1 of the first contact portion 10a is smaller than the second depth d2 of the second contact portion 10b. Therefore, the p-type high-concentration regions 35b provided on the side and bottom of the contact portion 10x prevent the transistor threshold voltage from increasing. Therefore, the on-current of the MOSFET 200 is prevented from decreasing.

[0182] Furthermore, the MOSFET 200 of the second embodiment includes a field plate electrode 50. The second contact portion 10b improves the avalanche resistance, making it possible to increase the n-type impurity concentration in the drift region 34 between the trenches 31. Therefore, by providing the second contact portion 10b, the electrical resistance of the drift region 34 can be reduced and the on-current of the MOSFET 200 can be increased.

[0183] According to the MOSFET 200 of the second embodiment, a MOSFET with improved avalanche resistance can be realized.

[0184] From the viewpoint of improving the avalanche resistance of the MOSFET 200, the second depth d2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first depth d1 of the first contact portion 10a.

[0185] From the viewpoint of suppressing a decrease in the on-current of the MOSFET 200, it is preferable that the first length L1 of the first contact portion 10a be longer than the second length L2 of the second contact portion 10b. Furthermore, from the viewpoint of suppressing a decrease in the on-current of the MOSFET 200, it is more preferable that the first length L1 of the first contact portion 10a be at least twice the second length L2 of the second contact portion 10b, and even more preferably at least five times the second length L2 of the second contact portion 10b.

[0186] (First Modification) The semiconductor device of the first modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the second portion is in contact with the third semiconductor region.

[0187] The semiconductor device according to the first modification of the second embodiment is a MOSFET 210. The MOSFET 210 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0188] Fig. 17 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the second embodiment. Fig. 17 is a cross-section taken along line HH' in Fig. 18. Fig. 17 is a view corresponding to Fig. 13 of the second embodiment.

[0189] Fig. 18 is a schematic top view of a part of a semiconductor device according to a first modified example of the second embodiment, and corresponds to Fig. 14 of the second embodiment.

[0190] In the MOSFET 210 according to the first modification of the second embodiment, the second contact portion 10b is in contact with the source region 36. In the MOSFET 210, the source region 36 is provided in the semiconductor layer 30 around the second contact portion 10b.

[0191] According to the MOSFET 210 of the second modification of the second embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 200 of the second embodiment.

[0192] (Second Modification) The semiconductor device of the second variant of the second embodiment differs from the semiconductor device of the second embodiment in that the second depth of the second portion is deeper than the first depth of the first portion, and the second width in the second direction of the second portion is wider than the first width in the second direction of the first portion.

[0193] The semiconductor device according to the second modification of the second embodiment is a MOSFET 220. The MOSFET 220 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0194] Fig. 19 is a schematic cross-sectional view of a part of a semiconductor device according to a second modification of the second embodiment, and corresponds to Fig. 13 of the second embodiment.

[0195] In a MOSFET 220 according to the second modification of the second embodiment, the second width w2 of the second contact portion 10b is greater than the first width w1 of the first contact portion 10a. The second width w2 is, for example, 1.2 to 3 times the first width w1.

[0196] In the MOSFET 220 according to the second modification of the second embodiment, the discharge of holes from the second contact portion 10b is further promoted.

[0197] According to the MOSFET 220 of the second modification of the second embodiment, a MOSFET with improved avalanche resistance can be realized, similar to the MOSFET 200 of the second embodiment.

[0198] As a modification of the second embodiment, for example, as in the second modification of the first embodiment, it is also possible to adopt a configuration in which the repeating pattern of the first contact portion and the second contact portion is not shifted in the first direction between the first gate electrode and the second gate electrode and between the second gate electrode and the third gate electrode.

[0199] As a modification of the second embodiment, for example, it is possible to adopt a configuration in which no field plate electrode is provided, as in the third modification of the first embodiment.

[0200] As a modification of the second embodiment, for example, a planar gate MOSFET without a trench can be used, as in the fourth modification of the first embodiment.

[0201] Furthermore, as a modification of the second embodiment, for example, it is possible to adopt a configuration in which the gate electrode is divided into two parts in the second direction, as in the fifth modification of the first embodiment.

[0202] As described above, according to the second embodiment and the modified example, a semiconductor device with improved avalanche resistance can be realized.

[0203] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor devices of the first and second embodiments in that it further comprises an element region including a third semiconductor region and a termination region surrounding the element region without including the third semiconductor region, and the first portion is provided in the element region and the second portion is provided in the termination region. Hereinafter, some description of content that overlaps with the first or second embodiment may be omitted.

[0204] The semiconductor device of the third embodiment is a MOSFET 300. The MOSFET 300 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0205] 20(a) and 20(b) are schematic diagrams of the semiconductor device of the third embodiment. Fig. 20(a) shows the front surface of a MOSFET 300. Fig. 20(b) shows the back surface of the MOSFET 300.

[0206] 20(a), a source electrode 10, a gate electrode pad 12, and a gate electrode wiring 12x are provided on the surface side of the MOSFET 300. The gate electrode wiring 12x is connected to the gate electrode pad 12.

[0207] As shown in FIG. 20(b), a drain electrode 20 is provided on the back surface side of the MOSFET 300.

[0208] A plurality of transistors are provided below the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 12 to control the switching operation of the transistors.

[0209] 20(a), a MOSFET 300 includes an element region 301 and a termination region 302. The termination region 302 surrounds the element region 301. In FIG. 20(a), the hatched region is the element region 301, and the outer periphery of the element region 301 is the termination region 302.

[0210] The element region 301 includes a transistor. The element region 301 includes a source region 36 of the transistor. The termination region 302 does not include a transistor. The termination region 302 does not include a source region 36.

[0211] Termination region 102 includes, for example, a termination structure for improving the breakdown voltage of MOSFET 300. The termination structure is, for example, a resurf structure or a guard ring structure.

[0212] Fig. 21 is a schematic top view of a part of the third embodiment, showing region X in Fig. 20(a). Fig. 21 is a view including the boundary between the element region 301 and the termination region 302.

[0213] Fig. 21 is a diagram showing a layout pattern of a MOSFET 300. Fig. 21 shows a layout pattern of a trench 31, a body region 35, and a source region 36. Fig. 21 shows the layout pattern on the surface of a semiconductor layer 30.

[0214] 21 , the plurality of trenches 31 extend in a first direction. Some of the trenches 31 extend in the first direction beyond the boundary between the element region 301 and the termination region 302. The trenches 31 at the ends in the second direction are entirely provided outside the element region 301.

[0215] 21 , a source region 36 is provided on the surface of the semiconductor layer 30 in the element region 301. On the other hand, no source region 36 is provided on the surface of the semiconductor layer 30 in the termination region 302. A body region 35 is provided on the surface of the semiconductor layer 30 in the termination region 302.

[0216] Fig. 22 is a schematic top view of a portion of the semiconductor device of the third embodiment. Fig. 22 is a view corresponding to region Xa in Fig. 21. Fig. 21 is a view including the boundary between the element region 301 and the termination region 302.

[0217] Fig. 22 is a diagram of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 22 is a diagram excluding components above the first face F1.

[0218] 23 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment, taken along the line JJ' in FIG.

[0219] 24 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment, taken along the line KK' in FIG.

[0220] The source electrode 10 includes a first contact portion 10a, a second contact portion 10b, and a surface portion 10c.

[0221] The first contact portion 10a is provided in the element region 301. The second contact portion 10b is provided in the termination region 302.

[0222] The first contact portion 10a is provided between the semiconductor layer 30 and the surface portion 10c. The first contact portion 10a is provided between two gate electrodes 40 adjacent to each other in the second direction. The first contact portion 10a is provided, for example, between the first gate electrode 40a and the second gate electrode 40b. The first contact portion 10a is provided, for example, between the second gate electrode 40b and the third gate electrode 40c.

[0223] The first contact portion 10a is in contact with the semiconductor layer 30. The first contact portion 10a is in contact with the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the body region 35. The first contact portion 10a is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the high-concentration region 35b of the body region 35.

[0224] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0225] The first contact portion 10a is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the first contact portion 10a is sandwiched between the source regions 36 in the second direction.

[0226] The width of the first contact portion 10a in the second direction is the first width (w1 in FIG. 23). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0227] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 23). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0228] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0229] The second contact portion 10b is provided between the semiconductor layer 30 and the surface layer portion 10c. The second contact portion 10b is provided between two gate electrodes 40 adjacent to each other in the second direction. The second contact portion 10b is provided, for example, between the first gate electrode 40a and the second gate electrode 40b. The second contact portion 10b is provided, for example, between the second gate electrode 40b and the third gate electrode 40c.

[0230] The second contact portion 10b is provided in a first direction of the first contact portion 10a.

[0231] The second contact portion 10b is in contact with the semiconductor layer 30. The second contact portion 10b is in contact with the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the body region 35. The second contact portion 10b is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the high-concentration region 35b of the body region 35.

[0232] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0233] The second contact portion 10b is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the second contact portion 10b is sandwiched between the body regions 35 in the second direction.

[0234] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 24). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first face F1 of the second contact portion 10b.

[0235] The second width w2 of the second contact portion 10b is greater than the first width w1 of the first contact portion 10a, and is, for example, 1.2 to 3 times the first width w1.

[0236] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 24). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0237] The second depth d2 of the second contact portion 10b is, for example, deeper than the depth of the source region .

[0238] The second depth d2 of the second contact portion 10b is, for example, substantially the same as the first depth d1 of the first contact portion 10a.

[0239] The surface layer portion 10c is provided on the plurality of first contact portions 10a and the plurality of second contact portions 10b, and electrically connects the plurality of first contact portions 10a and the plurality of second contact portions 10b.

[0240] The surface layer portion 10c is a region to which, for example, a bonding wire is connected when the MOSFET 300 is mounted.

[0241] Next, the operation and effects of the semiconductor device of the third embodiment will be described.

[0242] In the MOSFET 300 of the third embodiment, the second width w2 of the second contact portion 10b provided in the termination region 302 is wider than the first width w1 of the first contact portion 10a provided in the element region 301. By widening the second width w2 of the second contact portion 10b, the discharge of holes from the second contact portion 10b is promoted. Therefore, the avalanche resistance of the MOSFET 300 is improved.

[0243] In the MOSFET 300, the second contact portion 10b is provided only in the termination region 302, which does not include a transistor. The second contact portion 10b is not provided in the element region 301, which includes a transistor. Therefore, the provision of the second contact portion 10b does not change the on-current of the MOSFET 300.

[0244] From the viewpoint of improving the avalanche resistance of the MOSFET 300, the second width w2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first width w1 of the first contact portion 10a.

[0245] (First Modification) The semiconductor device of the first variant of the third embodiment differs from the semiconductor device of the third embodiment in that the first width of the first portion and the second width of the second portion are the same, and the second depth of the second portion is deeper than the first depth of the first portion.

[0246] The semiconductor device according to the first modification of the third embodiment is a MOSFET 310. The MOSFET 310 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0247] Fig. 25 is a schematic top view of a part of a semiconductor device according to a first modified example of the third embodiment, including the boundary between the element region 301 and the termination region 302. Fig. 25 corresponds to Fig. 22 of the third embodiment.

[0248] Fig. 26 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the third embodiment. Fig. 26 is a cross-section taken along line LL' in Fig. 25. Fig. 26 is a view corresponding to Fig. 23 of the third embodiment.

[0249] Fig. 27 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the third embodiment. Fig. 27 is a cross-section taken along line MM' in Fig. 25. Fig. 27 is a view corresponding to Fig. 24 of the third embodiment.

[0250] 28 is a schematic cross-sectional view of a part of a semiconductor device according to a first modification of the third embodiment, taken along the line NN' in FIG.

[0251] The source electrode 10 includes a first contact portion 10a, a second contact portion 10b, and a surface portion 10c.

[0252] The first contact portion 10a is provided in the element region 301. The second contact portion 10b is provided in the termination region 302.

[0253] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0254] The width of the first contact portion 10a in the second direction is the first width (w1 in FIG. 26). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0255] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 26). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0256] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0257] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0258] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 27). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first face F1 of the second contact portion 10b.

[0259] The second width w2 of the second contact portion 10b is, for example, substantially the same as the first width w1 of the first contact portion 10a.

[0260] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 27). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0261] The second depth d2 of the second contact portion 10b is deeper than the depth of the source region .

[0262] The second depth d2 of the second contact portion 10b is deeper than the first depth d1 of the first contact portion 10a, and is, for example, 1.2 to 2 times the first depth d1 of the first contact portion 10a.

[0263] Between two gate electrodes 40 adjacent to each other in the second direction, a second contact portion 10b is provided in the first direction of a first contact portion 10a, as shown in Fig. 25. As shown in Fig. 28, the depth in the third direction of a contact portion including the first contact portion 10a and the second contact portion 10b increases along the first direction.

[0264] In the MOSFET 310 according to the first modification of the third embodiment, the second depth d2 of the second contact portion 10b provided in the termination region 302 is deeper than the first depth d1 of the first contact portion 10a provided in the element region 301. Increasing the second depth d2 of the second contact portion 10b promotes the discharge of holes from the second contact portion 10b. This improves the avalanche resistance of the MOSFET 310.

[0265] From the viewpoint of improving the avalanche resistance of the MOSFET 310, the second depth d2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first depth d1 of the first contact portion 10a.

[0266] As a modification of the third embodiment, for example, it is possible to adopt a configuration in which no field plate electrode is provided, as in the third modification of the first embodiment.

[0267] As a modification of the third embodiment, for example, a planar gate MOSFET without a trench can be used, as in the fourth modification of the first embodiment.

[0268] Furthermore, as a modification of the third embodiment, for example, it is also possible to adopt a configuration in which the gate electrode is divided into two parts in the second direction, as in the fifth modification of the first embodiment.

[0269] Furthermore, as a modified example of the third embodiment, for example, as in the second modified example of the second embodiment, it is also possible to configure the second depth d2 of the second contact portion 10b to be deeper than the first depth d1 of the first contact portion 10a, and the second width w2 of the second contact portion 10b to be wider than the first width w1 of the first contact portion 10a.

[0270] As described above, according to the third embodiment and its modifications, a semiconductor device with improved avalanche resistance can be realized.

[0271] (Fourth embodiment) A semiconductor device according to a fourth embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a first gate electrode provided on the first surface side of the semiconductor layer and extending in a first direction parallel to the first surface; and a second gate electrode provided on the first surface side of the semiconductor layer and extending in the first direction, the second gate electrode provided on the first surface side of the semiconductor layer and extending in a second direction parallel to the first surface and perpendicular to the first direction. a third gate electrode provided on the first surface side of the semiconductor layer, extending in a first direction, with a second gate electrode provided between the first gate electrode and the third gate electrode; a first gate insulating layer provided between the first gate electrode and the semiconductor layer; a second gate insulating layer provided between the second gate electrode and the semiconductor layer; a third gate insulating layer provided between the third gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer, electrically connected to the third semiconductor region; and a second electrode provided on the second surface side of the semiconductor layer, electrically connected to the first semiconductor region. The first electrode includes a first portion and a second portion, the first portion being provided between the first gate electrode and the second gate electrode, the second portion being provided between the second gate electrode and the third gate electrode, the second portion being provided in a second direction of the first portion, the first portion contacting the second semiconductor region and the third semiconductor region, the second portion contacting the second semiconductor region but not the third semiconductor region, the first portion being sandwiched between one part of the semiconductor layer and another part in the second direction, the second portion being sandwiched between one part of the semiconductor layer and another part in the second direction, the second width of the second portion in the second direction being wider than the first width of the first portion in the second direction, or the second depth of the second portion being deeper than the first depth of the first portion. The semiconductor device of the fourth embodiment differs from the semiconductor devices of the first, second, and third embodiments in that the first portion is not provided between the same two gate electrodes as the second portion. Hereinafter, some of the content that overlaps with the first, second, or third embodiment may be omitted.

[0272] The semiconductor device of the fourth embodiment is a MOSFET 400. The MOSFET 400 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0273] The MOSFET 400 includes a source electrode 10 (first electrode), a drain electrode 20 (second electrode), a semiconductor layer 30, a first gate electrode 40a, a second gate electrode 40b, a third gate electrode 40c, a first gate insulating layer 45a, a second gate insulating layer 45b, a third gate insulating layer 45c, a first field plate electrode 50a, a second field plate electrode 50b, a third field plate electrode 50c, a first field plate insulating layer 55a, a second field plate insulating layer 55b, a third field plate insulating layer 55c, a first inter-electrode insulating layer 60a, a second inter-electrode insulating layer 60b, a third inter-electrode insulating layer 60c, and an interlayer insulating layer 70.

[0274] Hereinafter, the first gate electrode 40a, the second gate electrode 40b, and the third gate electrode 40c may be individually or collectively referred to simply as gate electrodes 40. Furthermore, the first gate insulating layer 45a, the second gate insulating layer 45b, and the third gate insulating layer 45c may be individually or collectively referred to simply as gate insulating layers 45. Furthermore, the first field plate electrode 50a, the second field plate electrode 50b, and the third field plate electrode 50c may be individually or collectively referred to simply as field plate electrodes 50. Furthermore, the first field plate insulating layer 55a, the second field plate insulating layer 55b, and the third field plate insulating layer 55c may be individually or collectively referred to simply as field plate insulating layers 55. Furthermore, the first interelectrode insulating layer 60a, the second interelectrode insulating layer 60b, and the third interelectrode insulating layer 60c may be individually or collectively referred to simply as interelectrode insulating layer 60.

[0275] The source electrode 10 includes a first contact portion 10a (first portion), a second contact portion 10b (second portion), and a surface portion 10c.

[0276] The semiconductor layer 30 includes a first trench 31a, a second trench 31b, a third trench 31c, and a + shaped drain region 33, n - a p-type drift region 34 (first semiconductor region), a p-type body region 35 (second semiconductor region), and an n-type + The source region 36 (third semiconductor region) is of a crystalline form.

[0277] Hereinafter, the first trench 31a, the second trench 31b, and the third trench 31c may be referred to simply as trenches 31 individually or collectively.

[0278] The body region 35 includes a low-concentration region 35a (first region) and a high-concentration region 35b (second region).

[0279] 29(a) and 29(b) are schematic diagrams of the semiconductor device of the fourth embodiment. Fig. 29(a) shows the front surface of the MOSFET 400. Fig. 29(b) shows the back surface of the MOSFET 400.

[0280] 29(a), a source electrode 10, a gate electrode pad 12, and a gate electrode wiring 12x are provided on the surface side of the MOSFET 400. The gate electrode wiring 12x is connected to the gate electrode pad 12.

[0281] As shown in FIG. 29(b), a drain electrode 20 is provided on the back surface side of the MOSFET 400.

[0282] A plurality of transistors are provided below the source electrode 10. The gate electrode pad 12 and the gate electrode wiring 12x are electrically connected to the gate electrodes of the transistors. A gate voltage is applied to the gate electrode pad 12 to control the switching operation of the transistors.

[0283] 29(a), a MOSFET 400 includes an element region 401 and a termination region 402. The termination region 402 surrounds the element region 401. In FIG. 29(a), the hatched region is the element region 401, and the outer periphery of the element region 401 is the termination region 402.

[0284] The element region 401 includes a transistor. The element region 401 includes a source region 36 of the transistor. The termination region 402 does not include a transistor. The termination region 402 does not include a source region 36.

[0285] Termination region 402 includes, for example, a termination structure for improving the breakdown voltage of MOSFET 400. The termination structure is, for example, a resurf structure or a guard ring structure.

[0286] Fig. 30 is a schematic top view of a part of the fourth embodiment, showing region Y in Fig. 29(a). Fig. 30 is a view including the boundary between the element region 401 and the termination region 402.

[0287] Fig. 30 is a diagram showing a layout pattern of a MOSFET 400. Fig. 30 shows a layout pattern of a trench 31, a body region 35, and a source region 36. Fig. 30 shows the layout pattern on the surface of a semiconductor layer 30.

[0288] 30 , the plurality of trenches 31 extend in a first direction. Among the plurality of trenches 31, the trench 31 located at the end in the second direction is entirely provided outside the element region 401. Among the plurality of trenches 31, the trench 31 located at the end in the second direction is entirely provided in the termination region 402.

[0289] 30 , a source region 36 is provided on the surface of the semiconductor layer 30 in the element region 401. On the other hand, no source region 36 is provided on the surface of the semiconductor layer 30 in the termination region 402. A body region 35 is provided on the surface of the semiconductor layer 30 in the termination region 402.

[0290] Fig. 31 is a schematic top view of a part of the semiconductor device of the fourth embodiment. Fig. 31 is a view corresponding to the region Ya in Fig. 30. Fig. 31 is a view including the boundary between the element region 401 and the termination region 402.

[0291] Fig. 31 is a diagram of a position corresponding to the first face F1 of the semiconductor layer 30. Fig. 31 is a diagram excluding components above the first face F1.

[0292] 32 is a schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment, taken along line OO' of FIG.

[0293] The first gate electrode 40a is at least partially provided within the element region 401. The third gate electrode 40c is entirely provided within the termination region 402. The second gate electrode 40b is provided between the first gate electrode 40a and the third gate electrode 40c.

[0294] A portion of the semiconductor layer 30 located between the first gate electrode 40 a and the second gate electrode 40 b in the second direction includes the source region 36. Another portion of the semiconductor layer 30 located between the second gate electrode 40 b and the third gate electrode 40 c in the second direction does not include the source region 36.

[0295] The semiconductor layer 30 between the first trench 31a and the second trench 31b includes a source region 36. The semiconductor layer 30 between the second trench 31b and the third trench 31c does not include the source region 36.

[0296] The source electrode 10 includes a first contact portion 10a, a second contact portion 10b, and a surface portion 10c.

[0297] The first contact portion 10a is provided in the element region 401. The second contact portion 10b is provided in the termination region 402. The second contact portion 10b is provided in a second direction from the first contact portion 10a.

[0298] The first contact portion 10a is provided between the semiconductor layer 30 and the surface portion 10c. The first contact portion 10a is provided between the first gate electrode 40a and the second gate electrode 40b. The first contact portion 10a is not provided between the second gate electrode 40b and the third gate electrode 40c.

[0299] The first contact portion 10a is in contact with the semiconductor layer 30. The first contact portion 10a is in contact with the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the body region 35. The first contact portion 10a is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the first contact portion 10a are in contact with the high-concentration region 35b of the body region 35.

[0300] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0301] The first contact portion 10a is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the first contact portion 10a is sandwiched between the source regions 36 in the second direction.

[0302] The width of the first contact portion 10a in the second direction is the first width (w1 in FIG. 32). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0303] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 32). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0304] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0305] The second contact portion 10b is provided between the semiconductor layer 30 and the surface layer portion 10c. The second contact portion 10b is provided between the second gate electrode 40b and the third gate electrode 40c. The second contact portion 10b is not provided, for example, between the first gate electrode 40a and the second gate electrode 40b.

[0306] The second contact portion 10b is provided in a second direction from the first contact portion 10a.

[0307] The second contact portion 10b is in contact with the semiconductor layer 30. The second contact portion 10b is in contact with the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the body region 35. The second contact portion 10b is in contact with, for example, the high-concentration region 35b of the body region 35. For example, the bottom surface and side surface of the second contact portion 10b are in contact with the high-concentration region 35b of the body region 35.

[0308] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0309] The second contact portion 10b is sandwiched in the second direction between one part of the semiconductor layer 30 and another part of the semiconductor layer 30. For example, the second contact portion 10b is sandwiched between the body regions 35 in the second direction.

[0310] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 32). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first face F1 of the second contact portion 10b.

[0311] The second width w2 of the second contact portion 10b is greater than the first width w1 of the first contact portion 10a, and is, for example, 1.2 to 3 times the first width w1.

[0312] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 32). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0313] The second depth d2 of the second contact portion 10b is, for example, substantially the same as the first depth d1 of the first contact portion 10a.

[0314] The surface layer portion 10c is provided on the first contact portion 10a and the second contact portion 10b, and electrically connects the first contact portions 10a and the second contact portions 10b.

[0315] The surface layer portion 10c is a region to which, for example, a bonding wire is connected when the MOSFET 400 is mounted.

[0316] Next, the operation and effects of the semiconductor device of the fourth embodiment will be described.

[0317] In the MOSFET 400 of the fourth embodiment, the second width w2 of the second contact portion 10b provided in the termination region 402 is wider than the first width w1 of the first contact portion 10a provided in the element region 401. By widening the second width w2 of the second contact portion 10b, the discharge of holes from the second contact portion 10b is promoted. Therefore, the avalanche resistance of the MOSFET 400 is improved.

[0318] In the MOSFET 400, the second contact portion 10b is provided only in the termination region 402, which does not include a transistor. The second contact portion 10b is not provided in the element region 401, which includes a transistor. Therefore, the provision of the second contact portion 10b does not change the on-current of the MOSFET 400.

[0319] From the viewpoint of improving the avalanche resistance of the MOSFET 400, the second width w2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first width w1 of the first contact portion 10a.

[0320] (First Modification) The semiconductor device of the first variant of the fourth embodiment differs from the semiconductor device of the fourth embodiment in that the first width of the first portion and the second width of the second portion are the same, and the second depth of the second portion is deeper than the first depth of the first portion.

[0321] The semiconductor device according to the first modification of the fourth embodiment is a MOSFET 410. The MOSFET 410 is a vertical trench gate MOSFET in which a gate electrode and a field plate electrode are provided in a trench.

[0322] Fig. 33 is a schematic top view of a part of a semiconductor device according to a first modified example of the fourth embodiment, including the boundary between an element region 401 and a termination region 402. Fig. 33 corresponds to Fig. 31 of the fourth embodiment.

[0323] Fig. 34 is a schematic cross-sectional view of a part of a semiconductor device according to a first modified example of the fourth embodiment. Fig. 34 is a cross-section taken along line OO' in Fig. 33. Fig. 34 is a view corresponding to Fig. 32 of the fourth embodiment.

[0324] The source electrode 10 includes a first contact portion 10a, a second contact portion 10b, and a surface portion 10c.

[0325] The first contact portion 10a is provided in the element region 401. The second contact portion 10b is provided in the termination region 402.

[0326] The first contact portion 10a contacts the source region 36. For example, the side surface of the first contact portion 10a contacts the source region 36.

[0327] The width of the first contact portion 10a in the second direction is the first width (w1 in FIG. 34). The first width w1 of the first contact portion 10a in the second direction is, for example, the width of the first contact portion 10a in the second direction at the position of the first face F1.

[0328] The depth of the first contact portion 10a in the third direction is the first depth (d1 in FIG. 34). The depth of the first contact portion 10a in the third direction is the depth based on the first plane F1.

[0329] The first depth d1 of the first contact portion 10a is, for example, deeper than the depth of the source region .

[0330] The second contact portion 10b does not contact the source region 36. The source region 36 is not provided around the second contact portion 10b.

[0331] The width of the second contact portion 10b in the second direction is the second width (w2 in FIG. 34). The second width w2 of the second contact portion 10b in the second direction is, for example, the width in the second direction at the position of the first face F1 of the second contact portion 10b.

[0332] The second width w2 of the second contact portion 10b is, for example, substantially the same as the first width w1 of the first contact portion 10a.

[0333] The depth of the second contact portion 10b in the third direction is the second depth (d2 in FIG. 34). The depth of the second contact portion 10b in the third direction is the depth based on the first plane F1.

[0334] The second depth d2 of the second contact portion 10b is deeper than the first depth d1 of the first contact portion 10a, and is, for example, 1.2 to 2 times the first depth d1 of the first contact portion 10a.

[0335] The second contact portion 10b is provided in a second direction of the first contact portion 10a.

[0336] In the MOSFET 410 according to the first modification of the fourth embodiment, the second depth d2 of the second contact portion 10b provided in the termination region 302 is deeper than the first depth d1 of the first contact portion 10a provided in the element region 301. Increasing the second depth d2 of the second contact portion 10b promotes the discharge of holes from the second contact portion 10b. This improves the avalanche resistance of the MOSFET 410.

[0337] From the viewpoint of improving the avalanche resistance of the MOSFET 410, the second depth d2 of the second contact portion 10b is preferably 1.2 times or more, and more preferably 1.5 times or more, the first depth d1 of the first contact portion 10a.

[0338] As a modification of the fourth embodiment, for example, it is possible to adopt a configuration in which no field plate electrode is provided, as in the third modification of the first embodiment.

[0339] As a modification of the fourth embodiment, for example, a planar gate MOSFET without a trench can be used, as in the fourth modification of the first embodiment.

[0340] Furthermore, as a modification of the fourth embodiment, for example, it is possible to adopt a configuration in which the gate electrode is divided into two parts in the second direction, as in the fifth modification of the first embodiment.

[0341] Furthermore, as a modified example of the fourth embodiment, for example, as in the second modified example of the second embodiment, it is also possible to configure the second depth d2 of the second contact portion 10b to be deeper than the first depth d1 of the first contact portion 10a, and the second width w2 of the second contact portion 10b to be wider than the first width w1 of the first contact portion 10a.

[0342] As a modification of the fourth embodiment, for example, the fourth embodiment and the third embodiment can be combined.

[0343] As described above, according to the fourth embodiment and its modifications, a semiconductor device with improved avalanche resistance can be realized.

[0344] In the first to fourth embodiments, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0345] In the first to fourth embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible to configure the first conductivity type as p-type and the second conductivity type as n-type. In other words, the MOSFET can be a p-channel MOSFET that uses holes as carriers.

[0346] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0347] 10 source electrode (first electrode) 10a First contact portion 10a (first portion) 10b Second contact portion 10b (second portion) 20 Drain electrode (second electrode) 30 Semiconductor layer 31 Trench 31a First Trench 31b Second trench 31c Third Trench 34 drift region (first semiconductor region) 35 Body region (second semiconductor region) 35a Low concentration region (first region) 35b High concentration region (second region) 36 source region (third semiconductor region) 40 gate electrode 40a First gate electrode 40b Second gate electrode 40c third gate electrode 45 Gate insulating layer 45a first gate insulating layer 45b second gate insulating layer 45c Third gate insulating layer 50 Field plate electrode 50a First field plate electrode 50b Second field plate electrode 50c Third field plate electrode 55 Field plate insulating layer 55a First field plate insulating layer 55b Second field plate insulating layer 55c Third field plate insulating layer 60 Interelectrode insulating layer 60a First inter-electrode insulating layer 60b Second inter-electrode insulating layer 60c Third inter-electrode insulating layer 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 301 Element isolation region 302 Termination area 400 MOSFET (semiconductor device) 401 Element isolation region 402 Termination area F1 First Side F2 Second side L1 First length L2 Second length d1 First depth d2 Second depth w1 First width w2 Second width

Claims

1. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a semiconductor layer comprising: a first gate electrode provided on the first surface side of the semiconductor layer and extending in a first direction parallel to the first surface; a second gate electrode provided on the first surface side of the semiconductor layer, extending in the first direction, and provided in a second direction with respect to the first gate electrode that is parallel to the first surface and perpendicular to the first direction; a first gate insulating layer provided between the first gate electrode and the semiconductor layer; a second gate insulating layer provided between the second gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region; the first electrode includes a first portion and a second portion; the first portion and the second portion are provided between the first gate electrode and the second gate electrode, the first portion and the second portion are in contact with the second semiconductor region; the second portion is provided in the first direction of the first portion, the first portion is sandwiched between one part and another part of the semiconductor layer in the second direction; the second portion is sandwiched between one part and another part of the semiconductor layer in the second direction; A semiconductor device, wherein a second width of the second portion in the second direction is wider than a first width of the first portion in the second direction, or a second depth of the second portion is deeper than a first depth of the first portion.

2. 2. The semiconductor device according to claim 1, wherein said first electrode includes a plurality of said first portions and a plurality of said second portions, said first portions and said second portions being alternately and repeatedly provided in said first direction.

3. 2. The semiconductor device according to claim 1, wherein said first portion is in contact with said third semiconductor region, and said second portion is not in contact with said third semiconductor region.

4. the semiconductor layer further includes a first trench provided on the first surface side and extending in the first direction, and a second trench provided on the first surface side and extending in the first direction, the first gate electrode is disposed in the first trench; 2. The semiconductor device according to claim 1, wherein said second gate electrode is provided in said second trench.

5. a first field plate electrode provided in the first trench and between the first gate electrode and the second surface; a second field plate electrode provided in the second trench and between the second gate electrode and the second surface; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer; a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode; 5. The semiconductor device according to claim 4, further comprising a second inter-electrode insulating layer provided between said second gate electrode and said second field plate electrode.

6. an element region including the third semiconductor region; a termination region that does not include the third semiconductor region and surrounds the element region, 2. The semiconductor device according to claim 1, wherein said first portion is provided in said element region, and said second portion is provided in said termination region.

7. 2. The semiconductor device according to claim 1, wherein said second width is 1.2 times or more and 3 times or less than said first width.

8. 2. The semiconductor device according to claim 1, wherein said second depth is 1.2 times or more and 2 times or less than said first depth.

9. 2. The semiconductor device according to claim 1, wherein the second semiconductor region includes a first region and a second region provided between the first region and the first surface, in contact with the first portion and the second portion, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the first region.

10. 2. The semiconductor device according to claim 1, wherein a first length of said first portion in said first direction is longer than a second length of said second portion in said first direction.

11. 2. The semiconductor device according to claim 1, wherein said second width is greater than said first width and said second depth is greater than said first depth.

12. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a semiconductor layer comprising: a first gate electrode provided on the first surface side of the semiconductor layer and extending in a first direction parallel to the first surface; a second gate electrode provided on the first surface side of the semiconductor layer, extending in the first direction, and provided in a second direction with respect to the first gate electrode that is parallel to the first surface and perpendicular to the first direction; a third gate electrode provided on the first surface side of the semiconductor layer, extending in the first direction, and having the second gate electrode between it and the first gate electrode; a first gate insulating layer provided between the first gate electrode and the semiconductor layer; a second gate insulating layer provided between the second gate electrode and the semiconductor layer; a third gate insulating layer provided between the third gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region; Equipped with the first electrode includes a first portion and a second portion; the first portion is provided between the first gate electrode and the second gate electrode; the second portion is provided between the second gate electrode and the third gate electrode, the second portion is provided in the second direction of the first portion, the first portion contacts the second semiconductor region and the third semiconductor region; the second portion is in contact with the second semiconductor region but not in contact with the third semiconductor region; the first portion is sandwiched between one part and another part of the semiconductor layer in the second direction; the second portion is sandwiched between one part and another part of the semiconductor layer in the second direction; A semiconductor device, wherein a second width of the second portion in the second direction is wider than a first width of the first portion in the second direction, or a second depth of the second portion is deeper than a first depth of the first portion.

13. a portion of the semiconductor layer located between the first gate electrode and the second gate electrode in the second direction includes the third semiconductor region; The semiconductor device according to claim 12 , wherein another portion of the semiconductor layer, the position in the second direction being between the second gate electrode and the third gate electrode, does not include the third semiconductor region.

14. an element region including the third semiconductor region; a termination region that does not include the third semiconductor region and surrounds the element region, 13. The semiconductor device according to claim 12, wherein said first portion is provided in said element region, and said second portion is provided in said termination region.

15. the first gate electrode is provided in the element region, 15. The semiconductor device according to claim 14, wherein said third gate electrode is provided in said termination region.

16. the semiconductor layer further includes a first trench provided on the first surface side and extending in the first direction, a second trench provided on the first surface side and extending in the first direction, and a third trench provided on the first surface side and extending in the first direction; the first gate electrode is disposed in the first trench; the second gate electrode is disposed in the second trench; The semiconductor device according to claim 12 , wherein the third gate electrode is provided in the third trench.

17. a first field plate electrode provided in the first trench and between the first gate electrode and the second surface; a second field plate electrode provided in the second trench and between the second gate electrode and the second surface; a third field plate electrode provided in the third trench and between the third gate electrode and the second surface; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer; a third field plate insulating layer provided between the third field plate electrode and the semiconductor layer; a first inter-electrode insulating layer provided between the first gate electrode and the first field plate electrode; a second inter-electrode insulating layer provided between the second gate electrode and the second field plate electrode; 17. The semiconductor device according to claim 16, further comprising: a third inter-electrode insulating layer provided between said third gate electrode and said third field plate electrode.

18. 13. The semiconductor device according to claim 12, wherein said second width is 1.2 times or more and 3 times or less than said first width.

19. 13. The semiconductor device according to claim 12, wherein said second depth is 1.2 times or more and 2 times or less than said first depth.

20. 13. The semiconductor device according to claim 12, wherein the second semiconductor region includes: a first region; and a second region provided between the first region and the first surface, in contact with the first portion and the second portion, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the first region.

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